1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI Express nexus driver tunables 31 */ 32 33 #include <sys/types.h> 34 #include <sys/cmn_err.h> 35 #include <sys/time.h> 36 #include <sys/pci.h> 37 #include "px_space.h" 38 39 /*LINTLIBRARY*/ 40 41 uint32_t px_spurintr_duration = 60000000; /* One minute */ 42 uint64_t px_spurintr_msgs = PX_SPURINTR_MSG_DEFAULT; 43 44 /* 45 * The variable controls the default setting of the command register 46 * for pci devices. See init_child() for details. 47 * 48 * This flags also controls the setting of bits in the bridge control 49 * register pci to pci bridges. See init_child() for details. 50 */ 51 ushort_t px_command_default = PCI_COMM_SERR_ENABLE | 52 PCI_COMM_WAIT_CYC_ENAB | 53 PCI_COMM_PARITY_DETECT | 54 PCI_COMM_ME | 55 PCI_COMM_MAE | 56 PCI_COMM_IO; 57 58 /* 59 * The following variable enables a workaround for the following obp bug: 60 * 61 * 1234181 - obp should set latency timer registers in pci 62 * configuration header 63 * 64 * Until this bug gets fixed in the obp, the following workaround should 65 * be enabled. 66 */ 67 uint_t px_set_latency_timer_register = 1; 68 69 /* 70 * The following driver parameters are defined as variables to allow 71 * patching for debugging and tuning. Flags that can be set on a per 72 * PBM basis are bit fields where the PBM device instance number maps 73 * to the bit position. 74 */ 75 uint_t px_mmu_error_intr_enable = (uint_t)-1; 76 uint_t px_rerun_disable = 0; 77 78 uint_t px_error_intr_enable = (uint_t)-1; 79 uint_t px_dwsync_disable = 0; 80 uint_t px_intsync_disable = 0; 81 82 uint_t px_intr_retry_intv = 5; /* for interrupt retry reg */ 83 uint8_t px_latency_timer = 0x40; /* for pci latency timer reg */ 84 uint_t px_panic_on_fatal_errors = 1; /* should be 1 at beta */ 85 uint_t px_thermal_intr_fatal = 1; /* thermal interrupts fatal */ 86 uint_t px_buserr_interrupt = 1; /* safari buserr interrupt */ 87 uint_t px_ctx_no_active_flush = 0; /* cannot handle active ctx flush */ 88 uint_t px_use_contexts = 1; 89 90 hrtime_t px_intrpend_timeout = 5ull * NANOSEC; /* 5 seconds in nanoseconds */ 91 92 uint64_t px_perr_fatal = -1ull; 93 uint64_t px_serr_fatal = -1ull; 94 uint64_t px_errtrig_pa = 0x0; 95 96 /* 97 * The following flag controls behavior of the ino handler routine 98 * when multiple interrupts are attached to a single ino. Typically 99 * this case would occur for the ino's assigned to the PCI bus slots 100 * with multi-function devices or bus bridges. 101 * 102 * Setting the flag to zero causes the ino handler routine to return 103 * after finding the first interrupt handler to claim the interrupt. 104 * 105 * Setting the flag to non-zero causes the ino handler routine to 106 * return after making one complete pass through the interrupt 107 * handlers. 108 */ 109 uint_t px_check_all_handlers = 1; 110 111 /* 112 * The following value is the number of consecutive unclaimed interrupts that 113 * will be tolerated for a particular ino_p before the interrupt is deemed to 114 * be jabbering and is blocked. 115 */ 116 uint_t px_unclaimed_intr_max = 20; 117 118 /* 119 * The following value will cause the nexus driver to block an ino after 120 * px_unclaimed_intr_max unclaimed interrupts have been seen. Setting this 121 * value to 0 will cause interrupts to never be blocked, no matter how many 122 * unclaimed interrupts are seen on a particular ino. 123 */ 124 uint_t px_unclaimed_intr_block = 1; 125 126 uint_t px_lock_tlb = 0; 127 128 uint64_t px_dvma_debug_on = 0; 129 uint64_t px_dvma_debug_off = 0; 130 uint32_t px_dvma_debug_rec = 512; 131 132 /* 133 * dvma address space allocation cache variables 134 */ 135 uint_t px_dvma_page_cache_entries = 0x200; /* # of chunks (1 << bits) */ 136 uint_t px_dvma_page_cache_clustsz = 0x8; /* # of pages per chunk */ 137 #ifdef PX_DMA_PROF 138 uint_t px_dvmaft_npages = 0; /* FT fail due npages */ 139 uint_t px_dvmaft_limit = 0; /* FT fail due limits */ 140 uint_t px_dvmaft_free = 0; /* FT free */ 141 uint_t px_dvmaft_success = 0; /* FT success */ 142 uint_t px_dvmaft_exhaust = 0; /* FT vmem fallback */ 143 uint_t px_dvma_vmem_alloc = 0; /* vmem alloc */ 144 uint_t px_dvma_vmem_xalloc = 0; /* vmem xalloc */ 145 uint_t px_dvma_vmem_xfree = 0; /* vmem xfree */ 146 uint_t px_dvma_vmem_free = 0; /* vmem free */ 147 #endif 148 uint_t px_disable_fdvma = 0; 149 uint_t px_mmu_ctx_lock_failure = 0; 150 151 /* 152 * This flag preserves prom MMU settings by copying prom TSB entries 153 * to corresponding kernel TSB entry locations. It should be removed 154 * after the interface properties from obp have become default. 155 */ 156 uint_t px_preserve_mmu_tsb = 1; 157 158 /* 159 * memory callback list id callback list for kmem_alloc failure clients 160 */ 161 uintptr_t px_kmem_clid = 0; 162 163 uint_t px_err_log_all = 0; 164 165 uint64_t px_tlu_ue_intr_mask = PX_ERR_EN_ALL; 166 uint64_t px_tlu_ue_log_mask = PX_ERR_EN_ALL; 167 uint64_t px_tlu_ue_count_mask = PX_ERR_EN_ALL; 168 169 uint64_t px_tlu_ce_intr_mask = PX_ERR_MASK_NONE; 170 uint64_t px_tlu_ce_log_mask = PX_ERR_MASK_NONE; 171 uint64_t px_tlu_ce_count_mask = PX_ERR_MASK_NONE; 172 173 uint64_t px_tlu_oe_intr_mask = PX_ERR_EN_ALL & ~0x800; 174 uint64_t px_tlu_oe_log_mask = PX_ERR_EN_ALL; 175 uint64_t px_tlu_oe_count_mask = PX_ERR_EN_ALL; 176 177 uint64_t px_mmu_intr_mask = PX_ERR_EN_ALL; 178 uint64_t px_mmu_log_mask = PX_ERR_EN_ALL; 179 uint64_t px_mmu_count_mask = PX_ERR_EN_ALL; 180 181 uint64_t px_imu_intr_mask = PX_ERR_EN_ALL; 182 uint64_t px_imu_log_mask = PX_ERR_EN_ALL; 183 uint64_t px_imu_count_mask = PX_ERR_EN_ALL; 184 185 uint64_t px_ilu_intr_mask = PX_ERR_EN_ALL; 186 uint64_t px_ilu_log_mask = PX_ERR_EN_ALL; 187 uint64_t px_ilu_count_mask = PX_ERR_EN_ALL; 188 189 uint64_t px_cb_intr_mask = PX_ERR_EN_ALL; 190 uint64_t px_cb_log_mask = PX_ERR_EN_ALL; 191 uint64_t px_cb_count_mask = PX_ERR_EN_ALL; 192 193 uint64_t px_lpul_intr_mask = PX_ERR_MASK_NONE; 194 uint64_t px_lpul_log_mask = PX_ERR_EN_ALL; 195 uint64_t px_lpul_count_mask = PX_ERR_EN_ALL; 196 197 uint64_t px_lpup_intr_mask = PX_ERR_MASK_NONE; 198 uint64_t px_lpup_log_mask = PX_ERR_EN_ALL; 199 uint64_t px_lpup_count_mask = PX_ERR_EN_ALL; 200 201 uint64_t px_lpur_intr_mask = PX_ERR_MASK_NONE; 202 uint64_t px_lpur_log_mask = PX_ERR_EN_ALL; 203 uint64_t px_lpur_count_mask = PX_ERR_EN_ALL; 204 205 uint64_t px_lpux_intr_mask = 0x50; /* mask all ? */ 206 uint64_t px_lpux_log_mask = PX_ERR_EN_ALL; 207 uint64_t px_lpux_count_mask = PX_ERR_EN_ALL; 208 209 uint64_t px_lpus_intr_mask = PX_ERR_MASK_NONE; /* mask all ? */ 210 uint64_t px_lpus_log_mask = PX_ERR_EN_ALL; 211 uint64_t px_lpus_count_mask = PX_ERR_EN_ALL; 212 213 uint64_t px_lpug_intr_mask = PX_ERR_MASK_NONE; 214 uint64_t px_lpug_log_mask = PX_ERR_EN_ALL; 215 uint64_t px_lpug_count_mask = PX_ERR_EN_ALL; 216 217 /* timeout in micro seconds for receiving PME_To_ACK */ 218 uint64_t px_pme_to_ack_timeout = PX_PME_TO_ACK_TIMEOUT; 219 220 /* PIL at which PME_To_ACK message interrupt is handled */ 221 uint32_t px_pwr_pil = PX_PWR_PIL; 222