1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * PCI Express PEC implementation: 28 * initialization 29 * Bus error interrupt handler 30 */ 31 32 #include <sys/types.h> 33 #include <sys/kmem.h> 34 #include <sys/spl.h> 35 #include <sys/sysmacros.h> 36 #include <sys/sunddi.h> 37 #include <sys/machsystm.h> /* ldphysio() */ 38 #include <sys/async.h> 39 #include <sys/ddi_impldefs.h> 40 #include <sys/ontrap.h> 41 #include <sys/membar.h> 42 #include "px_obj.h" 43 44 /*LINTLIBRARY*/ 45 46 extern uint_t px_ranges_phi_mask; 47 48 static uint_t px_pec_error_intr(caddr_t a); 49 static int px_pec_msg_add_intr(px_t *px_p); 50 static void px_pec_msg_rem_intr(px_t *px_p); 51 52 int 53 px_pec_attach(px_t *px_p) 54 { 55 px_pec_t *pec_p; 56 int i, len; 57 int nrange = px_p->px_ranges_length / sizeof (px_ranges_t); 58 dev_info_t *dip = px_p->px_dip; 59 px_ranges_t *rangep = px_p->px_ranges_p; 60 int ret; 61 62 /* 63 * Allocate a state structure for the PEC and cross-link it 64 * to its per px node state structure. 65 */ 66 pec_p = kmem_zalloc(sizeof (px_pec_t), KM_SLEEP); 67 px_p->px_pec_p = pec_p; 68 pec_p->pec_px_p = px_p; 69 70 len = snprintf(pec_p->pec_nameinst_str, 71 sizeof (pec_p->pec_nameinst_str), 72 "%s%d", NAMEINST(dip)); 73 pec_p->pec_nameaddr_str = pec_p->pec_nameinst_str + ++len; 74 (void) snprintf(pec_p->pec_nameaddr_str, 75 sizeof (pec_p->pec_nameinst_str) - len, 76 "%s@%s", NAMEADDR(dip)); 77 78 /* 79 * Add interrupt handlers to process correctable/fatal/non fatal 80 * PCIE messages. 81 */ 82 if ((ret = px_pec_msg_add_intr(px_p)) != DDI_SUCCESS) { 83 px_pec_msg_rem_intr(px_p); 84 return (ret); 85 } 86 87 /* 88 * Get this pec's mem32 and mem64 segments to determine whether 89 * a dma object originates from ths pec. i.e. dev to dev dma 90 */ 91 for (i = 0; i < nrange; i++, rangep++) { 92 uint64_t rng_addr, rng_size, *pfnbp, *pfnlp; 93 uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK; 94 95 switch (rng_type) { 96 case PCI_ADDR_MEM32: 97 pfnbp = &pec_p->pec_base32_pfn; 98 pfnlp = &pec_p->pec_last32_pfn; 99 break; 100 101 case PCI_ADDR_MEM64: 102 pfnbp = &pec_p->pec_base64_pfn; 103 pfnlp = &pec_p->pec_last64_pfn; 104 break; 105 106 case PCI_ADDR_CONFIG: 107 case PCI_ADDR_IO: 108 default: 109 continue; 110 } 111 rng_addr = (uint64_t)(rangep->parent_high & 112 px_ranges_phi_mask) << 32; 113 rng_addr |= (uint64_t)rangep->parent_low; 114 rng_size = (uint64_t)rangep->size_high << 32; 115 rng_size |= (uint64_t)rangep->size_low; 116 117 *pfnbp = mmu_btop(rng_addr); 118 *pfnlp = mmu_btop(rng_addr + rng_size); 119 } 120 121 /* 122 * This lock is for serializing safe acc calls. It is not associated 123 * with an iblock cookie. 124 */ 125 mutex_init(&pec_p->pec_pokefault_mutex, NULL, MUTEX_DRIVER, NULL); 126 127 return (DDI_SUCCESS); 128 } 129 130 void 131 px_pec_detach(px_t *px_p) 132 { 133 dev_info_t *dip = px_p->px_dip; 134 px_pec_t *pec_p = px_p->px_pec_p; 135 136 /* 137 * Free the pokefault mutex. 138 */ 139 DBG(DBG_DETACH, dip, "px_pec_detach:\n"); 140 mutex_destroy(&pec_p->pec_pokefault_mutex); 141 142 /* 143 * Remove interrupt handlers to process correctable/fatal/non fatal 144 * PCIE messages. 145 */ 146 px_pec_msg_rem_intr(px_p); 147 148 /* 149 * Free the pec state structure. 150 */ 151 kmem_free(pec_p, sizeof (px_pec_t)); 152 px_p->px_pec_p = NULL; 153 } 154 155 /* 156 * pec_msg_add_intr: 157 * 158 * Add interrupt handlers to process correctable/fatal/non fatal 159 * PCIE messages. 160 */ 161 static int 162 px_pec_msg_add_intr(px_t *px_p) 163 { 164 dev_info_t *dip = px_p->px_dip; 165 px_pec_t *pec_p = px_p->px_pec_p; 166 ddi_intr_handle_impl_t hdl; 167 int ret = DDI_SUCCESS; 168 169 DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_add_intr\n"); 170 171 /* Initialize handle */ 172 bzero(&hdl, sizeof (ddi_intr_handle_impl_t)); 173 hdl.ih_cb_func = (ddi_intr_handler_t *)px_err_fabric_intr; 174 hdl.ih_ver = DDI_INTR_VERSION; 175 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 176 hdl.ih_dip = dip; 177 178 /* Add correctable error message handler */ 179 hdl.ih_pri = PX_ERR_LOW_PIL; 180 181 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 182 MSG_REC, (msgcode_t)PCIE_CORR_MSG, -1, 183 &pec_p->pec_corr_msg_msiq_id)) != DDI_SUCCESS) { 184 DBG(DBG_MSG, px_p->px_dip, 185 "PCIE_CORR_MSG registration failed\n"); 186 return (DDI_FAILURE); 187 } 188 189 px_lib_msg_setmsiq(dip, PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 190 px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_VALID); 191 192 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 193 px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id), 194 PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC, 195 PCIE_CORR_MSG)) != DDI_SUCCESS) { 196 DBG(DBG_MSG, px_p->px_dip, 197 "PCIE_CORR_MSG update interrupt state failed\n"); 198 return (DDI_FAILURE); 199 } 200 201 /* Add non-fatal error message handler */ 202 hdl.ih_pri = PX_ERR_PIL; 203 204 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 205 MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, -1, 206 &pec_p->pec_non_fatal_msg_msiq_id)) != DDI_SUCCESS) { 207 DBG(DBG_MSG, px_p->px_dip, 208 "PCIE_NONFATAL_MSG registration failed\n"); 209 return (DDI_FAILURE); 210 } 211 212 px_lib_msg_setmsiq(dip, PCIE_NONFATAL_MSG, 213 pec_p->pec_non_fatal_msg_msiq_id); 214 px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, PCIE_MSG_VALID); 215 216 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 217 px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id), 218 PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC, 219 PCIE_NONFATAL_MSG)) != DDI_SUCCESS) { 220 DBG(DBG_MSG, px_p->px_dip, 221 "PCIE_NONFATAL_MSG update interrupt state failed\n"); 222 return (DDI_FAILURE); 223 } 224 225 /* Add fatal error message handler */ 226 hdl.ih_pri = PX_ERR_PIL; 227 228 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 229 MSG_REC, (msgcode_t)PCIE_FATAL_MSG, -1, 230 &pec_p->pec_fatal_msg_msiq_id)) != DDI_SUCCESS) { 231 DBG(DBG_MSG, px_p->px_dip, 232 "PCIE_FATAL_MSG registration failed\n"); 233 return (DDI_FAILURE); 234 } 235 236 px_lib_msg_setmsiq(dip, PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 237 px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_VALID); 238 239 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 240 px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), PX_ERR_PIL, 241 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) { 242 DBG(DBG_MSG, px_p->px_dip, 243 "PCIE_FATAL_MSG update interrupt state failed\n"); 244 return (DDI_FAILURE); 245 } 246 247 return (ret); 248 } 249 250 /* 251 * px_pec_msg_rem_intr: 252 * 253 * Remove interrupt handlers to process correctable/fatal/non fatal 254 * PCIE messages. For now, all these PCIe messages are mapped to 255 * same MSIQ. 256 */ 257 static void 258 px_pec_msg_rem_intr(px_t *px_p) 259 { 260 dev_info_t *dip = px_p->px_dip; 261 px_pec_t *pec_p = px_p->px_pec_p; 262 ddi_intr_handle_impl_t hdl; 263 264 DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_rem_intr: dip 0x%p\n", dip); 265 266 /* Initialize handle */ 267 bzero(&hdl, sizeof (ddi_intr_handle_impl_t)); 268 hdl.ih_ver = DDI_INTR_VERSION; 269 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 270 hdl.ih_dip = dip; 271 272 /* Remove correctable error message handler */ 273 if (pec_p->pec_corr_msg_msiq_id >= 0) { 274 px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_INVALID); 275 276 hdl.ih_pri = PX_ERR_LOW_PIL; 277 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 278 PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 279 280 (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 281 px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id), 282 PX_ERR_LOW_PIL, PX_INTR_STATE_DISABLE, MSG_REC, 283 PCIE_CORR_MSG); 284 285 pec_p->pec_corr_msg_msiq_id = (msiqid_t)-1; 286 } 287 288 /* Remove non-fatal error message handler */ 289 if (pec_p->pec_non_fatal_msg_msiq_id >= 0) { 290 px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, 291 PCIE_MSG_INVALID); 292 293 hdl.ih_pri = PX_ERR_PIL; 294 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 295 PCIE_NONFATAL_MSG, pec_p->pec_non_fatal_msg_msiq_id); 296 297 (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 298 px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id), 299 PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, 300 PCIE_NONFATAL_MSG); 301 302 pec_p->pec_non_fatal_msg_msiq_id = (msiqid_t)-1; 303 } 304 305 /* Remove fatal error message handler */ 306 if (pec_p->pec_fatal_msg_msiq_id >= 0) { 307 px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_INVALID); 308 309 hdl.ih_pri = PX_ERR_PIL; 310 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 311 PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 312 313 (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 314 px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), 315 PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG); 316 317 pec_p->pec_fatal_msg_msiq_id = (msiqid_t)-1; 318 } 319 } 320