xref: /titanic_51/usr/src/uts/sun4/io/px/px_msiq.c (revision ccbf80fa3b6bf6b986dca9037e5ad9d6c9f9fa65)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  * px_msiq.c
30  */
31 
32 #include <sys/types.h>
33 #include <sys/kmem.h>
34 #include <sys/conf.h>
35 #include <sys/ddi.h>
36 #include <sys/sunddi.h>
37 #include <sys/modctl.h>
38 #include <sys/disp.h>
39 #include <sys/stat.h>
40 #include <sys/ddi_impldefs.h>
41 #include "px_obj.h"
42 
43 static void px_msiq_get_props(px_t *px_p);
44 
45 /*
46  * px_msiq_attach()
47  */
48 int
49 px_msiq_attach(px_t *px_p)
50 {
51 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
52 	size_t		msiq_size;
53 	int		i, ret = DDI_SUCCESS;
54 
55 	DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_attach\n");
56 
57 	/*
58 	 * Check for all MSIQ related properties and
59 	 * save all information.
60 	 *
61 	 * Avaialble MSIQs and its properties.
62 	 */
63 	px_msiq_get_props(px_p);
64 
65 	/*
66 	 * 10% of available MSIQs are reserved for the PCIe messages.
67 	 * Around 90% of available MSIQs are reserved for the MSI/Xs.
68 	 */
69 	msiq_state_p->msiq_msg_qcnt = howmany(msiq_state_p->msiq_cnt, 10);
70 	msiq_state_p->msiq_msi_qcnt = msiq_state_p->msiq_cnt -
71 	    msiq_state_p->msiq_msg_qcnt;
72 
73 	msiq_state_p->msiq_1st_msi_qid = msiq_state_p->msiq_1st_msiq_id;
74 	msiq_state_p->msiq_next_msi_qid = msiq_state_p->msiq_1st_msi_qid;
75 
76 	msiq_state_p->msiq_1st_msg_qid = msiq_state_p->msiq_1st_msiq_id +
77 	    msiq_state_p->msiq_msi_qcnt;
78 	msiq_state_p->msiq_next_msg_qid = msiq_state_p->msiq_1st_msg_qid;
79 
80 	mutex_init(&msiq_state_p->msiq_mutex, NULL, MUTEX_DRIVER, NULL);
81 	msiq_state_p->msiq_p = kmem_zalloc(msiq_state_p->msiq_cnt *
82 	    sizeof (px_msiq_t), KM_SLEEP);
83 	msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t);
84 	msiq_state_p->msiq_buf_p = kmem_zalloc(msiq_state_p->msiq_cnt *
85 	    msiq_size, KM_SLEEP);
86 
87 	for (i = 0; i < msiq_state_p->msiq_cnt; i++) {
88 		msiq_state_p->msiq_p[i].msiq_id =
89 		    msiq_state_p->msiq_1st_msiq_id + i;
90 		msiq_state_p->msiq_p[i].msiq_state = MSIQ_STATE_FREE;
91 
92 		msiq_state_p->msiq_p[i].msiq_base_p = (msiqhead_t *)
93 		    ((caddr_t)msiq_state_p->msiq_buf_p + (i * msiq_size));
94 	}
95 
96 	if ((ret = px_lib_msiq_init(px_p->px_dip)) != DDI_SUCCESS)
97 		px_msiq_detach(px_p);
98 
99 	return (ret);
100 }
101 
102 /*
103  * px_msiq_detach()
104  */
105 void
106 px_msiq_detach(px_t *px_p)
107 {
108 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
109 
110 	DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_detach\n");
111 
112 	(void) px_lib_msiq_fini(px_p->px_dip);
113 	kmem_free(msiq_state_p->msiq_buf_p, msiq_state_p->msiq_cnt *
114 	    msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t));
115 
116 	mutex_destroy(&msiq_state_p->msiq_mutex);
117 	kmem_free(msiq_state_p->msiq_p,
118 	    msiq_state_p->msiq_cnt * sizeof (px_msiq_t));
119 
120 	bzero(&px_p->px_ib_p->ib_msiq_state, sizeof (px_msiq_state_t));
121 }
122 
123 /*
124  * px_msiq_resume()
125  */
126 void
127 px_msiq_resume(px_t *px_p)
128 {
129 	px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
130 	int		i;
131 
132 	for (i = 0; i < msiq_state_p->msiq_cnt; i++)
133 		(void) px_lib_msiq_gethead(px_p->px_dip, i,
134 		    &msiq_state_p->msiq_p[i].msiq_curr_head_idx);
135 }
136 
137 /*
138  * px_msiq_alloc()
139  */
140 int
141 px_msiq_alloc(px_t *px_p, msiq_rec_type_t rec_type, msiqid_t *msiq_id_p)
142 {
143 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
144 	msiqid_t	first_msiq_id, *next_msiq_index;
145 	uint_t		msiq_cnt;
146 	int		i;
147 
148 	DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_alloc\n");
149 
150 	mutex_enter(&msiq_state_p->msiq_mutex);
151 
152 	if (rec_type == MSG_REC) {
153 		msiq_cnt = msiq_state_p->msiq_msg_qcnt;
154 		first_msiq_id = msiq_state_p->msiq_1st_msg_qid;
155 		next_msiq_index = &msiq_state_p->msiq_next_msg_qid;
156 	} else {
157 		msiq_cnt = msiq_state_p->msiq_msi_qcnt;
158 		first_msiq_id = msiq_state_p->msiq_1st_msi_qid;
159 		next_msiq_index = &msiq_state_p->msiq_next_msi_qid;
160 	}
161 
162 	/* Allocate MSIQs */
163 	for (i = first_msiq_id; i < (first_msiq_id + msiq_cnt); i++) {
164 		if (msiq_state_p->msiq_p[i].msiq_state == MSIQ_STATE_FREE) {
165 			msiq_state_p->msiq_p[i].msiq_state = MSIQ_STATE_INUSE;
166 			break;
167 		}
168 	}
169 
170 	/*
171 	 * There are no free MSIQ.
172 	 * Use next available MSIQ.
173 	 */
174 	if (i >= (first_msiq_id + msiq_cnt))
175 		i = *next_msiq_index;
176 
177 	*msiq_id_p = msiq_state_p->msiq_p[i].msiq_id;
178 	DBG(DBG_MSIQ, px_p->px_dip,
179 	    "px_msiq_alloc: msiq_id 0x%x\n", *msiq_id_p);
180 
181 	(*next_msiq_index)++;
182 
183 	if (*next_msiq_index >= (first_msiq_id + msiq_cnt))
184 		*next_msiq_index = first_msiq_id;
185 
186 	mutex_exit(&msiq_state_p->msiq_mutex);
187 	return (DDI_SUCCESS);
188 }
189 
190 /*
191  * px_msiq_free()
192  */
193 int
194 px_msiq_free(px_t *px_p, msiqid_t msiq_id)
195 {
196 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
197 	int		i, ret = DDI_SUCCESS;
198 
199 	DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_free: msiq_id 0x%x", msiq_id);
200 
201 	mutex_enter(&msiq_state_p->msiq_mutex);
202 
203 	for (i = 0; i < msiq_state_p->msiq_cnt; i++) {
204 		if (msiq_state_p->msiq_p[i].msiq_id == msiq_id) {
205 			msiq_state_p->msiq_p[i].msiq_state = MSIQ_STATE_FREE;
206 			break;
207 		}
208 	}
209 
210 	if (i >= msiq_state_p->msiq_cnt) {
211 		DBG(DBG_MSIQ, px_p->px_dip,
212 		    "px_msiq_free: Invalid msiq_id 0x%x", msiq_id);
213 		ret = DDI_FAILURE;
214 	}
215 
216 	mutex_exit(&msiq_state_p->msiq_mutex);
217 	return (ret);
218 }
219 
220 /*
221  * px_msiqid_to_devino()
222  */
223 devino_t
224 px_msiqid_to_devino(px_t *px_p, msiqid_t msiq_id)
225 {
226 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
227 	devino_t	devino;
228 
229 	devino = msiq_state_p->msiq_1st_devino +
230 	    msiq_id - msiq_state_p->msiq_1st_msiq_id;
231 
232 	DBG(DBG_MSIQ, px_p->px_dip, "px_msiqid_to_devino: "
233 	    "msiq_id 0x%x devino 0x%x\n", msiq_id, devino);
234 
235 	return (devino);
236 }
237 
238 /*
239  * px_devino_to_msiqid()
240  */
241 msiqid_t
242 px_devino_to_msiqid(px_t *px_p, devino_t devino)
243 {
244 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
245 	msiqid_t	msiq_id;
246 
247 	msiq_id = msiq_state_p->msiq_1st_msiq_id +
248 	    devino - msiq_state_p->msiq_1st_devino;
249 
250 	DBG(DBG_MSIQ, px_p->px_dip, "px_devino_to_msiq: "
251 	    "devino 0x%x msiq_id 0x%x\n", devino, msiq_id);
252 
253 	return (msiq_id);
254 }
255 
256 /*
257  * px_msiq_get_props()
258  */
259 static void
260 px_msiq_get_props(px_t *px_p)
261 {
262 	px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
263 	int	ret = DDI_SUCCESS;
264 	int	length = sizeof (int);
265 	char	*valuep = NULL;
266 
267 	DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_get_props\n");
268 
269 	/* #msi-eqs */
270 	msiq_state_p->msiq_cnt = ddi_getprop(DDI_DEV_T_ANY, px_p->px_dip,
271 	    DDI_PROP_DONTPASS, "#msi-eqs", PX_DEFAULT_MSIQ_CNT);
272 
273 	DBG(DBG_MSIQ, px_p->px_dip, "obp: msiq_cnt=%d\n",
274 	    msiq_state_p->msiq_cnt);
275 
276 	/* msi-eq-size */
277 	msiq_state_p->msiq_rec_cnt = ddi_getprop(DDI_DEV_T_ANY, px_p->px_dip,
278 	    DDI_PROP_DONTPASS, "msi-eq-size", PX_DEFAULT_MSIQ_REC_CNT);
279 
280 	DBG(DBG_MSIQ, px_p->px_dip, "obp: msiq_rec_cnt=%d\n",
281 	    msiq_state_p->msiq_rec_cnt);
282 
283 	/* msi-eq-to-devino: msi-eq#, devino# fields */
284 	ret = ddi_prop_op(DDI_DEV_T_ANY, px_p->px_dip, PROP_LEN_AND_VAL_ALLOC,
285 	    DDI_PROP_DONTPASS, "msi-eq-to-devino", (caddr_t)&valuep,
286 	    &length);
287 
288 	if (ret == DDI_PROP_SUCCESS) {
289 		msiq_state_p->msiq_1st_msiq_id =
290 		    ((px_msi_eq_to_devino_t *)valuep)->msi_eq_no;
291 		msiq_state_p->msiq_1st_devino =
292 		    ((px_msi_eq_to_devino_t *)valuep)->devino_no;
293 		kmem_free(valuep, (size_t)length);
294 	} else {
295 		msiq_state_p->msiq_1st_msiq_id = PX_DEFAULT_MSIQ_1ST_MSIQ_ID;
296 		msiq_state_p->msiq_1st_devino = PX_DEFAULT_MSIQ_1ST_DEVINO;
297 	}
298 
299 	DBG(DBG_MSIQ, px_p->px_dip, "obp: msiq_1st_msiq_id=%d\n",
300 	    msiq_state_p->msiq_1st_msiq_id);
301 
302 	DBG(DBG_MSIQ, px_p->px_dip, "obp: msiq_1st_devino=%d\n",
303 	    msiq_state_p->msiq_1st_devino);
304 }
305