1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_IB_H 28 #define _SYS_PX_IB_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/ddi_subrdefs.h> 37 #include <sys/pci_tools.h> 38 39 typedef struct px_ib_ino_info px_ib_ino_info_t; 40 41 /* 42 * interrupt block soft state structure: 43 * 44 * Each px node may share an interrupt block structure with its peer 45 * node or have its own private interrupt block structure. 46 */ 47 typedef struct px_ib px_ib_t; 48 struct px_ib { 49 px_t *ib_px_p; /* link back to px soft state */ 50 px_ib_ino_info_t *ib_ino_lst; /* ino link list */ 51 kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 52 kmutex_t ib_intr_lock; /* lock for internal intr */ 53 54 px_msiq_state_t ib_msiq_state; /* MSIQ soft state */ 55 px_msi_state_t ib_msi_state; /* MSI soft state */ 56 }; 57 58 /* 59 * The following structure represents an interrupt entry for an INO. 60 */ 61 typedef struct px_ih { 62 dev_info_t *ih_dip; /* devinfo structure */ 63 uint32_t ih_inum; /* interrupt number for this device */ 64 uint_t (*ih_handler)(); /* interrupt handler */ 65 caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 66 caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 67 ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 68 uint_t ih_intr_state; /* Only used for fixed interrupts */ 69 msiq_rec_type_t ih_rec_type; /* MSI or PCIe record type */ 70 msgcode_t ih_msg_code; /* MSI number or PCIe message code */ 71 struct px_ih *ih_next; /* next entry in list */ 72 uint64_t ih_ticks; /* ticks spent in this handler */ 73 uint64_t ih_nsec; /* nsec spent in this handler */ 74 kstat_t *ih_ksp; 75 struct px_ib_ino_info *ih_ino_p; /* only for use by kstat */ 76 } px_ih_t; 77 78 /* Only used for fixed or legacy interrupts */ 79 #define PX_INTR_STATE_DISABLE 0 /* disabled */ 80 #define PX_INTR_STATE_ENABLE 1 /* enabled */ 81 82 /* 83 * ino structure : one per each ino with interrupt registered 84 */ 85 struct px_ib_ino_info { 86 devino_t ino_ino; /* INO number - 8 bit */ 87 sysino_t ino_sysino; /* Virtual inumber */ 88 uint16_t ino_ih_size; /* size of the px intrspec list */ 89 px_ih_t *ino_ih_head; /* intr spec (part of ppd) list head */ 90 px_ih_t *ino_ih_tail; /* intr spec (part of ppd) list tail */ 91 px_ih_t *ino_ih_start; /* starting point in intr spec list */ 92 px_ib_t *ino_ib_p; /* link back to interrupt block state */ 93 uint32_t ino_pil; /* PIL for this ino */ 94 uint_t ino_unclaimed; /* number of unclaimed interrupts */ 95 clock_t ino_spurintr_begin; /* begin time of spurious intr */ 96 cpuid_t ino_cpuid; /* cpu that ino is targeting */ 97 int32_t ino_intr_weight; /* intr wt of devices sharing ino */ 98 px_msiq_t *ino_msiq_p; /* Pointer to MSIQ used */ 99 struct px_ib_ino_info *ino_next; 100 }; 101 102 #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 103 #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 104 105 #define PX_INTR_ENABLE(dip, sysino, cpuid) \ 106 (void) px_lib_intr_settarget(dip, sysino, cpuid); \ 107 (void) px_lib_intr_setstate(dip, sysino, INTR_IDLE_STATE); \ 108 (void) px_lib_intr_setvalid(dip, sysino, INTR_VALID); 109 110 #define PX_INTR_DISABLE(dip, sysino) \ 111 (void) px_lib_intr_setvalid(dip, sysino, INTR_NOTVALID); 112 113 extern int px_ib_attach(px_t *px_p); 114 extern void px_ib_detach(px_t *px_p); 115 extern void px_ib_intr_enable(px_t *px_p, cpuid_t cpuid, devino_t ino); 116 extern void px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait); 117 extern void px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino, 118 boolean_t wait_flag); 119 120 extern px_ib_ino_info_t *px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num); 121 extern px_ib_ino_info_t *px_ib_new_ino(px_ib_t *ib_p, devino_t ino_num, 122 px_ih_t *ih_p); 123 extern void px_ib_delete_ino(px_ib_t *ib_p, px_ib_ino_info_t *ino_p); 124 extern void px_ib_free_ino_all(px_ib_t *ib_p); 125 extern int px_ib_ino_add_intr(px_t *px_p, px_ib_ino_info_t *ino_p, 126 px_ih_t *ih_p); 127 extern int px_ib_ino_rem_intr(px_t *px_p, px_ib_ino_info_t *ino_p, 128 px_ih_t *ih_p); 129 extern px_ih_t *px_ib_ino_locate_intr(px_ib_ino_info_t *ino_p, dev_info_t *dip, 130 uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code); 131 extern px_ih_t *px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum, 132 uint_t (*int_handler)(caddr_t int_handler_arg1, 133 caddr_t int_handler_arg2), caddr_t int_handler_arg1, 134 caddr_t int_handler_arg2, msiq_rec_type_t rec_type, msgcode_t msg_code); 135 extern void px_ib_free_ih(px_ih_t *ih_p); 136 extern int px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum, 137 devino_t ino, uint_t new_intr_state); 138 extern uint8_t pxtool_ib_get_ino_devs(px_t *px_p, uint32_t ino, 139 uint8_t *devs_ret, pcitool_intr_dev_t *devs); 140 extern void px_ib_log_new_cpu(px_ib_t *ib_p, uint32_t old_cpu_id, 141 uint32_t new_cpu_id, uint32_t ino); 142 143 144 #ifdef __cplusplus 145 } 146 #endif 147 148 #endif /* _SYS_PX_IB_H */ 149