1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PX Fault Management Architecture 30 */ 31 #include <sys/types.h> 32 #include <sys/sunndi.h> 33 #include <sys/sunddi.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/fm/util.h> 36 #include <sys/membar.h> 37 #include "px_obj.h" 38 39 #define PX_PCIE_PANIC_BITS \ 40 (PCIE_AER_UCE_DLP | PCIE_AER_UCE_FCP | PCIE_AER_UCE_TO | \ 41 PCIE_AER_UCE_RO | PCIE_AER_UCE_MTLP | PCIE_AER_UCE_ECRC | \ 42 PCIE_AER_UCE_UR) 43 #define PX_PCIE_NO_PANIC_BITS \ 44 (PCIE_AER_UCE_TRAINING | PCIE_AER_UCE_SD | PCIE_AER_UCE_CA | \ 45 PCIE_AER_UCE_UC) 46 47 static void px_err_fill_pfd(dev_info_t *rpdip, px_err_pcie_t *regs); 48 static int px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, 49 px_err_pcie_t *regs); 50 51 #if defined(DEBUG) 52 static void px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs, int severity); 53 #else /* DEBUG */ 54 #define px_pcie_log 0 && 55 #endif /* DEBUG */ 56 57 /* external functions */ 58 extern int pci_xcap_locate(ddi_acc_handle_t h, uint16_t id, uint16_t *base_p); 59 extern int pci_lcap_locate(ddi_acc_handle_t h, uint8_t id, uint16_t *base_p); 60 61 /* 62 * Initialize px FMA support 63 */ 64 int 65 px_fm_attach(px_t *px_p) 66 { 67 px_p->px_fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 68 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 69 70 /* 71 * Initialize pci_target_queue for FMA handling of 72 * pci errors. 73 */ 74 pci_targetq_init(); 75 76 /* 77 * check parents' capability 78 */ 79 ddi_fm_init(px_p->px_dip, &px_p->px_fm_cap, &px_p->px_fm_ibc); 80 81 /* 82 * parents need to be ereport and error handling capable 83 */ 84 ASSERT(px_p->px_fm_cap && 85 (DDI_FM_ERRCB_CAPABLE | DDI_FM_EREPORT_CAPABLE)); 86 87 /* 88 * Initialize lock to synchronize fabric error handling 89 */ 90 mutex_init(&px_p->px_fm_mutex, NULL, MUTEX_DRIVER, 91 (void *)px_p->px_fm_ibc); 92 93 /* 94 * register error callback in parent 95 */ 96 ddi_fm_handler_register(px_p->px_dip, px_fm_callback, px_p); 97 98 return (DDI_SUCCESS); 99 } 100 101 /* 102 * Deregister FMA 103 */ 104 void 105 px_fm_detach(px_t *px_p) 106 { 107 ddi_fm_handler_unregister(px_p->px_dip); 108 mutex_destroy(&px_p->px_fm_mutex); 109 ddi_fm_fini(px_p->px_dip); 110 } 111 112 /* 113 * Function used to setup access functions depending on level of desired 114 * protection. 115 */ 116 void 117 px_fm_acc_setup(ddi_map_req_t *mp, dev_info_t *rdip) 118 { 119 uchar_t fflag; 120 ddi_acc_hdl_t *hp; 121 ddi_acc_impl_t *ap; 122 123 hp = mp->map_handlep; 124 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 125 fflag = ap->ahi_common.ah_acc.devacc_attr_access; 126 127 if (mp->map_op == DDI_MO_MAP_LOCKED) { 128 ndi_fmc_insert(rdip, ACC_HANDLE, (void *)hp, NULL); 129 switch (fflag) { 130 case DDI_FLAGERR_ACC: 131 ap->ahi_get8 = i_ddi_prot_get8; 132 ap->ahi_get16 = i_ddi_prot_get16; 133 ap->ahi_get32 = i_ddi_prot_get32; 134 ap->ahi_get64 = i_ddi_prot_get64; 135 ap->ahi_put8 = i_ddi_prot_put8; 136 ap->ahi_put16 = i_ddi_prot_put16; 137 ap->ahi_put32 = i_ddi_prot_put32; 138 ap->ahi_put64 = i_ddi_prot_put64; 139 ap->ahi_rep_get8 = i_ddi_prot_rep_get8; 140 ap->ahi_rep_get16 = i_ddi_prot_rep_get16; 141 ap->ahi_rep_get32 = i_ddi_prot_rep_get32; 142 ap->ahi_rep_get64 = i_ddi_prot_rep_get64; 143 ap->ahi_rep_put8 = i_ddi_prot_rep_put8; 144 ap->ahi_rep_put16 = i_ddi_prot_rep_put16; 145 ap->ahi_rep_put32 = i_ddi_prot_rep_put32; 146 ap->ahi_rep_put64 = i_ddi_prot_rep_put64; 147 break; 148 case DDI_CAUTIOUS_ACC : 149 ap->ahi_get8 = i_ddi_caut_get8; 150 ap->ahi_get16 = i_ddi_caut_get16; 151 ap->ahi_get32 = i_ddi_caut_get32; 152 ap->ahi_get64 = i_ddi_caut_get64; 153 ap->ahi_put8 = i_ddi_caut_put8; 154 ap->ahi_put16 = i_ddi_caut_put16; 155 ap->ahi_put32 = i_ddi_caut_put32; 156 ap->ahi_put64 = i_ddi_caut_put64; 157 ap->ahi_rep_get8 = i_ddi_caut_rep_get8; 158 ap->ahi_rep_get16 = i_ddi_caut_rep_get16; 159 ap->ahi_rep_get32 = i_ddi_caut_rep_get32; 160 ap->ahi_rep_get64 = i_ddi_caut_rep_get64; 161 ap->ahi_rep_put8 = i_ddi_caut_rep_put8; 162 ap->ahi_rep_put16 = i_ddi_caut_rep_put16; 163 ap->ahi_rep_put32 = i_ddi_caut_rep_put32; 164 ap->ahi_rep_put64 = i_ddi_caut_rep_put64; 165 break; 166 default: 167 break; 168 } 169 } else if (mp->map_op == DDI_MO_UNMAP) { 170 ndi_fmc_remove(rdip, ACC_HANDLE, (void *)hp); 171 } 172 } 173 174 /* 175 * Function used to initialize FMA for our children nodes. Called 176 * through pci busops when child node calls ddi_fm_init. 177 */ 178 /*ARGSUSED*/ 179 int 180 px_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 181 ddi_iblock_cookie_t *ibc_p) 182 { 183 px_t *px_p = DIP_TO_STATE(dip); 184 185 ASSERT(ibc_p != NULL); 186 *ibc_p = px_p->px_fm_ibc; 187 188 return (px_p->px_fm_cap); 189 } 190 191 /* 192 * lock access for exclusive PCIe access 193 */ 194 void 195 px_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle) 196 { 197 px_pec_t *pec_p = ((px_t *)DIP_TO_STATE(dip))->px_pec_p; 198 199 /* 200 * Exclusive access has been used for cautious put/get, 201 * Both utilize i_ddi_ontrap which, on sparcv9, implements 202 * similar protection as what on_trap() does, and which calls 203 * membar #Sync to flush out all cpu deferred errors 204 * prior to get/put operation, so here we're not calling 205 * membar #Sync - a difference from what's in pci_bus_enter(). 206 */ 207 mutex_enter(&pec_p->pec_pokefault_mutex); 208 pec_p->pec_acc_hdl = handle; 209 } 210 211 /* 212 * unlock access for exclusive PCIe access 213 */ 214 /* ARGSUSED */ 215 void 216 px_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle) 217 { 218 px_t *px_p = DIP_TO_STATE(dip); 219 px_pec_t *pec_p = px_p->px_pec_p; 220 221 pec_p->pec_acc_hdl = NULL; 222 mutex_exit(&pec_p->pec_pokefault_mutex); 223 } 224 225 226 /* 227 * PCI error callback which is registered with our parent to call 228 * for PCIe logging when the CPU traps due to PCIe Uncorrectable Errors 229 * and PCI BERR/TO/UE on IO Loads. 230 */ 231 /*ARGSUSED*/ 232 int 233 px_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data) 234 { 235 dev_info_t *pdip = ddi_get_parent(dip); 236 px_t *px_p = (px_t *)impl_data; 237 int i, acc_type = 0; 238 int lookup, rc_err, fab_err = PF_NO_PANIC; 239 uint32_t addr, addr_high, addr_low; 240 pcie_req_id_t bdf; 241 px_ranges_t *ranges_p; 242 int range_len; 243 244 /* 245 * If the current thread already owns the px_fm_mutex, then we 246 * have encountered an error while processing a previous 247 * error. Attempting to take the mutex again will cause the 248 * system to deadlock. 249 */ 250 if (px_p->px_fm_mutex_owner == curthread) 251 return (DDI_FM_FATAL); 252 253 i_ddi_fm_handler_exit(pdip); 254 mutex_enter(&px_p->px_fm_mutex); 255 px_p->px_fm_mutex_owner = curthread; 256 257 addr_high = (uint32_t)((uint64_t)derr->fme_bus_specific >> 32); 258 addr_low = (uint32_t)((uint64_t)derr->fme_bus_specific); 259 260 /* 261 * Make sure this failed load came from this PCIe port. Check by 262 * matching the upper 32 bits of the address with the ranges property. 263 */ 264 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 265 i = 0; 266 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 267 if (ranges_p->parent_high == addr_high) { 268 switch (ranges_p->child_high & PCI_ADDR_MASK) { 269 case PCI_ADDR_CONFIG: 270 acc_type = PF_CFG_ADDR; 271 addr = NULL; 272 bdf = (pcie_req_id_t)(addr_low >> 12); 273 break; 274 case PCI_ADDR_MEM32: 275 acc_type = PF_DMA_ADDR; 276 addr = addr_low; 277 bdf = NULL; 278 break; 279 } 280 break; 281 } 282 } 283 284 /* This address doesn't belong to this leaf, just return with OK */ 285 if (!acc_type) { 286 px_p->px_fm_mutex_owner = NULL; 287 mutex_exit(&px_p->px_fm_mutex); 288 i_ddi_fm_handler_enter(pdip); 289 return (DDI_FM_OK); 290 } 291 292 rc_err = px_err_cmn_intr(px_p, derr, PX_TRAP_CALL, PX_FM_BLOCK_ALL); 293 lookup = pf_hdl_lookup(dip, derr->fme_ena, acc_type, addr, bdf); 294 295 if (!px_lib_is_in_drain_state(px_p)) { 296 /* 297 * This is to ensure that device corresponding to the addr of 298 * the failed PIO/CFG load gets scanned. 299 */ 300 px_rp_en_q(px_p, bdf, addr, 301 (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)); 302 fab_err = pf_scan_fabric(dip, derr, px_p->px_dq_p, 303 &px_p->px_dq_tail); 304 } 305 306 px_p->px_fm_mutex_owner = NULL; 307 mutex_exit(&px_p->px_fm_mutex); 308 i_ddi_fm_handler_enter(pdip); 309 310 if ((rc_err & (PX_PANIC | PX_PROTECTED)) || (fab_err & PF_PANIC) || 311 (lookup == PF_HDL_NOTFOUND)) 312 return (DDI_FM_FATAL); 313 else if ((rc_err == PX_NO_ERROR) && (fab_err == PF_NO_ERROR)) 314 return (DDI_FM_OK); 315 316 return (DDI_FM_NONFATAL); 317 } 318 319 /* 320 * px_err_fabric_intr: 321 * Interrupt handler for PCIE fabric block. 322 * o lock 323 * o create derr 324 * o px_err_cmn_intr(leaf, with jbc) 325 * o send ereport(fire fmri, derr, payload = BDF) 326 * o dispatch (leaf) 327 * o unlock 328 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 329 */ 330 /* ARGSUSED */ 331 uint_t 332 px_err_fabric_intr(px_t *px_p, msgcode_t msg_code, pcie_req_id_t rid) 333 { 334 dev_info_t *rpdip = px_p->px_dip; 335 int rc_err, fab_err = PF_NO_PANIC; 336 ddi_fm_error_t derr; 337 338 mutex_enter(&px_p->px_fm_mutex); 339 px_p->px_fm_mutex_owner = curthread; 340 341 /* Create the derr */ 342 bzero(&derr, sizeof (ddi_fm_error_t)); 343 derr.fme_version = DDI_FME_VERSION; 344 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 345 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 346 347 /* Ensure that the rid of the fabric message will get scanned. */ 348 px_rp_en_q(px_p, rid, NULL, NULL); 349 350 rc_err = px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_PCIE); 351 352 /* call rootport dispatch */ 353 if (!px_lib_is_in_drain_state(px_p)) { 354 fab_err = pf_scan_fabric(rpdip, &derr, px_p->px_dq_p, 355 &px_p->px_dq_tail); 356 } 357 358 px_p->px_fm_mutex_owner = NULL; 359 mutex_exit(&px_p->px_fm_mutex); 360 361 px_err_panic(rc_err, PX_RC, fab_err); 362 363 return (DDI_INTR_CLAIMED); 364 } 365 366 /* 367 * px_err_safeacc_check: 368 * Check to see if a peek/poke and cautious access is currently being 369 * done on a particular leaf. 370 * 371 * Safe access reads induced fire errors will be handled by cpu trap handler 372 * which will call px_fm_callback() which calls this function. In that 373 * case, the derr fields will be set by trap handler with the correct values. 374 * 375 * Safe access writes induced errors will be handled by px interrupt 376 * handlers, this function will fill in the derr fields. 377 * 378 * If a cpu trap does occur, it will quiesce all other interrupts allowing 379 * the cpu trap error handling to finish before Fire receives an interrupt. 380 * 381 * If fire does indeed have an error when a cpu trap occurs as a result of 382 * a safe access, a trap followed by a Mondo/Fabric interrupt will occur. 383 * In which case derr will be initialized as "UNEXPECTED" by the interrupt 384 * handler and this function will need to find if this error occured in the 385 * middle of a safe access operation. 386 * 387 * @param px_p leaf in which to check access 388 * @param derr fm err data structure to be updated 389 */ 390 void 391 px_err_safeacc_check(px_t *px_p, ddi_fm_error_t *derr) 392 { 393 px_pec_t *pec_p = px_p->px_pec_p; 394 int acctype = pec_p->pec_safeacc_type; 395 396 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 397 398 if (derr->fme_flag != DDI_FM_ERR_UNEXPECTED) { 399 return; 400 } 401 402 /* safe access checking */ 403 switch (acctype) { 404 case DDI_FM_ERR_EXPECTED: 405 /* 406 * cautious access protection, protected from all err. 407 */ 408 ddi_fm_acc_err_get(pec_p->pec_acc_hdl, derr, 409 DDI_FME_VERSION); 410 derr->fme_flag = acctype; 411 derr->fme_acc_handle = pec_p->pec_acc_hdl; 412 break; 413 case DDI_FM_ERR_POKE: 414 /* 415 * ddi_poke protection, check nexus and children for 416 * expected errors. 417 */ 418 membar_sync(); 419 derr->fme_flag = acctype; 420 break; 421 case DDI_FM_ERR_PEEK: 422 derr->fme_flag = acctype; 423 break; 424 } 425 } 426 427 /* 428 * Suggest panic if any EQ (except CE q) has overflown. 429 */ 430 int 431 px_err_check_eq(dev_info_t *dip) 432 { 433 px_t *px_p = DIP_TO_STATE(dip); 434 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 435 px_pec_t *pec_p = px_p->px_pec_p; 436 msiqid_t eq_no = msiq_state_p->msiq_1st_msiq_id; 437 pci_msiq_state_t msiq_state; 438 int i; 439 440 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 441 if (i + eq_no == pec_p->pec_corr_msg_msiq_id) /* skip CE q */ 442 continue; 443 if ((px_lib_msiq_getstate(dip, i + eq_no, &msiq_state) != 444 DDI_SUCCESS) || msiq_state == PCI_MSIQ_STATE_ERROR) 445 return (PX_PANIC); 446 } 447 return (PX_NO_PANIC); 448 } 449 450 static void 451 px_err_fill_pfd(dev_info_t *rpdip, px_err_pcie_t *regs) 452 { 453 px_t *px_p = DIP_TO_STATE(rpdip); 454 pf_data_t pf_data = {0}; 455 pcie_req_id_t fault_bdf = 0; 456 uint32_t fault_addr = 0; 457 uint16_t s_status = 0; 458 459 pf_data.rp_bdf = px_p->px_bdf; 460 461 /* 462 * set RC s_status in PCI term to coordinate with downstream fabric 463 * errors ananlysis. 464 */ 465 if (regs->primary_ue & PCIE_AER_UCE_UR) 466 s_status = PCI_STAT_R_MAST_AB; 467 if (regs->primary_ue & PCIE_AER_UCE_CA) 468 s_status = PCI_STAT_R_TARG_AB; 469 if (regs->primary_ue & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_ECRC)) 470 s_status = PCI_STAT_PERROR; 471 472 if (regs->primary_ue & (PCIE_AER_UCE_UR | PCIE_AER_UCE_CA)) { 473 pf_data.aer_h0 = regs->rx_hdr1; 474 pf_data.aer_h1 = regs->rx_hdr2; 475 pf_data.aer_h2 = regs->rx_hdr3; 476 pf_data.aer_h3 = regs->rx_hdr4; 477 478 pf_tlp_decode(rpdip, &pf_data, &fault_bdf, NULL, NULL); 479 } else if (regs->primary_ue & PCIE_AER_UCE_PTLP) { 480 pcie_tlp_hdr_t *tlp_p; 481 482 pf_data.aer_h0 = regs->rx_hdr1; 483 pf_data.aer_h1 = regs->rx_hdr2; 484 pf_data.aer_h2 = regs->rx_hdr3; 485 pf_data.aer_h3 = regs->rx_hdr4; 486 487 tlp_p = (pcie_tlp_hdr_t *)&pf_data.aer_h0; 488 if (tlp_p->type == PCIE_TLP_TYPE_CPL) 489 pf_tlp_decode(rpdip, &pf_data, &fault_bdf, NULL, NULL); 490 491 pf_data.aer_h0 = regs->tx_hdr1; 492 pf_data.aer_h1 = regs->tx_hdr2; 493 pf_data.aer_h2 = regs->tx_hdr3; 494 pf_data.aer_h3 = regs->tx_hdr4; 495 496 pf_tlp_decode(rpdip, &pf_data, NULL, &fault_addr, NULL); 497 } 498 499 px_rp_en_q(px_p, fault_bdf, fault_addr, s_status); 500 } 501 502 int 503 px_err_check_pcie(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) 504 { 505 uint32_t ce_reg, ue_reg; 506 int err = PX_NO_ERROR; 507 508 ce_reg = regs->ce_reg; 509 if (ce_reg) 510 err |= (ce_reg & px_fabric_die_rc_ce) ? PX_PANIC : PX_NO_ERROR; 511 512 ue_reg = regs->ue_reg; 513 if (!ue_reg) 514 goto done; 515 516 if (ue_reg & PCIE_AER_UCE_PTLP) 517 err |= px_pcie_ptlp(dip, derr, regs); 518 519 if (ue_reg & PX_PCIE_PANIC_BITS) 520 err |= PX_PANIC; 521 522 if (ue_reg & PX_PCIE_NO_PANIC_BITS) 523 err |= PX_NO_PANIC; 524 525 /* Scan the fabric to clean up error bits, for the following errors. */ 526 if (ue_reg & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_CA | PCIE_AER_UCE_UR)) 527 px_err_fill_pfd(dip, regs); 528 done: 529 px_pcie_log(dip, regs, err); 530 return (err); 531 } 532 533 #if defined(DEBUG) 534 static void 535 px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs, int severity) 536 { 537 DBG(DBG_ERR_INTR, dip, 538 "A PCIe RC error has occured with a severity of \"%s\"\n" 539 "\tCE: 0x%x UE: 0x%x Primary UE: 0x%x\n" 540 "\tTX Hdr: 0x%x 0x%x 0x%x 0x%x\n\tRX Hdr: 0x%x 0x%x 0x%x 0x%x\n", 541 (severity & PX_PANIC) ? "PANIC" : "NO PANIC", regs->ce_reg, 542 regs->ue_reg, regs->primary_ue, regs->tx_hdr1, regs->tx_hdr2, 543 regs->tx_hdr3, regs->tx_hdr4, regs->rx_hdr1, regs->rx_hdr2, 544 regs->rx_hdr3, regs->rx_hdr4); 545 } 546 #endif /* DEBUG */ 547 548 /* 549 * look through poisoned TLP cases and suggest panic/no panic depend on 550 * handle lookup. 551 */ 552 static int 553 px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) 554 { 555 px_t *px_p = DIP_TO_STATE(dip); 556 pf_data_t pf_data; 557 pcie_req_id_t bdf; 558 uint32_t addr, trans_type; 559 int tlp_sts, tlp_cmd; 560 int sts = PF_HDL_NOTFOUND; 561 562 if (regs->primary_ue != PCIE_AER_UCE_PTLP) 563 return (PX_PANIC); 564 565 if (!regs->rx_hdr1) 566 goto done; 567 568 pf_data.rp_bdf = px_p->px_bdf; 569 pf_data.aer_h0 = regs->rx_hdr1; 570 pf_data.aer_h1 = regs->rx_hdr2; 571 pf_data.aer_h2 = regs->rx_hdr3; 572 pf_data.aer_h3 = regs->rx_hdr4; 573 574 tlp_sts = pf_tlp_decode(dip, &pf_data, &bdf, &addr, &trans_type); 575 tlp_cmd = ((pcie_tlp_hdr_t *)(&pf_data.aer_h0))->type; 576 577 if (tlp_sts == DDI_FAILURE) 578 goto done; 579 580 switch (tlp_cmd) { 581 case PCIE_TLP_TYPE_CPL: 582 case PCIE_TLP_TYPE_CPLLK: 583 /* 584 * Usually a PTLP is a CPL with data. Grab the completer BDF 585 * from the RX TLP, and the original address from the TX TLP. 586 */ 587 if (regs->tx_hdr1) { 588 pf_data.aer_h0 = regs->tx_hdr1; 589 pf_data.aer_h1 = regs->tx_hdr2; 590 pf_data.aer_h2 = regs->tx_hdr3; 591 pf_data.aer_h3 = regs->tx_hdr4; 592 593 sts = pf_tlp_decode(dip, &pf_data, NULL, &addr, 594 &trans_type); 595 } /* FALLTHRU */ 596 case PCIE_TLP_TYPE_IO: 597 case PCIE_TLP_TYPE_MEM: 598 case PCIE_TLP_TYPE_MEMLK: 599 sts = pf_hdl_lookup(dip, derr->fme_ena, trans_type, addr, bdf); 600 break; 601 default: 602 sts = PF_HDL_NOTFOUND; 603 } 604 done: 605 return (sts == PF_HDL_NOTFOUND ? PX_PANIC : PX_NO_PANIC); 606 } 607 608 /* 609 * This function appends a pf_data structure to the error q which is used later 610 * during PCIe fabric scan. It signifies: 611 * o errs rcvd in RC, that may have been propagated to/from the fabric 612 * o the fabric scan code should scan the device path of fault bdf/addr 613 * 614 * fault_bdf: The bdf that caused the fault, which may have error bits set. 615 * fault_addr: The PIO addr that caused the fault, such as failed PIO, but not 616 * failed DMAs. 617 * s_status: Secondary Status equivalent to why the fault occured. 618 * (ie S-TA/MA, R-TA) 619 * Either the fault bdf or addr may be NULL, but not both. 620 */ 621 int px_foo = 0; 622 void 623 px_rp_en_q(px_t *px_p, pcie_req_id_t fault_bdf, uint32_t fault_addr, 624 uint16_t s_status) 625 { 626 pf_data_t pf_data = {0}; 627 628 if (!fault_bdf && !fault_addr) 629 return; 630 631 pf_data.dev_type = PCIE_PCIECAP_DEV_TYPE_ROOT; 632 if (px_foo) { 633 pf_data.fault_bdf = px_foo; 634 px_foo = 0; 635 } else 636 pf_data.fault_bdf = fault_bdf; 637 638 pf_data.bdf = px_p->px_bdf; 639 pf_data.rp_bdf = px_p->px_bdf; 640 pf_data.fault_addr = fault_addr; 641 pf_data.s_status = s_status; 642 pf_data.send_erpt = PF_SEND_ERPT_NO; 643 644 (void) pf_en_dq(&pf_data, px_p->px_dq_p, &px_p->px_dq_tail, -1); 645 } 646 647 /* 648 * Panic if the err tunable is set and that we are not already in the middle 649 * of panic'ing. 650 */ 651 #define MSZ (sizeof (fm_msg) -strlen(fm_msg) - 1) 652 void 653 px_err_panic(int err, int msg, int fab_err) 654 { 655 char fm_msg[96] = ""; 656 int ferr = PX_NO_ERROR; 657 658 if (panicstr) 659 return; 660 661 if (!(err & px_die)) 662 goto fabric; 663 if (msg & PX_RC) 664 (void) strncat(fm_msg, px_panic_rc_msg, MSZ); 665 if (msg & PX_RP) 666 (void) strncat(fm_msg, px_panic_rp_msg, MSZ); 667 if (msg & PX_HB) 668 (void) strncat(fm_msg, px_panic_hb_msg, MSZ); 669 670 fabric: 671 if (fab_err & PF_PANIC) 672 ferr = PX_PANIC; 673 if (fab_err & ~(PF_PANIC | PF_NO_ERROR)) 674 ferr = PX_NO_PANIC; 675 if (ferr & px_die) { 676 if (strlen(fm_msg)) 677 (void) strncat(fm_msg, " and", MSZ); 678 (void) strncat(fm_msg, px_panic_fab_msg, MSZ); 679 } 680 681 if (strlen(fm_msg)) 682 fm_panic("Fatal error has occured in:%s.", fm_msg); 683 } 684