1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * PX Fault Management Architecture 28 */ 29 #include <sys/types.h> 30 #include <sys/sunndi.h> 31 #include <sys/sunddi.h> 32 #include <sys/fm/protocol.h> 33 #include <sys/fm/util.h> 34 #include <sys/fm/io/pci.h> 35 #include <sys/membar.h> 36 #include "px_obj.h" 37 38 extern uint_t px_ranges_phi_mask; 39 40 #define PX_PCIE_PANIC_BITS \ 41 (PCIE_AER_UCE_DLP | PCIE_AER_UCE_FCP | PCIE_AER_UCE_TO | \ 42 PCIE_AER_UCE_RO | PCIE_AER_UCE_MTLP | PCIE_AER_UCE_ECRC) 43 #define PX_PCIE_NO_PANIC_BITS \ 44 (PCIE_AER_UCE_TRAINING | PCIE_AER_UCE_SD | PCIE_AER_UCE_CA | \ 45 PCIE_AER_UCE_UC | PCIE_AER_UCE_UR) 46 47 /* 48 * Global panicing state variabled used to control if further error handling 49 * should occur. If the system is already panic'ing or if PX itself has 50 * recommended panic'ing the system, no further error handling should occur to 51 * prevent the system from hanging. 52 */ 53 boolean_t px_panicing = B_FALSE; 54 55 static pf_data_t *px_get_pfd(px_t *px_p); 56 57 static int px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, 58 px_err_pcie_t *regs); 59 60 #if defined(DEBUG) 61 static void px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs); 62 #else /* DEBUG */ 63 #define px_pcie_log 0 && 64 #endif /* DEBUG */ 65 66 /* 67 * Initialize px FMA support 68 */ 69 int 70 px_fm_attach(px_t *px_p) 71 { 72 int i; 73 dev_info_t *dip = px_p->px_dip; 74 pcie_bus_t *bus_p; 75 76 px_p->px_fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 77 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 78 79 /* 80 * check parents' capability 81 */ 82 ddi_fm_init(dip, &px_p->px_fm_cap, &px_p->px_fm_ibc); 83 84 /* 85 * parents need to be ereport and error handling capable 86 */ 87 ASSERT(px_p->px_fm_cap && 88 (DDI_FM_ERRCB_CAPABLE | DDI_FM_EREPORT_CAPABLE)); 89 90 /* 91 * Initialize lock to synchronize fabric error handling 92 */ 93 mutex_init(&px_p->px_fm_mutex, NULL, MUTEX_DRIVER, 94 (void *)px_p->px_fm_ibc); 95 96 97 pcie_rc_init_bus(dip); 98 99 px_p->px_pfd_idx = 0; 100 for (i = 0; i < 5; i++) 101 pcie_rc_init_pfd(dip, &px_p->px_pfd_arr[i]); 102 PCIE_DIP2PFD(dip) = px_p->px_pfd_arr; 103 104 bus_p = PCIE_DIP2BUS(dip); 105 bus_p->bus_rp_bdf = px_p->px_bdf; 106 bus_p->bus_rp_dip = dip; 107 108 /* 109 * register error callback in parent 110 */ 111 ddi_fm_handler_register(dip, px_fm_callback, px_p); 112 113 return (DDI_SUCCESS); 114 } 115 116 /* 117 * Deregister FMA 118 */ 119 void 120 px_fm_detach(px_t *px_p) 121 { 122 int i; 123 124 ddi_fm_handler_unregister(px_p->px_dip); 125 mutex_destroy(&px_p->px_fm_mutex); 126 ddi_fm_fini(px_p->px_dip); 127 for (i = 0; i < 5; i++) 128 pcie_rc_fini_pfd(&px_p->px_pfd_arr[i]); 129 pcie_rc_fini_bus(px_p->px_dip); 130 } 131 132 /* 133 * Function used to setup access functions depending on level of desired 134 * protection. 135 */ 136 void 137 px_fm_acc_setup(ddi_map_req_t *mp, dev_info_t *rdip, pci_regspec_t *rp) 138 { 139 uchar_t fflag; 140 ndi_err_t *errp; 141 ddi_acc_hdl_t *hp; 142 ddi_acc_impl_t *ap; 143 144 hp = mp->map_handlep; 145 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 146 fflag = ap->ahi_common.ah_acc.devacc_attr_access; 147 148 if (mp->map_op == DDI_MO_MAP_LOCKED) { 149 ndi_fmc_insert(rdip, ACC_HANDLE, (void *)hp, NULL); 150 switch (fflag) { 151 case DDI_FLAGERR_ACC: 152 ap->ahi_get8 = i_ddi_prot_get8; 153 ap->ahi_get16 = i_ddi_prot_get16; 154 ap->ahi_get32 = i_ddi_prot_get32; 155 ap->ahi_get64 = i_ddi_prot_get64; 156 ap->ahi_put8 = i_ddi_prot_put8; 157 ap->ahi_put16 = i_ddi_prot_put16; 158 ap->ahi_put32 = i_ddi_prot_put32; 159 ap->ahi_put64 = i_ddi_prot_put64; 160 ap->ahi_rep_get8 = i_ddi_prot_rep_get8; 161 ap->ahi_rep_get16 = i_ddi_prot_rep_get16; 162 ap->ahi_rep_get32 = i_ddi_prot_rep_get32; 163 ap->ahi_rep_get64 = i_ddi_prot_rep_get64; 164 ap->ahi_rep_put8 = i_ddi_prot_rep_put8; 165 ap->ahi_rep_put16 = i_ddi_prot_rep_put16; 166 ap->ahi_rep_put32 = i_ddi_prot_rep_put32; 167 ap->ahi_rep_put64 = i_ddi_prot_rep_put64; 168 impl_acc_err_init(hp); 169 errp = ((ddi_acc_impl_t *)hp)->ahi_err; 170 if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == 171 PCI_ADDR_CONFIG) 172 errp->err_cf = px_err_cfg_hdl_check; 173 else 174 errp->err_cf = px_err_pio_hdl_check; 175 break; 176 case DDI_CAUTIOUS_ACC : 177 ap->ahi_get8 = i_ddi_caut_get8; 178 ap->ahi_get16 = i_ddi_caut_get16; 179 ap->ahi_get32 = i_ddi_caut_get32; 180 ap->ahi_get64 = i_ddi_caut_get64; 181 ap->ahi_put8 = i_ddi_caut_put8; 182 ap->ahi_put16 = i_ddi_caut_put16; 183 ap->ahi_put32 = i_ddi_caut_put32; 184 ap->ahi_put64 = i_ddi_caut_put64; 185 ap->ahi_rep_get8 = i_ddi_caut_rep_get8; 186 ap->ahi_rep_get16 = i_ddi_caut_rep_get16; 187 ap->ahi_rep_get32 = i_ddi_caut_rep_get32; 188 ap->ahi_rep_get64 = i_ddi_caut_rep_get64; 189 ap->ahi_rep_put8 = i_ddi_caut_rep_put8; 190 ap->ahi_rep_put16 = i_ddi_caut_rep_put16; 191 ap->ahi_rep_put32 = i_ddi_caut_rep_put32; 192 ap->ahi_rep_put64 = i_ddi_caut_rep_put64; 193 impl_acc_err_init(hp); 194 errp = ((ddi_acc_impl_t *)hp)->ahi_err; 195 if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == 196 PCI_ADDR_CONFIG) 197 errp->err_cf = px_err_cfg_hdl_check; 198 else 199 errp->err_cf = px_err_pio_hdl_check; 200 break; 201 default: 202 /* Illegal state, remove the handle from cache */ 203 ndi_fmc_remove(rdip, ACC_HANDLE, (void *)hp); 204 break; 205 } 206 } else if (mp->map_op == DDI_MO_UNMAP) { 207 ndi_fmc_remove(rdip, ACC_HANDLE, (void *)hp); 208 } 209 } 210 211 /* 212 * Function used to initialize FMA for our children nodes. Called 213 * through pci busops when child node calls ddi_fm_init. 214 */ 215 /*ARGSUSED*/ 216 int 217 px_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 218 ddi_iblock_cookie_t *ibc_p) 219 { 220 px_t *px_p = DIP_TO_STATE(dip); 221 222 ASSERT(ibc_p != NULL); 223 *ibc_p = px_p->px_fm_ibc; 224 225 return (px_p->px_fm_cap); 226 } 227 228 /* 229 * lock access for exclusive PCIe access 230 */ 231 void 232 px_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle) 233 { 234 px_pec_t *pec_p = ((px_t *)DIP_TO_STATE(dip))->px_pec_p; 235 236 /* 237 * Exclusive access has been used for cautious put/get, 238 * Both utilize i_ddi_ontrap which, on sparcv9, implements 239 * similar protection as what on_trap() does, and which calls 240 * membar #Sync to flush out all cpu deferred errors 241 * prior to get/put operation, so here we're not calling 242 * membar #Sync - a difference from what's in pci_bus_enter(). 243 */ 244 mutex_enter(&pec_p->pec_pokefault_mutex); 245 pec_p->pec_acc_hdl = handle; 246 } 247 248 /* 249 * unlock access for exclusive PCIe access 250 */ 251 /* ARGSUSED */ 252 void 253 px_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle) 254 { 255 px_t *px_p = DIP_TO_STATE(dip); 256 px_pec_t *pec_p = px_p->px_pec_p; 257 258 pec_p->pec_acc_hdl = NULL; 259 mutex_exit(&pec_p->pec_pokefault_mutex); 260 } 261 262 static uint64_t 263 px_in_addr_range(dev_info_t *dip, px_ranges_t *ranges_p, uint64_t addr) 264 { 265 uint64_t addr_low, addr_high; 266 267 addr_low = (uint64_t)(ranges_p->parent_high & px_ranges_phi_mask) << 32; 268 addr_low |= (uint64_t)ranges_p->parent_low; 269 addr_high = addr_low + ((uint64_t)ranges_p->size_high << 32) + 270 (uint64_t)ranges_p->size_low; 271 272 DBG(DBG_ERR_INTR, dip, "Addr: 0x%llx high: 0x%llx low: 0x%llx\n", 273 addr, addr_high, addr_low); 274 275 if ((addr < addr_high) && (addr >= addr_low)) 276 return (addr_low); 277 278 return (0); 279 } 280 281 /* 282 * PCI error callback which is registered with our parent to call 283 * for PCIe logging when the CPU traps due to PCIe Uncorrectable Errors 284 * and PCI BERR/TO/UE on IO Loads. 285 */ 286 /*ARGSUSED*/ 287 int 288 px_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data) 289 { 290 dev_info_t *pdip = ddi_get_parent(dip); 291 px_t *px_p = (px_t *)impl_data; 292 int i, acc_type = 0; 293 int lookup, rc_err, fab_err; 294 uint64_t addr, base_addr; 295 uint64_t fault_addr = (uint64_t)derr->fme_bus_specific; 296 pcie_req_id_t bdf = PCIE_INVALID_BDF; 297 px_ranges_t *ranges_p; 298 int range_len; 299 300 /* 301 * If the current thread already owns the px_fm_mutex, then we 302 * have encountered an error while processing a previous 303 * error. Attempting to take the mutex again will cause the 304 * system to deadlock. 305 */ 306 if (px_p->px_fm_mutex_owner == curthread) 307 return (DDI_FM_FATAL); 308 309 i_ddi_fm_handler_exit(pdip); 310 if (px_fm_enter(px_p) != DDI_SUCCESS) { 311 i_ddi_fm_handler_enter(pdip); 312 return (DDI_FM_FATAL); 313 } 314 315 /* 316 * Make sure this failed load came from this PCIe port. Check by 317 * matching the upper 32 bits of the address with the ranges property. 318 */ 319 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 320 i = 0; 321 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 322 base_addr = px_in_addr_range(dip, ranges_p, fault_addr); 323 if (base_addr) { 324 switch (ranges_p->child_high & PCI_ADDR_MASK) { 325 case PCI_ADDR_CONFIG: 326 acc_type = PF_ADDR_CFG; 327 addr = NULL; 328 bdf = (pcie_req_id_t)((fault_addr >> 12) & 329 0xFFFF); 330 break; 331 case PCI_ADDR_IO: 332 case PCI_ADDR_MEM64: 333 case PCI_ADDR_MEM32: 334 acc_type = PF_ADDR_PIO; 335 addr = fault_addr - base_addr; 336 bdf = PCIE_INVALID_BDF; 337 break; 338 } 339 break; 340 } 341 } 342 343 /* This address doesn't belong to this leaf, just return with OK */ 344 if (!acc_type) { 345 px_fm_exit(px_p); 346 i_ddi_fm_handler_enter(pdip); 347 return (DDI_FM_OK); 348 } 349 350 rc_err = px_err_cmn_intr(px_p, derr, PX_TRAP_CALL, PX_FM_BLOCK_ALL); 351 lookup = pf_hdl_lookup(dip, derr->fme_ena, acc_type, (uint64_t)addr, 352 bdf); 353 354 px_rp_en_q(px_p, bdf, addr, 355 (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)); 356 357 fab_err = px_scan_fabric(px_p, dip, derr); 358 359 px_fm_exit(px_p); 360 i_ddi_fm_handler_enter(pdip); 361 362 if (!px_die) 363 return (DDI_FM_OK); 364 365 if ((rc_err & (PX_PANIC | PX_PROTECTED)) || 366 (fab_err & PF_ERR_FATAL_FLAGS) || 367 (lookup == PF_HDL_NOTFOUND)) 368 return (DDI_FM_FATAL); 369 else if ((rc_err == PX_NO_ERROR) && (fab_err == PF_ERR_NO_ERROR)) 370 return (DDI_FM_OK); 371 372 return (DDI_FM_NONFATAL); 373 } 374 375 /* 376 * px_err_fabric_intr: 377 * Interrupt handler for PCIE fabric block. 378 * o lock 379 * o create derr 380 * o px_err_cmn_intr(leaf, with jbc) 381 * o send ereport(fire fmri, derr, payload = BDF) 382 * o dispatch (leaf) 383 * o unlock 384 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 385 */ 386 /* ARGSUSED */ 387 uint_t 388 px_err_fabric_intr(px_t *px_p, msgcode_t msg_code, pcie_req_id_t rid) 389 { 390 dev_info_t *rpdip = px_p->px_dip; 391 int rc_err, fab_err; 392 ddi_fm_error_t derr; 393 uint32_t rp_status; 394 uint16_t ce_source, ue_source; 395 396 if (px_fm_enter(px_p) != DDI_SUCCESS) 397 goto done; 398 399 /* Create the derr */ 400 bzero(&derr, sizeof (ddi_fm_error_t)); 401 derr.fme_version = DDI_FME_VERSION; 402 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 403 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 404 405 px_err_safeacc_check(px_p, &derr); 406 407 if (msg_code == PCIE_MSG_CODE_ERR_COR) { 408 rp_status = PCIE_AER_RE_STS_CE_RCVD; 409 ce_source = rid; 410 ue_source = 0; 411 } else { 412 rp_status = PCIE_AER_RE_STS_FE_NFE_RCVD; 413 ce_source = 0; 414 ue_source = rid; 415 if (msg_code == PCIE_MSG_CODE_ERR_NONFATAL) 416 rp_status |= PCIE_AER_RE_STS_NFE_MSGS_RCVD; 417 else { 418 rp_status |= PCIE_AER_RE_STS_FE_MSGS_RCVD; 419 rp_status |= PCIE_AER_RE_STS_FIRST_UC_FATAL; 420 } 421 } 422 423 if (derr.fme_flag == DDI_FM_ERR_UNEXPECTED) { 424 ddi_fm_ereport_post(rpdip, PCI_ERROR_SUBCLASS "." PCIEX_FABRIC, 425 derr.fme_ena, 426 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 427 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 428 "pcie_adv_rp_status", DATA_TYPE_UINT32, rp_status, 429 "pcie_adv_rp_command", DATA_TYPE_UINT32, 0, 430 "pcie_adv_rp_ce_src_id", DATA_TYPE_UINT16, ce_source, 431 "pcie_adv_rp_ue_src_id", DATA_TYPE_UINT16, ue_source, 432 NULL); 433 } 434 435 /* Ensure that the rid of the fabric message will get scanned. */ 436 px_rp_en_q(px_p, rid, NULL, NULL); 437 438 rc_err = px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_PCIE); 439 440 /* call rootport dispatch */ 441 fab_err = px_scan_fabric(px_p, rpdip, &derr); 442 443 px_err_panic(rc_err, PX_RC, fab_err, B_TRUE); 444 px_fm_exit(px_p); 445 px_err_panic(rc_err, PX_RC, fab_err, B_FALSE); 446 447 done: 448 return (DDI_INTR_CLAIMED); 449 } 450 451 /* 452 * px_scan_fabric: 453 * 454 * Check for drain state and if there is anything to scan. 455 */ 456 int 457 px_scan_fabric(px_t *px_p, dev_info_t *rpdip, ddi_fm_error_t *derr) { 458 int fab_err = 0; 459 460 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 461 462 if (!px_lib_is_in_drain_state(px_p) && px_p->px_pfd_idx) { 463 fab_err = pf_scan_fabric(rpdip, derr, px_p->px_pfd_arr); 464 px_p->px_pfd_idx = 0; 465 } 466 467 return (fab_err); 468 } 469 470 /* 471 * px_err_safeacc_check: 472 * Check to see if a peek/poke and cautious access is currently being 473 * done on a particular leaf. 474 * 475 * Safe access reads induced fire errors will be handled by cpu trap handler 476 * which will call px_fm_callback() which calls this function. In that 477 * case, the derr fields will be set by trap handler with the correct values. 478 * 479 * Safe access writes induced errors will be handled by px interrupt 480 * handlers, this function will fill in the derr fields. 481 * 482 * If a cpu trap does occur, it will quiesce all other interrupts allowing 483 * the cpu trap error handling to finish before Fire receives an interrupt. 484 * 485 * If fire does indeed have an error when a cpu trap occurs as a result of 486 * a safe access, a trap followed by a Mondo/Fabric interrupt will occur. 487 * In which case derr will be initialized as "UNEXPECTED" by the interrupt 488 * handler and this function will need to find if this error occured in the 489 * middle of a safe access operation. 490 * 491 * @param px_p leaf in which to check access 492 * @param derr fm err data structure to be updated 493 */ 494 void 495 px_err_safeacc_check(px_t *px_p, ddi_fm_error_t *derr) 496 { 497 px_pec_t *pec_p = px_p->px_pec_p; 498 int acctype = pec_p->pec_safeacc_type; 499 500 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 501 502 if (derr->fme_flag != DDI_FM_ERR_UNEXPECTED) { 503 return; 504 } 505 506 /* safe access checking */ 507 switch (acctype) { 508 case DDI_FM_ERR_EXPECTED: 509 /* 510 * cautious access protection, protected from all err. 511 */ 512 ddi_fm_acc_err_get(pec_p->pec_acc_hdl, derr, 513 DDI_FME_VERSION); 514 derr->fme_flag = acctype; 515 derr->fme_acc_handle = pec_p->pec_acc_hdl; 516 break; 517 case DDI_FM_ERR_POKE: 518 /* 519 * ddi_poke protection, check nexus and children for 520 * expected errors. 521 */ 522 membar_sync(); 523 derr->fme_flag = acctype; 524 break; 525 case DDI_FM_ERR_PEEK: 526 derr->fme_flag = acctype; 527 break; 528 } 529 } 530 531 /* 532 * Suggest panic if any EQ (except CE q) has overflown. 533 */ 534 int 535 px_err_check_eq(dev_info_t *dip) 536 { 537 px_t *px_p = DIP_TO_STATE(dip); 538 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 539 px_pec_t *pec_p = px_p->px_pec_p; 540 msiqid_t eq_no = msiq_state_p->msiq_1st_msiq_id; 541 pci_msiq_state_t msiq_state; 542 int i; 543 544 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 545 if (i + eq_no == pec_p->pec_corr_msg_msiq_id) /* skip CE q */ 546 continue; 547 if ((px_lib_msiq_getstate(dip, i + eq_no, &msiq_state) != 548 DDI_SUCCESS) || msiq_state == PCI_MSIQ_STATE_ERROR) 549 return (PX_PANIC); 550 } 551 return (PX_NO_PANIC); 552 } 553 554 /* ARGSUSED */ 555 int 556 px_err_check_pcie(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) 557 { 558 px_t *px_p = DIP_TO_STATE(dip); 559 pf_data_t *pfd_p = px_get_pfd(px_p); 560 int i; 561 pf_pcie_adv_err_regs_t *adv_reg = PCIE_ADV_REG(pfd_p); 562 563 /* 564 * set RC s_status in PCI term to coordinate with downstream fabric 565 * errors ananlysis. 566 */ 567 if (regs->primary_ue & PCIE_AER_UCE_UR) 568 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = PCI_STAT_R_MAST_AB; 569 if (regs->primary_ue & PCIE_AER_UCE_CA) 570 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = PCI_STAT_R_TARG_AB; 571 if (regs->primary_ue & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_ECRC)) 572 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = PCI_STAT_PERROR; 573 574 if (!regs->primary_ue) 575 goto done; 576 577 adv_reg->pcie_ce_status = regs->ce_reg; 578 adv_reg->pcie_ue_status = regs->ue_reg | regs->primary_ue; 579 PCIE_ADV_HDR(pfd_p, 0) = regs->rx_hdr1; 580 PCIE_ADV_HDR(pfd_p, 1) = regs->rx_hdr2; 581 PCIE_ADV_HDR(pfd_p, 2) = regs->rx_hdr3; 582 PCIE_ADV_HDR(pfd_p, 3) = regs->rx_hdr4; 583 for (i = regs->primary_ue; i != 1; i = i >> 1) 584 adv_reg->pcie_adv_ctl++; 585 586 if (regs->primary_ue & (PCIE_AER_UCE_UR | PCIE_AER_UCE_CA)) { 587 if (pf_tlp_decode(PCIE_DIP2BUS(dip), adv_reg) == DDI_SUCCESS) 588 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = 589 adv_reg->pcie_ue_tgt_bdf; 590 } else if (regs->primary_ue & PCIE_AER_UCE_PTLP) { 591 if (pf_tlp_decode(PCIE_DIP2BUS(dip), adv_reg) == DDI_SUCCESS) { 592 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = 593 adv_reg->pcie_ue_tgt_bdf; 594 if (adv_reg->pcie_ue_tgt_trans == 595 PF_ADDR_PIO) 596 PCIE_ROOT_FAULT(pfd_p)->scan_addr = 597 adv_reg->pcie_ue_tgt_addr; 598 } 599 600 /* 601 * Normally for Poisoned Completion TLPs we can look at the 602 * transmit log header for the original request and the original 603 * address, however this doesn't seem to be working. HW BUG. 604 */ 605 } 606 607 done: 608 px_pcie_log(dip, regs); 609 610 /* Return No Error here and let the pcie misc module analyse it */ 611 return (PX_NO_ERROR); 612 } 613 614 #if defined(DEBUG) 615 static void 616 px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs) 617 { 618 DBG(DBG_ERR_INTR, dip, 619 "A PCIe RC error has occured\n" 620 "\tCE: 0x%x UE: 0x%x Primary UE: 0x%x\n" 621 "\tTX Hdr: 0x%x 0x%x 0x%x 0x%x\n\tRX Hdr: 0x%x 0x%x 0x%x 0x%x\n", 622 regs->ce_reg, regs->ue_reg, regs->primary_ue, 623 regs->tx_hdr1, regs->tx_hdr2, regs->tx_hdr3, regs->tx_hdr4, 624 regs->rx_hdr1, regs->rx_hdr2, regs->rx_hdr3, regs->rx_hdr4); 625 } 626 #endif 627 628 /* 629 * look through poisoned TLP cases and suggest panic/no panic depend on 630 * handle lookup. 631 */ 632 static int 633 px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) 634 { 635 pf_pcie_adv_err_regs_t adv_reg; 636 pcie_req_id_t bdf; 637 uint64_t addr; 638 uint32_t trans_type; 639 int tlp_sts, tlp_cmd; 640 int lookup = PF_HDL_NOTFOUND; 641 642 if (regs->primary_ue != PCIE_AER_UCE_PTLP) 643 return (PX_PANIC); 644 645 if (!regs->rx_hdr1) 646 goto done; 647 648 adv_reg.pcie_ue_hdr[0] = regs->rx_hdr1; 649 adv_reg.pcie_ue_hdr[1] = regs->rx_hdr2; 650 adv_reg.pcie_ue_hdr[2] = regs->rx_hdr3; 651 adv_reg.pcie_ue_hdr[3] = regs->rx_hdr4; 652 653 tlp_sts = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 654 tlp_cmd = ((pcie_tlp_hdr_t *)(adv_reg.pcie_ue_hdr))->type; 655 656 if (tlp_sts == DDI_FAILURE) 657 goto done; 658 659 bdf = adv_reg.pcie_ue_tgt_bdf; 660 addr = adv_reg.pcie_ue_tgt_addr; 661 trans_type = adv_reg.pcie_ue_tgt_trans; 662 663 switch (tlp_cmd) { 664 case PCIE_TLP_TYPE_CPL: 665 case PCIE_TLP_TYPE_CPLLK: 666 /* 667 * Usually a PTLP is a CPL with data. Grab the completer BDF 668 * from the RX TLP, and the original address from the TX TLP. 669 */ 670 if (regs->tx_hdr1) { 671 adv_reg.pcie_ue_hdr[0] = regs->tx_hdr1; 672 adv_reg.pcie_ue_hdr[1] = regs->tx_hdr2; 673 adv_reg.pcie_ue_hdr[2] = regs->tx_hdr3; 674 adv_reg.pcie_ue_hdr[3] = regs->tx_hdr4; 675 676 lookup = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 677 if (lookup != DDI_SUCCESS) 678 break; 679 addr = adv_reg.pcie_ue_tgt_addr; 680 trans_type = adv_reg.pcie_ue_tgt_trans; 681 } /* FALLTHRU */ 682 case PCIE_TLP_TYPE_IO: 683 case PCIE_TLP_TYPE_MEM: 684 case PCIE_TLP_TYPE_MEMLK: 685 lookup = pf_hdl_lookup(dip, derr->fme_ena, trans_type, addr, 686 bdf); 687 break; 688 default: 689 lookup = PF_HDL_NOTFOUND; 690 } 691 done: 692 return (lookup == PF_HDL_FOUND ? PX_NO_PANIC : PX_PANIC); 693 } 694 695 /* 696 * px_get_pdf automatically allocates a RC pf_data_t and returns a pointer to 697 * it. This function should be used when an error requires a fabric scan. 698 */ 699 static pf_data_t * 700 px_get_pfd(px_t *px_p) { 701 int idx = px_p->px_pfd_idx++; 702 pf_data_t *pfd_p = &px_p->px_pfd_arr[idx]; 703 704 /* Clear Old Data */ 705 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = PCIE_INVALID_BDF; 706 PCIE_ROOT_FAULT(pfd_p)->scan_addr = 0; 707 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = 0; 708 PCIE_ADV_REG(pfd_p)->pcie_ce_status = 0; 709 PCIE_ADV_REG(pfd_p)->pcie_ue_status = 0; 710 711 pfd_p->pe_next = NULL; 712 713 if (idx > 0) { 714 px_p->px_pfd_arr[idx - 1].pe_next = pfd_p; 715 pfd_p->pe_prev = &px_p->px_pfd_arr[idx - 1]; 716 } else { 717 pfd_p->pe_prev = NULL; 718 } 719 720 pfd_p->pe_valid = B_TRUE; 721 722 return (pfd_p); 723 } 724 725 /* 726 * This function appends a pf_data structure to the error q which is used later 727 * during PCIe fabric scan. It signifies: 728 * o errs rcvd in RC, that may have been propagated to/from the fabric 729 * o the fabric scan code should scan the device path of fault bdf/addr 730 * 731 * scan_bdf: The bdf that caused the fault, which may have error bits set. 732 * scan_addr: The PIO addr that caused the fault, such as failed PIO, but not 733 * failed DMAs. 734 * s_status: Secondary Status equivalent to why the fault occured. 735 * (ie S-TA/MA, R-TA) 736 * Either the scan bdf or addr may be NULL, but not both. 737 */ 738 void 739 px_rp_en_q(px_t *px_p, pcie_req_id_t scan_bdf, uint32_t scan_addr, 740 uint16_t s_status) 741 { 742 pf_data_t *pfd_p; 743 744 if (!PCIE_CHECK_VALID_BDF(scan_bdf) && !scan_addr) 745 return; 746 747 pfd_p = px_get_pfd(px_p); 748 749 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = scan_bdf; 750 PCIE_ROOT_FAULT(pfd_p)->scan_addr = (uint64_t)scan_addr; 751 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = s_status; 752 } 753 754 755 /* 756 * Find and Mark CFG Handles as failed associated with the given BDF. We should 757 * always know the BDF for CFG accesses, since it is encoded in the address of 758 * the TLP. Since there can be multiple cfg handles, mark them all as failed. 759 */ 760 /* ARGSUSED */ 761 int 762 px_err_cfg_hdl_check(dev_info_t *dip, const void *handle, const void *arg1, 763 const void *arg2) 764 { 765 int status = DDI_FM_FATAL; 766 uint32_t addr = *(uint32_t *)arg1; 767 uint16_t bdf = *(uint16_t *)arg2; 768 pcie_bus_t *bus_p; 769 770 DBG(DBG_ERR_INTR, dip, "Check CFG Hdl: dip 0x%p addr 0x%x bdf=0x%x\n", 771 dip, addr, bdf); 772 773 bus_p = PCIE_DIP2BUS(dip); 774 775 /* 776 * Because CFG and IO Acc Handlers are on the same cache list and both 777 * types of hdls gets called for both types of errors. For this checker 778 * only mark the device as "Non-Fatal" if the addr == NULL and bdf != 779 * NULL. 780 */ 781 status = (!addr && (PCIE_CHECK_VALID_BDF(bdf) && 782 (bus_p->bus_bdf == bdf))) ? DDI_FM_NONFATAL : DDI_FM_FATAL; 783 784 return (status); 785 } 786 787 /* 788 * Find and Mark all ACC Handles associated with a give address and BDF as 789 * failed. If the BDF != NULL, then check to see if the device has a ACC Handle 790 * associated with ADDR. If the handle is not found, mark all the handles as 791 * failed. If the BDF == NULL, mark the handle as failed if it is associated 792 * with ADDR. 793 */ 794 int 795 px_err_pio_hdl_check(dev_info_t *dip, const void *handle, const void *arg1, 796 const void *arg2) 797 { 798 dev_info_t *px_dip = PCIE_DIP2BUS(dip)->bus_rp_dip; 799 px_t *px_p = INST_TO_STATE(ddi_get_instance(px_dip)); 800 px_ranges_t *ranges_p; 801 int range_len; 802 ddi_acc_handle_t ap = (ddi_acc_handle_t)handle; 803 ddi_acc_hdl_t *hp = impl_acc_hdl_get(ap); 804 int i, status = DDI_FM_FATAL; 805 uint64_t fault_addr = *(uint64_t *)arg1; 806 uint16_t bdf = *(uint16_t *)arg2; 807 uint64_t base_addr, range_addr; 808 uint_t size; 809 810 DBG(DBG_ERR_INTR, dip, "Check PIO Hdl: dip 0x%x addr 0x%x bdf=0x%x\n", 811 dip, fault_addr, bdf); 812 813 /* Normalize the base addr to the addr and strip off the HB info. */ 814 base_addr = (hp->ah_pfn << MMU_PAGESHIFT) + hp->ah_offset; 815 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 816 i = 0; 817 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 818 range_addr = px_in_addr_range(dip, ranges_p, base_addr); 819 if (range_addr) { 820 switch (ranges_p->child_high & PCI_ADDR_MASK) { 821 case PCI_ADDR_IO: 822 case PCI_ADDR_MEM64: 823 case PCI_ADDR_MEM32: 824 base_addr = base_addr - range_addr; 825 break; 826 } 827 break; 828 } 829 } 830 831 /* 832 * Mark the handle as failed if the ADDR is mapped, or if we 833 * know the BDF and ADDR == 0. 834 */ 835 size = hp->ah_len; 836 if (((fault_addr >= base_addr) && (fault_addr < (base_addr + size))) || 837 ((fault_addr == NULL) && (PCIE_CHECK_VALID_BDF(bdf) && 838 (bdf == PCIE_DIP2BUS(dip)->bus_bdf)))) 839 status = DDI_FM_NONFATAL; 840 841 return (status); 842 } 843 844 /* 845 * Find and Mark all DNA Handles associated with a give address and BDF as 846 * failed. If the BDF != NULL, then check to see if the device has a DMA Handle 847 * associated with ADDR. If the handle is not found, mark all the handles as 848 * failed. If the BDF == NULL, mark the handle as failed if it is associated 849 * with ADDR. 850 */ 851 int 852 px_err_dma_hdl_check(dev_info_t *dip, const void *handle, const void *arg1, 853 const void *arg2) 854 { 855 ddi_dma_impl_t *pcie_dp; 856 int status = DDI_FM_FATAL; 857 uint32_t addr = *(uint32_t *)arg1; 858 uint16_t bdf = *(uint16_t *)arg2; 859 uint32_t base_addr; 860 uint_t size; 861 862 DBG(DBG_ERR_INTR, dip, "Check PIO Hdl: dip 0x%x addr 0x%x bdf=0x%x\n", 863 dip, addr, bdf); 864 865 pcie_dp = (ddi_dma_impl_t *)handle; 866 base_addr = (uint32_t)pcie_dp->dmai_mapping; 867 size = pcie_dp->dmai_size; 868 869 /* 870 * Mark the handle as failed if the ADDR is mapped, or if we 871 * know the BDF and ADDR == 0. 872 */ 873 if (((addr >= base_addr) && (addr < (base_addr + size))) || 874 ((addr == NULL) && PCIE_CHECK_VALID_BDF(bdf))) 875 status = DDI_FM_NONFATAL; 876 877 return (status); 878 } 879 880 int 881 px_fm_enter(px_t *px_p) { 882 if (px_panicing || (px_p->px_fm_mutex_owner == curthread)) 883 return (DDI_FAILURE); 884 885 mutex_enter(&px_p->px_fm_mutex); 886 /* 887 * In rare cases when trap occurs and in the middle of scanning the 888 * fabric, a PIO will fail in the scan fabric. The CPU error handling 889 * code will correctly panic the system, while a mondo for the failed 890 * PIO may also show up. Normally the mondo will try to grab the mutex 891 * and wait until the callback finishes. But in this rare case, 892 * mutex_enter actually suceeds also continues to scan the fabric. 893 * 894 * This code below is designed specifically to check for this case. If 895 * we successfully grab the px_fm_mutex, the px_fm_mutex_owner better be 896 * NULL. If it isn't that means we are in the rare corner case. Return 897 * DDI_FAILURE, this should prevent PX from doing anymore error 898 * handling. 899 */ 900 if (px_p->px_fm_mutex_owner) { 901 return (DDI_FAILURE); 902 } 903 904 px_p->px_fm_mutex_owner = curthread; 905 906 if (px_panicing) { 907 px_fm_exit(px_p); 908 return (DDI_FAILURE); 909 } 910 return (DDI_SUCCESS); 911 } 912 913 void 914 px_fm_exit(px_t *px_p) { 915 px_p->px_fm_mutex_owner = NULL; 916 mutex_exit(&px_p->px_fm_mutex); 917 } 918 919 /* 920 * Panic if the err tunable is set and that we are not already in the middle 921 * of panic'ing. 922 * 923 * rc_err = Error severity of PX specific errors 924 * msg = Where the error was detected 925 * fabric_err = Error severity of PCIe Fabric errors 926 * isTest = Test if error severity causes panic 927 */ 928 #define MSZ (sizeof (fm_msg) -strlen(fm_msg) - 1) 929 void 930 px_err_panic(int rc_err, int msg, int fabric_err, boolean_t isTest) 931 { 932 char fm_msg[96] = ""; 933 int ferr = PX_NO_ERROR; 934 935 if (panicstr) { 936 px_panicing = B_TRUE; 937 return; 938 } 939 940 if (!(rc_err & px_die)) 941 goto fabric; 942 if (msg & PX_RC) 943 (void) strncat(fm_msg, px_panic_rc_msg, MSZ); 944 if (msg & PX_RP) 945 (void) strncat(fm_msg, px_panic_rp_msg, MSZ); 946 if (msg & PX_HB) 947 (void) strncat(fm_msg, px_panic_hb_msg, MSZ); 948 949 fabric: 950 if (fabric_err & PF_ERR_FATAL_FLAGS) 951 ferr = PX_PANIC; 952 else if (fabric_err & ~(PF_ERR_FATAL_FLAGS | PF_ERR_NO_ERROR)) 953 ferr = PX_NO_PANIC; 954 955 if (ferr & px_die) { 956 if (strlen(fm_msg)) { 957 (void) strncat(fm_msg, " and", MSZ); 958 } 959 (void) strncat(fm_msg, px_panic_fab_msg, MSZ); 960 } 961 962 if (strlen(fm_msg)) { 963 px_panicing = B_TRUE; 964 if (!isTest) 965 fm_panic("Fatal error has occured in:%s.(0x%x)(0x%x)", 966 fm_msg, rc_err, fabric_err); 967 } 968 } 969