xref: /titanic_51/usr/src/uts/sun4/io/px/px_devctl.c (revision 42487ff1899d230ad6c2d55cf9573489ca5eb770)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 /*
30  * PCI nexus HotPlug devctl interface
31  */
32 #include <sys/types.h>
33 #include <sys/conf.h>
34 #include <sys/kmem.h>
35 #include <sys/async.h>
36 #include <sys/sysmacros.h>
37 #include <sys/sunddi.h>
38 #include <sys/sunndi.h>
39 #include <sys/ddi_impldefs.h>
40 #include <sys/open.h>
41 #include <sys/errno.h>
42 #include <sys/file.h>
43 #include <sys/policy.h>
44 #include <sys/hotplug/pci/pcihp.h>
45 #include "px_obj.h"
46 #include <sys/pci_tools.h>
47 #include "px_tools_ext.h"
48 #include "pcie_pwr.h"
49 
50 /*LINTLIBRARY*/
51 
52 static int px_open(dev_t *devp, int flags, int otyp, cred_t *credp);
53 static int px_close(dev_t dev, int flags, int otyp, cred_t *credp);
54 static int px_ioctl(dev_t dev, int cmd, intptr_t arg, int mode,
55 						cred_t *credp, int *rvalp);
56 static int px_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
57     int flags, char *name, caddr_t valuep, int *lengthp);
58 
59 struct cb_ops px_cb_ops = {
60 	px_open,			/* open */
61 	px_close,			/* close */
62 	nodev,				/* strategy */
63 	nodev,				/* print */
64 	nodev,				/* dump */
65 	nodev,				/* read */
66 	nodev,				/* write */
67 	px_ioctl,			/* ioctl */
68 	nodev,				/* devmap */
69 	nodev,				/* mmap */
70 	nodev,				/* segmap */
71 	nochpoll,			/* poll */
72 	px_prop_op,			/* cb_prop_op */
73 	NULL,				/* streamtab */
74 	D_NEW | D_MP | D_HOTPLUG,	/* Driver compatibility flag */
75 	CB_REV,				/* rev */
76 	nodev,				/* int (*cb_aread)() */
77 	nodev				/* int (*cb_awrite)() */
78 };
79 
80 /* ARGSUSED3 */
81 static int
82 px_open(dev_t *devp, int flags, int otyp, cred_t *credp)
83 {
84 	px_t *px_p;
85 	int rval;
86 	uint_t orig_px_soft_state;
87 
88 	/*
89 	 * Make sure the open is for the right file type.
90 	 */
91 	if (otyp != OTYP_CHR)
92 		return (EINVAL);
93 
94 	/*
95 	 * Get the soft state structure for the device.
96 	 */
97 	px_p = PX_DEV_TO_SOFTSTATE(*devp);
98 	if (px_p == NULL)
99 		return (ENXIO);
100 
101 	/*
102 	 * Handle the open by tracking the device state.
103 	 */
104 	DBG(DBG_OPEN, px_p->px_dip, "devp=%x: flags=%x\n", devp, flags);
105 	mutex_enter(&px_p->px_mutex);
106 	orig_px_soft_state = px_p->px_soft_state;
107 	if (flags & FEXCL) {
108 		if (px_p->px_soft_state != PX_SOFT_STATE_CLOSED) {
109 			mutex_exit(&px_p->px_mutex);
110 			DBG(DBG_OPEN, px_p->px_dip, "busy\n");
111 			return (EBUSY);
112 		}
113 		px_p->px_soft_state = PX_SOFT_STATE_OPEN_EXCL;
114 	} else {
115 		if (px_p->px_soft_state == PX_SOFT_STATE_OPEN_EXCL) {
116 			mutex_exit(&px_p->px_mutex);
117 			DBG(DBG_OPEN, px_p->px_dip, "busy\n");
118 			return (EBUSY);
119 		}
120 		px_p->px_soft_state = PX_SOFT_STATE_OPEN;
121 	}
122 
123 	if (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)
124 		if (rval = (pcihp_get_cb_ops())->cb_open(devp, flags,
125 		    otyp, credp)) {
126 			px_p->px_soft_state = orig_px_soft_state;
127 			mutex_exit(&px_p->px_mutex);
128 			return (rval);
129 		}
130 
131 	px_p->px_open_count++;
132 	mutex_exit(&px_p->px_mutex);
133 	return (0);
134 }
135 
136 
137 /* ARGSUSED */
138 static int
139 px_close(dev_t dev, int flags, int otyp, cred_t *credp)
140 {
141 	px_t *px_p;
142 	int rval;
143 
144 	if (otyp != OTYP_CHR)
145 		return (EINVAL);
146 
147 	px_p = PX_DEV_TO_SOFTSTATE(dev);
148 	if (px_p == NULL)
149 		return (ENXIO);
150 
151 	DBG(DBG_CLOSE, px_p->px_dip, "dev=%x: flags=%x\n", dev, flags);
152 	mutex_enter(&px_p->px_mutex);
153 
154 	if (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)
155 		if (rval = (pcihp_get_cb_ops())->cb_close(dev, flags,
156 		    otyp, credp)) {
157 			mutex_exit(&px_p->px_mutex);
158 			return (rval);
159 		}
160 
161 	px_p->px_soft_state = PX_SOFT_STATE_CLOSED;
162 	px_p->px_open_count = 0;
163 	mutex_exit(&px_p->px_mutex);
164 	return (0);
165 }
166 
167 /* ARGSUSED */
168 static int
169 px_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, int *rvalp)
170 {
171 	px_t *px_p;
172 	dev_info_t *dip;
173 	struct devctl_iocdata *dcp;
174 	uint_t bus_state;
175 	int rv = DDI_SUCCESS;
176 	int minor = getminor(dev);
177 
178 	px_p = PX_DEV_TO_SOFTSTATE(dev);
179 	if (px_p == NULL)
180 		return (ENXIO);
181 
182 	dip = px_p->px_dip;
183 	DBG(DBG_IOCTL, dip, "dev=%x: cmd=%x\n", dev, cmd);
184 
185 #ifdef	PX_DMA_TEST
186 	if (IS_DMATEST(cmd)) {
187 		*rvalp = px_dma_test(cmd, dip, px_p, arg);
188 		return (0);
189 	}
190 #endif	/* PX_DMA_TEST */
191 
192 	switch (PCIHP_AP_MINOR_NUM_TO_PCI_DEVNUM(minor)) {
193 
194 	/*
195 	 * PCI tools.
196 	 */
197 	case PCI_TOOL_REG_MINOR_NUM:
198 
199 		switch (cmd) {
200 		case PCITOOL_DEVICE_SET_REG:
201 		case PCITOOL_DEVICE_GET_REG:
202 
203 			/* Require full privileges. */
204 			if (secpolicy_kmdb(credp))
205 				rv = EPERM;
206 			else
207 				rv = pxtool_dev_reg_ops(dip,
208 				    (void *)arg, cmd, mode);
209 			break;
210 
211 		case PCITOOL_NEXUS_SET_REG:
212 		case PCITOOL_NEXUS_GET_REG:
213 
214 			/* Require full privileges. */
215 			if (secpolicy_kmdb(credp))
216 				rv = EPERM;
217 			else
218 				rv = pxtool_bus_reg_ops(dip,
219 				    (void *)arg, cmd, mode);
220 			break;
221 
222 		default:
223 			rv = ENOTTY;
224 		}
225 		return (rv);
226 
227 	case PCI_TOOL_INTR_MINOR_NUM:
228 
229 		switch (cmd) {
230 		case PCITOOL_DEVICE_SET_INTR:
231 
232 		/*
233 		 * Require PRIV_SYS_RES_CONFIG,
234 		 * same as psradm
235 		 */
236 		if (secpolicy_ponline(credp)) {
237 			rv = EPERM;
238 			break;
239 		}
240 
241 		/*FALLTHRU*/
242 		/* These require no special privileges. */
243 		case PCITOOL_DEVICE_GET_INTR:
244 		case PCITOOL_DEVICE_NUM_INTR:
245 			rv = pxtool_intr(dip, (void *)arg, cmd, mode);
246 			break;
247 
248 		default:
249 			rv = ENOTTY;
250 		}
251 		return (rv);
252 
253 	default:
254 		if (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)
255 			return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd,
256 			    arg, mode, credp, rvalp));
257 		break;
258 	}
259 
260 	if ((cmd & ~PPMREQ_MASK) == PPMREQ) {
261 
262 		/* Need privileges to use these ioctls. */
263 		if (drv_priv(credp)) {
264 			DBG(DBG_TOOLS, dip,
265 			    "px_tools: Insufficient privileges\n");
266 
267 			return (EPERM);
268 		}
269 		return (px_lib_pmctl(cmd, px_p));
270 	}
271 
272 	/*
273 	 * We can use the generic implementation for these ioctls
274 	 */
275 	switch (cmd) {
276 	case DEVCTL_DEVICE_GETSTATE:
277 	case DEVCTL_DEVICE_ONLINE:
278 	case DEVCTL_DEVICE_OFFLINE:
279 	case DEVCTL_BUS_GETSTATE:
280 		return (ndi_devctl_ioctl(dip, cmd, arg, mode, 0));
281 	}
282 
283 	/*
284 	 * read devctl ioctl data
285 	 */
286 	if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS)
287 		return (EFAULT);
288 
289 	switch (cmd) {
290 
291 	case DEVCTL_DEVICE_RESET:
292 		DBG(DBG_IOCTL, dip, "DEVCTL_DEVICE_RESET\n");
293 		rv = ENOTSUP;
294 		break;
295 
296 
297 	case DEVCTL_BUS_QUIESCE:
298 		DBG(DBG_IOCTL, dip, "DEVCTL_BUS_QUIESCE\n");
299 		if (ndi_get_bus_state(dip, &bus_state) == NDI_SUCCESS)
300 			if (bus_state == BUS_QUIESCED)
301 				break;
302 		(void) ndi_set_bus_state(dip, BUS_QUIESCED);
303 		break;
304 
305 	case DEVCTL_BUS_UNQUIESCE:
306 		DBG(DBG_IOCTL, dip, "DEVCTL_BUS_UNQUIESCE\n");
307 		if (ndi_get_bus_state(dip, &bus_state) == NDI_SUCCESS)
308 			if (bus_state == BUS_ACTIVE)
309 				break;
310 		(void) ndi_set_bus_state(dip, BUS_ACTIVE);
311 		break;
312 
313 	case DEVCTL_BUS_RESET:
314 		DBG(DBG_IOCTL, dip, "DEVCTL_BUS_RESET\n");
315 		rv = ENOTSUP;
316 		break;
317 
318 	case DEVCTL_BUS_RESETALL:
319 		DBG(DBG_IOCTL, dip, "DEVCTL_BUS_RESETALL\n");
320 		rv = ENOTSUP;
321 		break;
322 
323 	default:
324 		rv = ENOTTY;
325 	}
326 
327 	ndi_dc_freehdl(dcp);
328 	return (rv);
329 }
330 
331 static int px_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
332     int flags, char *name, caddr_t valuep, int *lengthp)
333 {
334 	if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
335 	    "hotplug-capable"))
336 		return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip,
337 		    prop_op, flags, name, valuep, lengthp));
338 
339 	return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp));
340 }
341