1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Intel 82077 Floppy Disk Driver 31 */ 32 33 /* 34 * Notes 35 * 36 * 0. The driver supports two flavors of hardware design: 37 * "SUNW,fdtwo" - sun4m - 82077 with sun4m style Auxio 38 * "fdthree" - sun4u - 82077 with DMA 39 * In addition it supports an apparent bug in some versions of 40 * the 82077 controller. 41 * 42 * 1. The driver is mostly set up for multiple controllers, multiple 43 * drives. However- we *do* assume the use of the AUXIO register, and 44 * if we ever have > 1 fdc, we'll have to see what that means. This 45 * is all intrinsically machine specific, but there isn't much we 46 * can do about it. 47 * 48 * 2. The driver also is structured to deal with one drive active at 49 * a time. This is because the 82072 chip (no longer supported) was 50 * known to be buggy with respect to overlapped seeks. 51 * 52 * 3. The high level interrupt code is in assembler, and runs in a 53 * sparc trap window. It acts as a pseudo-dma engine as well as 54 * handles a couple of other interrupts. When it gets its job done, 55 * it schedules a second stage interrupt (soft interrupt) which 56 * is then fielded here in fd_lointr. When DMA is used, the fdintr_dma 57 * interrupt handler is used. 58 * 59 * 4. Nearly all locking is done on a lower level MUTEX_DRIVER 60 * mutex. The locking is quite conservative, and is generally 61 * established very close to any of the entries into the driver. 62 * There is nearly no locking done of the high level MUTEX_DRIVER 63 * mutex (which generally is a SPIN mutex because the floppy usually 64 * interrupts above LOCK_LEVEL). The assembler high level interrupt 65 * handler grabs the high level mutex, but the code in the driver 66 * here is especially structured to not need to do this. 67 * 68 * 5. Fdrawioctl commands that pass data are not optimized for 69 * speed. If they need to be faster, the driver structure will 70 * have to be redone such that fdrawioctl calls physio after 71 * cons'ing up a uio structure and that fdstart will be able 72 * to detect that a particular buffer is a 'special' buffer. 73 * 74 * 6. Removable media support is not complete. 75 * 76 */ 77 78 #include <sys/param.h> 79 #include <sys/buf.h> 80 #include <sys/ioctl.h> 81 #include <sys/uio.h> 82 #include <sys/open.h> 83 #include <sys/conf.h> 84 #include <sys/file.h> 85 #include <sys/cmn_err.h> 86 #include <sys/debug.h> 87 #include <sys/kmem.h> 88 #include <sys/stat.h> 89 #include <sys/autoconf.h> 90 91 #include <sys/dklabel.h> 92 93 #include <sys/vtoc.h> 94 #include <sys/dkio.h> 95 #include <sys/fdio.h> 96 97 #include <sys/ddi.h> 98 #include <sys/sunddi.h> 99 #include <sys/kstat.h> 100 101 /* 102 * included to check for ELC or SLC which report floppy controller that 103 */ 104 #include <sys/cpu.h> 105 106 #include "sys/fdvar.h" 107 #include "sys/fdreg.h" 108 #include "sys/dma_i8237A.h" 109 110 /* 111 * Defines 112 */ 113 #define KIOSP KSTAT_IO_PTR(un->un_iostat) 114 #define KIOIP KSTAT_INTR_PTR(fdc->c_intrstat) 115 #define MEDIUM_DENSITY 0x40 116 #define SEC_SIZE_CODE (fdctlr.c_csb->csb_unit]->un_chars->medium ? 3 : 2) 117 #define CMD_READ (MT + SK + FDRAW_RDCMD + MFM) 118 #define CMD_WRITE (MT + FDRAW_WRCMD + MFM) 119 #define C CE_CONT 120 #define FD_POLLABLE_PROP "pollable" /* prom property */ 121 #define FD_MANUAL_EJECT "manual" /* prom property */ 122 #define FD_UNIT "unit" /* prom property */ 123 124 /* 125 * Sony MP-F17W-50D Drive Parameters 126 * High Capacity 127 * Capacity unformatted 2Mb 128 * Capacity formatted 1.47Mb 129 * Encoding method MFM 130 * Recording density 17434 bpi 131 * Track density 135 tpi 132 * Cylinders 80 133 * Heads 2 134 * Tracks 160 135 * Rotational speed 300 rpm 136 * Transfer rate 250/500 kbps 137 * Latency (average) 100 ms 138 * Access time 139 * Average 95 ms 140 * Track to track 3 ms 141 * Head settling time 15 ms 142 * Motor start time 500 ms 143 * Head load time ? ms 144 */ 145 146 /* 147 * The max_fd_dma_len is used only when southbridge is present. 148 * It has been observed that when IFB tests are run the floppy dma could get 149 * starved and result in underrun errors. After experimenting it was found that 150 * doing dma in chunks of 2048 works OK. 151 * The reason for making this a global variable is that there could be 152 * situations under which the customer would like to get full performance 153 * from floppy. He may not be having IFB boards that cause underrun errors. 154 * Under those conditions we could set this value to a much higher value 155 * by editing /etc/system file. 156 */ 157 int max_fd_dma_len = 2048; 158 159 static void quiesce_fd_interrupt(struct fdctlr *); 160 161 /* 162 * Character/block entry points function prototypes 163 */ 164 static int fd_open(dev_t *, int, int, cred_t *); 165 static int fd_close(dev_t, int, int, cred_t *); 166 static int fd_strategy(struct buf *); 167 static int fd_read(dev_t, struct uio *, cred_t *); 168 static int fd_write(dev_t, struct uio *, cred_t *); 169 static int fd_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 170 static int 171 fd_prop_op(dev_t, dev_info_t *, ddi_prop_op_t, int, char *, caddr_t, int *); 172 173 /* 174 * Device operations (dev_ops) entries function prototypes 175 */ 176 static int fd_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, 177 void **result); 178 static int fd_attach(dev_info_t *, ddi_attach_cmd_t); 179 static int fd_detach(dev_info_t *, ddi_detach_cmd_t); 180 static int fd_power(dev_info_t *dip, int component, int level); 181 182 /* 183 * Internal functions 184 */ 185 static int fd_attach_check_drive(struct fdctlr *fdc); 186 static int fd_attach_det_ctlr(dev_info_t *dip, struct fdctlr *fdc); 187 static int fd_attach_map_regs(dev_info_t *dip, struct fdctlr *fdc); 188 static int fd_attach_register_interrupts(dev_info_t *dip, struct fdctlr *fdc, 189 int *hard); 190 static int fd_build_label_vtoc(struct fdunit *, struct vtoc *); 191 static void fd_build_user_vtoc(struct fdunit *, struct vtoc *); 192 static int fdcheckdisk(struct fdctlr *fdc, int unit); 193 static int fd_check_media(dev_t dev, enum dkio_state state); 194 static void fd_cleanup(dev_info_t *dip, struct fdctlr *fdc, int hard, 195 int locks); 196 static void fdeject(struct fdctlr *, int unit); 197 static int fdexec(struct fdctlr *fdc, int flags); 198 static void fdexec_turn_on_motor(struct fdctlr *fdc, int flags, uint_t unit); 199 static int fdformat(struct fdctlr *fdc, int unit, int cyl, int hd); 200 static caddr_t fd_getauxiova(); 201 static struct fdctlr *fd_getctlr(dev_t); 202 static void fdgetcsb(struct fdctlr *); 203 static int fdgetlabel(struct fdctlr *fdc, int unit); 204 enum dkio_state fd_get_media_state(struct fdctlr *, int); 205 static uint_t fdintr_dma(); 206 static int fd_isauxiodip(dev_info_t *); 207 static uint_t fd_lointr(caddr_t arg); 208 static void fd_media_watch(void *); 209 static void fdmotoff(void *); 210 static int fd_part_is_open(struct fdunit *un, int part); 211 static int fdrawioctl(struct fdctlr *, int, intptr_t, int); 212 static int fdrecalseek(struct fdctlr *fdc, int unit, int arg, int execflg); 213 static int fdrecover(struct fdctlr *); 214 static void fdretcsb(struct fdctlr *); 215 static int fdreset(struct fdctlr *); 216 static int fdrw(struct fdctlr *fdc, int, int, int, int, int, caddr_t, uint_t); 217 static void fdselect(struct fdctlr *fdc, int unit, int onoff); 218 static int fdsensedrv(struct fdctlr *fdc, int unit); 219 static int fdsense_chng(struct fdctlr *, int unit); 220 static void fdstart(struct fdctlr *); 221 static int fdstart_dma(register struct fdctlr *fdc, caddr_t addr, uint_t len); 222 static int fd_unit_is_open(struct fdunit *); 223 static void fdunpacklabel(struct packed_label *, struct dk_label *); 224 static int fd_unbind_handle(struct fdctlr *); 225 static void fdwatch(void *); 226 static void set_rotational_speed(struct fdctlr *, int); 227 static int fd_get_media_info(struct fdunit *un, caddr_t buf, int flag); 228 static int fd_pm_lower_power(struct fdctlr *fdc); 229 static int fd_pm_raise_power(struct fdctlr *fdc); 230 static void create_pm_components(dev_info_t *dip); 231 static void set_data_count_register(struct fdctlr *fdc, uint32_t count); 232 static uint32_t get_data_count_register(struct fdctlr *fdc); 233 static void reset_dma_controller(struct fdctlr *fdc); 234 static void set_data_address_register(struct fdctlr *fdc, uint32_t address); 235 static uint32_t get_dma_control_register(struct fdctlr *fdc); 236 static void set_dma_mode(struct fdctlr *fdc, int val); 237 static void set_dma_control_register(struct fdctlr *fdc, uint32_t val); 238 static void release_sb_dma(struct fdctlr *fdc); 239 240 /* 241 * External functions 242 */ 243 extern uint_t fd_intr(caddr_t); /* defined in fd_asm.s */ 244 extern uint_t fd_fastintr(void); /* defined in fd_asm.s */ 245 extern void set_auxioreg(); 246 extern void call_debug(); 247 248 249 250 /* 251 * The following macro checks whether the device in a SUSPENDED state. 252 * As per WDD guide lines the I/O requests to a suspended device should 253 * be blocked until the device is resumed. 254 * Here we cv_wait on c_suspend_cv, and there is a cv_broadcast() in 255 * DDI_RESUME to wake up this thread. 256 * 257 * NOTE: This code is not tested because the kernel threads are suspended 258 * before the device is suspended. So there can not be any I/O requests on 259 * a suspended device until the cpr implementation changes.. 260 */ 261 262 #define CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc) \ 263 {\ 264 while (fdc->c_un->un_state == FD_STATE_SUSPENDED) {\ 265 cv_wait(&fdc->c_suspend_cv, \ 266 &fdc->c_lolock);\ 267 }\ 268 } 269 270 /* 271 * bss (uninitialized data) 272 */ 273 struct fdctlr *fdctlrs; /* linked list of controllers */ 274 275 /* 276 * initialized data 277 */ 278 279 static int fd_check_media_time = 5000000; /* 5 second state check */ 280 static int fd_pollable = 0; 281 static uchar_t rwretry = 10; 282 static uchar_t skretry = 5; 283 /* This variable allows the dynamic change of the burst size */ 284 static int fd_burstsize = DCSR_BURST_0 | DCSR_BURST_1; 285 286 static struct driver_minor_data { 287 char *name; 288 int minor; 289 int type; 290 } fd_minor [] = { 291 { "a", 0, S_IFBLK}, 292 { "b", 1, S_IFBLK}, 293 { "c", 2, S_IFBLK}, 294 { "a,raw", 0, S_IFCHR}, 295 { "b,raw", 1, S_IFCHR}, 296 { "c,raw", 2, S_IFCHR}, 297 {0} 298 }; 299 300 /* 301 * If the interrupt handler is invoked and no controllers expect an 302 * interrupt, the kernel panics. The following message is printed out. 303 */ 304 char *panic_msg = "fd_intr: unexpected interrupt\n"; 305 306 /* 307 * Specify/Configure cmd parameters 308 */ 309 static uchar_t fdspec[2] = { 0xc2, 0x33 }; /* "specify" parameters */ 310 static uchar_t fdconf[3] = { 0x64, 0x58, 0x00 }; /* "configure" parameters */ 311 312 /* When DMA is used, set the ND bit to 0 */ 313 #define SPEC_DMA_MODE 0x32 314 315 /* 316 * default characteristics 317 */ 318 static struct fd_char fdtypes[] = { 319 { /* struct fd_char fdchar_1.7MB density */ 320 0, /* medium */ 321 500, /* transfer rate */ 322 80, /* number of cylinders */ 323 2, /* number of heads */ 324 512, /* sector size */ 325 21, /* sectors per track */ 326 -1, /* (NA) # steps per data track */ 327 }, 328 { /* struct fd_char fdchar_highdens */ 329 0, /* medium */ 330 500, /* transfer rate */ 331 80, /* number of cylinders */ 332 2, /* number of heads */ 333 512, /* sector size */ 334 18, /* sectors per track */ 335 -1, /* (NA) # steps per data track */ 336 }, 337 { /* struct fd_char fdchar_meddens */ 338 1, /* medium */ 339 500, /* transfer rate */ 340 77, /* number of cylinders */ 341 2, /* number of heads */ 342 1024, /* sector size */ 343 8, /* sectors per track */ 344 -1, /* (NA) # steps per data track */ 345 }, 346 { /* struct fd_char fdchar_lowdens */ 347 0, /* medium */ 348 250, /* transfer rate */ 349 80, /* number of cylinders */ 350 2, /* number of heads */ 351 512, /* sector size */ 352 9, /* sectors per track */ 353 -1, /* (NA) # steps per data track */ 354 } 355 }; 356 357 358 static int nfdtypes = sizeof (fdtypes) / sizeof (fdtypes[0]); 359 360 361 /* 362 * Default Label & partition maps 363 */ 364 365 static struct packed_label fdlbl_high_21 = { 366 { "3.5\" floppy cyl 80 alt 0 hd 2 sec 21" }, 367 300, /* rotations per minute */ 368 80, /* # physical cylinders */ 369 0, /* alternates per cylinder */ 370 1, /* interleave factor */ 371 80, /* # of data cylinders */ 372 0, /* # of alternate cylinders */ 373 2, /* # of heads in this partition */ 374 21, /* # of 512 byte sectors per track */ 375 { 376 { 0, 79 * 2 * 21 }, /* part 0 - all but last cyl */ 377 { 79, 1 * 2 * 21 }, /* part 1 - just the last cyl */ 378 { 0, 80 * 2 * 21 }, /* part 2 - "the whole thing" */ 379 }, 380 { 0, /* version */ 381 "", /* volume label */ 382 3, /* no. of partitions */ 383 { 0 }, /* partition hdrs, sec 2 */ 384 { 0 }, /* mboot info. unsupported */ 385 VTOC_SANE, /* verify vtoc sanity */ 386 { 0 }, /* reserved space */ 387 0, /* timestamp */ 388 }, 389 }; 390 391 static struct packed_label fdlbl_high_80 = { 392 { "3.5\" floppy cyl 80 alt 0 hd 2 sec 18" }, 393 300, /* rotations per minute */ 394 80, /* # physical cylinders */ 395 0, /* alternates per cylinder */ 396 1, /* interleave factor */ 397 80, /* # of data cylinders */ 398 0, /* # of alternate cylinders */ 399 2, /* # of heads in this partition */ 400 18, /* # of 512 byte sectors per track */ 401 { 402 { 0, 79 * 2 * 18 }, /* part 0 - all but last cyl */ 403 { 79, 1 * 2 * 18 }, /* part 1 - just the last cyl */ 404 { 0, 80 * 2 * 18 }, /* part 2 - "the whole thing" */ 405 }, 406 { 0, /* version */ 407 "", /* volume label */ 408 3, /* no. of partitions */ 409 { 0 }, /* partition hdrs, sec 2 */ 410 { 0 }, /* mboot info. unsupported */ 411 VTOC_SANE, /* verify vtoc sanity */ 412 { 0 }, /* reserved space */ 413 0, /* timestamp */ 414 }, 415 }; 416 417 /* 418 * A medium density diskette has 1024 byte sectors. The dk_label structure 419 * assumes a sector is DEVBSIZE (512) bytes. 420 */ 421 static struct packed_label fdlbl_medium_80 = { 422 { "3.5\" floppy cyl 77 alt 0 hd 2 sec 8" }, 423 360, /* rotations per minute */ 424 77, /* # physical cylinders */ 425 0, /* alternates per cylinder */ 426 1, /* interleave factor */ 427 77, /* # of data cylinders */ 428 0, /* # of alternate cylinders */ 429 2, /* # of heads in this partition */ 430 16, /* # of 512 byte sectors per track */ 431 { 432 { 0, 76 * 2 * 8 * 2 }, /* part 0 - all but last cyl */ 433 { 76, 1 * 2 * 8 * 2 }, /* part 1 - just the last cyl */ 434 { 0, 77 * 2 * 8 * 2 }, /* part 2 - "the whole thing" */ 435 }, 436 { 0, /* version */ 437 "", /* volume label */ 438 3, /* no. of partitions */ 439 { 0 }, /* partition hdrs, sec 2 */ 440 { 0 }, /* mboot info. unsupported */ 441 VTOC_SANE, /* verify vtoc sanity */ 442 { 0 }, /* reserved space */ 443 0, /* timestamp */ 444 }, 445 }; 446 447 static struct packed_label fdlbl_low_80 = { 448 { "3.5\" floppy cyl 80 alt 0 hd 2 sec 9" }, 449 300, /* rotations per minute */ 450 80, /* # physical cylinders */ 451 0, /* alternates per cylinder */ 452 1, /* interleave factor */ 453 80, /* # of data cylinders */ 454 0, /* # of alternate cylinders */ 455 2, /* # of heads in this partition */ 456 9, /* # of 512 byte sectors per track */ 457 { 458 { 0, 79 * 2 * 9 }, /* part 0 - all but last cyl */ 459 { 79, 1 * 2 * 9 }, /* part 1 - just the last cyl */ 460 { 0, 80 * 2 * 9 }, /* part 2 - "the whole thing" */ 461 }, 462 { 0, /* version */ 463 "", /* volume label */ 464 3, /* no. of partitions */ 465 { 0 }, /* partition hdrs, sec 2 */ 466 { 0 }, /* mboot info. unsupported */ 467 VTOC_SANE, /* verify vtoc sanity */ 468 { 0 }, /* reserved space */ 469 0, /* timestamp */ 470 }, 471 }; 472 473 static struct fdcmdinfo { 474 char *cmdname; /* command name */ 475 uchar_t ncmdbytes; /* number of bytes of command */ 476 uchar_t nrsltbytes; /* number of bytes in result */ 477 uchar_t cmdtype; /* characteristics */ 478 } fdcmds[] = { 479 "", 0, 0, 0, /* - */ 480 "", 0, 0, 0, /* - */ 481 "read_track", 9, 7, 1, /* 2 */ 482 "specify", 3, 0, 3, /* 3 */ 483 "sense_drv_status", 2, 1, 3, /* 4 */ 484 "write", 9, 7, 1, /* 5 */ 485 "read", 9, 7, 1, /* 6 */ 486 "recalibrate", 2, 0, 2, /* 7 */ 487 "sense_int_status", 1, 2, 3, /* 8 */ 488 "write_del", 9, 7, 1, /* 9 */ 489 "read_id", 2, 7, 2, /* A */ 490 "motor_on/off", 1, 0, 4, /* B */ 491 "read_del", 9, 7, 1, /* C */ 492 "format_track", 10, 7, 1, /* D */ 493 "dump_reg", 1, 10, 4, /* E */ 494 "seek", 3, 0, 2, /* F */ 495 "", 0, 0, 0, /* - */ 496 "", 0, 0, 0, /* - */ 497 "", 0, 0, 0, /* - */ 498 "configure", 4, 0, 4, /* 13 */ 499 /* relative seek */ 500 }; 501 502 static struct cb_ops fd_cb_ops = { 503 fd_open, /* open */ 504 fd_close, /* close */ 505 fd_strategy, /* strategy */ 506 nodev, /* print */ 507 nodev, /* dump */ 508 fd_read, /* read */ 509 fd_write, /* write */ 510 fd_ioctl, /* ioctl */ 511 nodev, /* devmap */ 512 nodev, /* mmap */ 513 nodev, /* segmap */ 514 nochpoll, /* poll */ 515 fd_prop_op, /* cb_prop_op */ 516 0, /* streamtab */ 517 D_NEW | D_MP /* Driver compatibility flag */ 518 }; 519 520 static struct dev_ops fd_ops = { 521 DEVO_REV, /* devo_rev, */ 522 0, /* refcnt */ 523 fd_info, /* info */ 524 nulldev, /* identify */ 525 nulldev, /* probe */ 526 fd_attach, /* attach */ 527 fd_detach, /* detach */ 528 nodev, /* reset */ 529 &fd_cb_ops, /* driver operations */ 530 (struct bus_ops *)0, /* bus operations */ 531 fd_power /* power */ 532 }; 533 534 535 /* 536 * error handling 537 * 538 * for debugging, set rwretry and skretry = 1 539 * set fderrlevel to 1 540 * set fderrmask to 224 or 100644 541 * 542 * after debug set rwretry to 10, skretry to 5, and fderrlevel to 3 543 * set fderrmask to FDEM_ALL 544 * remove the define FD_DEBUG 545 * 546 */ 547 548 static unsigned int fderrmask = (unsigned int)FDEM_ALL; 549 static int fderrlevel = 3; 550 551 static int tosec = 16; /* long timeouts for sundiag for now */ 552 553 /* 554 * loadable module support 555 */ 556 557 #include <sys/modctl.h> 558 559 extern struct mod_ops mod_driverops; 560 static struct modldrv modldrv = { 561 &mod_driverops, /* Type of module. driver here */ 562 "Floppy Driver v%I%", /* Name of the module. */ 563 &fd_ops, /* Driver ops vector */ 564 }; 565 566 static struct modlinkage modlinkage = { 567 MODREV_1, 568 &modldrv, 569 NULL 570 }; 571 572 int 573 _init(void) 574 { 575 return (mod_install(&modlinkage)); 576 } 577 578 int 579 _info(struct modinfo *modinfop) 580 { 581 return (mod_info(&modlinkage, modinfop)); 582 } 583 584 int 585 _fini(void) 586 { 587 int e; 588 589 if ((e = mod_remove(&modlinkage)) != 0) 590 return (e); 591 592 /* ddi_soft_state_fini() */ 593 return (0); 594 } 595 596 /* ARGSUSED */ 597 static int 598 fd_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 599 { 600 struct fdctlr *fdc; 601 struct driver_minor_data *dmdp; 602 int instance = ddi_get_instance(dip); 603 int hard_intr_set = 0; 604 605 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: start\n")); 606 607 switch (cmd) { 608 case DDI_ATTACH: 609 break; 610 case DDI_RESUME: 611 612 if (!(fdc = fd_getctlr(instance << FDINSTSHIFT))) { 613 return (DDI_FAILURE); 614 } 615 quiesce_fd_interrupt(fdc); 616 if (fdc->c_fdtype & FDCTYPE_SB) 617 if (ddi_add_intr(dip, 0, &fdc->c_block, 0, 618 fdintr_dma, (caddr_t)0) != DDI_SUCCESS) { 619 return (DDI_FAILURE); 620 } 621 622 (void) pm_raise_power(dip, 0, PM_LEVEL_ON); 623 mutex_enter(&fdc->c_lolock); 624 /* 625 * Wake up any thread blocked due to I/O requests 626 * while the device was suspended. 627 */ 628 cv_broadcast(&fdc->c_suspend_cv); 629 mutex_exit(&fdc->c_lolock); 630 return (DDI_SUCCESS); 631 632 default: 633 return (DDI_FAILURE); 634 } 635 636 637 /* 638 * Check for the pollable property 639 * A pollable floppy drive currently only exists on the 640 * Sparcstation Voyager. This drive does not need to 641 * be turned on in order to sense whether or not a diskette 642 * is present. 643 */ 644 if (ddi_getprop(DDI_DEV_T_ANY, dip, 645 DDI_PROP_DONTPASS, FD_POLLABLE_PROP, 0)) 646 fd_pollable = 1; 647 648 fdc = kmem_zalloc(sizeof (*fdc), KM_SLEEP); 649 fdc->c_dip = dip; 650 651 652 fdc->c_next = fdctlrs; 653 fdctlrs = fdc; 654 655 /* Determine which type of controller is present and initialize it */ 656 if (fd_attach_det_ctlr(dip, fdc) == DDI_FAILURE) { 657 fd_cleanup(dip, fdc, hard_intr_set, 0); 658 return (DDI_FAILURE); 659 } 660 /* Finish mapping the device registers & setting up structures */ 661 if (fd_attach_map_regs(dip, fdc) == DDI_FAILURE) { 662 fd_cleanup(dip, fdc, hard_intr_set, 0); 663 return (DDI_FAILURE); 664 } 665 666 /* 667 * Initialize the DMA limit structures if it's being used. 668 */ 669 if (fdc->c_fdtype & FDCTYPE_DMA) { 670 fdc->c_fd_dma_lim.dma_attr_version = DMA_ATTR_V0; 671 fdc->c_fd_dma_lim.dma_attr_addr_lo = 0x00000000ull; 672 fdc->c_fd_dma_lim.dma_attr_addr_hi = 0xfffffffeull; 673 fdc->c_fd_dma_lim.dma_attr_count_max = 0xffffff; 674 if (fdc->c_fdtype & FDCTYPE_SB) { 675 fdc->c_fd_dma_lim.dma_attr_align = FD_SB_DMA_ALIGN; 676 } else { 677 fdc->c_fd_dma_lim.dma_attr_align = 1; 678 } 679 fdc->c_fd_dma_lim.dma_attr_burstsizes = 0x0; 680 fdc->c_fd_dma_lim.dma_attr_minxfer = 1; 681 fdc->c_fd_dma_lim.dma_attr_maxxfer = 0xffff; 682 fdc->c_fd_dma_lim.dma_attr_seg = 0xffff; 683 fdc->c_fd_dma_lim.dma_attr_sgllen = 1; 684 fdc->c_fd_dma_lim.dma_attr_granular = 512; 685 686 if (ddi_dma_alloc_handle(dip, &fdc->c_fd_dma_lim, 687 DDI_DMA_DONTWAIT, 0, &fdc->c_dmahandle) != DDI_SUCCESS) { 688 fd_cleanup(dip, fdc, hard_intr_set, 0); 689 return (DDI_FAILURE); 690 } 691 692 if (fdc->c_fdtype & FDCTYPE_SB) { 693 ddi_device_acc_attr_t dev_attr; 694 size_t rlen; 695 696 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 697 dev_attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 698 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 699 700 if (ddi_dma_mem_alloc(fdc->c_dmahandle, 701 (size_t)(32*1024), &dev_attr, DDI_DMA_CONSISTENT, 702 DDI_DMA_SLEEP, NULL, (caddr_t *)&fdc->dma_buf, 703 &rlen, &fdc->c_dma_buf_handle) != DDI_SUCCESS) { 704 fd_cleanup(dip, fdc, hard_intr_set, 0); 705 return (DDI_FAILURE); 706 } 707 708 } 709 } 710 711 712 /* Register the interrupts */ 713 if (fd_attach_register_interrupts(dip, fdc, 714 &hard_intr_set) == DDI_FAILURE) { 715 fd_cleanup(dip, fdc, hard_intr_set, 0); 716 FDERRPRINT(FDEP_L1, FDEM_ATTA, 717 (C, "fd_attach: registering interrupts failed\n")); 718 return (DDI_FAILURE); 719 } 720 721 722 /* 723 * set initial controller/drive/disk "characteristics/geometry" 724 * 725 * NOTE: The driver only supports one floppy drive. The hardware 726 * only supports one drive because there is only one auxio register 727 * for one drive. 728 */ 729 fdc->c_un = kmem_zalloc(sizeof (struct fdunit), KM_SLEEP); 730 fdc->c_un->un_chars = kmem_alloc(sizeof (struct fd_char), KM_SLEEP); 731 fdc->c_un->un_iostat = kstat_create("fd", 0, "fd0", "disk", 732 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 733 if (fdc->c_un->un_iostat) { 734 fdc->c_un->un_iostat->ks_lock = &fdc->c_lolock; 735 kstat_install(fdc->c_un->un_iostat); 736 } 737 738 fdc->c_un->un_drive = kmem_zalloc(sizeof (struct fd_drive), KM_SLEEP); 739 740 /* check for the manual eject property */ 741 if (ddi_getprop(DDI_DEV_T_ANY, dip, 742 DDI_PROP_DONTPASS, FD_MANUAL_EJECT, 0)) { 743 fdc->c_un->un_drive->fdd_ejectable = 0; 744 } else { 745 /* an absence of the property indicates auto eject */ 746 fdc->c_un->un_drive->fdd_ejectable = -1; 747 } 748 749 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: ejectable? %d\n", 750 fdc->c_un->un_drive->fdd_ejectable)); 751 752 /* 753 * Check for the drive id. If the drive id property doesn't exist 754 * then the drive id is set to 0 755 */ 756 fdc->c_un->un_unit_no = ddi_getprop(DDI_DEV_T_ANY, dip, 757 DDI_PROP_DONTPASS, FD_UNIT, 0); 758 759 760 if (fdc->c_fdtype & FDCTYPE_SB) { 761 fdc->sb_dma_channel = ddi_getprop(DDI_DEV_T_ANY, dip, 762 DDI_PROP_DONTPASS, "dma-channel", 0); 763 } 764 765 766 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: unit %d\n", 767 fdc->c_un->un_unit_no)); 768 769 /* Initially set the characteristics to high density */ 770 fdc->c_un->un_curfdtype = 1; 771 *fdc->c_un->un_chars = fdtypes[fdc->c_un->un_curfdtype]; 772 fdunpacklabel(&fdlbl_high_80, &fdc->c_un->un_label); 773 774 /* Make sure drive is present */ 775 if (fd_attach_check_drive(fdc) == DDI_FAILURE) { 776 fd_cleanup(dip, fdc, hard_intr_set, 1); 777 return (DDI_FAILURE); 778 } 779 780 for (dmdp = fd_minor; dmdp->name != NULL; dmdp++) { 781 if (ddi_create_minor_node(dip, dmdp->name, dmdp->type, 782 (instance << FDINSTSHIFT) | dmdp->minor, 783 DDI_NT_FD, 0) == DDI_FAILURE) { 784 fd_cleanup(dip, fdc, hard_intr_set, 1); 785 return (DDI_FAILURE); 786 } 787 } 788 789 create_pm_components(dip); 790 791 /* 792 * Add a zero-length attribute to tell the world we support 793 * kernel ioctls (for layered drivers) 794 */ 795 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 796 DDI_KERNEL_IOCTL, NULL, 0); 797 798 ddi_report_dev(dip); 799 800 FDERRPRINT(FDEP_L1, FDEM_ATTA, 801 (C, "attached 0x%x\n", ddi_get_instance(dip))); 802 803 return (DDI_SUCCESS); 804 } 805 806 /* 807 * Finish mapping the registers and initializing structures 808 */ 809 static int 810 fd_attach_map_regs(dev_info_t *dip, struct fdctlr *fdc) 811 { 812 ddi_device_acc_attr_t attr; 813 814 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 815 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 816 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 817 818 /* Map the DMA registers of the platform supports DMA */ 819 if (fdc->c_fdtype & FDCTYPE_SB) { 820 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&fdc->c_dma_regs, 821 0, sizeof (struct sb_dma_reg), &attr, 822 &fdc->c_handlep_dma)) { 823 return (DDI_FAILURE); 824 } 825 826 827 } else if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 828 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&fdc->c_dma_regs, 829 0, sizeof (struct cheerio_dma_reg), &attr, 830 &fdc->c_handlep_dma)) { 831 return (DDI_FAILURE); 832 } 833 } 834 835 /* Reset the DMA engine and enable floppy interrupts */ 836 reset_dma_controller(fdc); 837 set_dma_control_register(fdc, DCSR_INIT_BITS); 838 839 /* Finish initializing structures associated with the device regs */ 840 switch (fdc->c_fdtype & FDCTYPE_CTRLMASK) { 841 case FDCTYPE_82077: 842 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "type is 82077\n")); 843 /* 844 * Initialize addrs of key registers 845 */ 846 fdc->c_control = 847 (uchar_t *)&fdc->c_reg->fdc_82077_reg.fdc_control; 848 fdc->c_fifo = (uchar_t *)&fdc->c_reg->fdc_82077_reg.fdc_fifo; 849 fdc->c_dor = (uchar_t *)&fdc->c_reg->fdc_82077_reg.fdc_dor; 850 fdc->c_dir = (uchar_t *)&fdc->c_reg->fdc_82077_reg.fdc_dir; 851 852 853 FDERRPRINT(FDEP_L1, FDEM_ATTA, ((int)C, 854 (char *)"fdattach: msr/dsr at %p\n", 855 (void *)fdc->c_control)); 856 857 /* 858 * The 82077 doesn't use the first configuration parameter 859 * so let's adjust that while we know we're an 82077. 860 */ 861 fdconf[0] = 0; 862 863 quiesce_fd_interrupt(fdc); 864 break; 865 default: 866 break; 867 } 868 869 return (0); 870 } 871 872 /* 873 * Determine which type of floppy controller is present and 874 * initialize the registers accordingly 875 */ 876 static int 877 fd_attach_det_ctlr(dev_info_t *dip, struct fdctlr *fdc) 878 { 879 ddi_device_acc_attr_t attr; 880 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 881 /* DDI_NEVERSWAP_ACC since the controller has a byte interface. */ 882 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 883 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 884 885 FDERRPRINT(FDEP_L1, FDEM_ATTA, 886 (C, "fdattach_det_cltr: start \n")); 887 888 /* 889 * First, map in the controller's registers 890 * The controller has an 8-bit interface, so byte 891 * swapping isn't needed 892 */ 893 894 if (ddi_regs_map_setup(dip, 0, (caddr_t *)&fdc->c_reg, 895 0, sizeof (union fdcreg), 896 &attr, 897 &fdc->c_handlep_cont)) { 898 return (DDI_FAILURE); 899 } 900 901 FDERRPRINT(FDEP_L1, FDEM_ATTA, 902 (C, "fdattach_det_cltr: mapped floppy regs\n")); 903 904 905 /* 906 * Set platform specific characteristics based on the device-tree 907 * node name. 908 */ 909 910 911 if (strcmp(ddi_get_name(dip), "SUNW,fdtwo") == 0) { 912 fdc->c_fdtype |= FDCTYPE_SLAVIO; 913 fdc->c_fdtype |= FDCTYPE_82077; 914 fdc->c_auxiova = fd_getauxiova(dip); 915 fdc->c_auxiodata = (uchar_t)(AUX_MBO4M|AUX_TC4M); 916 fdc->c_auxiodata2 = (uchar_t)AUX_TC4M; 917 FDERRPRINT(FDEP_L1, FDEM_ATTA, 918 (C, "fdattach: slavio will be used!\n")); 919 920 921 /* 922 * Check the binding name to identify whether it is a South bridge based 923 * system or not. 924 */ 925 } else if (strcmp(ddi_get_name(dip), "pnpALI,1533,0") == 0) { 926 927 fdc->c_fdtype |= FDCTYPE_SB; 928 fdc->c_fdtype |= FDCTYPE_82077; 929 fdc->c_fdtype |= FDCTYPE_DMA; 930 931 FDERRPRINT(FDEP_L1, FDEM_ATTA, 932 (C, "fdattach: southbridge will be used!\n")); 933 934 /* 935 * The driver assumes high density characteristics until 936 * the diskette is looked at. 937 */ 938 939 fdc->c_fdtype |= FDCTYPE_DMA8237; 940 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: DMA used\n")); 941 942 943 } else if (strcmp(ddi_get_name(dip), "fdthree") == 0) { 944 945 fdc->c_fdtype |= FDCTYPE_CHEERIO; 946 fdc->c_fdtype |= FDCTYPE_82077; 947 948 FDERRPRINT(FDEP_L1, FDEM_ATTA, 949 (C, "fdattach: cheerio will be used!\n")); 950 /* 951 * The cheerio auxio register should be memory mapped. The 952 * auxio register on other platforms is shared and mapped 953 * elsewhere in the kernel 954 */ 955 if (ddi_regs_map_setup(dip, 2, (caddr_t *)&fdc->c_auxio_reg, 956 0, sizeof (uint_t), &attr, &fdc->c_handlep_aux)) { 957 return (DDI_FAILURE); 958 } 959 960 /* 961 * The driver assumes high density characteristics until 962 * the diskette is looked at. 963 */ 964 Set_auxio(fdc, AUX_HIGH_DENSITY); 965 FDERRPRINT(FDEP_L1, FDEM_ATTA, 966 (C, "fdattach: auxio register 0x%x\n", 967 *fdc->c_auxio_reg)); 968 969 fdc->c_fdtype |= FDCTYPE_DMA; 970 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: DMA used\n")); 971 972 } 973 974 if (fdc->c_fdtype == 0) { 975 FDERRPRINT(FDEP_L1, FDEM_ATTA, 976 (C, "fdattach: no controller!\n")); 977 return (DDI_FAILURE); 978 } else { 979 return (0); 980 } 981 } 982 983 984 /* 985 * Register the floppy interrupts 986 */ 987 static int 988 fd_attach_register_interrupts(dev_info_t *dip, struct fdctlr *fdc, int *hard) 989 { 990 ddi_iblock_cookie_t iblock_cookie_soft; 991 int status; 992 993 /* 994 * First call ddi_get_iblock_cookie() to retrieve the 995 * the interrupt block cookie so that the mutexes may 996 * be initialized before adding the interrupt. If the 997 * mutexes are initialized after adding the interrupt, there 998 * could be a race condition. 999 */ 1000 if (ddi_get_iblock_cookie(dip, 0, &fdc->c_block) != DDI_SUCCESS) { 1001 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1002 (C, "fdattach: ddi_get_iblock_cookie failed\n")); 1003 return (DDI_FAILURE); 1004 1005 } 1006 1007 /* Initialize high level mutex */ 1008 mutex_init(&fdc->c_hilock, NULL, MUTEX_DRIVER, fdc->c_block); 1009 1010 /* 1011 * Try to register fast trap handler, if unable try standard 1012 * interrupt handler, else bad 1013 */ 1014 1015 if (fdc->c_fdtype & FDCTYPE_DMA) { 1016 if (ddi_add_intr(dip, 0, &fdc->c_block, 0, 1017 fdintr_dma, (caddr_t)0) == DDI_SUCCESS) { 1018 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1019 (C, "fdattach: standard intr\n")); 1020 1021 /* 1022 * When DMA is used, the low level lock 1023 * is used in the hard interrupt handler. 1024 */ 1025 mutex_init(&fdc->c_lolock, NULL, 1026 MUTEX_DRIVER, fdc->c_block); 1027 1028 *hard = 1; 1029 } else { 1030 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1031 (C, "fdattach: can't add dma intr\n")); 1032 1033 mutex_destroy(&fdc->c_hilock); 1034 1035 return (DDI_FAILURE); 1036 } 1037 } else { 1038 /* 1039 * Platforms that don't support DMA have both hard 1040 * and soft interrupts. 1041 */ 1042 if (ddi_add_intr(dip, 0, &fdc->c_block, 0, 1043 fd_intr, (caddr_t)0) == DDI_SUCCESS) { 1044 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1045 (C, "fdattach: standard intr\n")); 1046 *hard = 1; 1047 1048 /* fast traps are not enabled */ 1049 fdc->c_fasttrap = 0; 1050 1051 } else { 1052 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1053 (C, "fdattach: can't add intr\n")); 1054 1055 mutex_destroy(&fdc->c_hilock); 1056 1057 return (DDI_FAILURE); 1058 } 1059 1060 1061 /* 1062 * Initialize the soft interrupt handler. First call 1063 * ddi_get_soft_iblock_cookie() so that the mutex may 1064 * be initialized before the handler is added. 1065 */ 1066 status = ddi_get_soft_iblock_cookie(dip, DDI_SOFTINT_LOW, 1067 &iblock_cookie_soft); 1068 1069 1070 if (status != DDI_SUCCESS) { 1071 mutex_destroy(&fdc->c_hilock); 1072 return (DDI_FAILURE); 1073 } 1074 1075 /* 1076 * Initialize low level mutex which is used in the soft 1077 * interrupt handler 1078 */ 1079 mutex_init(&fdc->c_lolock, NULL, MUTEX_DRIVER, 1080 iblock_cookie_soft); 1081 1082 if (ddi_add_softintr(dip, DDI_SOFTINT_LOW, &fdc->c_softid, 1083 NULL, NULL, 1084 fd_lointr, 1085 (caddr_t)fdc) != DDI_SUCCESS) { 1086 1087 mutex_destroy(&fdc->c_hilock); 1088 mutex_destroy(&fdc->c_lolock); 1089 1090 return (DDI_FAILURE); 1091 } 1092 } 1093 1094 fdc->c_intrstat = kstat_create("fd", 0, "fdc0", "controller", 1095 KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT); 1096 if (fdc->c_intrstat) { 1097 fdc->c_hiintct = &KIOIP->intrs[KSTAT_INTR_HARD]; 1098 kstat_install(fdc->c_intrstat); 1099 } 1100 1101 /* condition variable to wait on while an io transaction occurs */ 1102 cv_init(&fdc->c_iocv, NULL, CV_DRIVER, NULL); 1103 1104 /* condition variable for the csb */ 1105 cv_init(&fdc->c_csbcv, NULL, CV_DRIVER, NULL); 1106 1107 /* condition variable for motor on waiting period */ 1108 cv_init(&fdc->c_motoncv, NULL, CV_DRIVER, NULL); 1109 1110 /* semaphore to serialize opens and closes */ 1111 sema_init(&fdc->c_ocsem, 1, NULL, SEMA_DRIVER, NULL); 1112 1113 /* condition variable to wait on suspended floppy controller. */ 1114 cv_init(&fdc->c_suspend_cv, NULL, CV_DRIVER, NULL); 1115 1116 return (0); 1117 } 1118 1119 /* 1120 * Make sure the drive is present 1121 * - acquires the low level lock 1122 */ 1123 static int 1124 fd_attach_check_drive(struct fdctlr *fdc) 1125 { 1126 int tmp_fderrlevel; 1127 int unit = fdc->c_un->un_unit_no; 1128 1129 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1130 (C, "fd_attach_check_drive\n")); 1131 1132 1133 mutex_enter(&fdc->c_lolock); 1134 switch (fdc->c_fdtype & FDCTYPE_CTRLMASK) { 1135 1136 /* insure that the eject line is reset */ 1137 case FDCTYPE_82077: 1138 1139 /* 1140 * Everything but the motor enable, drive select, 1141 * and reset bits are turned off. These three 1142 * bits remain as they are. 1143 */ 1144 /* LINTED */ 1145 Set_dor(fdc, ~((MOTEN(unit))|DRVSEL|RESET), 0); 1146 1147 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1148 (C, "fdattach: Dor 0x%x\n", Dor(fdc))); 1149 1150 drv_usecwait(5); 1151 if (unit == 0) { 1152 /* LINTED */ 1153 Set_dor(fdc, RESET|DRVSEL, 1); 1154 } else { 1155 1156 /* LINTED */ 1157 Set_dor(fdc, DRVSEL, 0); 1158 /* LINTED */ 1159 Set_dor(fdc, RESET, 1); 1160 } 1161 1162 drv_usecwait(5); 1163 1164 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1165 (C, "fdattach: Dor 0x%x\n", Dor(fdc))); 1166 1167 if (!((fdc->c_fdtype & FDCTYPE_CHEERIO) || 1168 (fdc->c_fdtype & FDCTYPE_SB))) { 1169 set_auxioreg(AUX_TC4M, 0); 1170 } 1171 break; 1172 default: 1173 break; 1174 } 1175 1176 1177 fdgetcsb(fdc); 1178 if (fdreset(fdc) != 0) { 1179 mutex_exit(&fdc->c_lolock); 1180 return (DDI_FAILURE); 1181 } 1182 1183 1184 /* check for drive present */ 1185 1186 tmp_fderrlevel = fderrlevel; 1187 1188 1189 fderrlevel = FDEP_LMAX; 1190 1191 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1192 (C, "fdattach: call fdrecalseek\n")); 1193 1194 /* Make sure the drive is present */ 1195 if (fdrecalseek(fdc, unit, -1, 0) != 0) { 1196 timeout_id_t timeid = fdc->c_mtimeid; 1197 fderrlevel = tmp_fderrlevel; 1198 fdc->c_mtimeid = 0; 1199 mutex_exit(&fdc->c_lolock); 1200 1201 1202 /* Do not hold the mutex over the call to untimeout */ 1203 if (timeid) { 1204 (void) untimeout(timeid); 1205 } 1206 1207 FDERRPRINT(FDEP_L2, FDEM_ATTA, 1208 (C, "fd_attach: no drive?\n")); 1209 1210 return (DDI_FAILURE); 1211 } 1212 1213 fderrlevel = tmp_fderrlevel; 1214 1215 fdselect(fdc, unit, 0); /* deselect drive zero (used in fdreset) */ 1216 fdretcsb(fdc); 1217 mutex_exit(&fdc->c_lolock); 1218 1219 return (0); 1220 } 1221 1222 /* 1223 * Clean up routine used by fd_detach and fd_attach 1224 * 1225 * Note: if the soft id is non-zero, then ddi_add_softintr() completed 1226 * successfully. I can not make the same assumption about the iblock_cookie 1227 * for the high level interrupt handler. So, the hard parameter indicates 1228 * whether or not a high level interrupt handler has been added. 1229 * 1230 * If the locks parameter is nonzero, then all mutexes, semaphores and 1231 * condition variables will be destroyed. 1232 * 1233 * Does not assume the low level mutex is held. 1234 * 1235 */ 1236 static void 1237 fd_cleanup(dev_info_t *dip, struct fdctlr *fdc, int hard, int locks) 1238 { 1239 1240 1241 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1242 (C, "fd_cleanup instance: %d ctlr: 0x%x\n", 1243 ddi_get_instance(dip), (int)fdc)); 1244 1245 1246 if (fdc == NULL) { 1247 return; 1248 } 1249 1250 /* 1251 * Remove interrupt handlers first before anything else 1252 * is deallocated. 1253 */ 1254 1255 /* Remove hard interrupt if one is registered */ 1256 if (hard) { 1257 ddi_remove_intr(dip, (uint_t)0, fdc->c_block); 1258 } 1259 1260 /* Remove soft interrupt if one is registered */ 1261 if (fdc->c_softid != NULL) 1262 ddi_remove_softintr(fdc->c_softid); 1263 1264 1265 /* Remove timers */ 1266 if (fdc->c_fdtype & FDCTYPE_82077) { 1267 if (fdc->c_mtimeid) 1268 (void) untimeout(fdc->c_mtimeid); 1269 /* 1270 * Need to turn off motor (includes select/LED for South Bridge 1271 * chipset) just in case it was on when timer was removed 1272 */ 1273 fdmotoff(fdc); 1274 } 1275 if (fdc->c_timeid) 1276 (void) untimeout(fdc->c_timeid); 1277 1278 1279 /* Remove memory handles */ 1280 if (fdc->c_handlep_cont) 1281 ddi_regs_map_free(&fdc->c_handlep_cont); 1282 1283 if (fdc->c_handlep_aux) 1284 ddi_regs_map_free(&fdc->c_handlep_aux); 1285 1286 if (fdc->c_handlep_dma) 1287 ddi_regs_map_free(&fdc->c_handlep_dma); 1288 1289 if (fdc->c_dma_buf_handle != NULL) 1290 ddi_dma_mem_free(&fdc->c_dma_buf_handle); 1291 1292 if (fdc->c_dmahandle != NULL) 1293 ddi_dma_free_handle(&fdc->c_dmahandle); 1294 1295 1296 /* Remove all minor nodes */ 1297 ddi_remove_minor_node(dip, NULL); 1298 1299 1300 1301 /* Remove unit structure if one exists */ 1302 if (fdc->c_un != (struct fdunit *)NULL) { 1303 1304 ASSERT(!mutex_owned(&fdc->c_lolock)); 1305 1306 if (fdc->c_un->un_iostat) 1307 kstat_delete(fdc->c_un->un_iostat); 1308 fdc->c_un->un_iostat = NULL; 1309 1310 if (fdc->c_un->un_chars) 1311 kmem_free(fdc->c_un->un_chars, sizeof (struct fd_char)); 1312 1313 if (fdc->c_un->un_drive) 1314 kmem_free(fdc->c_un->un_drive, 1315 sizeof (struct fd_drive)); 1316 1317 kmem_free((caddr_t)fdc->c_un, sizeof (struct fdunit)); 1318 } 1319 1320 if (fdc->c_intrstat) { 1321 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1322 (C, "fd_cleanup: delete intrstat\n")); 1323 1324 kstat_delete(fdc->c_intrstat); 1325 } 1326 1327 fdc->c_intrstat = NULL; 1328 1329 if (locks) { 1330 cv_destroy(&fdc->c_iocv); 1331 cv_destroy(&fdc->c_csbcv); 1332 cv_destroy(&fdc->c_motoncv); 1333 cv_destroy(&fdc->c_suspend_cv); 1334 sema_destroy(&fdc->c_ocsem); 1335 mutex_destroy(&fdc->c_hilock); 1336 mutex_destroy(&fdc->c_lolock); 1337 } 1338 1339 1340 fdctlrs = fdc->c_next; 1341 kmem_free(fdc, sizeof (*fdc)); 1342 1343 1344 } 1345 1346 1347 static int 1348 fd_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1349 { 1350 int instance = ddi_get_instance(dip); 1351 struct fdctlr *fdc = fd_getctlr(instance << FDINSTSHIFT); 1352 timeout_id_t c_mtimeid; 1353 1354 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_detach\n")); 1355 1356 switch (cmd) { 1357 1358 case DDI_DETACH: 1359 /* 1360 * The hard parameter is set to 1. If detach is called, then 1361 * attach must have passed meaning that the high level 1362 * interrupt handler was successfully added. 1363 * Similarly, the locks parameter is also set to 1. 1364 */ 1365 fd_cleanup(dip, fdc, 1, 1); 1366 1367 ddi_prop_remove_all(dip); 1368 1369 return (DDI_SUCCESS); 1370 1371 case DDI_SUSPEND: 1372 if (!fdc) 1373 return (DDI_FAILURE); 1374 1375 1376 mutex_enter(&fdc->c_lolock); 1377 fdgetcsb(fdc); /* Wait for I/O to finish */ 1378 c_mtimeid = fdc->c_mtimeid; 1379 fdretcsb(fdc); 1380 mutex_exit(&fdc->c_lolock); 1381 1382 (void) untimeout(c_mtimeid); 1383 /* 1384 * After suspend, the system could be powered off. 1385 * When it is later powered on the southbridge floppy 1386 * controller will tristate the interrupt line causing 1387 * continuous dma interrupts. 1388 * To avoid getting continuous fd interrupts we will remove the 1389 * dma interrupt handler installed. We will re-install the 1390 * handler when we RESUME. 1391 */ 1392 if (fdc->c_fdtype & FDCTYPE_SB) 1393 ddi_remove_intr(dip, 0, fdc->c_block); 1394 1395 fdc->c_un->un_state = FD_STATE_SUSPENDED; 1396 1397 return (DDI_SUCCESS); 1398 1399 default: 1400 return (DDI_FAILURE); 1401 } 1402 } 1403 1404 /* ARGSUSED */ 1405 static int 1406 fd_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 1407 { 1408 register struct fdctlr *fdc; 1409 register int error; 1410 1411 switch (infocmd) { 1412 1413 case DDI_INFO_DEVT2DEVINFO: 1414 if ((fdc = fd_getctlr((dev_t)arg)) == NULL) { 1415 error = DDI_FAILURE; 1416 } else { 1417 *result = fdc->c_dip; 1418 error = DDI_SUCCESS; 1419 } 1420 break; 1421 1422 case DDI_INFO_DEVT2INSTANCE: 1423 *result = 0; 1424 error = DDI_SUCCESS; 1425 break; 1426 1427 default: 1428 error = DDI_FAILURE; 1429 } 1430 return (error); 1431 } 1432 1433 /* 1434 * property operation routine. return the number of blocks for the partition 1435 * in question or forward the request to the property facilities. 1436 */ 1437 static int 1438 fd_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, int mod_flags, 1439 char *name, caddr_t valuep, int *lengthp) 1440 { 1441 struct fdunit *un; 1442 struct fdctlr *fdc; 1443 uint64_t nblocks64; 1444 1445 /* 1446 * Our dynamic properties are all device specific and size oriented. 1447 * Requests issued under conditions where size is valid are passed 1448 * to ddi_prop_op_nblocks with the size information, otherwise the 1449 * request is passed to ddi_prop_op. 1450 */ 1451 if (dev == DDI_DEV_T_ANY) { 1452 pass: return (ddi_prop_op(dev, dip, prop_op, mod_flags, 1453 name, valuep, lengthp)); 1454 } else { 1455 fdc = fd_getctlr(dev); 1456 if (fdc == NULL) 1457 goto pass; 1458 1459 /* we have size if diskette opened and label read */ 1460 un = fdc->c_un; 1461 if ((un == NULL) || !fd_unit_is_open(fdc->c_un)) 1462 goto pass; 1463 1464 /* get nblocks value */ 1465 nblocks64 = (ulong_t) 1466 un->un_label.dkl_map[FDPARTITION(dev)].dkl_nblk; 1467 1468 return (ddi_prop_op_nblocks(dev, dip, prop_op, mod_flags, 1469 name, valuep, lengthp, nblocks64)); 1470 } 1471 } 1472 1473 /* ARGSUSED3 */ 1474 static int 1475 fd_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 1476 { 1477 dev_t dev; 1478 int part; 1479 struct fdctlr *fdc; 1480 struct fdunit *un; 1481 struct dk_map32 *dkm; 1482 uchar_t pbit; 1483 int err, part_is_open; 1484 int unit; 1485 1486 dev = *devp; 1487 fdc = fd_getctlr(dev); 1488 if ((fdc == NULL) || ((un = fdc->c_un) == NULL)) { 1489 return (ENXIO); 1490 } 1491 1492 unit = fdc->c_un->un_unit_no; 1493 1494 /* 1495 * Serialize opens/closes 1496 */ 1497 1498 sema_p(&fdc->c_ocsem); 1499 1500 /* check partition */ 1501 part = FDPARTITION(dev); 1502 pbit = 1 << part; 1503 dkm = &un->un_label.dkl_map[part]; 1504 if (dkm->dkl_nblk == 0) { 1505 sema_v(&fdc->c_ocsem); 1506 return (ENXIO); 1507 } 1508 1509 FDERRPRINT(FDEP_L1, FDEM_OPEN, 1510 (C, "fdopen: ctlr %d unit %d part %d\n", 1511 ddi_get_instance(fdc->c_dip), unit, part)); 1512 1513 FDERRPRINT(FDEP_L1, FDEM_OPEN, 1514 (C, "fdopen: flag 0x%x", flag)); 1515 1516 1517 /* 1518 * Insure that drive is present with a recalibrate on first open. 1519 */ 1520 (void) pm_busy_component(fdc->c_dip, 0); 1521 1522 mutex_enter(&fdc->c_lolock); 1523 1524 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 1525 1526 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 1527 mutex_exit(&fdc->c_lolock); 1528 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 1529 != DDI_SUCCESS) { 1530 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power change \ 1531 failed. \n")); 1532 1533 sema_v(&fdc->c_ocsem); 1534 (void) pm_idle_component(fdc->c_dip, 0); 1535 return (EIO); 1536 } 1537 mutex_enter(&fdc->c_lolock); 1538 } 1539 if (fd_unit_is_open(un) == 0) { 1540 fdgetcsb(fdc); 1541 /* 1542 * no check changed! 1543 */ 1544 err = fdrecalseek(fdc, unit, -1, 0); 1545 fdretcsb(fdc); 1546 if (err) { 1547 FDERRPRINT(FDEP_L3, FDEM_OPEN, 1548 (C, "fd%d: drive not ready\n", 0)); 1549 /* deselect drv on last close */ 1550 fdselect(fdc, unit, 0); 1551 mutex_exit(&fdc->c_lolock); 1552 sema_v(&fdc->c_ocsem); 1553 (void) pm_idle_component(fdc->c_dip, 0); 1554 return (EIO); 1555 } 1556 } 1557 1558 /* 1559 * Check for previous exclusive open, or trying to exclusive open 1560 */ 1561 if (otyp == OTYP_LYR) { 1562 part_is_open = (un->un_lyropen[part] != 0); 1563 } else { 1564 part_is_open = fd_part_is_open(un, part); 1565 } 1566 if ((un->un_exclmask & pbit) || ((flag & FEXCL) && part_is_open)) { 1567 mutex_exit(&fdc->c_lolock); 1568 sema_v(&fdc->c_ocsem); 1569 FDERRPRINT(FDEP_L2, FDEM_OPEN, (C, "fd:just return\n")); 1570 (void) pm_idle_component(fdc->c_dip, 0); 1571 return (EBUSY); 1572 } 1573 1574 /* don't attempt access, just return successfully */ 1575 if (flag & (FNDELAY | FNONBLOCK)) { 1576 FDERRPRINT(FDEP_L2, FDEM_OPEN, 1577 (C, "fd: return busy..\n")); 1578 goto out; 1579 } 1580 1581 fdc->c_csb.csb_unit = (uchar_t)unit; 1582 if (fdgetlabel(fdc, unit)) { 1583 /* didn't find label (couldn't read anything) */ 1584 FDERRPRINT(FDEP_L3, FDEM_OPEN, 1585 (C, 1586 "fd%d: unformatted diskette or no diskette in the drive\n", 1587 0)); 1588 if (fd_unit_is_open(un) == 0) { 1589 /* deselect drv on last close */ 1590 fdselect(fdc, unit, 0); 1591 } 1592 1593 mutex_exit(&fdc->c_lolock); 1594 sema_v(&fdc->c_ocsem); 1595 (void) pm_idle_component(fdc->c_dip, 0); 1596 return (EIO); 1597 } 1598 1599 /* 1600 * if opening for writing, check write protect on diskette 1601 */ 1602 if (flag & FWRITE) { 1603 fdgetcsb(fdc); 1604 err = fdsensedrv(fdc, unit) & WP_SR3; 1605 fdretcsb(fdc); 1606 if (err) { 1607 if (fd_unit_is_open(un) == 0) 1608 fdselect(fdc, unit, 0); 1609 mutex_exit(&fdc->c_lolock); 1610 sema_v(&fdc->c_ocsem); 1611 (void) pm_idle_component(fdc->c_dip, 0); 1612 return (EROFS); 1613 } 1614 } 1615 1616 out: 1617 /* 1618 * mark open as having succeeded 1619 */ 1620 if (flag & FEXCL) { 1621 un->un_exclmask |= pbit; 1622 } 1623 if (otyp == OTYP_LYR) { 1624 un->un_lyropen[part]++; 1625 } else { 1626 un->un_regopen[otyp] |= pbit; 1627 } 1628 mutex_exit(&fdc->c_lolock); 1629 sema_v(&fdc->c_ocsem); 1630 (void) pm_idle_component(fdc->c_dip, 0); 1631 return (0); 1632 } 1633 /* 1634 * fd_part_is_open 1635 * return 1 if the partition is open 1636 * return 0 otherwise 1637 */ 1638 static int 1639 fd_part_is_open(struct fdunit *un, int part) 1640 { 1641 int i; 1642 for (i = 0; i < OTYPCNT - 1; i++) 1643 if (un->un_regopen[i] & (1 << part)) 1644 return (1); 1645 return (0); 1646 } 1647 1648 1649 /* ARGSUSED */ 1650 static int 1651 fd_close(dev_t dev, int flag, int otyp, cred_t *cred_p) 1652 { 1653 int unit, part_is_closed, part; 1654 register struct fdctlr *fdc; 1655 register struct fdunit *un; 1656 1657 fdc = fd_getctlr(dev); 1658 if (!fdc || !(un = fdc->c_un)) 1659 return (ENXIO); 1660 1661 1662 unit = fdc->c_un->un_unit_no; 1663 FDERRPRINT(FDEP_L1, FDEM_CLOS, (C, "fd_close\n")); 1664 part = FDPARTITION(dev); 1665 1666 sema_p(&fdc->c_ocsem); 1667 mutex_enter(&fdc->c_lolock); 1668 1669 if (otyp == OTYP_LYR) { 1670 un->un_lyropen[part]--; 1671 part_is_closed = (un->un_lyropen[part] == 0); 1672 } else { 1673 un->un_regopen[otyp] &= ~(1<<part); 1674 part_is_closed = 1; 1675 } 1676 if (part_is_closed) 1677 un->un_exclmask &= ~(1<<part); 1678 1679 if (fd_unit_is_open(un) == 0) { 1680 /* deselect drive on last close */ 1681 fdselect(fdc, unit, 0); 1682 un->un_flags &= ~FDUNIT_CHANGED; 1683 } 1684 mutex_exit(&fdc->c_lolock); 1685 sema_v(&fdc->c_ocsem); 1686 1687 return (0); 1688 } 1689 1690 /* 1691 * fd_strategy 1692 * checks operation, hangs buf struct off fdctlr, calls fdstart 1693 * if not already busy. Note that if we call start, then the operation 1694 * will already be done on return (start sleeps). 1695 */ 1696 static int 1697 fd_strategy(register struct buf *bp) 1698 { 1699 struct fdctlr *fdc; 1700 struct fdunit *un; 1701 uint_t phys_blkno; 1702 struct dk_map32 *dkm; 1703 1704 FDERRPRINT(FDEP_L1, FDEM_STRA, 1705 (C, "fd_strategy: bp = 0x%p, dev = 0x%lx\n", 1706 (void *)bp, bp->b_edev)); 1707 FDERRPRINT(FDEP_L1, FDEM_STRA, 1708 (C, "b_blkno=%x b_flags=%x b_count=%x\n", 1709 (int)bp->b_blkno, bp->b_flags, (int)bp->b_bcount)); 1710 fdc = fd_getctlr(bp->b_edev); 1711 un = fdc->c_un; 1712 dkm = &un->un_label.dkl_map[FDPARTITION(bp->b_edev)]; 1713 1714 /* 1715 * If it's medium density and the block no. isn't a multiple 1716 * of 1K, then return an error. 1717 */ 1718 if (un->un_chars->fdc_medium) { 1719 phys_blkno = (uint_t)bp->b_blkno >> 1; 1720 if (bp->b_blkno & 1) { 1721 FDERRPRINT(FDEP_L3, FDEM_STRA, 1722 (C, "b_blkno=0x%lx is not 1k aligned\n", 1723 (long)bp->b_blkno)); 1724 bp->b_error = EINVAL; 1725 bp->b_resid = bp->b_bcount; 1726 bp->b_flags |= B_ERROR; 1727 biodone(bp); 1728 return (0); 1729 } 1730 } else { 1731 phys_blkno = (uint_t)bp->b_blkno; 1732 } 1733 1734 1735 /* If the block number is past the end, return an error */ 1736 if ((phys_blkno > dkm->dkl_nblk)) { 1737 FDERRPRINT(FDEP_L3, FDEM_STRA, 1738 (C, "fd%d: block %ld is past the end! (nblk=%d)\n", 1739 0, (long)bp->b_blkno, dkm->dkl_nblk)); 1740 bp->b_error = ENOSPC; 1741 bp->b_resid = bp->b_bcount; 1742 bp->b_flags |= B_ERROR; 1743 biodone(bp); 1744 return (0); 1745 } 1746 1747 /* if at end of file, skip out now */ 1748 if (phys_blkno == dkm->dkl_nblk) { 1749 FDERRPRINT(FDEP_L1, FDEM_STRA, 1750 (C, "b_blkno is at the end!\n")); 1751 1752 if ((bp->b_flags & B_READ) == 0) { 1753 /* a write needs to get an error! */ 1754 bp->b_error = ENOSPC; 1755 bp->b_flags |= B_ERROR; 1756 1757 FDERRPRINT(FDEP_L1, FDEM_STRA, 1758 (C, "block is at end and this is a write\n")); 1759 1760 } 1761 1762 bp->b_resid = bp->b_bcount; 1763 biodone(bp); 1764 return (0); 1765 } 1766 1767 /* if operation not a multiple of sector size, is error! */ 1768 if (bp->b_bcount % un->un_chars->fdc_sec_size) { 1769 FDERRPRINT(FDEP_L3, FDEM_STRA, 1770 (C, "fd%d: requested transfer size(0x%lx) is not" 1771 " multiple of sector size(0x%x)\n", 0, 1772 bp->b_bcount, un->un_chars->fdc_sec_size)); 1773 FDERRPRINT(FDEP_L3, FDEM_STRA, 1774 (C, " b_blkno=0x%lx b_flags=0x%x\n", 1775 (long)bp->b_blkno, bp->b_flags)); 1776 bp->b_error = EINVAL; 1777 bp->b_resid = bp->b_bcount; 1778 bp->b_flags |= B_ERROR; 1779 biodone(bp); 1780 return (0); 1781 1782 } 1783 1784 /* 1785 * Put the buf request in the controller's queue, FIFO. 1786 */ 1787 bp->av_forw = 0; 1788 sema_p(&fdc->c_ocsem); 1789 1790 (void) pm_busy_component(fdc->c_dip, 0); 1791 1792 mutex_enter(&fdc->c_lolock); 1793 1794 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 1795 1796 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 1797 mutex_exit(&fdc->c_lolock); 1798 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 1799 != DDI_SUCCESS) { 1800 sema_v(&fdc->c_ocsem); 1801 (void) pm_idle_component(fdc->c_dip, 0); 1802 bp->b_error = EIO; 1803 bp->b_resid = bp->b_bcount; 1804 bp->b_flags |= B_ERROR; 1805 biodone(bp); 1806 return (0); 1807 } else { 1808 mutex_enter(&fdc->c_lolock); 1809 } 1810 } 1811 if (un->un_iostat) { 1812 kstat_waitq_enter(KIOSP); 1813 } 1814 if (fdc->c_actf) 1815 fdc->c_actl->av_forw = bp; 1816 else 1817 fdc->c_actf = bp; 1818 fdc->c_actl = bp; 1819 1820 1821 /* call fdstart to start the transfer */ 1822 fdstart(fdc); 1823 1824 mutex_exit(&fdc->c_lolock); 1825 sema_v(&fdc->c_ocsem); 1826 (void) pm_idle_component(fdc->c_dip, 0); 1827 return (0); 1828 } 1829 1830 /* ARGSUSED2 */ 1831 static int 1832 fd_read(dev_t dev, struct uio *uio, cred_t *cred_p) 1833 { 1834 FDERRPRINT(FDEP_L1, FDEM_RDWR, (C, "fd_read\n")); 1835 return (physio(fd_strategy, NULL, dev, B_READ, minphys, uio)); 1836 } 1837 1838 /* ARGSUSED2 */ 1839 static int 1840 fd_write(dev_t dev, struct uio *uio, cred_t *cred_p) 1841 { 1842 FDERRPRINT(FDEP_L1, FDEM_RDWR, (C, "fd_write\n")); 1843 return (physio(fd_strategy, NULL, dev, B_WRITE, minphys, uio)); 1844 } 1845 1846 static void 1847 fdmotoff(void *arg) 1848 { 1849 struct fdctlr *fdc = arg; 1850 int unit = fdc->c_un->un_unit_no; 1851 1852 mutex_enter(&fdc->c_lolock); 1853 1854 /* Just return if we're about to call untimeout */ 1855 if (fdc->c_mtimeid == 0) { 1856 mutex_exit(&fdc->c_lolock); 1857 return; 1858 } 1859 1860 FDERRPRINT(FDEP_L1, FDEM_MOFF, (C, "fdmotoff\n")); 1861 1862 fdc->c_mtimeid = 0; 1863 1864 if (!(Msr(fdc) & CB) && (Dor(fdc) & (MOTEN(unit)))) { 1865 /* LINTED */ 1866 Set_dor(fdc, MOTEN(unit), 0); 1867 } 1868 1869 mutex_exit(&fdc->c_lolock); 1870 } 1871 1872 /* ARGSUSED */ 1873 static int 1874 fd_ioctl(dev_t dev, int cmd, intptr_t arg, int flag, 1875 cred_t *cred_p, int *rval_p) 1876 { 1877 union { 1878 struct dk_cinfo dki; 1879 struct dk_geom dkg; 1880 struct dk_allmap32 dka; 1881 struct fd_char fdchar; 1882 struct fd_drive drvchar; 1883 int temp; 1884 } cpy; 1885 1886 struct vtoc vtoc; 1887 struct fdunit *un; 1888 struct fdctlr *fdc; 1889 int unit, dkunit; 1890 int err = 0; 1891 uint_t sec_size; 1892 enum dkio_state state; 1893 int transfer_rate; 1894 1895 FDERRPRINT(FDEP_L1, FDEM_IOCT, 1896 (C, "fd_ioctl: cmd 0x%x, arg 0x%lx\n", cmd, (long)arg)); 1897 1898 /* The minor number should always be 0 */ 1899 if (FDUNIT(dev) != 0) 1900 return (ENXIO); 1901 1902 fdc = fd_getctlr(dev); 1903 unit = fdc->c_un->un_unit_no; 1904 un = fdc->c_un; 1905 sec_size = un->un_chars->fdc_sec_size; 1906 bzero(&cpy, sizeof (cpy)); 1907 1908 switch (cmd) { 1909 case DKIOCINFO: 1910 cpy.dki.dki_addr = 0; 1911 1912 /* 1913 * The meaning of the dki_slave and dki_unit fields 1914 * is unclear. The sparc floppy driver follows the same 1915 * convention as sd.c in that the instance number is 1916 * returned in the dki_cnum field. The dki_slave field is 1917 * ignored. 1918 * 1919 * The dki_cnum contains the controller instance 1920 * and its value can be any positive number. Even 1921 * though currently Sparc platforms only support 1922 * one controller, the controller instance number 1923 * can be any number since it is assigned by the 1924 * system depending on the device properties. 1925 */ 1926 1927 cpy.dki.dki_cnum = FDCTLR(dev); 1928 1929 /* 1930 * Sparc platforms support only one floppy drive. 1931 * The device node for the controller is the same as 1932 * the device node for the drive. The x86 driver is 1933 * different in that it has a node for the controller 1934 * and a child node for each drive. Since Sparc supports 1935 * only one drive, the unit number will always be zero. 1936 */ 1937 1938 cpy.dki.dki_unit = FDUNIT(dev); 1939 1940 /* 1941 * The meaning of the dki_slave field is unclear. 1942 * So, I will leave it set to 0. 1943 */ 1944 1945 cpy.dki.dki_slave = 0; 1946 1947 cpy.dki.dki_ctype = (ushort_t)-1; 1948 if (fdc->c_fdtype & FDCTYPE_82077) 1949 cpy.dki.dki_ctype = DKC_INTEL82077; 1950 cpy.dki.dki_flags = DKI_FMTTRK; 1951 cpy.dki.dki_partition = FDPARTITION(dev); 1952 cpy.dki.dki_maxtransfer = maxphys / DEV_BSIZE; 1953 if (ddi_copyout((caddr_t)&cpy.dki, (caddr_t)arg, 1954 sizeof (cpy.dki), flag)) 1955 err = EFAULT; 1956 break; 1957 case DKIOCGGEOM: 1958 cpy.dkg.dkg_ncyl = un->un_chars->fdc_ncyl; 1959 cpy.dkg.dkg_nhead = un->un_chars->fdc_nhead; 1960 cpy.dkg.dkg_nsect = un->un_chars->fdc_secptrack; 1961 cpy.dkg.dkg_intrlv = un->un_label.dkl_intrlv; 1962 cpy.dkg.dkg_rpm = un->un_label.dkl_rpm; 1963 cpy.dkg.dkg_pcyl = un->un_chars->fdc_ncyl; 1964 cpy.dkg.dkg_read_reinstruct = 1965 (int)(cpy.dkg.dkg_nsect * cpy.dkg.dkg_rpm * 4) / 60000; 1966 cpy.dkg.dkg_write_reinstruct = cpy.dkg.dkg_read_reinstruct; 1967 if (ddi_copyout((caddr_t)&cpy.dkg, (caddr_t)arg, 1968 sizeof (cpy.dkg), flag)) 1969 err = EFAULT; 1970 break; 1971 case DKIOCSGEOM: 1972 FDERRPRINT(FDEP_L3, FDEM_IOCT, 1973 (C, "fd_ioctl: DKIOCSGEOM not supported\n")); 1974 err = ENOTTY; 1975 break; 1976 1977 /* 1978 * return the map of all logical partitions 1979 */ 1980 case DKIOCGAPART: 1981 /* 1982 * We don't have anything to do if the application is ILP32 1983 * because the label map has a 32-bit format. Otherwise 1984 * convert. 1985 */ 1986 if ((flag & DATAMODEL_MASK) == DATAMODEL_ILP32) { 1987 if (ddi_copyout(&un->un_label.dkl_map, 1988 (void *)arg, sizeof (struct dk_allmap32), flag)) 1989 err = EFAULT; 1990 } 1991 #ifdef _MULTI_DATAMODEL 1992 else { 1993 struct dk_allmap dk_allmap; 1994 1995 ASSERT((flag & DATAMODEL_MASK) == DATAMODEL_LP64); 1996 for (dkunit = 0; dkunit < NDKMAP; dkunit++) { 1997 dk_allmap.dka_map[dkunit].dkl_cylno = 1998 un->un_label.dkl_map[dkunit].dkl_cylno; 1999 dk_allmap.dka_map[dkunit].dkl_nblk = 2000 un->un_label.dkl_map[dkunit].dkl_nblk; 2001 } 2002 if (ddi_copyout(&dk_allmap, (void *)arg, 2003 sizeof (struct dk_allmap), flag)) 2004 err = EFAULT; 2005 } 2006 #endif /* _MULTI_DATAMODEL */ 2007 break; 2008 2009 /* 2010 * Set the map of all logical partitions 2011 */ 2012 case DKIOCSAPART: 2013 if ((flag & DATAMODEL_MASK) == DATAMODEL_ILP32) { 2014 if (ddi_copyin((const void *)arg, &cpy.dka, 2015 sizeof (cpy.dka), flag)) 2016 return (EFAULT); 2017 else { 2018 mutex_enter(&fdc->c_lolock); 2019 for (dkunit = 0; dkunit < NDKMAP; dkunit++) { 2020 un->un_label.dkl_map[dkunit] = 2021 cpy.dka.dka_map[dkunit]; 2022 } 2023 mutex_exit(&fdc->c_lolock); 2024 } 2025 } 2026 #ifdef _MULTI_DATAMODEL 2027 else { 2028 struct dk_allmap dk_allmap; 2029 2030 ASSERT((flag & DATAMODEL_MASK) == DATAMODEL_LP64); 2031 if (ddi_copyin((const void *)arg, &dk_allmap, 2032 sizeof (dk_allmap), flag)) 2033 return (EFAULT); 2034 else { 2035 mutex_enter(&fdc->c_lolock); 2036 for (dkunit = 0; dkunit < NDKMAP; dkunit++) { 2037 un->un_label.dkl_map[dkunit].dkl_cylno = 2038 dk_allmap.dka_map[dkunit].dkl_cylno; 2039 un->un_label.dkl_map[dkunit].dkl_nblk = 2040 dk_allmap.dka_map[dkunit].dkl_nblk; 2041 } 2042 mutex_exit(&fdc->c_lolock); 2043 } 2044 } 2045 #endif /* _MULTI_DATAMODEL */ 2046 break; 2047 2048 case DKIOCGVTOC: 2049 mutex_enter(&fdc->c_lolock); 2050 2051 /* 2052 * Exit if the diskette has no label. 2053 * Also, get the label to make sure the 2054 * correct one is being used since the diskette 2055 * may have changed 2056 */ 2057 if (fdgetlabel(fdc, unit)) { 2058 mutex_exit(&fdc->c_lolock); 2059 err = EINVAL; 2060 break; 2061 } 2062 2063 /* Build a vtoc from the diskette's label */ 2064 fd_build_user_vtoc(un, &vtoc); 2065 mutex_exit(&fdc->c_lolock); 2066 2067 #ifdef _MULTI_DATAMODEL 2068 switch (ddi_model_convert_from(flag & FMODELS)) { 2069 case DDI_MODEL_ILP32: { 2070 struct vtoc32 vtoc32; 2071 2072 vtoctovtoc32(vtoc, vtoc32); 2073 if (ddi_copyout(&vtoc32, (void *)arg, 2074 sizeof (struct vtoc32), flag)) 2075 return (EFAULT); 2076 break; 2077 } 2078 2079 case DDI_MODEL_NONE: 2080 if (ddi_copyout(&vtoc, (void *)arg, 2081 sizeof (vtoc), flag)) 2082 return (EFAULT); 2083 break; 2084 } 2085 #else /* ! _MULTI_DATAMODEL */ 2086 if (ddi_copyout(&vtoc, (void *)arg, sizeof (vtoc), flag)) 2087 return (EFAULT); 2088 #endif /* _MULTI_DATAMODEL */ 2089 break; 2090 2091 case DKIOCSVTOC: 2092 2093 #ifdef _MULTI_DATAMODEL 2094 switch (ddi_model_convert_from(flag & FMODELS)) { 2095 case DDI_MODEL_ILP32: { 2096 struct vtoc32 vtoc32; 2097 2098 if (ddi_copyin((const void *)arg, &vtoc32, 2099 sizeof (struct vtoc32), flag)) { 2100 return (EFAULT); 2101 } 2102 vtoc32tovtoc(vtoc32, vtoc); 2103 break; 2104 } 2105 2106 case DDI_MODEL_NONE: 2107 if (ddi_copyin((const void *)arg, &vtoc, 2108 sizeof (vtoc), flag)) { 2109 return (EFAULT); 2110 } 2111 break; 2112 } 2113 #else /* ! _MULTI_DATAMODEL */ 2114 if (ddi_copyin((const void *)arg, &vtoc, sizeof (vtoc), flag)) 2115 return (EFAULT); 2116 #endif /* _MULTI_DATAMODEL */ 2117 2118 mutex_enter(&fdc->c_lolock); 2119 2120 /* 2121 * The characteristics structure must be filled in because 2122 * it helps build the vtoc. 2123 */ 2124 if ((un->un_chars->fdc_ncyl == 0) || 2125 (un->un_chars->fdc_nhead == 0) || 2126 (un->un_chars->fdc_secptrack == 0)) { 2127 mutex_exit(&fdc->c_lolock); 2128 err = EINVAL; 2129 break; 2130 } 2131 2132 if ((err = fd_build_label_vtoc(un, &vtoc)) != 0) { 2133 mutex_exit(&fdc->c_lolock); 2134 break; 2135 } 2136 2137 (void) pm_busy_component(fdc->c_dip, 0); 2138 2139 err = fdrw(fdc, unit, FDWRITE, 0, 0, 1, 2140 (caddr_t)&un->un_label, sizeof (struct dk_label)); 2141 mutex_exit(&fdc->c_lolock); 2142 (void) pm_idle_component(fdc->c_dip, 0); 2143 break; 2144 2145 case DKIOCSTATE: 2146 if (ddi_copyin((caddr_t)arg, (caddr_t)&state, 2147 sizeof (int), flag)) { 2148 err = EFAULT; 2149 break; 2150 } 2151 (void) pm_busy_component(fdc->c_dip, 0); 2152 2153 err = fd_check_media(dev, state); 2154 (void) pm_idle_component(fdc->c_dip, 0); 2155 2156 if (ddi_copyout((caddr_t)&un->un_media_state, 2157 (caddr_t)arg, sizeof (int), flag)) 2158 err = EFAULT; 2159 break; 2160 2161 case FDIOGCHAR: 2162 if (ddi_copyout((caddr_t)un->un_chars, (caddr_t)arg, 2163 sizeof (struct fd_char), flag)) 2164 err = EFAULT; 2165 break; 2166 2167 case FDIOSCHAR: 2168 if (ddi_copyin((caddr_t)arg, (caddr_t)&cpy.fdchar, 2169 sizeof (struct fd_char), flag)) { 2170 err = EFAULT; 2171 break; 2172 } 2173 2174 /* 2175 * Check the fields in the fdchar structure that are either 2176 * driver or controller dependent. 2177 */ 2178 2179 transfer_rate = cpy.fdchar.fdc_transfer_rate; 2180 if ((transfer_rate != 500) && (transfer_rate != 300) && 2181 (transfer_rate != 250) && (transfer_rate != 1000)) { 2182 FDERRPRINT(FDEP_L3, FDEM_IOCT, 2183 (C, "fd_ioctl: FDIOSCHAR odd transfer rate %d\n", 2184 cpy.fdchar.fdc_transfer_rate)); 2185 err = EINVAL; 2186 break; 2187 } 2188 2189 if ((cpy.fdchar.fdc_nhead < 1) || 2190 (cpy.fdchar.fdc_nhead > 2)) { 2191 FDERRPRINT(FDEP_L3, FDEM_IOCT, 2192 (C, "fd_ioctl: FDIOSCHAR bad no. of heads %d\n", 2193 cpy.fdchar.fdc_nhead)); 2194 err = EINVAL; 2195 break; 2196 } 2197 2198 /* 2199 * The number of cylinders must be between 0 and 255 2200 */ 2201 if ((cpy.fdchar.fdc_ncyl < 0) || (cpy.fdchar.fdc_ncyl > 255)) { 2202 FDERRPRINT(FDEP_L3, FDEM_IOCT, 2203 (C, "fd_ioctl: FDIOSCHAR bad cyl no %d\n", 2204 cpy.fdchar.fdc_ncyl)); 2205 err = EINVAL; 2206 break; 2207 } 2208 2209 /* Copy the fdchar structure */ 2210 2211 mutex_enter(&fdc->c_lolock); 2212 *(un->un_chars) = cpy.fdchar; 2213 2214 un->un_curfdtype = -1; 2215 2216 mutex_exit(&fdc->c_lolock); 2217 2218 break; 2219 case FDEJECT: /* eject disk */ 2220 case DKIOCEJECT: 2221 2222 /* 2223 * Fail the ioctl if auto-eject isn't supported 2224 */ 2225 if (fdc->c_un->un_drive->fdd_ejectable == 0) { 2226 2227 err = ENOSYS; 2228 2229 } else { 2230 (void) pm_busy_component(fdc->c_dip, 0); 2231 2232 mutex_enter(&fdc->c_lolock); 2233 2234 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 2235 2236 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 2237 mutex_exit(&fdc->c_lolock); 2238 if ((pm_raise_power(fdc->c_dip, 0, 2239 PM_LEVEL_ON)) != DDI_SUCCESS) { 2240 (void) pm_idle_component(fdc->c_dip, 0); 2241 err = EIO; 2242 } 2243 mutex_enter(&fdc->c_lolock); 2244 } 2245 } 2246 if (err == 0) { 2247 fdselect(fdc, unit, 1); 2248 fdeject(fdc, unit); 2249 mutex_exit(&fdc->c_lolock); 2250 } 2251 2252 (void) pm_idle_component(fdc->c_dip, 0); 2253 2254 /* 2255 * Make sure the drive is turned off 2256 */ 2257 if (fdc->c_fdtype & FDCTYPE_82077) { 2258 if (fdc->c_mtimeid == 0) { 2259 fdc->c_mtimeid = timeout(fdmotoff, fdc, 2260 Motoff_delay); 2261 } 2262 } 2263 2264 break; 2265 case FDGETCHANGE: /* disk changed */ 2266 2267 if (ddi_copyin((caddr_t)arg, (caddr_t)&cpy.temp, 2268 sizeof (int), flag)) { 2269 err = EFAULT; 2270 break; 2271 } 2272 2273 /* zero out the user's parameter */ 2274 cpy.temp = 0; 2275 2276 (void) pm_busy_component(fdc->c_dip, 0); 2277 2278 mutex_enter(&fdc->c_lolock); 2279 2280 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 2281 2282 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 2283 mutex_exit(&fdc->c_lolock); 2284 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 2285 != DDI_SUCCESS) { 2286 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power \ 2287 change failed. \n")); 2288 (void) pm_idle_component(fdc->c_dip, 0); 2289 return (EIO); 2290 } 2291 2292 mutex_enter(&fdc->c_lolock); 2293 } 2294 if (un->un_flags & FDUNIT_CHANGED) 2295 cpy.temp |= FDGC_HISTORY; 2296 else 2297 cpy.temp &= ~FDGC_HISTORY; 2298 un->un_flags &= ~FDUNIT_CHANGED; 2299 2300 if (fd_pollable) { 2301 /* 2302 * If it's a "pollable" floppy, then we don't 2303 * have to do all the fdcheckdisk nastyness to 2304 * figure out if the thing is still there. 2305 */ 2306 if (fdsense_chng(fdc, unit)) { 2307 cpy.temp |= FDGC_CURRENT; 2308 } else { 2309 cpy.temp &= ~FDGC_CURRENT; 2310 } 2311 } else { 2312 2313 if (fdsense_chng(fdc, unit)) { 2314 /* 2315 * check disk change signal is asserted. 2316 * Now find out if the floppy is 2317 * inserted 2318 */ 2319 if (fdcheckdisk(fdc, unit)) { 2320 cpy.temp |= FDGC_CURRENT; 2321 } else { 2322 /* 2323 * Yes, the floppy was 2324 * reinserted. Implies 2325 * floppy change. 2326 */ 2327 cpy.temp &= ~FDGC_CURRENT; 2328 cpy.temp |= FDGC_HISTORY; 2329 } 2330 } else { 2331 cpy.temp &= ~FDGC_CURRENT; 2332 } 2333 } 2334 2335 /* 2336 * For a pollable floppy, the floppy_change signal 2337 * reflects whether the floppy is in there or not. 2338 * We can not detect a floppy change if we don't poll 2339 * this signal when the floppy is being changed. 2340 * Because as soon as the floppy is put back, the 2341 * signal is reset. 2342 * BUT the pollable floppies are available only on 2343 * Sparcstation Voyager Voyagers (Gypsy) only and 2344 * those are motorized floppies. For motorized floppies, 2345 * the floppy can only (assuming the user doesn't use a 2346 * pin to take out the floppy) be taken out by 2347 * issuing 'eject' command which sets the 2348 * un->un_ejected flag. So, if the following 2349 * condition is true, we can assume there 2350 * was a floppy change. 2351 */ 2352 if (un->un_ejected && !(cpy.temp & FDGC_CURRENT)) { 2353 cpy.temp |= FDGC_HISTORY; 2354 } 2355 un->un_ejected = 0; 2356 2357 2358 /* return the write-protection status */ 2359 fdgetcsb(fdc); 2360 if (fdsensedrv(fdc, unit) & WP_SR3) { 2361 cpy.temp |= FDGC_CURWPROT; 2362 } 2363 fdretcsb(fdc); 2364 mutex_exit(&fdc->c_lolock); 2365 2366 if (ddi_copyout((caddr_t)&cpy.temp, (caddr_t)arg, 2367 sizeof (int), flag)) 2368 err = EFAULT; 2369 (void) pm_idle_component(fdc->c_dip, 0); 2370 break; 2371 2372 case FDGETDRIVECHAR: 2373 2374 if (ddi_copyin((caddr_t)arg, (caddr_t)&cpy.drvchar, 2375 sizeof (struct fd_drive), flag)) { 2376 err = EFAULT; 2377 break; 2378 } 2379 2380 /* 2381 * Return the ejectable value based on the FD_MANUAL_EJECT 2382 * property 2383 */ 2384 cpy.drvchar.fdd_ejectable = fdc->c_un->un_drive->fdd_ejectable; 2385 cpy.drvchar.fdd_maxsearch = nfdtypes; /* 3 - hi m lo density */ 2386 if (fd_pollable) /* pollable device */ 2387 cpy.drvchar.fdd_flags |= FDD_POLLABLE; 2388 2389 /* the rest of the fd_drive struct is meaningless to us */ 2390 2391 if (ddi_copyout((caddr_t)&cpy.drvchar, (caddr_t)arg, 2392 sizeof (struct fd_drive), flag)) 2393 err = EFAULT; 2394 break; 2395 2396 case FDSETDRIVECHAR: 2397 FDERRPRINT(FDEP_L3, FDEM_IOCT, 2398 (C, "fd_ioctl: FDSETDRIVECHAR not supportedn\n")); 2399 err = ENOTTY; 2400 break; 2401 2402 case DKIOCREMOVABLE: { 2403 int i = 1; 2404 2405 /* no brainer: floppies are always removable */ 2406 if (ddi_copyout((caddr_t)&i, (caddr_t)arg, sizeof (int), 2407 flag)) { 2408 err = EFAULT; 2409 } 2410 break; 2411 } 2412 case DKIOCGMEDIAINFO: 2413 err = fd_get_media_info(un, (caddr_t)arg, flag); 2414 break; 2415 2416 2417 case FDIOCMD: 2418 { 2419 struct fd_cmd fc; 2420 int cyl, hd, spc, spt; 2421 int nblks; /* total no. of blocks */ 2422 2423 #ifdef _MULTI_DATAMODEL 2424 switch (ddi_model_convert_from(flag & FMODELS)) { 2425 case DDI_MODEL_ILP32: { 2426 struct fd_cmd32 fc32; 2427 2428 if (ddi_copyin((const void *)arg, &fc32, 2429 sizeof (fc32), flag)) { 2430 return (EFAULT); 2431 } 2432 fc.fdc_cmd = fc32.fdc_cmd; 2433 fc.fdc_flags = fc32.fdc_flags; 2434 fc.fdc_blkno = (daddr_t)fc32.fdc_blkno; 2435 fc.fdc_secnt = fc32.fdc_secnt; 2436 fc.fdc_bufaddr = (caddr_t)fc32.fdc_bufaddr; 2437 fc.fdc_buflen = fc32.fdc_buflen; 2438 fc.fdc_cmd = fc32.fdc_cmd; 2439 2440 break; 2441 } 2442 2443 case DDI_MODEL_NONE: 2444 if (ddi_copyin((const void *)arg, &fc, 2445 sizeof (fc), flag)) { 2446 return (EFAULT); 2447 } 2448 break; 2449 } 2450 #else /* ! _MULTI_DATAMODEL */ 2451 if (ddi_copyin((const void *)arg, &fc, sizeof (fc), flag)) { 2452 return (EFAULT); 2453 } 2454 #endif /* _MULTI_DATAMODEL */ 2455 2456 if (fc.fdc_cmd == FDCMD_READ || fc.fdc_cmd == FDCMD_WRITE) { 2457 auto struct iovec aiov; 2458 auto struct uio auio; 2459 struct uio *uio = &auio; 2460 2461 spc = (fc.fdc_cmd == FDCMD_READ)? B_READ: B_WRITE; 2462 2463 bzero(&auio, sizeof (struct uio)); 2464 bzero(&aiov, sizeof (struct iovec)); 2465 aiov.iov_base = fc.fdc_bufaddr; 2466 aiov.iov_len = (uint_t)fc.fdc_secnt * sec_size; 2467 uio->uio_iov = &aiov; 2468 2469 uio->uio_iovcnt = 1; 2470 uio->uio_resid = aiov.iov_len; 2471 uio->uio_segflg = UIO_USERSPACE; 2472 FDERRPRINT(FDEP_L2, FDEM_IOCT, 2473 (C, "fd_ioctl: call physio\n")); 2474 err = physio(fd_strategy, NULL, dev, 2475 spc, minphys, uio); 2476 break; 2477 } else if (fc.fdc_cmd != FDCMD_FORMAT_TRACK) { 2478 2479 /* 2480 * The manpage states that only the FDCMD_WRITE, 2481 * FDCMD_READ, and the FDCMD_FORMAT_TR are available. 2482 */ 2483 FDERRPRINT(FDEP_L1, FDEM_IOCT, 2484 (C, "fd_ioctl: FDIOCMD invalid command\n")); 2485 err = EINVAL; 2486 break; 2487 } 2488 2489 /* The command is FDCMD_FORMAT_TRACK */ 2490 2491 spt = un->un_chars->fdc_secptrack; /* sec/trk */ 2492 spc = un->un_chars->fdc_nhead * spt; /* sec/cyl */ 2493 cyl = fc.fdc_blkno / spc; 2494 hd = (fc.fdc_blkno % spc) / spt; 2495 2496 /* 2497 * Make sure the specified block number is in the correct 2498 * range. (block numbers start at 0) 2499 */ 2500 nblks = spc * un->un_chars->fdc_ncyl; 2501 2502 if (fc.fdc_blkno < 0 || fc.fdc_blkno > (nblks - 1)) { 2503 err = EINVAL; 2504 break; 2505 } 2506 2507 (void) pm_busy_component(fdc->c_dip, 0); 2508 2509 mutex_enter(&fdc->c_lolock); 2510 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 2511 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 2512 mutex_exit(&fdc->c_lolock); 2513 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 2514 != DDI_SUCCESS) { 2515 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power \ 2516 change failed. \n")); 2517 (void) pm_idle_component(fdc->c_dip, 0); 2518 return (EIO); 2519 } 2520 2521 mutex_enter(&fdc->c_lolock); 2522 } 2523 2524 if (fdformat(fdc, unit, cyl, hd)) 2525 err = EIO; 2526 2527 mutex_exit(&fdc->c_lolock); 2528 (void) pm_idle_component(fdc->c_dip, 0); 2529 2530 break; 2531 } 2532 2533 case FDRAW: 2534 2535 (void) pm_busy_component(fdc->c_dip, 0); 2536 err = fdrawioctl(fdc, unit, arg, flag); 2537 2538 (void) pm_idle_component(fdc->c_dip, 0); 2539 2540 break; 2541 #ifdef FD_DEBUG 2542 case IOCTL_DEBUG: 2543 fderrlevel--; 2544 if (fderrlevel < 0) 2545 fderrlevel = 3; 2546 cmn_err(C, "fdioctl: CHANGING debug to %d", fderrlevel); 2547 return (0); 2548 #endif /* FD_DEBUG */ 2549 default: 2550 FDERRPRINT(FDEP_L2, FDEM_IOCT, 2551 (C, "fd_ioctl: invalid ioctl 0x%x\n", cmd)); 2552 err = ENOTTY; 2553 break; 2554 } 2555 2556 return (err); 2557 } 2558 2559 /* 2560 * fdrawioctl 2561 * 2562 * - acquires the low level lock 2563 */ 2564 2565 static int 2566 fdrawioctl(struct fdctlr *fdc, int unit, intptr_t arg, int mode) 2567 { 2568 struct fd_raw fdr; 2569 #ifdef _MULTI_DATAMODEL 2570 struct fd_raw32 fdr32; 2571 #endif 2572 struct fdcsb *csb; 2573 int i, err, flag; 2574 caddr_t fa; 2575 uint_t fc; 2576 size_t real_length; 2577 int res; 2578 ddi_device_acc_attr_t attr; 2579 ddi_acc_handle_t mem_handle; 2580 2581 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 2582 attr.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC; 2583 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 2584 2585 ASSERT(fdc->c_un->un_unit_no == unit); 2586 2587 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2588 (C, "fdrawioctl: cmd[0]=0x%x\n", fdr.fdr_cmd[0])); 2589 2590 flag = B_READ; 2591 err = 0; 2592 fa = NULL; 2593 fc = (uint_t)0; 2594 2595 /* Copy in the arguments */ 2596 switch (ddi_model_convert_from(mode)) { 2597 #ifdef _MULTI_DATAMODEL 2598 case DDI_MODEL_ILP32: 2599 if (ddi_copyin((caddr_t)arg, (caddr_t)&fdr32, 2600 sizeof (fdr32), mode)) { 2601 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2602 (C, "fdrawioctl: copyin error, args32\n")); 2603 return (EFAULT); 2604 } 2605 bcopy(fdr32.fdr_cmd, fdr.fdr_cmd, sizeof (fdr.fdr_cmd)); 2606 fdr.fdr_cnum = fdr32.fdr_cnum; 2607 bcopy(fdr32.fdr_result, fdr.fdr_result, 2608 sizeof (fdr.fdr_result)); 2609 fdr.fdr_nbytes = fdr32.fdr_nbytes; 2610 fdr.fdr_addr = (caddr_t)fdr32.fdr_addr; 2611 break; 2612 #endif 2613 default: 2614 case DDI_MODEL_NONE: 2615 if (ddi_copyin((caddr_t)arg, (caddr_t)&fdr, 2616 sizeof (fdr), mode)) { 2617 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2618 (C, "fdrawioctl: copyin error, args\n")); 2619 return (EFAULT); 2620 } 2621 break; 2622 } 2623 2624 mutex_enter(&fdc->c_lolock); 2625 2626 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 2627 2628 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 2629 mutex_exit(&fdc->c_lolock); 2630 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 2631 != DDI_SUCCESS) { 2632 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power change \ 2633 failed. \n")); 2634 2635 (void) pm_idle_component(fdc->c_dip, 0); 2636 return (EIO); 2637 } 2638 mutex_enter(&fdc->c_lolock); 2639 } 2640 2641 fdgetcsb(fdc); 2642 csb = &fdc->c_csb; 2643 csb->csb_unit = (uchar_t)unit; 2644 2645 /* copy cmd bytes into csb */ 2646 for (i = 0; i <= fdr.fdr_cnum; i++) 2647 csb->csb_cmds[i] = fdr.fdr_cmd[i]; 2648 csb->csb_ncmds = (uchar_t)fdr.fdr_cnum; 2649 2650 csb->csb_maxretry = 0; /* let the application deal with errors */ 2651 csb->csb_retrys = 0; 2652 2653 switch (fdr.fdr_cmd[0] & 0x0f) { 2654 2655 case FDRAW_SPECIFY: 2656 /* 2657 * Ensure that the right DMA mode is selected. There is 2658 * currently no way for the user to tell if DMA is 2659 * happening so set the value for the user. 2660 */ 2661 2662 if (fdc->c_fdtype & FDCTYPE_DMA) 2663 csb->csb_cmds[2] = csb->csb_cmds[2] & 0xFE; 2664 else 2665 csb->csb_cmds[2] = csb->csb_cmds[2] | 0x1; 2666 2667 csb->csb_opflags = CSB_OFNORESULTS; 2668 csb->csb_nrslts = 0; 2669 break; 2670 2671 case FDRAW_SENSE_DRV: 2672 /* Insert the appropriate drive number */ 2673 csb->csb_cmds[1] = csb->csb_cmds[1] | (unit & DRV_MASK); 2674 csb->csb_opflags = CSB_OFIMMEDIATE; 2675 csb->csb_nrslts = 1; 2676 break; 2677 2678 case FDRAW_REZERO: 2679 case FDRAW_SEEK: 2680 /* Insert the appropriate drive number */ 2681 csb->csb_cmds[1] = csb->csb_cmds[1] | (unit & DRV_MASK); 2682 csb->csb_opflags = CSB_OFSEEKOPS + CSB_OFTIMEIT; 2683 csb->csb_nrslts = 2; 2684 break; 2685 2686 case FDRAW_FORMAT: 2687 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2688 (C, "fdrawioctl: cmd is fdfraw format\n")); 2689 2690 /* Insert the appropriate drive number */ 2691 csb->csb_cmds[1] = csb->csb_cmds[1] | (unit & DRV_MASK); 2692 csb->csb_opflags = CSB_OFXFEROPS + CSB_OFTIMEIT; 2693 csb->csb_nrslts = NRBRW; 2694 flag = B_WRITE; 2695 2696 /* 2697 * Allocate memory for the command. 2698 * If PIO is being used, then add an extra 16 bytes 2699 */ 2700 if (fdc->c_fdtype & FDCTYPE_DMA) { 2701 2702 fc = (uint_t)(fdr.fdr_nbytes); 2703 mutex_enter(&fdc->c_hilock); 2704 2705 res = ddi_dma_mem_alloc(fdc->c_dmahandle, fc, 2706 &attr, DDI_DMA_STREAMING, 2707 DDI_DMA_DONTWAIT, 0, &fa, &real_length, 2708 &mem_handle); 2709 2710 if (res != DDI_SUCCESS) { 2711 fdretcsb(fdc); 2712 mutex_exit(&fdc->c_lolock); 2713 mutex_exit(&fdc->c_hilock); 2714 return (EIO); 2715 } 2716 2717 fdc->c_csb.csb_read = CSB_WRITE; 2718 if (fdstart_dma(fdc, fa, fc) != 0) { 2719 ddi_dma_mem_free(&mem_handle); 2720 fdretcsb(fdc); 2721 mutex_exit(&fdc->c_lolock); 2722 mutex_exit(&fdc->c_hilock); 2723 return (EIO); 2724 } 2725 mutex_exit(&fdc->c_hilock); 2726 2727 } else { 2728 fc = (uint_t)(fdr.fdr_nbytes + 16); 2729 fa = kmem_zalloc(fc, KM_SLEEP); 2730 } 2731 2732 /* copy in the user's command bytes */ 2733 if (ddi_copyin(fdr.fdr_addr, fa, 2734 (uint_t)fdr.fdr_nbytes, mode)) { 2735 fdretcsb(fdc); 2736 mutex_exit(&fdc->c_lolock); 2737 2738 if (fdc->c_fdtype & FDCTYPE_DMA) { 2739 ddi_dma_mem_free(&mem_handle); 2740 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2741 (C, "fdrawioctl: (err)free dma memory\n")); 2742 } else { 2743 kmem_free(fa, fc); 2744 } 2745 2746 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2747 (C, "fdrawioctl: ddi_copyin error\n")); 2748 return (EFAULT); 2749 } 2750 2751 break; 2752 case FDRAW_WRCMD: 2753 case FDRAW_WRITEDEL: 2754 flag = B_WRITE; 2755 /* FALLTHROUGH */ 2756 case FDRAW_RDCMD: 2757 case FDRAW_READDEL: 2758 case FDRAW_READTRACK: 2759 /* Insert the appropriate drive number */ 2760 csb->csb_cmds[1] = csb->csb_cmds[1] | (unit & DRV_MASK); 2761 if (fdc->c_fdtype & FDCTYPE_SB) 2762 csb->csb_cmds[1] |= IPS; 2763 csb->csb_opflags = CSB_OFXFEROPS + CSB_OFTIMEIT; 2764 csb->csb_nrslts = NRBRW; 2765 break; 2766 2767 default: 2768 fdretcsb(fdc); 2769 mutex_exit(&fdc->c_lolock); 2770 return (EINVAL); 2771 } 2772 2773 if ((csb->csb_opflags & CSB_OFXFEROPS) && (fdr.fdr_nbytes == 0)) { 2774 fdretcsb(fdc); 2775 mutex_exit(&fdc->c_lolock); 2776 return (EINVAL); 2777 } 2778 csb->csb_opflags |= CSB_OFRAWIOCTL; 2779 2780 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2781 (C, "fdrawioctl: nbytes = %u\n", fdr.fdr_nbytes)); 2782 2783 if ((fdr.fdr_cmd[0] & 0x0f) != FDRAW_FORMAT) { 2784 if ((fc = (uint_t)fdr.fdr_nbytes) > 0) { 2785 /* 2786 * In SunOS 4.X, we used to as_fault things in. 2787 * We really cannot do this in 5.0/SVr4. Unless 2788 * someone really believes that speed is of the 2789 * essence here, it is just much simpler to do 2790 * this in kernel space and use copyin/copyout. 2791 */ 2792 if (fdc->c_fdtype & FDCTYPE_DMA) { 2793 mutex_enter(&fdc->c_hilock); 2794 res = ddi_dma_mem_alloc(fdc->c_dmahandle, fc, 2795 &attr, DDI_DMA_STREAMING, 2796 DDI_DMA_DONTWAIT, 0, &fa, &real_length, 2797 &mem_handle); 2798 2799 if (res != DDI_SUCCESS) { 2800 fdretcsb(fdc); 2801 mutex_exit(&fdc->c_lolock); 2802 mutex_exit(&fdc->c_hilock); 2803 return (EIO); 2804 } 2805 2806 if (flag == B_WRITE) 2807 fdc->c_csb.csb_read = CSB_WRITE; 2808 else 2809 fdc->c_csb.csb_read = CSB_READ; 2810 2811 if (fdstart_dma(fdc, fa, fc) != 0) { 2812 ddi_dma_mem_free(&mem_handle); 2813 fdretcsb(fdc); 2814 mutex_exit(&fdc->c_lolock); 2815 mutex_exit(&fdc->c_hilock); 2816 return (EIO); 2817 } 2818 mutex_exit(&fdc->c_hilock); 2819 2820 } else { 2821 fa = kmem_zalloc(fc, KM_SLEEP); 2822 } 2823 2824 if (flag == B_WRITE) { 2825 if (ddi_copyin(fdr.fdr_addr, fa, fc, mode)) { 2826 if (fdc->c_fdtype & FDCTYPE_DMA) 2827 ddi_dma_mem_free(&mem_handle); 2828 else 2829 kmem_free(fa, fc); 2830 fdretcsb(fdc); 2831 mutex_exit(&fdc->c_lolock); 2832 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2833 (C, "fdrawioctl: can't copy data\n")); 2834 2835 return (EFAULT); 2836 } 2837 } 2838 csb->csb_addr = fa; 2839 csb->csb_len = fc; 2840 } else { 2841 csb->csb_addr = 0; 2842 csb->csb_len = 0; 2843 } 2844 } else { 2845 csb->csb_addr = fa; 2846 csb->csb_len = fc; 2847 } 2848 2849 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2850 (C, "cmd: %x %x %x %x %x %x %x %x %x %x\n", csb->csb_cmds[0], 2851 csb->csb_cmds[1], csb->csb_cmds[2], csb->csb_cmds[3], 2852 csb->csb_cmds[4], csb->csb_cmds[5], csb->csb_cmds[6], 2853 csb->csb_cmds[7], csb->csb_cmds[8], csb->csb_cmds[9])); 2854 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2855 (C, "nbytes: %x, opflags: %x, addr: %p, len: %x\n", 2856 csb->csb_ncmds, csb->csb_opflags, (void *)csb->csb_addr, 2857 csb->csb_len)); 2858 2859 2860 /* 2861 * Note that we ignore any error return s from fdexec. 2862 * This is the way the driver has been, and it may be 2863 * that the raw ioctl senders simply don't want to 2864 * see any errors returned in this fashion. 2865 */ 2866 2867 if ((csb->csb_opflags & CSB_OFNORESULTS) || 2868 (csb->csb_opflags & CSB_OFIMMEDIATE)) { 2869 (void) fdexec(fdc, 0); /* don't sleep, don't check change */ 2870 } else { 2871 (void) fdexec(fdc, FDXC_SLEEP | FDXC_CHECKCHG); 2872 } 2873 2874 2875 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2876 (C, "rslt: %x %x %x %x %x %x %x %x %x %x\n", csb->csb_rslt[0], 2877 csb->csb_rslt[1], csb->csb_rslt[2], csb->csb_rslt[3], 2878 csb->csb_rslt[4], csb->csb_rslt[5], csb->csb_rslt[6], 2879 csb->csb_rslt[7], csb->csb_rslt[8], csb->csb_rslt[9])); 2880 2881 if ((fdr.fdr_cmd[0] & 0x0f) != FDRAW_FORMAT && fc && 2882 flag == B_READ && err == 0) { 2883 if (ddi_copyout(fa, fdr.fdr_addr, fc, mode)) { 2884 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2885 (C, "fdrawioctl: can't copy read data\n")); 2886 2887 err = EFAULT; 2888 } 2889 } 2890 2891 2892 if (fc) { 2893 if (fdc->c_fdtype & FDCTYPE_DMA) { 2894 ddi_dma_mem_free(&mem_handle); 2895 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2896 (C, "fdrawioctl: free dma memory\n")); 2897 } else { 2898 kmem_free(fa, fc); 2899 } 2900 } 2901 2902 2903 /* copy cmd results into fdr */ 2904 for (i = 0; (int)i <= (int)csb->csb_nrslts; i++) 2905 fdr.fdr_result[i] = csb->csb_rslt[i]; 2906 fdr.fdr_nbytes = fdc->c_csb.csb_rlen; /* return resid */ 2907 2908 switch (ddi_model_convert_from(mode)) { 2909 #ifdef _MULTI_DATAMODEL 2910 case DDI_MODEL_ILP32: 2911 bcopy(fdr.fdr_cmd, fdr32.fdr_cmd, sizeof (fdr32.fdr_cmd)); 2912 fdr32.fdr_cnum = fdr.fdr_cnum; 2913 bcopy(fdr.fdr_result, fdr32.fdr_result, 2914 sizeof (fdr32.fdr_result)); 2915 fdr32.fdr_nbytes = fdr.fdr_nbytes; 2916 fdr32.fdr_addr = (caddr32_t)fdr.fdr_addr; 2917 if (ddi_copyout(&fdr32, (caddr_t)arg, sizeof (fdr32), mode)) { 2918 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2919 (C, "fdrawioctl: can't copy results32\n")); 2920 err = EFAULT; 2921 } 2922 break; 2923 #endif 2924 case DDI_MODEL_NONE: 2925 default: 2926 if (ddi_copyout(&fdr, (caddr_t)arg, sizeof (fdr), mode)) { 2927 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2928 (C, "fdrawioctl: can't copy results\n")); 2929 err = EFAULT; 2930 } 2931 break; 2932 } 2933 2934 fdretcsb(fdc); 2935 mutex_exit(&fdc->c_lolock); 2936 return (0); 2937 } 2938 2939 /* 2940 * fdformat 2941 * format a track 2942 * For PIO, builds a table of sector data values with 16 bytes 2943 * (sizeof fdc's fifo) of dummy on end. This is so than when fdc->c_len 2944 * goes to 0 and fd_intr sends a TC that all the real formatting will 2945 * have already been done. 2946 * 2947 * - called with the low level lock held 2948 */ 2949 static int 2950 fdformat(struct fdctlr *fdc, int unit, int cyl, int hd) 2951 { 2952 struct fdcsb *csb; 2953 struct fdunit *un; 2954 struct fd_char *ch; 2955 int cmdresult; 2956 uchar_t *fmthdrs; 2957 caddr_t fd; 2958 int i; 2959 size_t real_length; 2960 ddi_device_acc_attr_t attr; 2961 ddi_acc_handle_t mem_handle; 2962 2963 FDERRPRINT(FDEP_L1, FDEM_FORM, 2964 (C, "fdformat cyl %d, hd %d\n", cyl, hd)); 2965 fdgetcsb(fdc); 2966 2967 ASSERT(fdc->c_un->un_unit_no == unit); 2968 2969 csb = &fdc->c_csb; 2970 un = fdc->c_un; 2971 ch = un->un_chars; 2972 2973 /* setup common things in csb */ 2974 csb->csb_unit = (uchar_t)unit; 2975 2976 /* 2977 * The controller needs to do a seek before 2978 * each format to get to right cylinder. 2979 */ 2980 if (fdrecalseek(fdc, unit, cyl, FDXC_CHECKCHG)) { 2981 fdretcsb(fdc); 2982 return (EIO); 2983 } 2984 2985 /* 2986 * now do the format itself 2987 */ 2988 csb->csb_nrslts = NRBRW; 2989 csb->csb_opflags = CSB_OFXFEROPS | CSB_OFTIMEIT; 2990 2991 csb->csb_cmds[0] = FDRAW_FORMAT; 2992 /* always or in MFM bit */ 2993 csb->csb_cmds[0] |= MFM; 2994 csb->csb_cmds[1] = (hd << 2) | (unit & 0x03); 2995 csb->csb_cmds[2] = ch->fdc_medium ? 3 : 2; 2996 csb->csb_cmds[3] = ch->fdc_secptrack; 2997 csb->csb_cmds[4] = GPLF; 2998 csb->csb_cmds[5] = FDATA; 2999 csb->csb_ncmds = 6; 3000 csb->csb_maxretry = rwretry; 3001 csb->csb_retrys = 0; 3002 3003 /* 3004 * NOTE: have to add size of fifo also - for dummy format action 3005 * if PIO is being used. 3006 */ 3007 3008 3009 if (fdc->c_fdtype & FDCTYPE_DMA) { 3010 3011 csb->csb_len = (uint_t)4 * ch->fdc_secptrack; 3012 3013 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 3014 attr.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC; 3015 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 3016 3017 mutex_enter(&fdc->c_hilock); 3018 3019 cmdresult = ddi_dma_mem_alloc(fdc->c_dmahandle, csb->csb_len, 3020 &attr, DDI_DMA_STREAMING, 3021 DDI_DMA_DONTWAIT, 0, &fd, &real_length, 3022 &mem_handle); 3023 3024 if (cmdresult != DDI_SUCCESS) { 3025 mutex_exit(&fdc->c_hilock); 3026 return (cmdresult); 3027 } 3028 3029 fdc->c_csb.csb_read = CSB_WRITE; 3030 if (fdstart_dma(fdc, fd, csb->csb_len) != 0) { 3031 ddi_dma_mem_free(&mem_handle); 3032 mutex_exit(&fdc->c_hilock); 3033 return (-1); 3034 } 3035 mutex_exit(&fdc->c_hilock); 3036 3037 3038 } else { 3039 csb->csb_len = (uint_t)4 * ch->fdc_secptrack + 16; 3040 fd = kmem_zalloc(csb->csb_len, KM_SLEEP); 3041 fmthdrs = (uchar_t *)fd; 3042 } 3043 3044 csb->csb_addr = (caddr_t)fd; 3045 3046 for (i = 1; i <= ch->fdc_secptrack; i++) { 3047 *fd++ = (uchar_t)cyl; /* cylinder */ 3048 *fd++ = (uchar_t)hd; /* head */ 3049 *fd++ = (uchar_t)i; /* sector number */ 3050 *fd++ = ch->fdc_medium ? 3 : 2; /* sec_size code */ 3051 } 3052 3053 if ((cmdresult = fdexec(fdc, FDXC_SLEEP | FDXC_CHECKCHG)) == 0) { 3054 if (csb->csb_cmdstat) 3055 cmdresult = EIO; /* XXX TBD NYD for now */ 3056 } 3057 3058 if (fdc->c_fdtype & FDCTYPE_DMA) { 3059 ddi_dma_mem_free(&mem_handle); 3060 } else { 3061 kmem_free((caddr_t)fmthdrs, csb->csb_len); 3062 } 3063 3064 fdretcsb(fdc); 3065 3066 return (cmdresult); 3067 } 3068 3069 /* 3070 * fdstart 3071 * called from fd_strategy() or from fdXXXX() to setup and 3072 * start operations of read or write only (using buf structs). 3073 * Because the chip doesn't handle crossing cylinder boundaries on 3074 * the fly, this takes care of those boundary conditions. Note that 3075 * it sleeps until the operation is done *within fdstart* - so that 3076 * when fdstart returns, the operation is already done. 3077 * 3078 * - called with the low level lock held 3079 * 3080 */ 3081 3082 static int slavio_index_pulse_work_around = 0; 3083 3084 static void 3085 fdstart(struct fdctlr *fdc) 3086 { 3087 struct buf *bp; 3088 struct fdcsb *csb; 3089 struct fdunit *un; 3090 struct fd_char *ch; 3091 struct dk_map32 *dkm; 3092 uint_t part; /* partition number for the transfer */ 3093 uint_t start_part; /* starting block of the partition */ 3094 uint_t last_part; /* last block of the partition */ 3095 uint_t blk; /* starting block of transfer on diskette */ 3096 uint_t sect; /* starting block's offset into track */ 3097 uint_t cyl; /* starting cylinder of the transfer */ 3098 uint_t bincyl; /* starting blocks's offset into cylinder */ 3099 uint_t secpcyl; /* number of sectors per cylinder */ 3100 uint_t phys_blkno; /* no. of blocks on the diskette */ 3101 uint_t head; /* one of two diskette heads */ 3102 uint_t unit; 3103 uint_t len, tlen; 3104 caddr_t addr; 3105 caddr_t temp_addr; 3106 uint_t partial_read = 0; 3107 int sb_temp_buf_used = 0; 3108 3109 bp = fdc->c_actf; 3110 3111 while (bp != NULL) { 3112 3113 fdc->c_actf = bp->av_forw; 3114 fdc->c_current = bp; 3115 3116 /* 3117 * Initialize the buf structure. The residual count is 3118 * initially the number of bytes to be read or written 3119 */ 3120 bp->b_flags &= ~B_ERROR; 3121 bp->b_error = 0; 3122 bp->b_resid = bp->b_bcount; 3123 bp_mapin(bp); /* map in buffers */ 3124 3125 addr = bp->b_un.b_addr; /* assign buffer address */ 3126 3127 /* 3128 * Find the unit and partition numbers. 3129 */ 3130 unit = fdc->c_un->un_unit_no; 3131 un = fdc->c_un; 3132 ch = un->un_chars; 3133 part = FDPARTITION(bp->b_edev); 3134 dkm = &un->un_label.dkl_map[part]; 3135 3136 if (un->un_chars->fdc_medium) { 3137 phys_blkno = bp->b_blkno >> 1; 3138 } else { 3139 phys_blkno = bp->b_blkno; 3140 } 3141 3142 if (un->un_iostat) { 3143 kstat_waitq_to_runq(KIOSP); 3144 } 3145 3146 FDERRPRINT(FDEP_L1, FDEM_STRT, 3147 (C, "fdstart: bp=0x%p blkno=0x%x bcount=0x%x\n", 3148 (void *)bp, (int)bp->b_blkno, (int)bp->b_bcount)); 3149 3150 /* 3151 * Get the csb and initialize the values that are the same 3152 * for DMA and PIO. 3153 */ 3154 fdgetcsb(fdc); /* get csb (maybe wait for it) */ 3155 csb = &fdc->c_csb; 3156 csb->csb_unit = unit; /* floppy unit number */ 3157 3158 3159 /* 3160 * bugID:4133425 : If the controller is SLAVIO, and 3161 * the read does not reach end of track, then modify 3162 * the tlen to read until the end of track to a temp 3163 * buffer and disable MT. After the read is over, 3164 * copy the useful portion of the data to 'addr'. 3165 * Enable this feature only when 3166 * slavio_index_pulse_work_aound variable is 3167 * set in /etc/system. 3168 */ 3169 3170 3171 if (bp->b_flags & B_READ) { 3172 if (((fdc->c_fdtype & FDCTYPE_SLAVIO) && 3173 slavio_index_pulse_work_around) || 3174 (fdc->c_fdtype & FDCTYPE_TCBUG)) 3175 csb->csb_cmds[0] = SK | FDRAW_RDCMD | MFM; 3176 else 3177 csb->csb_cmds[0] = MT | SK | FDRAW_RDCMD | MFM; 3178 } else { 3179 if (fdc->c_fdtype & FDCTYPE_TCBUG) 3180 csb->csb_cmds[0] = FDRAW_WRCMD | MFM; 3181 else 3182 csb->csb_cmds[0] = MT | FDRAW_WRCMD | MFM; 3183 } 3184 3185 3186 if (bp->b_flags & B_READ) 3187 fdc->c_csb.csb_read = CSB_READ; 3188 else 3189 fdc->c_csb.csb_read = CSB_WRITE; 3190 3191 3192 csb->csb_cmds[5] = ch->fdc_medium ? 3 : 2; /* sector size */ 3193 csb->csb_cmds[6] = ch->fdc_secptrack; /* EOT-# of sectors/trk */ 3194 csb->csb_cmds[7] = GPLN; /* GPL - gap 3 size code */ 3195 csb->csb_cmds[8] = SSSDTL; /* DTL - be 0xFF if N != 0 */ 3196 3197 csb->csb_ncmds = NCBRW; /* number of command bytes */ 3198 csb->csb_nrslts = NRBRW; /* number of result bytes */ 3199 3200 3201 /* 3202 * opflags for interrupt handler, et.al. 3203 */ 3204 csb->csb_opflags = CSB_OFXFEROPS | CSB_OFTIMEIT; 3205 3206 3207 /* 3208 * Make sure the transfer does not go off the end 3209 * of the partition. Limit the actual amount transferred 3210 * to fit the partition. 3211 */ 3212 3213 blk = phys_blkno; 3214 start_part = (dkm->dkl_cylno * ch->fdc_secptrack 3215 * ch->fdc_nhead); 3216 blk = blk + start_part; 3217 last_part = start_part + dkm->dkl_nblk; 3218 3219 if ((blk + (bp->b_bcount / ch->fdc_sec_size)) > last_part) 3220 len = (last_part - blk) * ch->fdc_sec_size; 3221 else 3222 len = (uint_t)bp->b_bcount; 3223 3224 /* 3225 * now we have the real start blk, 3226 * addr and len for xfer op 3227 * sectors per cylinder 3228 */ 3229 secpcyl = ch->fdc_nhead * ch->fdc_secptrack; 3230 3231 /* 3232 * The controller can transfer up to a cylinder at a time. 3233 * Early revs of the 82077 have a bug that causes the chip to 3234 * fail to respond to the Terminal Count signal. Due to this 3235 * bug, controllers with type FDCTYPE_TCBUG, only transfer up 3236 * to a track at a time. 3237 * See earlier comment for bugID:4133425 for index pulse 3238 * work around. 3239 */ 3240 3241 while (len != 0) { 3242 3243 cyl = blk / secpcyl; /* cylinder of transfer */ 3244 bincyl = blk % secpcyl; /* blk within cylinder */ 3245 head = bincyl / ch->fdc_secptrack; 3246 sect = (bincyl % ch->fdc_secptrack) + 1; 3247 /* sect w/in track */ 3248 3249 /* 3250 * If the desired block and length will go beyond the 3251 * cylinder end, limit it to the cylinder end. 3252 */ 3253 3254 if ((fdc->c_fdtype & FDCTYPE_SLAVIO) && 3255 slavio_index_pulse_work_around && 3256 (fdc->c_csb.csb_read == CSB_READ)) { 3257 3258 tlen = (ch->fdc_secptrack - sect + 1) * 3259 ch->fdc_sec_size; 3260 if (len < tlen) { 3261 partial_read = 1; 3262 temp_addr = (caddr_t)kmem_alloc(tlen, 3263 KM_SLEEP); 3264 } 3265 3266 } else if (fdc->c_fdtype & FDCTYPE_TCBUG) { 3267 tlen = len; 3268 if (len > ((ch->fdc_secptrack - sect + 1) * 3269 ch->fdc_sec_size)) 3270 tlen = (ch->fdc_secptrack - sect + 1) 3271 * ch->fdc_sec_size; 3272 } else { 3273 if (len > ((secpcyl - bincyl) 3274 * ch->fdc_sec_size)) 3275 tlen = (secpcyl - bincyl) 3276 * ch->fdc_sec_size; 3277 3278 else 3279 tlen = len; 3280 } 3281 if (fdc->c_fdtype & FDCTYPE_SB) { 3282 /* 3283 * To avoid underrun errors during IFB activity. 3284 */ 3285 if (tlen > max_fd_dma_len) 3286 tlen = max_fd_dma_len; 3287 } 3288 3289 FDERRPRINT(FDEP_L1, FDEM_STRT, 3290 (C, " blk 0x%x, addr 0x%p, len 0x%x\n", 3291 blk, (void *)addr, len)); 3292 FDERRPRINT(FDEP_L1, FDEM_STRT, 3293 (C, "cyl:%x, head:%x, sec:%x\n", 3294 cyl, head, sect)); 3295 3296 FDERRPRINT(FDEP_L1, FDEM_STRT, 3297 (C, " resid 0x%lx, tlen %d\n", 3298 bp->b_resid, tlen)); 3299 3300 /* 3301 * Finish programming the command 3302 */ 3303 csb->csb_cmds[1] = (head << 2) | unit; 3304 if (fdc->c_fdtype & FDCTYPE_SB) 3305 csb->csb_cmds[1] |= IPS; 3306 3307 csb->csb_cmds[2] = cyl; /* C - cylinder address */ 3308 csb->csb_cmds[3] = head; /* H - head number */ 3309 csb->csb_cmds[4] = sect; /* R - sector number */ 3310 if (fdc->c_fdtype & FDCTYPE_TCBUG) 3311 csb->csb_cmds[6] = sect + 3312 (tlen / ch->fdc_sec_size) - 1; 3313 3314 csb->csb_len = tlen; 3315 if (partial_read) 3316 csb->csb_addr = temp_addr; 3317 else 3318 csb->csb_addr = addr; 3319 3320 /* retry this many times max */ 3321 csb->csb_maxretry = rwretry; 3322 csb->csb_retrys = 0; 3323 3324 /* If platform supports DMA, set up DMA resources */ 3325 if (fdc->c_fdtype & FDCTYPE_DMA) { 3326 if ((fdc->c_fdtype & FDCTYPE_SB) && 3327 (((uint32_t)addr & 0xFFFF0000) != 3328 (((uint32_t)addr + tlen) & 0xFFFF0000))) { 3329 csb->csb_addr = fdc->dma_buf; 3330 sb_temp_buf_used = 1; 3331 if (csb->csb_read != CSB_READ) { 3332 bcopy(addr, fdc->dma_buf, tlen); 3333 } 3334 } 3335 mutex_enter(&fdc->c_hilock); 3336 3337 if (fdstart_dma(fdc, csb->csb_addr, 3338 tlen) != 0) { 3339 3340 bp->b_flags |= B_ERROR; 3341 bp->b_error = EAGAIN; 3342 3343 mutex_exit(&fdc->c_hilock); 3344 FDERRPRINT(FDEP_L1, FDEM_STRT, 3345 (C, "fdstart: no dma resources\n")); 3346 3347 break; 3348 } 3349 mutex_exit(&fdc->c_hilock); 3350 3351 } 3352 3353 bp->b_error = fdexec(fdc, FDXC_SLEEP|FDXC_CHECKCHG); 3354 if (bp->b_error != 0) { 3355 /* 3356 * error in fdexec 3357 */ 3358 FDERRPRINT(FDEP_L1, FDEM_STRT, (C, 3359 "fdstart: bad exec of bp: 0x%p, err %d\n", 3360 (void *)bp, bp->b_error)); 3361 3362 bp->b_flags |= B_ERROR; 3363 if (partial_read) { 3364 partial_read = 0; 3365 kmem_free(temp_addr, tlen); 3366 } 3367 break; 3368 } 3369 3370 /* 3371 * If it was a partial read, copy the useful 3372 * portion of data to 'addr'. 3373 */ 3374 if (partial_read) { 3375 partial_read = 0; 3376 bcopy(temp_addr, addr, len); 3377 kmem_free(temp_addr, tlen); 3378 tlen = len; 3379 } 3380 if ((fdc->c_fdtype & FDCTYPE_SB) && 3381 (csb->csb_read == CSB_READ)) { 3382 if (sb_temp_buf_used) { 3383 bcopy(fdc->dma_buf, addr, tlen); 3384 sb_temp_buf_used = 0; 3385 } 3386 } 3387 3388 blk += tlen / ch->fdc_sec_size; 3389 len -= tlen; 3390 addr += tlen; 3391 bp->b_resid -= tlen; 3392 3393 } 3394 3395 FDERRPRINT(FDEP_L1, FDEM_STRT, 3396 (C, "fdstart done: b_resid %lu, b_count %lu, csb_rlen %d\n", 3397 bp->b_resid, bp->b_bcount, fdc->c_csb.csb_rlen)); 3398 3399 fdc->c_current = 0; 3400 fdretcsb(fdc); 3401 if (un->un_iostat) { 3402 if (bp->b_flags & B_READ) { 3403 KIOSP->reads++; 3404 KIOSP->nread += 3405 (bp->b_bcount - bp->b_resid); 3406 } else { 3407 KIOSP->writes++; 3408 KIOSP->nwritten += (bp->b_bcount - bp->b_resid); 3409 } 3410 kstat_runq_exit(KIOSP); 3411 } 3412 biodone(bp); 3413 3414 /* 3415 * Look at the next buffer 3416 */ 3417 bp = fdc->c_actf; 3418 3419 } 3420 } 3421 3422 /* 3423 * Set up DMA resources 3424 * The DMA handle was initialized in fd_attach() 3425 * Assumes the handle has already been allocated by fd_attach() 3426 */ 3427 static int 3428 fdstart_dma(struct fdctlr *fdc, caddr_t addr, uint_t len) 3429 { 3430 int flags; /* flags for setting up resources */ 3431 int res; 3432 3433 FDERRPRINT(FDEP_L1, FDEM_SDMA, (C, "fdstart_dma: start\n")); 3434 3435 if (fdc->c_csb.csb_read == CSB_READ) { 3436 flags = DDI_DMA_READ; 3437 } else { 3438 flags = DDI_DMA_WRITE; 3439 } 3440 3441 3442 /* allow partial mapping to maximize the portability of the driver */ 3443 flags = flags | DDI_DMA_PARTIAL; 3444 3445 FDERRPRINT(FDEP_L1, FDEM_SDMA, (C, "fdstart_dma: amt. asked for %d\n", 3446 len)); 3447 3448 /* 3449 * Zero out the current cookie. This is done to ensure that 3450 * the previous transfers cookie information can in no way be 3451 * used. 3452 */ 3453 bzero((char *)&fdc->c_csb.csb_dmacookie, 3454 sizeof (fdc->c_csb.csb_dmacookie)); 3455 fdc->c_csb.csb_nwin = 0; 3456 fdc->c_csb.csb_windex = 0; 3457 fdc->c_csb.csb_ccount = 0; 3458 3459 res = ddi_dma_addr_bind_handle(fdc->c_dmahandle, NULL, addr, len, 3460 flags, DDI_DMA_DONTWAIT, 0, &fdc->c_csb.csb_dmacookie, 3461 &fdc->c_csb.csb_ccount); 3462 3463 switch (res) { 3464 case DDI_DMA_MAPPED: 3465 /* 3466 * There is one window. csb_windex is the index 3467 * into the array of windows. If there are n 3468 * windows then, (0 <= windex <= n-1). csb_windex 3469 * represents the index of the next window 3470 * to be processed. 3471 */ 3472 fdc->c_csb.csb_nwin = 1; 3473 fdc->c_csb.csb_windex = 1; 3474 3475 3476 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3477 (C, "fdstart_dma: DDI_DMA_MAPPED\n")); 3478 3479 break; 3480 case DDI_DMA_PARTIAL_MAP: 3481 3482 /* 3483 * obtain the number of DMA windows 3484 */ 3485 if (ddi_dma_numwin(fdc->c_dmahandle, 3486 &fdc->c_csb.csb_nwin) != DDI_SUCCESS) { 3487 return (-1); 3488 } 3489 3490 3491 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3492 (C, "fdstart_dma: partially mapped %d windows\n", 3493 fdc->c_csb.csb_nwin)); 3494 3495 /* 3496 * The DMA window currently in use is window number 3497 * one. 3498 */ 3499 fdc->c_csb.csb_windex = 1; 3500 3501 break; 3502 case DDI_DMA_NORESOURCES: 3503 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3504 (C, "fdstart_dma: no resources\n")); 3505 return (-1); 3506 case DDI_DMA_NOMAPPING: 3507 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3508 (C, "fdstart_dma: no mapping\n")); 3509 return (-1); 3510 case DDI_DMA_TOOBIG: 3511 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3512 (C, "fdstart_dma: too big\n")); 3513 return (-1); 3514 3515 case DDI_DMA_INUSE: 3516 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3517 (C, "fdstart_dma: dma inuse\n")); 3518 return (-1); 3519 default: 3520 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3521 (C, "fdstart_dma: result is 0x%x\n", res)); 3522 return (-1); 3523 3524 }; 3525 3526 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3527 (C, "fdstart_dma: bound the handle\n")); 3528 3529 ASSERT(fdc->c_csb.csb_dmacookie.dmac_size); 3530 3531 FDERRPRINT(FDEP_L1, FDEM_SDMA, (C, "fdstart_dma: done\n")); 3532 return (0); 3533 } 3534 3535 3536 /* 3537 * fd_unbind_handle: unbind a dma handle if one exists 3538 * return EIO if unbind failes 3539 */ 3540 static int 3541 fd_unbind_handle(struct fdctlr *fdc) 3542 { 3543 if ((fdc->c_fdtype & FDCTYPE_DMA) && 3544 ((fdc->c_csb.csb_read == CSB_READ) || 3545 (fdc->c_csb.csb_read == CSB_WRITE))) { 3546 mutex_enter(&fdc->c_hilock); 3547 3548 if (fdc->c_fdtype & FDCTYPE_SB) { 3549 if (fdc->sb_dma_lock) { 3550 release_sb_dma(fdc); 3551 } 3552 } 3553 3554 /* 3555 * If the byte count isn't zero, then the DMA engine is 3556 * still doing a transfer. If the byte count is nonzero, 3557 * reset the DMA engine to cause it to drain. 3558 */ 3559 3560 if (get_data_count_register(fdc) != 0) { 3561 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3562 (C, "unbind & byte count isn't zero\n")); 3563 3564 reset_dma_controller(fdc); 3565 set_dma_control_register(fdc, DCSR_INIT_BITS); 3566 } 3567 3568 if (ddi_dma_unbind_handle(fdc->c_dmahandle) != DDI_SUCCESS) { 3569 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3570 (C, "problem unbinding the handle\n")); 3571 mutex_exit(&fdc->c_hilock); 3572 return (EIO); 3573 } 3574 mutex_exit(&fdc->c_hilock); 3575 } 3576 return (0); 3577 } 3578 3579 /* 3580 * fdexec 3581 * all commands go through here. Assumes the command block 3582 * fdctlr.c_csb is filled in. The bytes are sent to the 3583 * controller and then we do whatever else the csb says - 3584 * like wait for immediate results, etc. 3585 * 3586 * All waiting for operations done is in here - to allow retrys 3587 * and checking for disk changed - so we don't have to worry 3588 * about sleeping at interrupt level. 3589 * 3590 * RETURNS: 0 if all ok, 3591 * ENXIO - diskette not in drive 3592 * EBUSY - if chip is locked or busy 3593 * EIO - for timeout during sending cmds to chip 3594 * 3595 * to sleep: set FDXC_SLEEP, to check for disk 3596 * changed: set FDXC_CHECKCHG 3597 * 3598 * - called with the lock held 3599 */ 3600 static int 3601 fdexec(struct fdctlr *fdc, int flags) 3602 { 3603 struct fdcsb *csb; 3604 int i; 3605 int to, unit; 3606 uchar_t tmp; 3607 caddr_t a = (caddr_t)fdc; 3608 3609 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: flags:%x\n", flags)); 3610 3611 ASSERT(mutex_owned(&fdc->c_lolock)); 3612 3613 csb = &fdc->c_csb; 3614 unit = csb->csb_unit; 3615 3616 3617 ASSERT(unit == fdc->c_un->un_unit_no); 3618 3619 retry: 3620 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: cmd is %s\n", 3621 fdcmds[csb->csb_cmds[0] & 0x1f].cmdname)); 3622 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: transfer rate = %d\n", 3623 fdc->c_un->un_chars->fdc_transfer_rate)); 3624 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: sec size = %d\n", 3625 fdc->c_un->un_chars->fdc_sec_size)); 3626 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: nblocks (512) = %d\n", 3627 fdc->c_un->un_label.dkl_map[2].dkl_nblk)); 3628 3629 if ((fdc->c_fdtype & FDCTYPE_CTRLMASK) == FDCTYPE_82077) { 3630 fdexec_turn_on_motor(fdc, flags, unit); 3631 } 3632 3633 3634 fdselect(fdc, unit, 1); /* select drive */ 3635 3636 /* 3637 * select data rate for this unit/command 3638 */ 3639 switch (fdc->c_un->un_chars->fdc_transfer_rate) { 3640 case 500: 3641 Dsr(fdc, 0); 3642 break; 3643 case 300: 3644 Dsr(fdc, 1); 3645 break; 3646 case 250: 3647 Dsr(fdc, 2); 3648 break; 3649 } 3650 drv_usecwait(2); 3651 3652 3653 /* 3654 * If checking for changed is enabled (i.e., not seeking in checkdisk), 3655 * we sample the DSKCHG line to see if the diskette has wandered away. 3656 */ 3657 if ((flags & FDXC_CHECKCHG) && fdsense_chng(fdc, unit)) { 3658 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "diskette changed\n")); 3659 fdc->c_un->un_flags |= FDUNIT_CHANGED; 3660 3661 if (fdcheckdisk(fdc, unit)) { 3662 3663 (void) fd_unbind_handle(fdc); 3664 return (ENXIO); 3665 3666 } 3667 } 3668 3669 /* 3670 * gather some statistics 3671 */ 3672 switch (csb->csb_cmds[0] & 0x1f) { 3673 case FDRAW_RDCMD: 3674 fdc->fdstats.rd++; 3675 break; 3676 case FDRAW_WRCMD: 3677 fdc->fdstats.wr++; 3678 break; 3679 case FDRAW_REZERO: 3680 fdc->fdstats.recal++; 3681 break; 3682 case FDRAW_FORMAT: 3683 fdc->fdstats.form++; 3684 break; 3685 default: 3686 fdc->fdstats.other++; 3687 break; 3688 } 3689 3690 /* 3691 * Always set the opmode *prior* to poking the chip. 3692 * This way we don't have to do any locking at high level. 3693 */ 3694 csb->csb_raddr = 0; 3695 csb->csb_rlen = 0; 3696 if (csb->csb_opflags & CSB_OFSEEKOPS) { 3697 csb->csb_opmode = 2; 3698 } else if (csb->csb_opflags & CSB_OFIMMEDIATE) { 3699 csb->csb_opmode = 0; 3700 } else { 3701 csb->csb_opmode = 1; /* normal data xfer commands */ 3702 csb->csb_raddr = csb->csb_addr; 3703 csb->csb_rlen = csb->csb_len; 3704 } 3705 3706 bzero((caddr_t)csb->csb_rslt, 10); 3707 csb->csb_status = 0; 3708 csb->csb_cmdstat = 0; 3709 3710 3711 /* 3712 * Program the DMA engine with the length and address of the transfer 3713 * (DMA is only used on a read or a write) 3714 */ 3715 if ((fdc->c_fdtype & FDCTYPE_DMA) && 3716 ((fdc->c_csb.csb_read == CSB_READ) || 3717 (fdc->c_csb.csb_read == CSB_WRITE))) { 3718 mutex_enter(&fdc->c_hilock); 3719 3720 /* Reset the dcsr to clear it of all errors */ 3721 3722 reset_dma_controller(fdc); 3723 3724 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "cookie addr 0x%p\n", 3725 (void *)fdc->c_csb.csb_dmacookie.dmac_laddress)); 3726 3727 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "cookie length %ld\n", 3728 fdc->c_csb.csb_dmacookie.dmac_size)); 3729 ASSERT(fdc->c_csb.csb_dmacookie.dmac_size); 3730 3731 set_data_count_register(fdc, 3732 fdc->c_csb.csb_dmacookie.dmac_size); 3733 set_data_address_register(fdc, 3734 fdc->c_csb.csb_dmacookie.dmac_laddress); 3735 3736 /* Program the DCSR */ 3737 3738 if (fdc->c_csb.csb_read == CSB_READ) 3739 set_dma_mode(fdc, CSB_READ); 3740 else 3741 set_dma_mode(fdc, CSB_WRITE); 3742 mutex_exit(&fdc->c_hilock); 3743 } 3744 3745 /* 3746 * I saw this (chip unexpectedly busy) happen when i shoved the 3747 * floppy into the drive while 3748 * running a dd if= /dev/rfd0c. so it *is* possible for this to happen. 3749 * we need to do a ctlr reset ... 3750 */ 3751 3752 if (Msr(fdc) & CB) { 3753 /* tried to give command to chip when it is busy! */ 3754 FDERRPRINT(FDEP_L3, FDEM_EXEC, 3755 (C, "fdc: unexpectedly busy-stat 0x%x\n", Msr(fdc))); 3756 csb->csb_cmdstat = 1; /* XXX TBD ERRS NYD for now */ 3757 3758 (void) fd_unbind_handle(fdc); 3759 return (EBUSY); 3760 } 3761 3762 /* Give command to the controller */ 3763 for (i = 0; i < (int)csb->csb_ncmds; i++) { 3764 3765 /* Test the readiness of the controller to receive the cmd */ 3766 for (to = FD_CRETRY; to; to--) { 3767 if ((Msr(fdc) & (DIO|RQM)) == RQM) 3768 break; 3769 } 3770 if (to == 0) { 3771 FDERRPRINT(FDEP_L2, FDEM_EXEC, 3772 (C, "fdc: no RQM - stat 0x%x\n", Msr(fdc))); 3773 csb->csb_cmdstat = 1; 3774 3775 (void) fd_unbind_handle(fdc); 3776 return (EIO); 3777 } 3778 3779 Set_Fifo(fdc, csb->csb_cmds[i]); 3780 3781 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3782 (C, "fdexec: sent 0x%x, Msr 0x%x\n", csb->csb_cmds[i], 3783 Msr(fdc))); 3784 3785 } 3786 3787 3788 /* 3789 * Start watchdog timer on data transfer type commands - required 3790 * in case a diskette is not present or is unformatted 3791 */ 3792 if (csb->csb_opflags & CSB_OFTIMEIT) { 3793 fdc->c_timeid = timeout(fdwatch, a, 3794 tosec * drv_usectohz(1000000)); 3795 } 3796 3797 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3798 (C, "fdexec: cmd sent, Msr 0x%x\n", Msr(fdc))); 3799 3800 /* If the operation has no results - then just return */ 3801 if (csb->csb_opflags & CSB_OFNORESULTS) { 3802 if (fdc->c_fdtype & FDCTYPE_82077) { 3803 if (fdc->c_mtimeid == 0) { 3804 fdc->c_mtimeid = timeout(fdmotoff, a, 3805 Motoff_delay); 3806 } 3807 } 3808 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: O K ..\n")); 3809 3810 /* 3811 * Make sure the last byte is received well by the 3812 * controller. On faster CPU, it may still be busy 3813 * by the time another command comes here. 3814 */ 3815 for (to = FD_CRETRY; to; to--) { 3816 if ((Msr(fdc) & (DIO|RQM)) == RQM) 3817 break; 3818 } 3819 if (to == 0) { 3820 csb->csb_cmdstat = 1; 3821 return (EIO); 3822 } 3823 3824 /* 3825 * An operation that has no results isn't doing DMA so, 3826 * there is no reason to try to unbind a handle 3827 */ 3828 return (0); 3829 } 3830 3831 /* 3832 * If this operation has no interrupt AND an immediate result 3833 * then we just busy wait for the results and stuff them into 3834 * the csb 3835 */ 3836 if (csb->csb_opflags & CSB_OFIMMEDIATE) { 3837 to = FD_RRETRY; 3838 csb->csb_nrslts = 0; 3839 /* 3840 * Wait while this command is still going on. 3841 */ 3842 while ((tmp = Msr(fdc)) & CB) { 3843 /* 3844 * If RQM + DIO, then a result byte is at hand. 3845 */ 3846 if ((tmp & (RQM|DIO|CB)) == (RQM|DIO|CB)) { 3847 csb->csb_rslt[csb->csb_nrslts++] = 3848 Fifo(fdc); 3849 /* 3850 * FDERRPRINT(FDEP_L4, FDEM_EXEC, 3851 * (C, "fdexec: got result 0x%x\n", 3852 * csb->csb_nrslts)); 3853 */ 3854 } else if (--to == 0) { 3855 FDERRPRINT(FDEP_L4, FDEM_EXEC, 3856 (C, "fdexec: timeout, Msr%x, nr%x\n", 3857 Msr(fdc), csb->csb_nrslts)); 3858 3859 csb->csb_status = 2; 3860 if (fdc->c_fdtype & FDCTYPE_82077) { 3861 if (fdc->c_mtimeid == 0) { 3862 fdc->c_mtimeid = timeout( 3863 fdmotoff, a, Motoff_delay); 3864 } 3865 } 3866 /* 3867 * There is no DMA happening. No need to 3868 * try freeing a handle. 3869 */ 3870 3871 return (EIO); 3872 } 3873 } 3874 } 3875 3876 /* 3877 * If told to sleep here, well then sleep! 3878 */ 3879 3880 if (flags & FDXC_SLEEP) { 3881 fdc->c_flags |= FDCFLG_WAITING; 3882 while (fdc->c_flags & FDCFLG_WAITING) { 3883 cv_wait(&fdc->c_iocv, &fdc->c_lolock); 3884 } 3885 } 3886 3887 /* 3888 * kludge for end-of-cylinder error which must be ignored!!! 3889 */ 3890 3891 if ((fdc->c_fdtype & FDCTYPE_TCBUG) && 3892 ((csb->csb_rslt[0] & IC_SR0) == 0x40) && 3893 (csb->csb_rslt[1] & EN_SR1)) 3894 csb->csb_rslt[0] &= ~IC_SR0; 3895 3896 /* 3897 * See if there was an error detected, if so, fdrecover() 3898 * will check it out and say what to do. 3899 * 3900 * Don't do this, though, if this was the Sense Drive Status 3901 * or the Dump Registers command. 3902 */ 3903 if (((csb->csb_rslt[0] & IC_SR0) || (fdc->c_csb.csb_dcsr_rslt) || 3904 (csb->csb_status)) && 3905 ((csb->csb_cmds[0] != FDRAW_SENSE_DRV) && 3906 (csb->csb_cmds[0] != DUMPREG))) { 3907 /* if it can restarted OK, then do so, else return error */ 3908 if (fdrecover(fdc) != 0) { 3909 if (fdc->c_fdtype & FDCTYPE_82077) { 3910 if (fdc->c_mtimeid == 0) { 3911 fdc->c_mtimeid = timeout(fdmotoff, 3912 a, Motoff_delay); 3913 } 3914 } 3915 3916 /* 3917 * If this was a dma transfer, unbind the handle so 3918 * that other transfers may use it. 3919 */ 3920 3921 (void) fd_unbind_handle(fdc); 3922 return (EIO); 3923 } else { 3924 /* ASSUMES that cmd is still intact in csb */ 3925 goto retry; 3926 } 3927 } 3928 3929 /* things went ok */ 3930 if (fdc->c_fdtype & FDCTYPE_82077) { 3931 if (fdc->c_mtimeid == 0) { 3932 fdc->c_mtimeid = timeout(fdmotoff, a, Motoff_delay); 3933 } 3934 } 3935 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: O K ..........\n")); 3936 3937 if (fd_unbind_handle(fdc)) 3938 return (EIO); 3939 3940 return (0); 3941 } 3942 3943 /* 3944 * Turn on the drive's motor 3945 * 3946 * - called with the low level lock held 3947 */ 3948 static void 3949 fdexec_turn_on_motor(struct fdctlr *fdc, int flags, uint_t unit) 3950 { 3951 clock_t local_lbolt; 3952 timeout_id_t timeid; 3953 3954 /* 3955 * The low level mutex may not be held over the call to 3956 * untimeout(). See the manpage for details. 3957 */ 3958 timeid = fdc->c_mtimeid; 3959 fdc->c_mtimeid = 0; 3960 if (timeid) { 3961 mutex_exit(&fdc->c_lolock); 3962 (void) untimeout(timeid); 3963 mutex_enter(&fdc->c_lolock); 3964 } 3965 3966 ASSERT(fdc->c_un->un_unit_no == unit); 3967 3968 3969 set_rotational_speed(fdc, unit); 3970 3971 if (!(Dor(fdc) & (MOTEN(unit)))) { 3972 /* 3973 * Turn on the motor 3974 */ 3975 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3976 (C, "fdexec: turning on motor\n")); 3977 3978 /* LINTED */ 3979 Set_dor(fdc, (MOTEN(unit)), 1); 3980 3981 if (flags & FDXC_SLEEP) { 3982 local_lbolt = ddi_get_lbolt(); 3983 (void) cv_timedwait(&fdc->c_motoncv, 3984 &fdc->c_lolock, local_lbolt + Moton_delay); 3985 } else { 3986 drv_usecwait(1000000); 3987 } 3988 } 3989 3990 } 3991 3992 /* 3993 * fdrecover 3994 * see if possible to retry an operation. 3995 * All we can do is restart the operation. If we are out of allowed 3996 * retries - return non-zero so that the higher levels will be notified. 3997 * 3998 * RETURNS: 0 if ok to restart, !0 if can't or out of retries 3999 * - called with the low level lock held 4000 */ 4001 static int 4002 fdrecover(struct fdctlr *fdc) 4003 { 4004 struct fdcsb *csb; 4005 4006 FDERRPRINT(FDEP_L1, FDEM_RECO, (C, "fdrecover\n")); 4007 csb = &fdc->c_csb; 4008 4009 if (fdc->c_flags & FDCFLG_TIMEDOUT) { 4010 struct fdcsb savecsb; 4011 4012 fdc->c_flags ^= FDCFLG_TIMEDOUT; 4013 csb->csb_rslt[1] |= TO_SR1; 4014 FDERRPRINT(FDEP_L1, FDEM_RECO, 4015 (C, "fd%d: %s timed out\n", csb->csb_unit, 4016 fdcmds[csb->csb_cmds[0] & 0x1f].cmdname)); 4017 4018 /* use private csb */ 4019 savecsb = fdc->c_csb; 4020 bzero(&fdc->c_csb, sizeof (struct fdcsb)); 4021 FDERRPRINT(FDEP_L1, FDEM_RECO, (C, "fdc: resetting\n")); 4022 4023 (void) fdreset(fdc); 4024 4025 if (fdc->c_fdtype & FDCTYPE_DMA) { 4026 mutex_enter(&fdc->c_hilock); 4027 /* Reset the DMA engine as well */ 4028 reset_dma_controller(fdc); 4029 set_dma_control_register(fdc, DCSR_INIT_BITS); 4030 mutex_exit(&fdc->c_hilock); 4031 } 4032 4033 4034 /* check change first?? */ 4035 /* don't ckchg in fdexec, too convoluted */ 4036 (void) fdrecalseek(fdc, savecsb.csb_unit, -1, 0); 4037 fdc->c_csb = savecsb; /* restore original csb */ 4038 } 4039 4040 /* 4041 * gather statistics on errors 4042 */ 4043 if (csb->csb_rslt[1] & DE_SR1) { 4044 fdc->fdstats.de++; 4045 } 4046 if (csb->csb_rslt[1] & OR_SR1) { 4047 fdc->fdstats.run++; 4048 } 4049 if (csb->csb_rslt[1] & (ND_SR1+MA_SR1)) { 4050 fdc->fdstats.bfmt++; 4051 } 4052 if (csb->csb_rslt[1] & TO_SR1) { 4053 fdc->fdstats.to++; 4054 } 4055 4056 /* 4057 * If raw ioctl don't examine results just pass status 4058 * back via fdraw. Raw commands are timed too, so put this 4059 * after the above check. 4060 */ 4061 if (csb->csb_opflags & CSB_OFRAWIOCTL) { 4062 return (1); 4063 } 4064 4065 4066 /* 4067 * if there was a pci bus error, do not retry 4068 */ 4069 4070 if (csb->csb_dcsr_rslt == 1) { 4071 FDERRPRINT(FDEP_L3, FDEM_RECO, 4072 (C, "fd%d: host bus error\n", 0)); 4073 return (1); 4074 } 4075 4076 /* 4077 * If there was an error with the DMA functions, do not retry 4078 */ 4079 if (csb->csb_dma_rslt == 1) { 4080 FDERRPRINT(FDEP_L1, FDEM_RECO, 4081 (C, "fd%d: DMA interface error\n", csb->csb_unit)); 4082 return (1); 4083 } 4084 4085 4086 /* 4087 * if we have run out of retries, return an error 4088 * XXX need better status interp 4089 */ 4090 4091 csb->csb_retrys++; 4092 if (csb->csb_retrys > csb->csb_maxretry) { 4093 FDERRPRINT(FDEP_L3, FDEM_RECO, 4094 (C, "fd%d: %s failed (%x %x %x)\n", 4095 0, fdcmds[csb->csb_cmds[0] & 0x1f].cmdname, 4096 csb->csb_rslt[0], csb->csb_rslt[1], csb->csb_rslt[2])); 4097 if (csb->csb_rslt[1] & NW_SR1) { 4098 FDERRPRINT(FDEP_L3, FDEM_RECO, 4099 (C, "fd%d: not writable\n", 0)); 4100 } 4101 if (csb->csb_rslt[1] & DE_SR1) { 4102 FDERRPRINT(FDEP_L3, FDEM_RECO, 4103 (C, "fd%d: crc error blk %d\n", 0, 4104 (int)fdc->c_current->b_blkno)); 4105 } 4106 if (csb->csb_rslt[1] & OR_SR1) { 4107 if (fdc->c_fdtype & FDCTYPE_SB) { 4108 /* 4109 * When using southbridge chip we need to 4110 * retry atleast 10 times to shake off the 4111 * underrun err. 4112 */ 4113 if (csb->csb_retrys <= rwretry) 4114 return (0); 4115 } 4116 FDERRPRINT(FDEP_L3, FDEM_RECO, 4117 (C, "fd%d: over/underrun\n", 0)); 4118 } 4119 4120 if (csb->csb_rslt[1] & (ND_SR1+MA_SR1)) { 4121 FDERRPRINT(FDEP_L3, FDEM_RECO, 4122 (C, "fd%d: bad format\n", 0)); 4123 } 4124 4125 if (csb->csb_rslt[1] & TO_SR1) { 4126 FDERRPRINT(FDEP_L3, FDEM_RECO, 4127 (C, "fd%d: timeout\n", 0)); 4128 } 4129 4130 csb->csb_cmdstat = 1; /* failed - give up */ 4131 return (1); 4132 } 4133 4134 if (csb->csb_opflags & CSB_OFSEEKOPS) { 4135 /* seek, recal type commands - just look at st0 */ 4136 FDERRPRINT(FDEP_L2, FDEM_RECO, 4137 (C, "fd%d: %s error : st0 0x%x\n", csb->csb_unit, 4138 fdcmds[csb->csb_cmds[0] & 0x1f].cmdname, 4139 csb->csb_rslt[0])); 4140 } 4141 if (csb->csb_opflags & CSB_OFXFEROPS) { 4142 /* rd, wr, fmt type commands - look at st0, st1, st2 */ 4143 FDERRPRINT(FDEP_L2, FDEM_RECO, 4144 (C, "fd%d: %s error : st0=0x%x st1=0x%x st2=0x%x\n", 4145 csb->csb_unit, fdcmds[csb->csb_cmds[0] & 0x1f].cmdname, 4146 csb->csb_rslt[0], csb->csb_rslt[1], csb->csb_rslt[2])); 4147 } 4148 4149 return (0); /* tell fdexec to retry */ 4150 } 4151 4152 /* 4153 * Interrupt handle for DMA 4154 */ 4155 4156 static uint_t 4157 fdintr_dma() 4158 { 4159 struct fdctlr *fdc; 4160 off_t off; 4161 size_t len; 4162 uint_t ccount; 4163 uint_t windex; 4164 uint_t done = 0; 4165 int tmp_dcsr; 4166 int to; 4167 uchar_t tmp; 4168 int i = 0; 4169 int res = DDI_INTR_UNCLAIMED; 4170 int not_cheerio = 1; 4171 4172 /* search for a controller that's expecting an interrupt */ 4173 fdc = fdctlrs; 4174 4175 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 4176 tmp_dcsr = get_dma_control_register(fdc); 4177 if (!(tmp_dcsr & DCSR_INT_PEND) && !(DCSR_ERR_PEND & tmp_dcsr)) 4178 return (res); 4179 not_cheerio = 0; 4180 } 4181 4182 mutex_enter(&fdc->c_hilock); 4183 4184 if (fdc->c_csb.csb_opmode == 0x0) { 4185 fdc->c_csb.csb_opmode = 2; 4186 } 4187 if (fdc->sb_dma_lock) { 4188 release_sb_dma(fdc); 4189 } 4190 4191 /* 4192 * An interrupt can come from either the floppy controller or 4193 * or the DMA engine. The DMA engine will only issue an 4194 * interrupt if there was an error. 4195 */ 4196 4197 switch (fdc->c_csb.csb_opmode) { 4198 case 0x1: 4199 /* read/write/format data-xfer case */ 4200 4201 FDERRPRINT(FDEP_L1, FDEM_INTR, 4202 (C, "fdintr_dma: opmode 1\n")); 4203 4204 /* 4205 * See if the interrupt is from the floppy 4206 * controller. If there is, take out the status bytes. 4207 */ 4208 4209 if (not_cheerio || (tmp_dcsr & DCSR_INT_PEND)) { 4210 4211 FDERRPRINT(FDEP_L1, FDEM_INTR, 4212 (C, "fdintr_dma: INT_PEND \n")); 4213 4214 res = DDI_INTR_CLAIMED; 4215 4216 to = FD_RRETRY; 4217 fdc->c_csb.csb_nrslts = 0; 4218 4219 /* check status */ 4220 i = 0; 4221 4222 /* 4223 * CB turns off once all the result bytes are 4224 * read. 4225 * 4226 * NOTE: the counters are there so that the 4227 * handler will never get stuck in a loop. 4228 * If the counters do reach their maximum 4229 * values, then a catastrophic error has 4230 * occurred. This should never be the case. 4231 * The counters only came into play during 4232 * development. 4233 */ 4234 while (((tmp = Msr(fdc)) & CB) && 4235 (i < 1000001)) { 4236 4237 /* 4238 * If RQM + DIO, then a result byte 4239 * is at hand. 4240 */ 4241 if ((tmp & (RQM|DIO|CB)) == 4242 (RQM|DIO|CB)) { 4243 fdc->c_csb.csb_rslt 4244 [fdc->c_csb.csb_nrslts++] 4245 = Fifo(fdc); 4246 4247 FDERRPRINT(FDEP_L1, FDEM_INTR, 4248 (C, "fdintr_dma: res 0x%x\n", 4249 fdc->c_csb.csb_rslt 4250 [fdc->c_csb.csb_nrslts 4251 - 1])); 4252 4253 } else if (--to == 0) { 4254 /* 4255 * controller was never 4256 * ready to give results 4257 */ 4258 fdc->c_csb.csb_status = 2; 4259 break; 4260 } 4261 i++; 4262 } 4263 if (i == 10000) { 4264 FDERRPRINT(FDEP_L1, FDEM_INTR, 4265 (C, "First loop overran\n")); 4266 } 4267 } 4268 4269 /* 4270 * See if the interrupt is from the DMA engine, 4271 * which will only interrupt on an error 4272 */ 4273 if ((!not_cheerio) && (tmp_dcsr & DCSR_ERR_PEND)) { 4274 4275 res = DDI_INTR_CLAIMED; 4276 4277 done = 1; 4278 fdc->c_csb.csb_dcsr_rslt = 1; 4279 FDERRPRINT(FDEP_L1, FDEM_INTR, 4280 (C, "fdintr_dma: Error pending\n")); 4281 reset_dma_controller(fdc); 4282 set_dma_control_register(fdc, DCSR_INIT_BITS); 4283 break; 4284 } 4285 4286 /* TCBUG kludge */ 4287 if ((fdc->c_fdtype & FDCTYPE_TCBUG) && 4288 ((fdc->c_csb.csb_rslt[0] & IC_SR0) == 0x40) && 4289 (fdc->c_csb.csb_rslt[1] & EN_SR1)) { 4290 4291 fdc->c_csb.csb_rslt[0] &= ~IC_SR0; 4292 4293 fdc->c_csb.csb_rslt[1] &= ~EN_SR1; 4294 4295 4296 } 4297 4298 4299 /* Exit if there were errors in the DMA */ 4300 if (((fdc->c_csb.csb_rslt[0] & IC_SR0) != 0) || 4301 (fdc->c_csb.csb_rslt[1] != 0) || 4302 (fdc->c_csb.csb_rslt[2] != 0)) { 4303 done = 1; 4304 FDERRPRINT(FDEP_L1, FDEM_INTR, 4305 (C, "fdintr_dma: errors in command\n")); 4306 4307 4308 break; 4309 } 4310 4311 4312 FDERRPRINT(FDEP_L1, FDEM_INTR, 4313 (C, "fdintr_dma: dbcr 0x%x\n", 4314 get_data_count_register(fdc))); 4315 /* 4316 * The csb_ccount is the number of cookies that still 4317 * need to be processed. A cookie was just processed 4318 * so decrement the cookie counter. 4319 */ 4320 if (fdc->c_csb.csb_ccount == 0) { 4321 done = 1; 4322 break; 4323 } 4324 fdc->c_csb.csb_ccount--; 4325 ccount = fdc->c_csb.csb_ccount; 4326 4327 windex = fdc->c_csb.csb_windex; 4328 4329 /* 4330 * If there are no more cookies and all the windows 4331 * have been DMA'd, then DMA is done. 4332 * 4333 */ 4334 if ((ccount == 0) && (windex == fdc->c_csb.csb_nwin)) { 4335 4336 done = 1; 4337 4338 /* 4339 * The handle is unbound in fdexec 4340 */ 4341 4342 break; 4343 } 4344 4345 if (ccount != 0) { 4346 /* process the next cookie */ 4347 ddi_dma_nextcookie(fdc->c_dmahandle, 4348 &fdc->c_csb.csb_dmacookie); 4349 4350 FDERRPRINT(FDEP_L1, FDEM_INTR, 4351 (C, "cookie addr 0x%" PRIx64 "\n", 4352 fdc->c_csb.csb_dmacookie.dmac_laddress)); 4353 4354 FDERRPRINT(FDEP_L1, FDEM_INTR, 4355 (C, "cookie length %lu\n", 4356 fdc->c_csb.csb_dmacookie.dmac_size)); 4357 4358 } else { 4359 4360 (void) ddi_dma_getwin(fdc->c_dmahandle, 4361 fdc->c_csb.csb_windex, 4362 &off, &len, 4363 &fdc->c_csb.csb_dmacookie, 4364 &fdc->c_csb.csb_ccount); 4365 fdc->c_csb.csb_windex++; 4366 4367 FDERRPRINT(FDEP_L1, FDEM_INTR, 4368 (C, "fdintr_dma: process %d window\n", 4369 fdc->c_csb.csb_windex)); 4370 4371 FDERRPRINT(FDEP_L1, FDEM_INTR, 4372 (C, "fdintr_dma: process no. cookies %d\n", 4373 fdc->c_csb.csb_ccount)); 4374 4375 FDERRPRINT(FDEP_L1, FDEM_INTR, 4376 (C, "cookie addr 0x%" PRIx64 "\n", 4377 fdc->c_csb.csb_dmacookie.dmac_laddress)); 4378 4379 FDERRPRINT(FDEP_L1, FDEM_INTR, 4380 (C, "cookie length %lu\n", 4381 fdc->c_csb.csb_dmacookie.dmac_size)); 4382 } 4383 4384 /* 4385 * Program the DMA engine with the length and 4386 * the address of the transfer 4387 */ 4388 4389 ASSERT(fdc->c_csb.csb_dmacookie.dmac_size); 4390 4391 set_data_count_register(fdc, 4392 fdc->c_csb.csb_dmacookie.dmac_size); 4393 set_data_address_register(fdc, 4394 fdc->c_csb.csb_dmacookie.dmac_laddress); 4395 4396 FDERRPRINT(FDEP_L1, FDEM_INTR, (C, 4397 "fdintr_dma: size 0x%lx\n", 4398 fdc->c_csb.csb_dmacookie.dmac_size)); 4399 4400 4401 /* reprogram the controller */ 4402 fdc->c_csb.csb_cmds[2] = fdc->c_csb.csb_rslt[3]; 4403 fdc->c_csb.csb_cmds[3] = fdc->c_csb.csb_rslt[4]; 4404 fdc->c_csb.csb_cmds[4] = fdc->c_csb.csb_rslt[5]; 4405 fdc->c_csb.csb_cmds[1] = (fdc->c_csb.csb_cmds[1] 4406 & ~0x04) | (fdc->c_csb.csb_rslt[4] << 2); 4407 4408 for (i = 0; i < (int)fdc->c_csb.csb_ncmds; i++) { 4409 4410 /* 4411 * Test the readiness of the controller 4412 * to receive the cmd 4413 */ 4414 for (to = FD_CRETRY; to; to--) { 4415 if ((Msr(fdc) & (DIO|RQM)) == RQM) 4416 break; 4417 } 4418 if (to == 0) { 4419 FDERRPRINT(FDEP_L2, FDEM_EXEC, 4420 (C, 4421 "fdc: no RQM - stat 0x%x\n", Msr(fdc))); 4422 /* stop the DMA from happening */ 4423 fdc->c_csb.csb_status = 2; 4424 done = 1; 4425 break; 4426 } 4427 4428 Set_Fifo(fdc, fdc->c_csb.csb_cmds[i]); 4429 4430 FDERRPRINT(FDEP_L1, FDEM_INTR, 4431 (C, 4432 "fdintr_dma: sent 0x%x, Msr 0x%x\n", 4433 fdc->c_csb.csb_cmds[i], Msr(fdc))); 4434 } 4435 4436 /* reenable DMA */ 4437 if ((!not_cheerio) && (!done)) 4438 set_dma_control_register(fdc, tmp_dcsr | 4439 DCSR_EN_DMA); 4440 break; 4441 4442 case 0x2: 4443 /* seek/recal type cmd */ 4444 FDERRPRINT(FDEP_L1, FDEM_INTR, 4445 (C, "fintr_dma: opmode 2\n")); 4446 4447 /* 4448 * See if the interrupt is from the DMA engine, 4449 * which will only interrupt if there was an error. 4450 */ 4451 if ((!not_cheerio) && (tmp_dcsr & DCSR_ERR_PEND)) { 4452 res = DDI_INTR_CLAIMED; 4453 done = 1; 4454 fdc->c_csb.csb_dcsr_rslt = 1; 4455 reset_dma_controller(fdc); 4456 set_dma_control_register(fdc, DCSR_INIT_BITS); 4457 4458 break; 4459 } 4460 4461 4462 /* See if the interrupt is from the floppy controller */ 4463 if (not_cheerio || (tmp_dcsr & DCSR_INT_PEND)) { 4464 4465 res = DDI_INTR_CLAIMED; 4466 4467 4468 /* 4469 * Wait until there's no longer a command 4470 * in progress 4471 */ 4472 4473 FDERRPRINT(FDEP_L1, FDEM_INTR, 4474 (C, "fdintr_dma: interrupt pending\n")); 4475 i = 0; 4476 while (((Msr(fdc) & CB)) && (i < 10000)) { 4477 i++; 4478 } 4479 4480 if (i == 10000) 4481 FDERRPRINT(FDEP_L1, FDEM_INTR, 4482 (C, "2nd loop overran !!!\n")); 4483 4484 /* 4485 * Check the RQM bit to see if the controller is 4486 * ready to transfer status of the command. 4487 */ 4488 i = 0; 4489 while ((!(Msr(fdc) & RQM)) && (i < 10000)) { 4490 i++; 4491 } 4492 4493 if (i == 10000) 4494 FDERRPRINT(FDEP_L1, FDEM_INTR, 4495 (C, "3rd loop overran !!!\n")); 4496 4497 /* 4498 * Issue the Sense Interrupt Status Command 4499 */ 4500 Set_Fifo(fdc, SNSISTAT); 4501 4502 i = 0; 4503 while ((!(Msr(fdc) & RQM)) && (i < 10000)) { 4504 i++; 4505 } 4506 if (i == 10000) 4507 FDERRPRINT(FDEP_L1, FDEM_INTR, 4508 (C, "4th loop overran !!!\n")); 4509 4510 /* Store the first result byte */ 4511 fdc->c_csb.csb_rslt[0] = Fifo(fdc); 4512 4513 i = 0; 4514 while ((!(Msr(fdc) & RQM)) && (i < 10000)) { 4515 i++; 4516 } 4517 if (i == 10000) 4518 FDERRPRINT(FDEP_L1, FDEM_INTR, 4519 (C, "5th loop overran !!!\n")); 4520 4521 /* Store the second result byte */ 4522 fdc->c_csb.csb_rslt[1] = Fifo(fdc); 4523 4524 done = 1; 4525 } 4526 4527 } 4528 4529 /* 4530 * We are done with the actual interrupt handling here. 4531 * The portion below should be actually be done by fd_lointr(). 4532 * We should be triggering the fd_lointr here and exiting. 4533 * However for want of time this will be done in the next FIX. 4534 * 4535 * Hence for now we will release hilock only and keep the remaining 4536 * code as it is. 4537 * Releasing of hilock ensures that we don't hold on to the 4538 * lolock and hilock at the same time. 4539 * hilock is acquired each time dma related registers are accessed. 4540 */ 4541 mutex_exit(&fdc->c_hilock); 4542 /* Make signal and get out of interrupt handler */ 4543 if (done) { 4544 mutex_enter(&fdc->c_lolock); 4545 4546 fdc->c_csb.csb_opmode = 0; 4547 4548 /* reset watchdog timer if armed and not already triggered */ 4549 4550 4551 if (fdc->c_timeid) { 4552 timeout_id_t timeid = fdc->c_timeid; 4553 fdc->c_timeid = 0; 4554 mutex_exit(&fdc->c_lolock); 4555 (void) untimeout(timeid); 4556 mutex_enter(&fdc->c_lolock); 4557 } 4558 4559 4560 if (fdc->c_flags & FDCFLG_WAITING) { 4561 /* 4562 * somebody's waiting on finish of fdctlr/csb, 4563 * wake them 4564 */ 4565 4566 FDERRPRINT(FDEP_L1, FDEM_INTR, 4567 (C, "fdintr_dma: signal the waiter\n")); 4568 4569 fdc->c_flags ^= FDCFLG_WAITING; 4570 cv_signal(&fdc->c_iocv); 4571 4572 /* 4573 * FDCFLG_BUSY is NOT cleared, NOR is the csb given 4574 * back; the operation just finished can look at the csb 4575 */ 4576 } else { 4577 FDERRPRINT(FDEP_L1, FDEM_INTR, 4578 (C, "fdintr_dma: nobody sleeping (%x %x %x)\n", 4579 fdc->c_csb.csb_rslt[0], fdc->c_csb.csb_rslt[1], 4580 fdc->c_csb.csb_rslt[2])); 4581 } 4582 mutex_exit(&fdc->c_lolock); 4583 } 4584 /* update high level interrupt counter */ 4585 if (fdc->c_intrstat) 4586 KIOIP->intrs[KSTAT_INTR_HARD]++; 4587 4588 4589 FDERRPRINT(FDEP_L1, FDEM_INTR, (C, "fdintr_dma: done\n")); 4590 return (res); 4591 } 4592 4593 /* 4594 * fd_lointr 4595 * This is the low level SW interrupt handler triggered by the high 4596 * level interrupt handler (or by fdwatch). 4597 */ 4598 static uint_t 4599 fd_lointr(caddr_t arg) 4600 { 4601 struct fdctlr *fdc = (struct fdctlr *)arg; 4602 struct fdcsb *csb; 4603 4604 csb = &fdc->c_csb; 4605 FDERRPRINT(FDEP_L1, FDEM_INTR, (C, "fdintr: opmode %d\n", 4606 csb->csb_opmode)); 4607 /* 4608 * Check that lowlevel interrupt really meant to trigger us. 4609 */ 4610 if (csb->csb_opmode != 4) { 4611 /* 4612 * This should probably be protected, but, what the 4613 * heck...the cost isn't worth the accuracy for this 4614 * statistic. 4615 */ 4616 if (fdc->c_intrstat) 4617 KIOIP->intrs[KSTAT_INTR_SPURIOUS]++; 4618 return (DDI_INTR_UNCLAIMED); 4619 } 4620 4621 mutex_enter(&fdc->c_lolock); 4622 csb->csb_opmode = 0; 4623 4624 /* reset watchdog timer if armed and not already triggered */ 4625 if (fdc->c_timeid) { 4626 timeout_id_t timeid = fdc->c_timeid; 4627 fdc->c_timeid = 0; 4628 mutex_exit(&fdc->c_lolock); 4629 (void) untimeout(timeid); 4630 mutex_enter(&fdc->c_lolock); 4631 4632 } 4633 4634 if (fdc->c_flags & FDCFLG_WAITING) { 4635 /* 4636 * somebody's waiting on finish of fdctlr/csb, wake them 4637 */ 4638 fdc->c_flags ^= FDCFLG_WAITING; 4639 cv_signal(&fdc->c_iocv); 4640 4641 /* 4642 * FDCFLG_BUSY is NOT cleared, NOR is the csb given back; so 4643 * the operation just finished can look at the csb 4644 */ 4645 } else { 4646 FDERRPRINT(FDEP_L3, FDEM_INTR, 4647 (C, "fdintr: nobody sleeping (%x %x %x)\n", 4648 csb->csb_rslt[0], csb->csb_rslt[1], csb->csb_rslt[2])); 4649 } 4650 if (fdc->c_intrstat) 4651 KIOIP->intrs[KSTAT_INTR_SOFT]++; 4652 mutex_exit(&fdc->c_lolock); 4653 return (DDI_INTR_CLAIMED); 4654 } 4655 4656 /* 4657 * fdwatch 4658 * is called from timein() when a floppy operation has expired. 4659 */ 4660 static void 4661 fdwatch(void *arg) 4662 { 4663 struct fdctlr *fdc = arg; 4664 int old_opmode; 4665 struct fdcsb *csb; 4666 4667 FDERRPRINT(FDEP_L1, FDEM_WATC, (C, "fdwatch\n")); 4668 4669 mutex_enter(&fdc->c_lolock); 4670 if (fdc->c_timeid == 0) { 4671 /* 4672 * fdintr got here first, ergo, no timeout condition.. 4673 */ 4674 4675 FDERRPRINT(FDEP_L1, FDEM_WATC, 4676 (C, "fdwatch: no timeout\n")); 4677 4678 mutex_exit(&fdc->c_lolock); 4679 return; 4680 } 4681 fdc->c_timeid = 0; 4682 csb = &fdc->c_csb; 4683 4684 mutex_enter(&fdc->c_hilock); 4685 /* 4686 * XXXX: We should probably reset the bloody chip 4687 */ 4688 old_opmode = csb->csb_opmode; 4689 4690 FDERRPRINT(FDEP_L1, FDEM_WATC, 4691 (C, "fd%d: timeout, opmode:%d\n", csb->csb_unit, old_opmode)); 4692 4693 csb->csb_opmode = 4; 4694 mutex_exit(&fdc->c_hilock); 4695 4696 FDERRPRINT(FDEP_L1, FDEM_WATC, (C, "fdwatch: cmd %s timed out\n", 4697 fdcmds[csb->csb_cmds[0] & 0x1f].cmdname)); 4698 fdc->c_flags |= FDCFLG_TIMEDOUT; 4699 csb->csb_status = CSB_CMDTO; 4700 4701 if ((fdc->c_fdtype & FDCTYPE_DMA) == 0) { 4702 ddi_trigger_softintr(fdc->c_softid); 4703 KIOIP->intrs[KSTAT_INTR_WATCHDOG]++; 4704 mutex_exit(&fdc->c_lolock); 4705 } else { 4706 mutex_exit(&fdc->c_lolock); 4707 (void) fd_lointr((caddr_t)fdctlrs); 4708 } 4709 } 4710 4711 /* 4712 * fdgetcsb 4713 * wait until the csb is free 4714 */ 4715 static void 4716 fdgetcsb(struct fdctlr *fdc) 4717 { 4718 FDERRPRINT(FDEP_L1, FDEM_GETC, (C, "fdgetcsb\n")); 4719 ASSERT(mutex_owned(&fdc->c_lolock)); 4720 while (fdc->c_flags & FDCFLG_BUSY) { 4721 fdc->c_flags |= FDCFLG_WANT; 4722 cv_wait(&fdc->c_csbcv, &fdc->c_lolock); 4723 } 4724 fdc->c_flags |= FDCFLG_BUSY; /* got it! */ 4725 } 4726 4727 /* 4728 * fdretcsb 4729 * return csb 4730 */ 4731 static void 4732 fdretcsb(struct fdctlr *fdc) 4733 { 4734 4735 ASSERT(mutex_owned(&fdc->c_lolock)); 4736 FDERRPRINT(FDEP_L1, FDEM_RETC, (C, "fdretcsb\n")); 4737 fdc->c_flags &= ~FDCFLG_BUSY; /* let go */ 4738 4739 fdc->c_csb.csb_read = 0; 4740 4741 if (fdc->c_flags & FDCFLG_WANT) { 4742 fdc->c_flags ^= FDCFLG_WANT; 4743 /* 4744 * broadcast the signal. One thread will wake up and 4745 * set the flags to FDCFLG_BUSY. If more than one thread is 4746 * waiting then each thread will wake up in turn. The first 4747 * thread to wake-up will set the FDCFLG_BUSY flag and the 4748 * subsequent threads will will wake-up, but reset the 4749 * flag to FDCFLG_WANT because the FDCFLG_BUSY bit is set. 4750 */ 4751 cv_broadcast(&fdc->c_csbcv); 4752 } 4753 } 4754 4755 4756 /* 4757 * fdreset 4758 * reset THE controller, and configure it to be 4759 * the way it ought to be 4760 * ASSUMES: that it already owns the csb/fdctlr! 4761 * 4762 * - called with the low level lock held 4763 */ 4764 static int 4765 fdreset(struct fdctlr *fdc) 4766 { 4767 struct fdcsb *csb; 4768 clock_t local_lbolt = 0; 4769 timeout_id_t timeid; 4770 4771 FDERRPRINT(FDEP_L1, FDEM_RESE, (C, "fdreset\n")); 4772 4773 ASSERT(mutex_owned(&fdc->c_lolock)); 4774 4775 /* count resets */ 4776 fdc->fdstats.reset++; 4777 4778 /* 4779 * On the 82077, the DSR will clear itself after a reset. Upon exiting 4780 * the reset, a polling interrupt will be generated. If the floppy 4781 * interrupt is enabled, it's possible for cv_signal() to be called 4782 * before cv_wait(). This will cause the system to hang. Turn off 4783 * the floppy interrupt to avoid this race condition 4784 */ 4785 if ((fdc->c_fdtype & FDCTYPE_CTRLMASK) == FDCTYPE_82077) { 4786 /* 4787 * We need to perform any timeouts before we Reset the 4788 * controller. We cannot afford to drop the c_lolock mutex after 4789 * Resetting the controller. The reason is that we get a spate 4790 * of interrupts until we take the controller out of reset. 4791 * The way we avoid this spate of continuous interrupts is by 4792 * holding on to the c_lolock and forcing the fdintr_dma routine 4793 * to go to sleep waiting for this mutex. 4794 */ 4795 /* Do not hold the mutex across the untimeout call */ 4796 timeid = fdc->c_mtimeid; 4797 fdc->c_mtimeid = 0; 4798 if (timeid) { 4799 mutex_exit(&fdc->c_lolock); 4800 (void) untimeout(timeid); 4801 mutex_enter(&fdc->c_lolock); 4802 } 4803 /* LINTED */ 4804 Set_dor(fdc, DMAGATE, 0); 4805 FDERRPRINT(FDEP_L1, FDEM_RESE, (C, "fdreset: set dor\n")); 4806 } 4807 4808 /* toggle software reset */ 4809 Dsr(fdc, SWR); 4810 4811 drv_usecwait(5); 4812 4813 FDERRPRINT(FDEP_L1, FDEM_RESE, 4814 (C, "fdreset: toggled software reset\n")); 4815 4816 /* 4817 * This sets the data rate to 500Kbps (for high density) 4818 * XXX should use current characteristics instead XXX 4819 */ 4820 Dsr(fdc, 0); 4821 drv_usecwait(5); 4822 switch (fdc->c_fdtype & FDCTYPE_CTRLMASK) { 4823 case FDCTYPE_82077: 4824 /* 4825 * when we bring the controller out of reset it will generate 4826 * a polling interrupt. fdintr() will field it and schedule 4827 * fd_lointr(). There will be no one sleeping but we are 4828 * expecting an interrupt so.... 4829 */ 4830 fdc->c_flags |= FDCFLG_WAITING; 4831 4832 /* 4833 * The reset bit must be cleared to take the 077 out of 4834 * reset state and the DMAGATE bit must be high to enable 4835 * interrupts. 4836 */ 4837 /* LINTED */ 4838 Set_dor(fdc, DMAGATE|RESET, 1); 4839 4840 FDERRPRINT(FDEP_L1, FDEM_ATTA, 4841 (C, "fdattach: Dor 0x%x\n", Dor(fdc))); 4842 4843 local_lbolt = ddi_get_lbolt(); 4844 if (cv_timedwait(&fdc->c_iocv, &fdc->c_lolock, 4845 local_lbolt + drv_usectohz(1000000)) == -1) { 4846 return (-1); 4847 } 4848 break; 4849 4850 default: 4851 fdc->c_flags |= FDCFLG_WAITING; 4852 4853 /* 4854 * A timed wait is not used because it's possible for the timer 4855 * to go off before the controller has a chance to interrupt. 4856 */ 4857 cv_wait(&fdc->c_iocv, &fdc->c_lolock); 4858 break; 4859 } 4860 csb = &fdc->c_csb; 4861 4862 /* setup common things in csb */ 4863 csb->csb_unit = fdc->c_un->un_unit_no; 4864 csb->csb_nrslts = 0; 4865 csb->csb_opflags = CSB_OFNORESULTS; 4866 csb->csb_maxretry = 0; 4867 csb->csb_retrys = 0; 4868 4869 csb->csb_read = CSB_NULL; 4870 4871 /* send SPECIFY command to fdc */ 4872 /* csb->unit is don't care */ 4873 csb->csb_cmds[0] = FDRAW_SPECIFY; 4874 csb->csb_cmds[1] = fdspec[0]; /* step rate, head unload time */ 4875 if (fdc->c_fdtype & FDCTYPE_DMA) 4876 csb->csb_cmds[2] = SPEC_DMA_MODE; 4877 else 4878 csb->csb_cmds[2] = fdspec[1]; /* head load time, DMA mode */ 4879 4880 csb->csb_ncmds = 3; 4881 4882 /* XXX for now ignore errors, they "CAN'T HAPPEN" */ 4883 (void) fdexec(fdc, 0); /* no FDXC_CHECKCHG, ... */ 4884 /* no results */ 4885 4886 /* send CONFIGURE command to fdc */ 4887 /* csb->unit is don't care */ 4888 csb->csb_cmds[0] = CONFIGURE; 4889 csb->csb_cmds[1] = fdconf[0]; /* motor info, motor delays */ 4890 csb->csb_cmds[2] = fdconf[1]; /* enaimplsk, disapoll, fifothru */ 4891 csb->csb_cmds[3] = fdconf[2]; /* track precomp */ 4892 csb->csb_ncmds = 4; 4893 4894 csb->csb_read = CSB_NULL; 4895 4896 csb->csb_retrys = 0; 4897 4898 /* XXX for now ignore errors, they "CAN'T HAPPEN" */ 4899 (void) fdexec(fdc, 0); /* no FDXC_CHECKCHG, ... */ 4900 return (0); 4901 } 4902 4903 /* 4904 * fdrecalseek 4905 * performs recalibrates or seeks if the "arg" is -1 does a 4906 * recalibrate on a drive, else it seeks to the cylinder of 4907 * the drive. The recalibrate is also used to find a drive, 4908 * ie if the drive is not there, the controller says "error" 4909 * on the operation 4910 * NOTE: that there is special handling of this operation in the hardware 4911 * interrupt routine - it causes the operation to appear to have results; 4912 * ie the results of the SENSE INTERRUPT STATUS that the hardware interrupt 4913 * function did for us. 4914 * NOTE: because it uses sleep/wakeup it must be protected in a critical 4915 * section so create one before calling it! 4916 * 4917 * RETURNS: 0 for ok, 4918 * else errno from fdexec, 4919 * or ENODEV if error (infers hardware type error) 4920 * 4921 * - called with the low level lock held 4922 */ 4923 static int 4924 fdrecalseek(struct fdctlr *fdc, int unit, int arg, int execflg) 4925 { 4926 struct fdcsb *csb; 4927 int result; 4928 4929 ASSERT(fdc->c_un->un_unit_no == unit); 4930 4931 FDERRPRINT(FDEP_L1, FDEM_RECA, (C, "fdrecalseek to %d\n", arg)); 4932 4933 /* XXX TODO: check see argument for <= num cyls OR < 256 */ 4934 4935 csb = &fdc->c_csb; 4936 csb->csb_unit = (uchar_t)unit; 4937 csb->csb_cmds[1] = unit & 0x03; 4938 4939 if (arg == -1) { /* is recal... */ 4940 csb->csb_cmds[0] = FDRAW_REZERO; 4941 csb->csb_ncmds = 2; 4942 } else { 4943 csb->csb_cmds[0] = FDRAW_SEEK; 4944 csb->csb_cmds[2] = (uchar_t)arg; 4945 csb->csb_ncmds = 3; 4946 } 4947 csb->csb_nrslts = 2; /* 2 for SENSE INTERRUPTS */ 4948 csb->csb_opflags = CSB_OFSEEKOPS | CSB_OFTIMEIT; 4949 /* 4950 * MAYBE NYD need to set retries to different values? - depending on 4951 * drive characteristics - if we get to high capacity drives 4952 */ 4953 csb->csb_maxretry = skretry; 4954 csb->csb_retrys = 0; 4955 4956 /* send cmd off to fdexec */ 4957 if (result = fdexec(fdc, FDXC_SLEEP | execflg)) { 4958 goto out; 4959 } 4960 4961 /* 4962 * if recal, test for equipment check error 4963 * ASSUMES result = 0 from above call 4964 */ 4965 if (arg == -1) { 4966 result = 0; 4967 } else { 4968 /* for seeks, any old error will do */ 4969 if ((csb->csb_rslt[0] & IC_SR0) || csb->csb_cmdstat) 4970 result = ENODEV; 4971 } 4972 4973 out: 4974 return (result); 4975 } 4976 4977 /* 4978 * fdsensedrv 4979 * do a sense_drive command. used by fdopen and fdcheckdisk. 4980 * 4981 * - called with the lock held 4982 */ 4983 static int 4984 fdsensedrv(struct fdctlr *fdc, int unit) 4985 { 4986 struct fdcsb *csb; 4987 4988 ASSERT(fdc->c_un->un_unit_no == unit); 4989 4990 csb = &fdc->c_csb; 4991 4992 /* setup common things in csb */ 4993 csb->csb_unit = (uchar_t)unit; 4994 csb->csb_opflags = CSB_OFIMMEDIATE; 4995 csb->csb_cmds[0] = FDRAW_SENSE_DRV; 4996 /* MOT bit set means don't delay */ 4997 csb->csb_cmds[1] = MOT | (unit & 0x03); 4998 csb->csb_ncmds = 2; 4999 csb->csb_nrslts = 1; 5000 csb->csb_maxretry = skretry; 5001 csb->csb_retrys = 0; 5002 5003 /* XXX for now ignore errors, they "CAN'T HAPPEN" */ 5004 (void) fdexec(fdc, 0); /* DON't check changed!, no sleep */ 5005 5006 FDERRPRINT(FDEP_L1, FDEM_CHEK, 5007 (C, "fdsensedrv: result 0x%x", csb->csb_rslt[0])); 5008 5009 return (csb->csb_rslt[0]); /* return status byte 3 */ 5010 } 5011 5012 /* 5013 * fdcheckdisk 5014 * check to see if the disk is still there - do a recalibrate, 5015 * then see if DSKCHG line went away, if so, diskette is in; else 5016 * it's (still) out. 5017 */ 5018 5019 static int 5020 fdcheckdisk(struct fdctlr *fdc, int unit) 5021 { 5022 auto struct fdcsb savecsb; 5023 struct fdcsb *csb; 5024 int err, st3; 5025 int seekto; /* where to seek for reset of DSKCHG */ 5026 5027 FDERRPRINT(FDEP_L1, FDEM_CHEK, 5028 (C, "fdcheckdisk, unit %d\n", unit)); 5029 5030 ASSERT(fdc->c_un->un_unit_no == unit); 5031 5032 /* 5033 * save old csb 5034 */ 5035 5036 csb = &fdc->c_csb; 5037 savecsb = fdc->c_csb; 5038 bzero((caddr_t)csb, sizeof (*csb)); 5039 5040 /* 5041 * Read drive status to see if at TRK0, if so, seek to cyl 1, 5042 * else seek to cyl 0. We do this because the controller is 5043 * "smart" enough to not send any step pulses (which are how 5044 * the DSKCHG line gets reset) if it sees TRK0 'cause it 5045 * knows the drive is already recalibrated. 5046 */ 5047 st3 = fdsensedrv(fdc, unit); 5048 5049 /* check TRK0 bit in status */ 5050 if (st3 & T0_SR3) 5051 seekto = 1; /* at TRK0, seek out */ 5052 else 5053 seekto = 0; 5054 5055 /* 5056 * DON'T recurse check changed 5057 */ 5058 err = fdrecalseek(fdc, unit, seekto, 0); 5059 5060 /* "restore" old csb, check change state */ 5061 fdc->c_csb = savecsb; 5062 5063 /* any recal/seek errors are too serious to attend to */ 5064 if (err) { 5065 FDERRPRINT(FDEP_L2, FDEM_CHEK, 5066 (C, "fdcheckdisk err %d\n", err)); 5067 return (err); 5068 } 5069 5070 /* 5071 * if disk change still asserted, no diskette in drive! 5072 */ 5073 if (fdsense_chng(fdc, csb->csb_unit)) { 5074 FDERRPRINT(FDEP_L2, FDEM_CHEK, 5075 (C, "fdcheckdisk no disk\n")); 5076 return (1); 5077 } 5078 return (0); 5079 } 5080 5081 /* 5082 * fdselect() - select drive, needed for external to chip select logic 5083 * fdeject() - ejects drive, must be previously selected 5084 * fdsense_chng() - sense disk changed line from previously selected drive 5085 * return s 1 is signal asserted, else 0 5086 */ 5087 /* ARGSUSED */ 5088 static void 5089 fdselect(struct fdctlr *fdc, int unit, int on) 5090 { 5091 5092 ASSERT(fdc->c_un->un_unit_no == unit); 5093 5094 FDERRPRINT(FDEP_L1, FDEM_DSEL, 5095 (C, "fdselect, unit %d, on = %d\n", unit, on)); 5096 5097 switch (fdc->c_fdtype & FDCTYPE_AUXIOMASK) { 5098 case FDCTYPE_MACHIO: 5099 set_auxioreg(AUX_DRVSELECT, on); 5100 break; 5101 5102 case FDCTYPE_SLAVIO: 5103 case FDCTYPE_CHEERIO: 5104 FDERRPRINT(FDEP_L1, FDEM_ATTA, 5105 (C, "fdselect: (before) Dor 0x%x\n", Dor(fdc))); 5106 5107 if (unit == 0) { 5108 Set_dor(fdc, DRVSEL, !on); 5109 } else { 5110 Set_dor(fdc, DRVSEL, on); 5111 } 5112 5113 FDERRPRINT(FDEP_L1, FDEM_ATTA, 5114 (C, "fdselect: Dor 0x%x\n", Dor(fdc))); 5115 5116 break; 5117 5118 default: 5119 break; 5120 } 5121 } 5122 5123 /* ARGSUSED */ 5124 static void 5125 fdeject(struct fdctlr *fdc, int unit) 5126 { 5127 struct fdunit *un; 5128 5129 ASSERT(fdc->c_un->un_unit_no == unit); 5130 5131 un = fdc->c_un; 5132 5133 FDERRPRINT(FDEP_L1, FDEM_EJEC, (C, "fdeject\n")); 5134 /* 5135 * assume delay of function calling sufficient settling time 5136 * eject line is NOT driven by inverter so it is true low 5137 */ 5138 switch (fdc->c_fdtype & FDCTYPE_AUXIOMASK) { 5139 case FDCTYPE_MACHIO: 5140 set_auxioreg(AUX_EJECT, 0); 5141 drv_usecwait(2); 5142 set_auxioreg(AUX_EJECT, 1); 5143 break; 5144 5145 case FDCTYPE_SLAVIO: 5146 if (!(Dor(fdc) & MOTEN(unit))) { 5147 /* LINTED */ 5148 Set_dor(fdc, MOTEN(unit), 1); 5149 } 5150 drv_usecwait(2); /* just to settle */ 5151 /* LINTED */ 5152 Set_dor(fdc, EJECT, 1); 5153 drv_usecwait(2); 5154 /* LINTED */ 5155 Set_dor(fdc, EJECT, 0); 5156 break; 5157 case FDCTYPE_CHEERIO: 5158 if (!(Dor(fdc) & MOTEN(unit))) { 5159 /* LINTED */ 5160 Set_dor(fdc, MOTEN(unit), 1); 5161 } 5162 drv_usecwait(2); /* just to settle */ 5163 /* LINTED */ 5164 Set_dor(fdc, EJECT_DMA, 1); 5165 drv_usecwait(2); 5166 /* LINTED */ 5167 Set_dor(fdc, EJECT_DMA, 0); 5168 break; 5169 } 5170 /* 5171 * XXX set ejected state? 5172 */ 5173 un->un_ejected = 1; 5174 } 5175 5176 /* ARGSUSED */ 5177 static int 5178 fdsense_chng(struct fdctlr *fdc, int unit) 5179 { 5180 int changed = 0; 5181 5182 FDERRPRINT(FDEP_L1, FDEM_SCHG, (C, "fdsense_chng:start\n")); 5183 5184 ASSERT(fdc->c_un->un_unit_no == unit); 5185 5186 /* 5187 * Do not turn on the motor of a pollable drive 5188 */ 5189 if (fd_pollable) { 5190 FDERRPRINT(FDEP_L1, FDEM_SCHG, (C, "pollable: don't turn on motor\n")); 5191 /* 5192 * Invert the sense of the DSKCHG for pollable drives 5193 */ 5194 if (Dir(fdc) & DSKCHG) 5195 changed = 0; 5196 else 5197 changed = 1; 5198 5199 return (changed); 5200 } 5201 5202 switch (fdc->c_fdtype & FDCTYPE_AUXIOMASK) { 5203 case FDCTYPE_MACHIO: 5204 if (*fdc->c_auxiova & AUX_DISKCHG) 5205 changed = 1; 5206 break; 5207 5208 case FDCTYPE_SB: 5209 case FDCTYPE_SLAVIO: 5210 case FDCTYPE_CHEERIO: 5211 if (!(Dor(fdc) & MOTEN(unit))) { 5212 /* LINTED */ 5213 Set_dor(fdc, MOTEN(unit), 1); 5214 } 5215 drv_usecwait(2); /* just to settle */ 5216 if (Dir(fdc) & DSKCHG) 5217 changed = 1; 5218 break; 5219 } 5220 5221 FDERRPRINT(FDEP_L1, FDEM_SCHG, (C, "fdsense_chng:end\n")); 5222 5223 return (changed); 5224 } 5225 5226 /* 5227 * if it can read a valid label it does so, else it will use a 5228 * default. If it can`t read the diskette - that is an error. 5229 * 5230 * RETURNS: 0 for ok - meaning that it could at least read the device, 5231 * !0 for error XXX TBD NYD error codes 5232 * 5233 * - called with the low level lock held 5234 */ 5235 static int 5236 fdgetlabel(struct fdctlr *fdc, int unit) 5237 { 5238 struct dk_label *label = NULL; 5239 struct fdunit *un; 5240 short *sp; 5241 short count; 5242 short xsum; /* checksum */ 5243 int i, tries; 5244 int err = 0; 5245 short oldlvl; 5246 5247 FDERRPRINT(FDEP_L1, FDEM_GETL, 5248 (C, "fdgetlabel: unit %d\n", unit)); 5249 5250 un = fdc->c_un; 5251 un->un_flags &= ~(FDUNIT_UNLABELED); 5252 5253 ASSERT(fdc->c_un->un_unit_no == unit); 5254 5255 /* Do not print errors since this is a private cmd */ 5256 5257 oldlvl = fderrlevel; 5258 5259 5260 fderrlevel = FDEP_L4; 5261 5262 label = (struct dk_label *) 5263 kmem_zalloc(sizeof (struct dk_label), KM_SLEEP); 5264 5265 /* 5266 * try different characteristics (ie densities) by attempting to read 5267 * from the diskette. The diskette may not be present or 5268 * is unformatted. 5269 * 5270 * First, the last sector of the first track is read. If this 5271 * passes, attempt to read the last sector + 1 of the first track. 5272 * For example, for a high density diskette, sector 18 is read. If 5273 * the diskette is high density, this will pass. Next, try to 5274 * read sector 19 of the first track. This should fail. If it 5275 * passes, this is not a high density diskette. Finally, read 5276 * the first sector which should contain a label. 5277 * 5278 * if un->un_curfdtype is -1 then the current characteristics 5279 * were set by FDIOSCHAR and need to try it as well as everything 5280 * in the table 5281 */ 5282 if (un->un_curfdtype == -1) { 5283 tries = nfdtypes+1; 5284 FDERRPRINT(FDEP_L1, FDEM_GETL, 5285 (C, "fdgetl: un_curfdtype is -1\n")); 5286 5287 } else { 5288 tries = nfdtypes; 5289 5290 /* Always start with the highest density (1.7MB) */ 5291 un->un_curfdtype = 0; 5292 *(un->un_chars) = fdtypes[un->un_curfdtype]; 5293 } 5294 5295 FDERRPRINT(FDEP_L1, FDEM_GETL, 5296 (C, "fdgetl: no. of tries %d\n", tries)); 5297 FDERRPRINT(FDEP_L1, FDEM_GETL, 5298 (C, "fdgetl: no. of curfdtype %d\n", un->un_curfdtype)); 5299 5300 for (i = 0; i < tries; i++) { 5301 FDERRPRINT(FDEP_L1, FDEM_GETL, 5302 (C, "fdgetl: trying %d\n", i)); 5303 5304 if (!(err = fdrw(fdc, unit, FDREAD, 0, 0, 5305 un->un_chars->fdc_secptrack, (caddr_t)label, 5306 sizeof (struct dk_label))) && 5307 5308 fdrw(fdc, unit, FDREAD, 0, 0, 5309 un->un_chars->fdc_secptrack + 1, 5310 (caddr_t)label, sizeof (struct dk_label)) && 5311 5312 !(err = fdrw(fdc, unit, FDREAD, 0, 0, 1, (caddr_t)label, 5313 sizeof (struct dk_label)))) { 5314 5315 FDERRPRINT(FDEP_L1, FDEM_GETL, 5316 (C, "fdgetl: succeeded\n")); 5317 5318 break; 5319 } 5320 5321 /* 5322 * try the next entry in the characteristics tbl 5323 * If curfdtype is -1, the nxt entry in tbl is 0 (the first). 5324 */ 5325 5326 un->un_curfdtype = (un->un_curfdtype + 1) % nfdtypes; 5327 *(un->un_chars) = fdtypes[un->un_curfdtype]; 5328 5329 5330 } 5331 5332 /* print errors again */ 5333 fderrlevel = oldlvl; 5334 5335 /* Couldn't read anything */ 5336 if (err) { 5337 5338 /* The default characteristics are high density (1.4MB) */ 5339 un->un_curfdtype = 1; 5340 *(un->un_chars) = fdtypes[un->un_curfdtype]; 5341 5342 fdunpacklabel(&fdlbl_high_80, &un->un_label); 5343 5344 FDERRPRINT(FDEP_L1, FDEM_GETL, 5345 (C, "fdgetl: Can't autosense diskette\n")); 5346 5347 goto out; 5348 } 5349 5350 FDERRPRINT(FDEP_L1, FDEM_GETL, 5351 (C, "fdgetl: fdtype=%d !!!\n", un->un_curfdtype)); 5352 FDERRPRINT(FDEP_L1, FDEM_GETL, 5353 (C, "fdgetl: rate=%d ssize=%d !!!\n", 5354 un->un_chars->fdc_transfer_rate, un->un_chars->fdc_sec_size)); 5355 5356 /* 5357 * _something_ was read - look for unixtype label 5358 */ 5359 if (label->dkl_magic != DKL_MAGIC) { 5360 5361 /* 5362 * The label isn't a unix label. However, the diskette 5363 * is formatted because we were able to read the first 5364 * cylinder. 5365 */ 5366 5367 FDERRPRINT(FDEP_L1, FDEM_GETL, 5368 (C, "fdgetl: not unix label\n")); 5369 5370 goto nolabel; 5371 } 5372 5373 /* 5374 * Checksum the label 5375 */ 5376 count = sizeof (struct dk_label)/sizeof (short); 5377 sp = (short *)label; 5378 xsum = 0; 5379 while (count--) 5380 xsum ^= *sp++; /* should add up to 0 */ 5381 if (xsum) { 5382 5383 /* 5384 * The checksum fails. However, the diskette is formatted 5385 * because we were able to read the first cylinder 5386 */ 5387 5388 FDERRPRINT(FDEP_L1, FDEM_GETL, 5389 (C, "fdgetl: bad cksum\n")); 5390 5391 goto nolabel; 5392 } 5393 5394 /* 5395 * The diskette has a unix label with a correct checksum. 5396 * Copy the label into the unit structure 5397 */ 5398 un->un_label = *label; 5399 5400 goto out; 5401 5402 nolabel: 5403 /* 5404 * The diskette doesn't have a correct unix label, but it is formatted. 5405 * Use a default label according to the diskette's density 5406 * (mark default used) 5407 */ 5408 FDERRPRINT(FDEP_L1, FDEM_GETL, 5409 (C, "fdgetlabel: unit %d\n", unit)); 5410 un->un_flags |= FDUNIT_UNLABELED; 5411 switch (un->un_chars->fdc_secptrack) { 5412 case 9: 5413 fdunpacklabel(&fdlbl_low_80, &un->un_label); 5414 break; 5415 case 8: 5416 fdunpacklabel(&fdlbl_medium_80, &un->un_label); 5417 break; 5418 case 18: 5419 fdunpacklabel(&fdlbl_high_80, &un->un_label); 5420 break; 5421 case 21: 5422 fdunpacklabel(&fdlbl_high_21, &un->un_label); 5423 break; 5424 default: 5425 fdunpacklabel(&fdlbl_high_80, &un->un_label); 5426 break; 5427 } 5428 5429 out: 5430 if (label != NULL) 5431 kmem_free((caddr_t)label, sizeof (struct dk_label)); 5432 return (err); 5433 } 5434 5435 /* 5436 * fdrw- used only for reading labels and for DKIOCSVTOC ioctl 5437 * which reads the 1 sector. 5438 */ 5439 static int 5440 fdrw(struct fdctlr *fdc, int unit, int rw, int cyl, int head, 5441 int sector, caddr_t bufp, uint_t len) 5442 { 5443 struct fdcsb *csb; 5444 struct fd_char *ch; 5445 int cmdresult = 0; 5446 caddr_t dma_addr; 5447 size_t real_length; 5448 int res; 5449 ddi_device_acc_attr_t attr; 5450 ddi_acc_handle_t mem_handle = NULL; 5451 5452 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fdrw\n")); 5453 5454 ASSERT(fdc->c_un->un_unit_no == unit); 5455 5456 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 5457 5458 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 5459 mutex_exit(&fdc->c_lolock); 5460 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 5461 != DDI_SUCCESS) { 5462 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power change \ 5463 failed. \n")); 5464 mutex_enter(&fdc->c_lolock); 5465 return (EIO); 5466 } 5467 5468 mutex_enter(&fdc->c_lolock); 5469 } 5470 5471 fdgetcsb(fdc); 5472 csb = &fdc->c_csb; 5473 ch = fdc->c_un->un_chars; 5474 if (rw == FDREAD) { 5475 if (fdc->c_fdtype & FDCTYPE_TCBUG) { 5476 /* 5477 * kludge for lack of Multitrack functionality 5478 */ 5479 csb->csb_cmds[0] = SK + FDRAW_RDCMD; 5480 } else 5481 csb->csb_cmds[0] = MT + SK + FDRAW_RDCMD; 5482 } else { /* write */ 5483 if (fdc->c_fdtype & FDCTYPE_TCBUG) { 5484 /* 5485 * kludge for lack of Multitrack functionality 5486 */ 5487 csb->csb_cmds[0] = FDRAW_WRCMD; 5488 } else 5489 csb->csb_cmds[0] = MT + FDRAW_WRCMD; 5490 } 5491 5492 if (rw == FDREAD) 5493 fdc->c_csb.csb_read = CSB_READ; 5494 else 5495 fdc->c_csb.csb_read = CSB_WRITE; 5496 5497 /* always or in MFM bit */ 5498 csb->csb_cmds[0] |= MFM; 5499 csb->csb_cmds[1] = (uchar_t)(unit | ((head & 0x1) << 2)); 5500 if (fdc->c_fdtype & FDCTYPE_SB) 5501 csb->csb_cmds[1] |= IPS; 5502 csb->csb_cmds[2] = (uchar_t)cyl; 5503 csb->csb_cmds[3] = (uchar_t)head; 5504 csb->csb_cmds[4] = (uchar_t)sector; 5505 csb->csb_cmds[5] = ch->fdc_medium ? 3 : 2; /* sector size code */ 5506 /* 5507 * kludge for end-of-cylinder error. 5508 */ 5509 if (fdc->c_fdtype & FDCTYPE_TCBUG) 5510 csb->csb_cmds[6] = sector + (len / ch->fdc_sec_size) - 1; 5511 else 5512 csb->csb_cmds[6] = 5513 (uchar_t)max(fdc->c_un->un_chars->fdc_secptrack, sector); 5514 csb->csb_len = len; 5515 csb->csb_cmds[7] = GPLN; 5516 csb->csb_cmds[8] = SSSDTL; 5517 csb->csb_ncmds = NCBRW; 5518 csb->csb_len = len; 5519 csb->csb_maxretry = 2; 5520 csb->csb_retrys = 0; 5521 bzero(csb->csb_rslt, NRBRW); 5522 csb->csb_nrslts = NRBRW; 5523 csb->csb_opflags = CSB_OFXFEROPS | CSB_OFTIMEIT; 5524 5525 /* If platform supports DMA, set up DMA resources */ 5526 if (fdc->c_fdtype & FDCTYPE_DMA) { 5527 5528 mutex_enter(&fdc->c_hilock); 5529 5530 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 5531 attr.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC; 5532 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 5533 5534 res = ddi_dma_mem_alloc(fdc->c_dmahandle, len, 5535 &attr, DDI_DMA_STREAMING, 5536 DDI_DMA_DONTWAIT, 0, &dma_addr, &real_length, 5537 &mem_handle); 5538 5539 if (res != DDI_SUCCESS) { 5540 FDERRPRINT(FDEP_L1, FDEM_RW, 5541 (C, "fdrw: dma mem alloc failed\n")); 5542 5543 fdretcsb(fdc); 5544 mutex_exit(&fdc->c_hilock); 5545 return (EIO); 5546 } 5547 5548 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fdrw: allocated memory")); 5549 5550 if (fdstart_dma(fdc, dma_addr, len) != 0) { 5551 fdretcsb(fdc); 5552 ddi_dma_mem_free(&mem_handle); 5553 mutex_exit(&fdc->c_hilock); 5554 return (-1); 5555 5556 } 5557 5558 /* 5559 * If the command is a write, copy the data to be written to 5560 * dma_addr. 5561 */ 5562 5563 if (fdc->c_csb.csb_read == CSB_WRITE) { 5564 bcopy((char *)bufp, (char *)dma_addr, len); 5565 } 5566 5567 csb->csb_addr = dma_addr; 5568 mutex_exit(&fdc->c_hilock); 5569 } else { 5570 csb->csb_addr = bufp; 5571 } 5572 5573 5574 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fdrw: call fdexec\n")); 5575 5576 if (fdexec(fdc, FDXC_SLEEP | FDXC_CHECKCHG) != 0) { 5577 fdretcsb(fdc); 5578 5579 if (mem_handle) 5580 ddi_dma_mem_free(&mem_handle); 5581 5582 return (EIO); 5583 5584 } 5585 5586 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fdrw: fdexec returned\n")); 5587 5588 /* 5589 * if DMA was used and the command was a read 5590 * copy the results into bufp 5591 */ 5592 if (fdc->c_fdtype & FDCTYPE_DMA) { 5593 if (fdc->c_csb.csb_read == CSB_READ) { 5594 bcopy((char *)dma_addr, (char *)bufp, len); 5595 } 5596 ddi_dma_mem_free(&mem_handle); 5597 } 5598 5599 if (csb->csb_cmdstat) 5600 cmdresult = EIO; /* XXX TBD NYD for now */ 5601 5602 fdretcsb(fdc); 5603 return (cmdresult); 5604 } 5605 5606 /* 5607 * fdunpacklabel 5608 * this unpacks a (packed) struct dk_label into a standard dk_label. 5609 */ 5610 static void 5611 fdunpacklabel(struct packed_label *from, struct dk_label *to) 5612 { 5613 FDERRPRINT(FDEP_L1, FDEM_PACK, (C, "fdpacklabel\n")); 5614 bzero((caddr_t)to, sizeof (*to)); 5615 bcopy((caddr_t)&from->dkl_vname, (caddr_t)to->dkl_asciilabel, 5616 sizeof (to->dkl_asciilabel)); 5617 to->dkl_rpm = from->dkl_rpm; /* rotations per minute */ 5618 to->dkl_pcyl = from->dkl_pcyl; /* # physical cylinders */ 5619 to->dkl_apc = from->dkl_apc; /* alternates per cylinder */ 5620 to->dkl_intrlv = from->dkl_intrlv; /* interleave factor */ 5621 to->dkl_ncyl = from->dkl_ncyl; /* # of data cylinders */ 5622 to->dkl_acyl = from->dkl_acyl; /* # of alternate cylinders */ 5623 to->dkl_nhead = from->dkl_nhead; /* # of heads in this partition */ 5624 to->dkl_nsect = from->dkl_nsect; /* # of 512 byte sectors per track */ 5625 /* logical partitions */ 5626 bcopy((caddr_t)from->dkl_map, (caddr_t)to->dkl_map, 5627 sizeof (struct dk_map32) * NDKMAP); 5628 to->dkl_vtoc = from->dkl_vtoc; 5629 } 5630 5631 static struct fdctlr * 5632 fd_getctlr(dev_t dev) 5633 { 5634 5635 struct fdctlr *fdc = fdctlrs; 5636 int ctlr = FDCTLR(dev); 5637 5638 while (fdc) { 5639 if (ddi_get_instance(fdc->c_dip) == ctlr) 5640 return (fdc); 5641 fdc = fdc->c_next; 5642 } 5643 return (fdc); 5644 } 5645 5646 static int 5647 fd_unit_is_open(struct fdunit *un) 5648 { 5649 int i; 5650 for (i = 0; i < NDKMAP; i++) 5651 if (un->un_lyropen[i]) 5652 return (1); 5653 for (i = 0; i < OTYPCNT - 1; i++) 5654 if (un->un_regopen[i]) 5655 return (1); 5656 return (0); 5657 } 5658 5659 /* 5660 * Return the a vtoc structure in *vtoc. 5661 * The vtoc is built from information in 5662 * the diskette's label. 5663 */ 5664 static void 5665 fd_build_user_vtoc(struct fdunit *un, struct vtoc *vtoc) 5666 { 5667 int i; 5668 int nblks; /* DEV_BSIZE sectors per cylinder */ 5669 struct dk_map2 *lpart; 5670 struct dk_map32 *lmap; 5671 struct partition *vpart; 5672 5673 bzero(vtoc, sizeof (struct vtoc)); 5674 5675 /* Initialize info. needed by mboot. (unsupported) */ 5676 vtoc->v_bootinfo[0] = un->un_label.dkl_vtoc.v_bootinfo[0]; 5677 vtoc->v_bootinfo[1] = un->un_label.dkl_vtoc.v_bootinfo[1]; 5678 vtoc->v_bootinfo[2] = un->un_label.dkl_vtoc.v_bootinfo[2]; 5679 5680 /* Fill in vtoc sanity and version information */ 5681 vtoc->v_sanity = un->un_label.dkl_vtoc.v_sanity; 5682 vtoc->v_version = un->un_label.dkl_vtoc.v_version; 5683 5684 /* Copy the volume name */ 5685 bcopy(un->un_label.dkl_vtoc.v_volume, 5686 vtoc->v_volume, LEN_DKL_VVOL); 5687 5688 /* 5689 * The dk_map32 structure is based on DEV_BSIZE byte blocks. 5690 * However, medium density diskettes have 1024 byte blocks. 5691 * The number of sectors per partition listed in the dk_map32 structure 5692 * accounts for this by multiplying the number of 1024 byte 5693 * blocks by 2. (See the packed_label initializations.) The 5694 * 1024 byte block size can not be listed for medium density 5695 * diskettes because the kernel is hard coded for DEV_BSIZE 5696 * blocks. 5697 */ 5698 vtoc->v_sectorsz = DEV_BSIZE; 5699 vtoc->v_nparts = un->un_label.dkl_vtoc.v_nparts; 5700 5701 /* Copy the reserved space */ 5702 bcopy(un->un_label.dkl_vtoc.v_reserved, 5703 vtoc->v_reserved, sizeof (un->un_label.dkl_vtoc.v_reserved)); 5704 /* 5705 * Convert partitioning information. 5706 * 5707 * Note the conversion from starting cylinder number 5708 * to starting sector number. 5709 */ 5710 lmap = un->un_label.dkl_map; 5711 lpart = un->un_label.dkl_vtoc.v_part; 5712 vpart = vtoc->v_part; 5713 5714 nblks = (un->un_chars->fdc_nhead * un->un_chars->fdc_secptrack * 5715 un->un_chars->fdc_sec_size) / DEV_BSIZE; 5716 5717 for (i = 0; i < V_NUMPAR; i++) { 5718 vpart->p_tag = lpart->p_tag; 5719 vpart->p_flag = lpart->p_flag; 5720 vpart->p_start = lmap->dkl_cylno * nblks; 5721 vpart->p_size = lmap->dkl_nblk; 5722 5723 lmap++; 5724 lpart++; 5725 vpart++; 5726 } 5727 5728 /* Initialize timestamp and label */ 5729 bcopy(un->un_label.dkl_vtoc.v_timestamp, 5730 vtoc->timestamp, sizeof (vtoc->timestamp)); 5731 5732 bcopy(un->un_label.dkl_asciilabel, 5733 vtoc->v_asciilabel, LEN_DKL_ASCII); 5734 } 5735 5736 /* 5737 * Build a label out of a vtoc structure. 5738 */ 5739 static int 5740 fd_build_label_vtoc(struct fdunit *un, struct vtoc *vtoc) 5741 { 5742 struct dk_map32 *lmap; 5743 struct dk_map2 *lpart; 5744 struct partition *vpart; 5745 int nblks; /* no. blocks per cylinder */ 5746 int ncyl; 5747 int i; 5748 short sum, *sp; 5749 5750 /* Sanity-check the vtoc */ 5751 if ((vtoc->v_sanity != VTOC_SANE) || 5752 (vtoc->v_nparts > NDKMAP) || (vtoc->v_nparts <= 0)) { 5753 FDERRPRINT(FDEP_L1, FDEM_IOCT, 5754 (C, "fd_build_label: sanity check on vtoc failed\n")); 5755 return (EINVAL); 5756 } 5757 5758 nblks = (un->un_chars->fdc_nhead * un->un_chars->fdc_secptrack * 5759 un->un_chars->fdc_sec_size) / DEV_BSIZE; 5760 5761 vpart = vtoc->v_part; 5762 5763 /* 5764 * Check the partition information in the vtoc. The starting sectors 5765 * must lie along partition boundaries. (NDKMAP entries are checked 5766 * to ensure that the unused entries are set to 0 if vtoc->v_nparts 5767 * is less than NDKMAP) 5768 */ 5769 5770 for (i = 0; i < NDKMAP; i++) { 5771 if ((vpart->p_start % nblks) != 0) { 5772 return (EINVAL); 5773 } 5774 ncyl = vpart->p_start % nblks; 5775 ncyl += vpart->p_size % nblks; 5776 if ((vpart->p_size % nblks) != 0) 5777 ncyl++; 5778 if (ncyl > un->un_chars->fdc_ncyl) { 5779 return (EINVAL); 5780 } 5781 vpart++; 5782 } 5783 5784 /* 5785 * reinitialize the existing label 5786 */ 5787 bzero(&un->un_label, sizeof (un->un_label)); 5788 5789 /* Put appropriate vtoc structure fields into the disk label */ 5790 un->un_label.dkl_vtoc.v_bootinfo[0] = (uint32_t)vtoc->v_bootinfo[0]; 5791 un->un_label.dkl_vtoc.v_bootinfo[1] = (uint32_t)vtoc->v_bootinfo[1]; 5792 un->un_label.dkl_vtoc.v_bootinfo[2] = (uint32_t)vtoc->v_bootinfo[2]; 5793 5794 un->un_label.dkl_vtoc.v_sanity = vtoc->v_sanity; 5795 un->un_label.dkl_vtoc.v_version = vtoc->v_version; 5796 5797 bcopy(vtoc->v_volume, un->un_label.dkl_vtoc.v_volume, LEN_DKL_VVOL); 5798 5799 un->un_label.dkl_vtoc.v_nparts = vtoc->v_nparts; 5800 5801 bcopy(vtoc->v_reserved, un->un_label.dkl_vtoc.v_reserved, 5802 sizeof (un->un_label.dkl_vtoc.v_reserved)); 5803 5804 /* 5805 * Initialize cylinder information in the label. 5806 * Note the conversion from starting sector number 5807 * to starting cylinder number. 5808 * Return error if division results in a remainder. 5809 */ 5810 lmap = un->un_label.dkl_map; 5811 lpart = un->un_label.dkl_vtoc.v_part; 5812 vpart = vtoc->v_part; 5813 5814 for (i = 0; i < (int)vtoc->v_nparts; i++) { 5815 lpart->p_tag = vtoc->v_part[i].p_tag; 5816 lpart->p_flag = vtoc->v_part[i].p_flag; 5817 lmap->dkl_cylno = vpart->p_start / nblks; 5818 lmap->dkl_nblk = vpart->p_size; 5819 5820 lmap++; 5821 lpart++; 5822 vpart++; 5823 } 5824 5825 /* Copy the timestamp and ascii label */ 5826 for (i = 0; i < NDKMAP; i++) { 5827 un->un_label.dkl_vtoc.v_timestamp[i] = vtoc->timestamp[i]; 5828 } 5829 5830 5831 bcopy(vtoc->v_asciilabel, un->un_label.dkl_asciilabel, LEN_DKL_ASCII); 5832 5833 FDERRPRINT(FDEP_L1, FDEM_IOCT, 5834 (C, "fd_build_label: asciilabel %s\n", 5835 un->un_label.dkl_asciilabel)); 5836 5837 /* Initialize the magic number */ 5838 un->un_label.dkl_magic = DKL_MAGIC; 5839 5840 un->un_label.dkl_pcyl = un->un_chars->fdc_ncyl; 5841 5842 /* 5843 * The fdc_secptrack filed of the fd_char structure is the number 5844 * of sectors per track where the sectors are fdc_sec_size. The 5845 * dkl_nsect field of the dk_label structure is the number of 5846 * 512 (DEVBSIZE) byte sectors per track. 5847 */ 5848 un->un_label.dkl_nsect = (un->un_chars->fdc_secptrack * 5849 un->un_chars->fdc_sec_size) / DEV_BSIZE; 5850 5851 5852 un->un_label.dkl_ncyl = un->un_label.dkl_pcyl; 5853 un->un_label.dkl_nhead = un->un_chars->fdc_nhead; 5854 un->un_label.dkl_rpm = un->un_chars->fdc_medium ? 360 : 300; 5855 un->un_label.dkl_intrlv = 1; 5856 5857 /* Create the checksum */ 5858 sum = 0; 5859 un->un_label.dkl_cksum = 0; 5860 sp = (short *)&un->un_label; 5861 i = sizeof (struct dk_label)/sizeof (short); 5862 while (i--) { 5863 sum ^= *sp++; 5864 } 5865 un->un_label.dkl_cksum = sum; 5866 5867 return (0); 5868 } 5869 5870 /* 5871 * Check for auxio register node 5872 */ 5873 5874 int 5875 fd_isauxiodip(dev_info_t *dip) 5876 { 5877 if (strcmp(ddi_get_name(dip), "auxio") == 0 || 5878 strcmp(ddi_get_name(dip), "auxiliary-io") == 0) { 5879 return (1); 5880 } 5881 return (0); 5882 } 5883 5884 /* 5885 * Search for auxio register node, then for address property 5886 */ 5887 5888 caddr_t 5889 fd_getauxiova(dev_info_t *dip) 5890 { 5891 dev_info_t *auxdip; 5892 caddr_t addr; 5893 5894 /* 5895 * Search sibling list, which happens to be safe inside attach 5896 */ 5897 auxdip = ddi_get_child(ddi_get_parent(dip)); 5898 while (auxdip) { 5899 if (fd_isauxiodip(auxdip)) 5900 break; 5901 auxdip = ddi_get_next_sibling(auxdip); 5902 } 5903 5904 if (auxdip == NULL) 5905 return (NULL); 5906 5907 addr = (caddr_t)(caddr32_t)ddi_getprop(DDI_DEV_T_ANY, 5908 auxdip, DDI_PROP_DONTPASS, "address", 0); 5909 5910 /* 5911 * The device tree on some sun4c machines (SS1+) incorrectly 5912 * reports the "auxiliary-io" as being word wide at an 5913 * aligned address rather than byte wide at an offset of 3. 5914 * Here we correct for this .. 5915 */ 5916 if (strcmp(ddi_get_name(auxdip), "auxiliary-io") == 0 && 5917 (((int)addr & 3) == 0)) 5918 addr += 3; 5919 5920 return (addr); 5921 } 5922 5923 5924 /* 5925 * set_rotational speed 5926 * 300 rpm for high and low density. 5927 * 360 rpm for medium density. 5928 * for now, we assume that 3rd density is supported only for Sun4M, 5929 * not for Clones. (else we would have to check for 82077, and do 5930 * specific things for the MEDIUM_DENSITY BIT for clones. 5931 * this code should not break CLONES. 5932 * 5933 * REMARK: there is a SOny requirement, to deselect the drive then 5934 * select it again after the medium density change, since the 5935 * leading edge of the select line latches the rotational Speed. 5936 * then after that, we have to wait 500 ms for the rotation to 5937 * stabilize. 5938 * 5939 */ 5940 static void 5941 set_rotational_speed(struct fdctlr *fdc, int unit) 5942 { 5943 int check; 5944 int is_medium; 5945 5946 ASSERT(fdc->c_un->un_unit_no == unit); 5947 5948 /* 5949 * if we do not have a Sun4m, medium density is not supported. 5950 */ 5951 if (fdc->c_fdtype & FDCTYPE_MACHIO) 5952 return; 5953 5954 /* 5955 * if FDUNIT_SET_SPEED is set, set the speed. 5956 * else, 5957 * if there is a change, do it, if not leave it alone. 5958 * there is a change if un->un_chars->fdc_medium does not match 5959 * un->un_flags & FDUNIT_MEDIUM 5960 * un->un_flags & FDUNIT_MEDIUM specifies the last setting. 5961 * un->un_chars->fdc_medium specifies next setting. 5962 * if there is a change, wait 500ms according to Sony spec. 5963 */ 5964 5965 is_medium = fdc->c_un->un_chars->fdc_medium; 5966 5967 if (fdc->c_un->un_flags & FDUNIT_SET_SPEED) { 5968 check = 1; 5969 } else { 5970 check = is_medium ^ 5971 ((fdc->c_un->un_flags & FDUNIT_MEDIUM) ? 1 : 0); 5972 5973 /* Set the un_flags if necessary */ 5974 5975 if (check) 5976 fdc->c_un->un_flags ^= FDUNIT_MEDIUM; 5977 } 5978 5979 fdc->c_un->un_flags &= ~FDUNIT_SET_SPEED; 5980 5981 5982 if (check) { 5983 5984 fdselect(fdc, unit, 0); 5985 drv_usecwait(5); 5986 5987 if ((fdc->c_fdtype & FDCTYPE_AUXIOMASK) == FDCTYPE_SLAVIO) { 5988 Set_dor(fdc, MEDIUM_DENSITY, is_medium); 5989 } 5990 5991 if ((fdc->c_fdtype & FDCTYPE_AUXIOMASK) == FDCTYPE_CHEERIO) { 5992 if (is_medium) { 5993 Set_auxio(fdc, AUX_MEDIUM_DENSITY); 5994 } else { 5995 Set_auxio(fdc, AUX_HIGH_DENSITY); 5996 } 5997 5998 } 5999 6000 if (is_medium) { 6001 drv_usecwait(5); 6002 } 6003 6004 fdselect(fdc, unit, 1); /* Sony requirement */ 6005 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "rotation:medium\n")); 6006 drv_usecwait(500000); 6007 } 6008 } 6009 6010 static void 6011 fd_media_watch(void *arg) 6012 { 6013 dev_t dev; 6014 struct fdunit *un; 6015 struct fdctlr *fdc; 6016 int unit; 6017 6018 dev = (dev_t)arg; 6019 fdc = fd_getctlr(dev); 6020 unit = fdc->c_un->un_unit_no; 6021 un = fdc->c_un; 6022 6023 mutex_enter(&fdc->c_lolock); 6024 6025 if (un->un_media_timeout_id == 0) { 6026 /* 6027 * Untimeout is about to be called. 6028 * Don't call fd_get_media_state again 6029 */ 6030 mutex_exit(&fdc->c_lolock); 6031 return; 6032 } 6033 6034 6035 un->un_media_state = fd_get_media_state(fdc, unit); 6036 cv_broadcast(&fdc->c_statecv); 6037 6038 mutex_exit(&fdc->c_lolock); 6039 6040 if (un->un_media_timeout) { 6041 un->un_media_timeout_id = timeout(fd_media_watch, 6042 (void *)(ulong_t)dev, un->un_media_timeout); 6043 } 6044 } 6045 6046 enum dkio_state 6047 fd_get_media_state(struct fdctlr *fdc, int unit) 6048 { 6049 enum dkio_state state; 6050 6051 ASSERT(fdc->c_un->un_unit_no == unit); 6052 6053 if (fdsense_chng(fdc, unit)) { 6054 /* check disk only if DSKCHG "high" */ 6055 if (fdcheckdisk(fdc, unit)) { 6056 state = DKIO_EJECTED; 6057 } else { 6058 state = DKIO_INSERTED; 6059 } 6060 } else { 6061 state = DKIO_INSERTED; 6062 } 6063 return (state); 6064 } 6065 6066 static int 6067 fd_check_media(dev_t dev, enum dkio_state state) 6068 { 6069 struct fdunit *un; 6070 struct fdctlr *fdc; 6071 int unit; 6072 6073 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fd_check_media: start\n")); 6074 6075 fdc = fd_getctlr(dev); 6076 unit = fdc->c_un->un_unit_no; 6077 un = fdc->c_un; 6078 6079 mutex_enter(&fdc->c_lolock); 6080 6081 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 6082 6083 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 6084 mutex_exit(&fdc->c_lolock); 6085 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 6086 != DDI_SUCCESS) { 6087 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power change \ 6088 failed. \n")); 6089 6090 (void) pm_idle_component(fdc->c_dip, 0); 6091 return (EIO); 6092 } 6093 6094 mutex_enter(&fdc->c_lolock); 6095 } 6096 6097 un->un_media_state = fd_get_media_state(fdc, unit); 6098 6099 /* turn on timeout */ 6100 un->un_media_timeout = drv_usectohz(fd_check_media_time); 6101 un->un_media_timeout_id = timeout(fd_media_watch, 6102 (void *)(ulong_t)dev, un->un_media_timeout); 6103 6104 while (un->un_media_state == state) { 6105 if (cv_wait_sig(&fdc->c_statecv, &fdc->c_lolock) == 0) { 6106 un->un_media_timeout = 0; 6107 mutex_exit(&fdc->c_lolock); 6108 return (EINTR); 6109 } 6110 } 6111 6112 if (un->un_media_timeout_id) { 6113 timeout_id_t timeid = un->un_media_timeout_id; 6114 un->un_media_timeout_id = 0; 6115 6116 mutex_exit(&fdc->c_lolock); 6117 (void) untimeout(timeid); 6118 mutex_enter(&fdc->c_lolock); 6119 } 6120 6121 if (un->un_media_state == DKIO_INSERTED) { 6122 if (fdgetlabel(fdc, unit)) { 6123 mutex_exit(&fdc->c_lolock); 6124 return (EIO); 6125 } 6126 } 6127 mutex_exit(&fdc->c_lolock); 6128 6129 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fd_check_media: end\n")); 6130 return (0); 6131 } 6132 6133 /* 6134 * fd_get_media_info : 6135 * Collects medium information for 6136 * DKIOCGMEDIAINFO ioctl. 6137 */ 6138 6139 static int 6140 fd_get_media_info(struct fdunit *un, caddr_t buf, int flag) 6141 { 6142 struct dk_minfo media_info; 6143 int err = 0; 6144 6145 media_info.dki_media_type = DK_FLOPPY; 6146 media_info.dki_lbsize = un->un_chars->fdc_sec_size; 6147 media_info.dki_capacity = un->un_chars->fdc_ncyl * 6148 un->un_chars->fdc_secptrack * un->un_chars->fdc_nhead; 6149 6150 if (ddi_copyout((caddr_t)&media_info, buf, 6151 sizeof (struct dk_minfo), flag)) 6152 err = EFAULT; 6153 return (err); 6154 } 6155 6156 /* 6157 * fd_power : 6158 * Power entry point of fd driver. 6159 */ 6160 6161 static int 6162 fd_power(dev_info_t *dip, int component, int level) 6163 { 6164 6165 struct fdctlr *fdc; 6166 int instance; 6167 int rval; 6168 6169 if ((level < PM_LEVEL_OFF) || (level > PM_LEVEL_ON) || 6170 (component != 0)) { 6171 return (DDI_FAILURE); 6172 } 6173 6174 instance = ddi_get_instance(dip); 6175 fdc = fd_getctlr(instance << FDINSTSHIFT); 6176 if (fdc->c_un == NULL) 6177 return (DDI_FAILURE); 6178 6179 if (level == PM_LEVEL_OFF) { 6180 rval = fd_pm_lower_power(fdc); 6181 } 6182 if (level == PM_LEVEL_ON) { 6183 rval = fd_pm_raise_power(fdc); 6184 } 6185 return (rval); 6186 } 6187 6188 /* 6189 * fd_pm_lower_power : 6190 * This function is called only during pm suspend. At this point, 6191 * the power management framework thinks the device is idle for 6192 * long enough to go to a low power mode. If the device is busy, 6193 * then this function returns DDI_FAILURE. 6194 */ 6195 6196 static int 6197 fd_pm_lower_power(struct fdctlr *fdc) 6198 { 6199 6200 mutex_enter(&fdc->c_lolock); 6201 6202 if ((fdc->c_un->un_state == FD_STATE_SUSPENDED) || 6203 (fdc->c_un->un_state == FD_STATE_STOPPED)) { 6204 mutex_exit(&fdc->c_lolock); 6205 return (DDI_SUCCESS); 6206 } 6207 6208 6209 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "fd_pm_lower_power called\n")); 6210 6211 /* if the device is busy then we fail the lower power request */ 6212 if (fdc->c_flags & FDCFLG_BUSY) { 6213 FDERRPRINT(FDEP_L2, FDEM_PWR, (C, "fd_pm_lower_power : \ 6214 controller is busy.\n")); 6215 mutex_exit(&fdc->c_lolock); 6216 return (DDI_FAILURE); 6217 } 6218 6219 fdc->c_un->un_state = FD_STATE_STOPPED; 6220 6221 mutex_exit(&fdc->c_lolock); 6222 return (DDI_SUCCESS); 6223 } 6224 6225 /* 6226 * fd_pm_raise_power : 6227 * This function performs the necessary steps for resuming a 6228 * device, either from pm suspend or CPR. Here the controller 6229 * is reset, initialized and the state is set to FD_STATE_NORMAL. 6230 */ 6231 6232 static int 6233 fd_pm_raise_power(struct fdctlr *fdc) 6234 { 6235 6236 struct fdunit *un = fdc->c_un; 6237 int unit; 6238 6239 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "fd_pm_raise_power called\n")); 6240 mutex_enter(&fdc->c_lolock); 6241 fdgetcsb(fdc); 6242 6243 /* Reset the dma engine */ 6244 if (fdc->c_fdtype & FDCTYPE_DMA) { 6245 mutex_enter(&fdc->c_hilock); 6246 reset_dma_controller(fdc); 6247 set_dma_control_register(fdc, DCSR_INIT_BITS); 6248 mutex_exit(&fdc->c_hilock); 6249 } 6250 6251 /* 6252 * Force a rotational speed set in the next 6253 * call to set_rotational_speed(). 6254 */ 6255 6256 fdc->c_un->un_flags |= FDUNIT_SET_SPEED; 6257 6258 /* Reset and configure the controller */ 6259 (void) fdreset(fdc); 6260 6261 unit = fdc->c_un->un_unit_no; 6262 6263 /* Recalibrate the drive */ 6264 if (fdrecalseek(fdc, unit, -1, 0) != 0) { 6265 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "raise_power : recalibrate \ 6266 failed\n")); 6267 fdretcsb(fdc); 6268 mutex_exit(&fdc->c_lolock); 6269 return (DDI_FAILURE); 6270 } 6271 6272 /* Select the drive through the AUXIO registers */ 6273 fdselect(fdc, unit, 0); 6274 un->un_state = FD_STATE_NORMAL; 6275 fdretcsb(fdc); 6276 mutex_exit(&fdc->c_lolock); 6277 return (DDI_SUCCESS); 6278 } 6279 6280 /* 6281 * create_pm_components : 6282 * creates the power management components for auto pm framework. 6283 */ 6284 6285 static void 6286 create_pm_components(dev_info_t *dip) 6287 { 6288 char *un_pm_comp[] = { "NAME=spindle-motor", "0=off", "1=on"}; 6289 6290 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 6291 "pm-components", un_pm_comp, 3) == DDI_PROP_SUCCESS) { 6292 6293 (void) pm_raise_power(dip, 0, PM_LEVEL_ON); 6294 } 6295 } 6296 6297 /* 6298 * set_data_count_register(struct fdctlr *fdc, uint32_t count) 6299 * Set the data count in appropriate dma register. 6300 */ 6301 6302 static void 6303 set_data_count_register(struct fdctlr *fdc, uint32_t count) 6304 { 6305 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6306 struct cheerio_dma_reg *dma_reg; 6307 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6308 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dbcr, count); 6309 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6310 struct sb_dma_reg *dma_reg; 6311 count = count - 1; /* 8237 needs it */ 6312 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6313 switch (fdc->sb_dma_channel) { 6314 case 0 : 6315 ddi_put16(fdc->c_handlep_dma, 6316 (ushort_t *)&dma_reg->sb_dma_regs[DMA_0WCNT], 6317 count & 0xFFFF); 6318 break; 6319 case 1 : 6320 ddi_put16(fdc->c_handlep_dma, 6321 (ushort_t *)&dma_reg->sb_dma_regs[DMA_1WCNT], 6322 count & 0xFFFF); 6323 break; 6324 case 2 : 6325 ddi_put16(fdc->c_handlep_dma, 6326 (ushort_t *)&dma_reg->sb_dma_regs[DMA_2WCNT], 6327 count & 0xFFFF); 6328 break; 6329 case 3 : 6330 ddi_put16(fdc->c_handlep_dma, 6331 (ushort_t *)&dma_reg->sb_dma_regs[DMA_3WCNT], 6332 count & 0xFFFF); 6333 break; 6334 default : 6335 FDERRPRINT(FDEP_L3, FDEM_SDMA, 6336 (C, "set_data_count: wrong channel %x\n", 6337 fdc->sb_dma_channel)); 6338 break; 6339 } 6340 } 6341 } 6342 6343 /* 6344 * get_data_count_register(struct fdctlr *fdc) 6345 * Read the data count from appropriate dma register. 6346 */ 6347 6348 static uint32_t 6349 get_data_count_register(struct fdctlr *fdc) 6350 { 6351 uint32_t retval = 0; 6352 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6353 struct cheerio_dma_reg *dma_reg; 6354 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6355 retval = ddi_get32(fdc->c_handlep_dma, &dma_reg->fdc_dbcr); 6356 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6357 struct sb_dma_reg *dma_reg; 6358 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6359 switch (fdc->sb_dma_channel) { 6360 case 0 : 6361 retval = ddi_get16(fdc->c_handlep_dma, 6362 (ushort_t *)&dma_reg->sb_dma_regs[DMA_0WCNT]); 6363 break; 6364 case 1 : 6365 retval = ddi_get16(fdc->c_handlep_dma, 6366 (ushort_t *)&dma_reg->sb_dma_regs[DMA_1WCNT]); 6367 break; 6368 case 2 : 6369 retval = ddi_get16(fdc->c_handlep_dma, 6370 (ushort_t *)&dma_reg->sb_dma_regs[DMA_2WCNT]); 6371 break; 6372 case 3 : 6373 retval = ddi_get16(fdc->c_handlep_dma, 6374 (ushort_t *)&dma_reg->sb_dma_regs[DMA_3WCNT]); 6375 break; 6376 default : 6377 FDERRPRINT(FDEP_L3, FDEM_SDMA, 6378 (C, "get_data_count: wrong channel %x\n", 6379 fdc->sb_dma_channel)); 6380 break; 6381 } 6382 retval = (uint32_t)((uint16_t)(retval +1)); 6383 } 6384 6385 return (retval); 6386 6387 } 6388 6389 /* 6390 * reset_dma_controller(struct fdctlr *fdc) 6391 * Reset and initialize the dma controller. 6392 */ 6393 6394 static void 6395 reset_dma_controller(struct fdctlr *fdc) 6396 { 6397 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6398 struct cheerio_dma_reg *dma_reg; 6399 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6400 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, DCSR_RESET); 6401 while (get_dma_control_register(fdc) & DCSR_CYC_PEND); 6402 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, 0); 6403 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6404 struct sb_dma_reg *dma_reg; 6405 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6406 ddi_put8(fdc->c_handlep_dma, &dma_reg->sb_dma_regs[DMAC1_MASK], 6407 (fdc->sb_dma_channel & 0x3)); 6408 6409 } 6410 } 6411 6412 /* 6413 * Get the DMA control register for CHEERIO. 6414 * For SouthBridge 8237 DMA controller, this register is not valid. 6415 * So, just return 0. 6416 */ 6417 static uint32_t 6418 get_dma_control_register(struct fdctlr *fdc) 6419 { 6420 uint32_t retval = 0; 6421 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6422 struct cheerio_dma_reg *dma_reg; 6423 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6424 retval = ddi_get32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr); 6425 } 6426 6427 return (retval); 6428 } 6429 6430 6431 /* 6432 * set_data_address_register(struct fdctlr *fdc) 6433 * Set the data address in appropriate dma register. 6434 */ 6435 static void 6436 set_data_address_register(struct fdctlr *fdc, uint32_t address) 6437 { 6438 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6439 struct cheerio_dma_reg *dma_reg; 6440 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6441 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dacr, address); 6442 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6443 struct sb_dma_reg *dma_reg; 6444 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6445 switch (fdc->sb_dma_channel) { 6446 case 0 : 6447 ddi_put8(fdc->c_handlep_dma, 6448 &dma_reg->sb_dma_regs[DMA_0PAGE], 6449 (address & 0xFF0000) >>16); 6450 ddi_put8(fdc->c_handlep_dma, 6451 &dma_reg->sb_dma_regs[DMA_0HPG], 6452 (address & 0xFF000000) >>24); 6453 ddi_put16(fdc->c_handlep_dma, 6454 (ushort_t *)&dma_reg->sb_dma_regs[DMA_0ADR], 6455 address & 0xFFFF); 6456 break; 6457 case 1 : 6458 ddi_put8(fdc->c_handlep_dma, 6459 &dma_reg->sb_dma_regs[DMA_1PAGE], 6460 (address & 0xFF0000) >>16); 6461 ddi_put8(fdc->c_handlep_dma, 6462 &dma_reg->sb_dma_regs[DMA_1HPG], 6463 (address & 0xFF000000) >>24); 6464 ddi_put16(fdc->c_handlep_dma, 6465 (ushort_t *)&dma_reg->sb_dma_regs[DMA_1ADR], 6466 address & 0xFFFF); 6467 break; 6468 case 2 : 6469 ddi_put8(fdc->c_handlep_dma, 6470 &dma_reg->sb_dma_regs[DMA_2PAGE], 6471 (address & 0xFF0000) >>16); 6472 ddi_put8(fdc->c_handlep_dma, 6473 &dma_reg->sb_dma_regs[DMA_2HPG], 6474 (address & 0xFF000000) >>24); 6475 ddi_put16(fdc->c_handlep_dma, 6476 (ushort_t *)&dma_reg->sb_dma_regs[DMA_2ADR], 6477 address & 0xFFFF); 6478 break; 6479 case 3 : 6480 ddi_put8(fdc->c_handlep_dma, 6481 &dma_reg->sb_dma_regs[DMA_3PAGE], 6482 (address & 0xFF0000) >>16); 6483 ddi_put8(fdc->c_handlep_dma, 6484 &dma_reg->sb_dma_regs[DMA_3HPG], 6485 (address & 0xFF000000) >>24); 6486 ddi_put16(fdc->c_handlep_dma, 6487 (ushort_t *)&dma_reg->sb_dma_regs[DMA_3ADR], 6488 address & 0xFFFF); 6489 break; 6490 default : 6491 FDERRPRINT(FDEP_L3, FDEM_SDMA, 6492 (C, "set_data_address: wrong channel %x\n", 6493 fdc->sb_dma_channel)); 6494 break; 6495 } 6496 } 6497 6498 } 6499 6500 6501 /* 6502 * set_dma_mode(struct fdctlr *fdc, int val) 6503 * Set the appropriate dma direction and registers. 6504 */ 6505 static void 6506 set_dma_mode(struct fdctlr *fdc, int val) 6507 { 6508 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6509 struct cheerio_dma_reg *dma_reg; 6510 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6511 if (val == CSB_READ) 6512 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, 6513 DCSR_INIT_BITS|DCSR_WRITE); 6514 else 6515 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, 6516 DCSR_INIT_BITS); 6517 6518 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6519 uint8_t mode_reg_val, chn_mask; 6520 struct sb_dma_reg *dma_reg; 6521 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6522 6523 if (val == CSB_READ) { 6524 mode_reg_val = fdc->sb_dma_channel | DMAMODE_READ 6525 | DMAMODE_SINGLE; 6526 } else { /* Read operation */ 6527 mode_reg_val = fdc->sb_dma_channel | DMAMODE_WRITE 6528 | DMAMODE_SINGLE; 6529 } 6530 ddi_put8(fdc->c_handlep_dma, &dma_reg->sb_dma_regs[DMAC1_MODE], 6531 mode_reg_val); 6532 chn_mask = 1 << (fdc->sb_dma_channel & 0x3); 6533 ddi_put8(fdc->c_handlep_dma, 6534 &dma_reg->sb_dma_regs[DMAC1_ALLMASK], ~chn_mask); 6535 fdc->sb_dma_lock = 1; 6536 } 6537 } 6538 6539 /* 6540 * This function is valid only for CHEERIO/RIO based 6541 * controllers. The control register for the dma channel 6542 * is initialized by this function. 6543 */ 6544 6545 static void 6546 set_dma_control_register(struct fdctlr *fdc, uint32_t val) 6547 { 6548 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6549 struct cheerio_dma_reg *dma_reg; 6550 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6551 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, val); 6552 } 6553 } 6554 6555 static void 6556 release_sb_dma(struct fdctlr *fdc) 6557 { 6558 struct sb_dma_reg *dma_reg; 6559 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6560 /* Unmask all the channels to release the DMA controller */ 6561 ddi_put8(fdc->c_handlep_dma, 6562 &dma_reg->sb_dma_regs[DMAC1_ALLMASK], NULL); 6563 fdc->sb_dma_lock = 0; 6564 } 6565 6566 static void 6567 quiesce_fd_interrupt(struct fdctlr *fdc) 6568 { 6569 /* 6570 * The following code is put here to take care of HW problem. 6571 * The HW problem is as follows: 6572 * 6573 * After poweron the Southbridge floppy controller asserts the 6574 * interrupt in tristate. This causes continuous interrupts to 6575 * be generated. 6576 * Until the Hardware is FIXED we will have to use the following code 6577 * to set the interrupt line to proper state after poweron. 6578 */ 6579 if (fdc->c_fdtype & FDCTYPE_SB) { 6580 ddi_put8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor), 6581 0x0); 6582 drv_usecwait(200); 6583 ddi_put8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor), 6584 0xC); 6585 drv_usecwait(200); 6586 Set_Fifo(fdc, 0xE6); 6587 drv_usecwait(200); 6588 } 6589 } 6590