1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* Integer Unit simulator for Sparc FPU simulator. */ 30 31 #include <sys/fpu/fpu_simulator.h> 32 #include <sys/fpu/globals.h> 33 34 #include <sys/regset.h> 35 #include <sys/privregs.h> 36 #include <sys/vis_simulator.h> 37 38 /* 39 * fbcc_sim() also handles V9 fbpcc, and ignores the prediction bit. 40 */ 41 static enum ftt_type 42 fbcc_sim( 43 fp_inst_type pinst, /* FPU instruction to simulate. */ 44 struct regs *pregs, /* Pointer to PCB image of registers. */ 45 kfpu_t *pfpu) /* Pointer to FPU register block. */ 46 47 { 48 fsr_type fsr; 49 int fbpcc = 0; 50 union { 51 fp_inst_type fi; 52 int32_t i; /* for sign_ext(disp22) */ 53 } fp; 54 enum fcc_type fcc; 55 enum icc_type { 56 fbn, fbne, fblg, fbul, fbl, fbug, fbg, fbu, 57 fba, fbe, fbue, fbge, fbuge, fble, fbule, fbo 58 } icc; 59 60 uint_t annul, takeit; 61 62 if (((pinst.op3 >> 3) & 0xf) == 5) 63 fbpcc = 1; 64 fsr.ll = pfpu->fpu_fsr; 65 if (fbpcc) { 66 uint_t nfcc = (pinst.op3 >> 1) & 0x3; 67 switch (nfcc) { 68 case fcc_0: 69 fcc = fsr.fcc0; 70 break; 71 case fcc_1: 72 fcc = fsr.fcc1; 73 break; 74 case fcc_2: 75 fcc = fsr.fcc2; 76 break; 77 case fcc_3: 78 fcc = fsr.fcc3; 79 break; 80 } 81 } else { 82 fcc = fsr.fcc0; 83 } 84 icc = (enum icc_type) (pinst.rd & 0xf); 85 annul = pinst.rd & 0x10; 86 87 switch (icc) { 88 case fbn: 89 takeit = 0; 90 break; 91 case fbl: 92 takeit = fcc == fcc_less; 93 break; 94 case fbg: 95 takeit = fcc == fcc_greater; 96 break; 97 case fbu: 98 takeit = fcc == fcc_unordered; 99 break; 100 case fbe: 101 takeit = fcc == fcc_equal; 102 break; 103 case fblg: 104 takeit = (fcc == fcc_less) || (fcc == fcc_greater); 105 break; 106 case fbul: 107 takeit = (fcc == fcc_unordered) || (fcc == fcc_less); 108 break; 109 case fbug: 110 takeit = (fcc == fcc_unordered) || (fcc == fcc_greater); 111 break; 112 case fbue: 113 takeit = (fcc == fcc_unordered) || (fcc == fcc_equal); 114 break; 115 case fbge: 116 takeit = (fcc == fcc_greater) || (fcc == fcc_equal); 117 break; 118 case fble: 119 takeit = (fcc == fcc_less) || (fcc == fcc_equal); 120 break; 121 case fbne: 122 takeit = fcc != fcc_equal; 123 break; 124 case fbuge: 125 takeit = fcc != fcc_less; 126 break; 127 case fbule: 128 takeit = fcc != fcc_greater; 129 break; 130 case fbo: 131 takeit = fcc != fcc_unordered; 132 break; 133 case fba: 134 takeit = 1; 135 break; 136 } 137 if (takeit) { /* Branch taken. */ 138 uintptr_t tpc; 139 140 fp.fi = pinst; 141 tpc = pregs->r_pc; 142 if (annul && (icc == fba)) { /* fba,a is wierd */ 143 if (fbpcc) { 144 pregs->r_pc = tpc + 145 (int)((fp.i << 13) >> 11); 146 } else { 147 pregs->r_pc = tpc + 148 (int)((fp.i << 10) >> 8); 149 } 150 pregs->r_npc = pregs->r_pc + 4; 151 } else { 152 pregs->r_pc = pregs->r_npc; 153 if (fbpcc) { 154 pregs->r_npc = tpc + 155 (int)((fp.i << 13) >> 11); 156 } else { 157 pregs->r_npc = tpc + 158 (int)((fp.i << 10) >> 8); 159 } 160 } 161 } else { /* Branch not taken. */ 162 if (annul) { /* Annul next instruction. */ 163 pregs->r_pc = pregs->r_npc + 4; 164 pregs->r_npc += 8; 165 } else { /* Execute next instruction. */ 166 pregs->r_pc = pregs->r_npc; 167 pregs->r_npc += 4; 168 } 169 } 170 return (ftt_none); 171 } 172 173 /* PUBLIC FUNCTIONS */ 174 175 enum ftt_type 176 _fp_iu_simulator( 177 fp_simd_type *pfpsd, /* FPU simulator data. */ 178 fp_inst_type pinst, /* FPU instruction to simulate. */ 179 struct regs *pregs, /* Pointer to PCB image of registers. */ 180 void *prw, /* Pointer to locals and ins. */ 181 kfpu_t *pfpu) /* Pointer to FPU register block. */ 182 { 183 switch (pinst.hibits) { 184 case 0: /* fbcc and V9 fbpcc */ 185 return (fbcc_sim(pinst, pregs, pfpu)); 186 case 2: 187 switch (pinst.op3) { 188 case 0x28: 189 if (pinst.rs1 == 0x13) 190 return (vis_rdgsr(pfpsd, pinst, pregs, 191 prw, pfpu)); 192 else 193 return (ftt_unimplemented); 194 case 0x30: 195 if (pinst.rd == 0x13) 196 return (vis_wrgsr(pfpsd, pinst, pregs, 197 prw, pfpu)); 198 else 199 return (ftt_unimplemented); 200 case 0x2C: 201 return (movcc(pfpsd, pinst, pregs, prw, pfpu)); 202 default: 203 return (ftt_unimplemented); 204 } 205 case 3: 206 return (fldst(pfpsd, pinst, pregs, prw)); 207 default: 208 return (ftt_unimplemented); 209 } 210 } 211