1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 25 */ 26 /* 27 * Copyright (c) 2010, Intel Corporation. 28 * All rights reserved. 29 */ 30 /* 31 * Copyright (c) 2015, Joyent, Inc. 32 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 33 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 34 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 #define FMT_CPUID_INTC_EDX \ 89 "\20" \ 90 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 91 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 92 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 93 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 94 95 /* 96 * cpuid instruction feature flags in %ecx (standard function 1) 97 */ 98 99 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 100 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 101 /* 0x00000004 - reserved */ 102 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 103 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 104 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 105 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 106 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 107 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 108 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 109 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 110 /* 0x00000800 - reserved */ 111 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 112 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 113 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 114 /* 0x00008000 - reserved */ 115 /* 0x00010000 - reserved */ 116 /* 0x00020000 - reserved */ 117 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 118 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 119 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 120 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 121 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 122 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 123 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 124 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 125 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 126 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 127 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 128 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 129 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 130 131 #define FMT_CPUID_INTC_ECX \ 132 "\20" \ 133 "\37rdrand\36f16c\35avx\34osxsav\33xsave" \ 134 "\32aes" \ 135 "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca" \ 136 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 137 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 138 139 /* 140 * cpuid instruction feature flags in %edx (extended function 0x80000001) 141 */ 142 143 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 144 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 145 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 146 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 147 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 148 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 149 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 150 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 151 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 152 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 153 /* 0x00000400 - sysc on K6m6 */ 154 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 155 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 156 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 157 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 158 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 159 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 160 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 161 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 162 /* 0x00040000 - reserved */ 163 /* 0x00080000 - reserved */ 164 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 165 /* 0x00200000 - reserved */ 166 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 167 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 168 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 169 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 170 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 171 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 172 /* 0x10000000 - reserved */ 173 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 174 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 175 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 176 177 #define FMT_CPUID_AMD_EDX \ 178 "\20" \ 179 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 180 "\30mmx\27mmxext\25nx\22pse\21pat" \ 181 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 182 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 183 184 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 185 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 186 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 187 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 188 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 189 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 190 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 191 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 192 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 193 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 194 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 195 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 196 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 197 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 198 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 199 200 #define FMT_CPUID_AMD_ECX \ 201 "\20" \ 202 "\22topoext" \ 203 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 204 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 205 206 /* 207 * Intel now seems to have claimed part of the "extended" function 208 * space that we previously for non-Intel implementors to use. 209 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 210 * is available in long mode i.e. what AMD indicate using bit 0. 211 * On the other hand, everything else is labelled as reserved. 212 */ 213 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 214 215 /* 216 * Intel also uses cpuid leaf 7 to have additional instructions and features. 217 * Like some other leaves, but unlike the current ones we care about, it 218 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 219 * with the potential use of additional sub-leaves in the future, we now 220 * specifically label the EBX features with their leaf and sub-leaf. 221 */ 222 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 223 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 224 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 225 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 Instrs */ 226 227 #define P5_MCHADDR 0x0 228 #define P5_CESR 0x11 229 #define P5_CTR0 0x12 230 #define P5_CTR1 0x13 231 232 #define K5_MCHADDR 0x0 233 #define K5_MCHTYPE 0x01 234 #define K5_TSC 0x10 235 #define K5_TR12 0x12 236 237 #define REG_PAT 0x277 238 239 #define REG_MC0_CTL 0x400 240 #define REG_MC5_MISC 0x417 241 #define REG_PERFCTR0 0xc1 242 #define REG_PERFCTR1 0xc2 243 244 #define REG_PERFEVNT0 0x186 245 #define REG_PERFEVNT1 0x187 246 247 #define REG_TSC 0x10 /* timestamp counter */ 248 #define REG_APIC_BASE_MSR 0x1b 249 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 250 251 #if !defined(__xpv) 252 /* 253 * AMD C1E 254 */ 255 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 256 #define AMD_ACTONCMPHALT_SHIFT 27 257 #define AMD_ACTONCMPHALT_MASK 3 258 #endif 259 260 #define MSR_DEBUGCTL 0x1d9 261 262 #define DEBUGCTL_LBR 0x01 263 #define DEBUGCTL_BTF 0x02 264 265 /* Intel P6, AMD */ 266 #define MSR_LBR_FROM 0x1db 267 #define MSR_LBR_TO 0x1dc 268 #define MSR_LEX_FROM 0x1dd 269 #define MSR_LEX_TO 0x1de 270 271 /* Intel P4 (pre-Prescott, non P4 M) */ 272 #define MSR_P4_LBSTK_TOS 0x1da 273 #define MSR_P4_LBSTK_0 0x1db 274 #define MSR_P4_LBSTK_1 0x1dc 275 #define MSR_P4_LBSTK_2 0x1dd 276 #define MSR_P4_LBSTK_3 0x1de 277 278 /* Intel Pentium M */ 279 #define MSR_P6M_LBSTK_TOS 0x1c9 280 #define MSR_P6M_LBSTK_0 0x040 281 #define MSR_P6M_LBSTK_1 0x041 282 #define MSR_P6M_LBSTK_2 0x042 283 #define MSR_P6M_LBSTK_3 0x043 284 #define MSR_P6M_LBSTK_4 0x044 285 #define MSR_P6M_LBSTK_5 0x045 286 #define MSR_P6M_LBSTK_6 0x046 287 #define MSR_P6M_LBSTK_7 0x047 288 289 /* Intel P4 (Prescott) */ 290 #define MSR_PRP4_LBSTK_TOS 0x1da 291 #define MSR_PRP4_LBSTK_FROM_0 0x680 292 #define MSR_PRP4_LBSTK_FROM_1 0x681 293 #define MSR_PRP4_LBSTK_FROM_2 0x682 294 #define MSR_PRP4_LBSTK_FROM_3 0x683 295 #define MSR_PRP4_LBSTK_FROM_4 0x684 296 #define MSR_PRP4_LBSTK_FROM_5 0x685 297 #define MSR_PRP4_LBSTK_FROM_6 0x686 298 #define MSR_PRP4_LBSTK_FROM_7 0x687 299 #define MSR_PRP4_LBSTK_FROM_8 0x688 300 #define MSR_PRP4_LBSTK_FROM_9 0x689 301 #define MSR_PRP4_LBSTK_FROM_10 0x68a 302 #define MSR_PRP4_LBSTK_FROM_11 0x68b 303 #define MSR_PRP4_LBSTK_FROM_12 0x68c 304 #define MSR_PRP4_LBSTK_FROM_13 0x68d 305 #define MSR_PRP4_LBSTK_FROM_14 0x68e 306 #define MSR_PRP4_LBSTK_FROM_15 0x68f 307 #define MSR_PRP4_LBSTK_TO_0 0x6c0 308 #define MSR_PRP4_LBSTK_TO_1 0x6c1 309 #define MSR_PRP4_LBSTK_TO_2 0x6c2 310 #define MSR_PRP4_LBSTK_TO_3 0x6c3 311 #define MSR_PRP4_LBSTK_TO_4 0x6c4 312 #define MSR_PRP4_LBSTK_TO_5 0x6c5 313 #define MSR_PRP4_LBSTK_TO_6 0x6c6 314 #define MSR_PRP4_LBSTK_TO_7 0x6c7 315 #define MSR_PRP4_LBSTK_TO_8 0x6c8 316 #define MSR_PRP4_LBSTK_TO_9 0x6c9 317 #define MSR_PRP4_LBSTK_TO_10 0x6ca 318 #define MSR_PRP4_LBSTK_TO_11 0x6cb 319 #define MSR_PRP4_LBSTK_TO_12 0x6cc 320 #define MSR_PRP4_LBSTK_TO_13 0x6cd 321 #define MSR_PRP4_LBSTK_TO_14 0x6ce 322 #define MSR_PRP4_LBSTK_TO_15 0x6cf 323 324 #define MCI_CTL_VALUE 0xffffffff 325 326 #define MTRR_TYPE_UC 0 327 #define MTRR_TYPE_WC 1 328 #define MTRR_TYPE_WT 4 329 #define MTRR_TYPE_WP 5 330 #define MTRR_TYPE_WB 6 331 #define MTRR_TYPE_UC_ 7 332 333 /* 334 * For Solaris we set up the page attritubute table in the following way: 335 * PAT0 Write-Back 336 * PAT1 Write-Through 337 * PAT2 Unchacheable- 338 * PAT3 Uncacheable 339 * PAT4 Write-Back 340 * PAT5 Write-Through 341 * PAT6 Write-Combine 342 * PAT7 Uncacheable 343 * The only difference from h/w default is entry 6. 344 */ 345 #define PAT_DEFAULT_ATTRIBUTE \ 346 ((uint64_t)MTRR_TYPE_WB | \ 347 ((uint64_t)MTRR_TYPE_WT << 8) | \ 348 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 349 ((uint64_t)MTRR_TYPE_UC << 24) | \ 350 ((uint64_t)MTRR_TYPE_WB << 32) | \ 351 ((uint64_t)MTRR_TYPE_WT << 40) | \ 352 ((uint64_t)MTRR_TYPE_WC << 48) | \ 353 ((uint64_t)MTRR_TYPE_UC << 56)) 354 355 #define X86FSET_LARGEPAGE 0 356 #define X86FSET_TSC 1 357 #define X86FSET_MSR 2 358 #define X86FSET_MTRR 3 359 #define X86FSET_PGE 4 360 #define X86FSET_DE 5 361 #define X86FSET_CMOV 6 362 #define X86FSET_MMX 7 363 #define X86FSET_MCA 8 364 #define X86FSET_PAE 9 365 #define X86FSET_CX8 10 366 #define X86FSET_PAT 11 367 #define X86FSET_SEP 12 368 #define X86FSET_SSE 13 369 #define X86FSET_SSE2 14 370 #define X86FSET_HTT 15 371 #define X86FSET_ASYSC 16 372 #define X86FSET_NX 17 373 #define X86FSET_SSE3 18 374 #define X86FSET_CX16 19 375 #define X86FSET_CMP 20 376 #define X86FSET_TSCP 21 377 #define X86FSET_MWAIT 22 378 #define X86FSET_SSE4A 23 379 #define X86FSET_CPUID 24 380 #define X86FSET_SSSE3 25 381 #define X86FSET_SSE4_1 26 382 #define X86FSET_SSE4_2 27 383 #define X86FSET_1GPG 28 384 #define X86FSET_CLFSH 29 385 #define X86FSET_64 30 386 #define X86FSET_AES 31 387 #define X86FSET_PCLMULQDQ 32 388 #define X86FSET_XSAVE 33 389 #define X86FSET_AVX 34 390 #define X86FSET_VMX 35 391 #define X86FSET_SVM 36 392 #define X86FSET_TOPOEXT 37 393 #define X86FSET_F16C 38 394 #define X86FSET_RDRAND 39 395 #define X86FSET_X2APIC 40 396 #define X86FSET_AVX2 41 397 #define X86FSET_BMI1 42 398 #define X86FSET_BMI2 43 399 #define X86FSET_FMA 44 400 #define X86FSET_SMEP 45 401 402 /* 403 * flags to patch tsc_read routine. 404 */ 405 #define X86_NO_TSC 0x0 406 #define X86_HAVE_TSCP 0x1 407 #define X86_TSC_MFENCE 0x2 408 #define X86_TSC_LFENCE 0x4 409 410 /* 411 * Intel Deep C-State invariant TSC in leaf 0x80000007. 412 */ 413 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 414 415 /* 416 * Intel Deep C-state always-running local APIC timer 417 */ 418 #define CPUID_CSTATE_ARAT (0x4) 419 420 /* 421 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 422 */ 423 #define CPUID_EPB_SUPPORT (1 << 3) 424 425 /* 426 * Intel TSC deadline timer 427 */ 428 #define CPUID_DEADLINE_TSC (1 << 24) 429 430 /* 431 * x86_type is a legacy concept; this is supplanted 432 * for most purposes by x86_featureset; modern CPUs 433 * should be X86_TYPE_OTHER 434 */ 435 #define X86_TYPE_OTHER 0 436 #define X86_TYPE_486 1 437 #define X86_TYPE_P5 2 438 #define X86_TYPE_P6 3 439 #define X86_TYPE_CYRIX_486 4 440 #define X86_TYPE_CYRIX_6x86L 5 441 #define X86_TYPE_CYRIX_6x86 6 442 #define X86_TYPE_CYRIX_GXm 7 443 #define X86_TYPE_CYRIX_6x86MX 8 444 #define X86_TYPE_CYRIX_MediaGX 9 445 #define X86_TYPE_CYRIX_MII 10 446 #define X86_TYPE_VIA_CYRIX_III 11 447 #define X86_TYPE_P4 12 448 449 /* 450 * x86_vendor allows us to select between 451 * implementation features and helps guide 452 * the interpretation of the cpuid instruction. 453 */ 454 #define X86_VENDOR_Intel 0 455 #define X86_VENDORSTR_Intel "GenuineIntel" 456 457 #define X86_VENDOR_IntelClone 1 458 459 #define X86_VENDOR_AMD 2 460 #define X86_VENDORSTR_AMD "AuthenticAMD" 461 462 #define X86_VENDOR_Cyrix 3 463 #define X86_VENDORSTR_CYRIX "CyrixInstead" 464 465 #define X86_VENDOR_UMC 4 466 #define X86_VENDORSTR_UMC "UMC UMC UMC " 467 468 #define X86_VENDOR_NexGen 5 469 #define X86_VENDORSTR_NexGen "NexGenDriven" 470 471 #define X86_VENDOR_Centaur 6 472 #define X86_VENDORSTR_Centaur "CentaurHauls" 473 474 #define X86_VENDOR_Rise 7 475 #define X86_VENDORSTR_Rise "RiseRiseRise" 476 477 #define X86_VENDOR_SiS 8 478 #define X86_VENDORSTR_SiS "SiS SiS SiS " 479 480 #define X86_VENDOR_TM 9 481 #define X86_VENDORSTR_TM "GenuineTMx86" 482 483 #define X86_VENDOR_NSC 10 484 #define X86_VENDORSTR_NSC "Geode by NSC" 485 486 /* 487 * Vendor string max len + \0 488 */ 489 #define X86_VENDOR_STRLEN 13 490 491 /* 492 * Some vendor/family/model/stepping ranges are commonly grouped under 493 * a single identifying banner by the vendor. The following encode 494 * that "revision" in a uint32_t with the 8 most significant bits 495 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 496 * family, and the remaining 16 typically forming a bitmask of revisions 497 * within that family with more significant bits indicating "later" revisions. 498 */ 499 500 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 501 #define _X86_CHIPREV_VENDOR_SHIFT 24 502 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 503 #define _X86_CHIPREV_FAMILY_SHIFT 16 504 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 505 506 #define _X86_CHIPREV_VENDOR(x) \ 507 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 508 #define _X86_CHIPREV_FAMILY(x) \ 509 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 510 #define _X86_CHIPREV_REV(x) \ 511 ((x) & _X86_CHIPREV_REV_MASK) 512 513 /* True if x matches in vendor and family and if x matches the given rev mask */ 514 #define X86_CHIPREV_MATCH(x, mask) \ 515 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 516 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 517 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 518 519 /* True if x matches in vendor and family, and rev is at least minx */ 520 #define X86_CHIPREV_ATLEAST(x, minx) \ 521 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 522 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 523 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 524 525 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 526 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 527 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 528 529 /* True if x matches in vendor, and family is at least minx */ 530 #define X86_CHIPFAM_ATLEAST(x, minx) \ 531 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 532 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 533 534 /* Revision default */ 535 #define X86_CHIPREV_UNKNOWN 0x0 536 537 /* 538 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 539 * sufficiently different that we will distinguish them; in all other 540 * case we will identify the major revision. 541 */ 542 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 543 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 544 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 545 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 546 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 547 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 548 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 549 550 /* 551 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 552 */ 553 #define X86_CHIPREV_AMD_10_REV_A \ 554 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 555 #define X86_CHIPREV_AMD_10_REV_B \ 556 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 557 #define X86_CHIPREV_AMD_10_REV_C2 \ 558 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 559 #define X86_CHIPREV_AMD_10_REV_C3 \ 560 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 561 #define X86_CHIPREV_AMD_10_REV_D0 \ 562 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 563 #define X86_CHIPREV_AMD_10_REV_D1 \ 564 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 565 #define X86_CHIPREV_AMD_10_REV_E \ 566 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 567 568 /* 569 * Definitions for AMD Family 0x11. 570 */ 571 #define X86_CHIPREV_AMD_11_REV_B \ 572 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 573 574 /* 575 * Definitions for AMD Family 0x12. 576 */ 577 #define X86_CHIPREV_AMD_12_REV_B \ 578 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 579 580 /* 581 * Definitions for AMD Family 0x14. 582 */ 583 #define X86_CHIPREV_AMD_14_REV_B \ 584 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 585 #define X86_CHIPREV_AMD_14_REV_C \ 586 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 587 588 /* 589 * Definitions for AMD Family 0x15 590 */ 591 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 592 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 593 594 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 595 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 596 597 /* 598 * Various socket/package types, extended as the need to distinguish 599 * a new type arises. The top 8 byte identfies the vendor and the 600 * remaining 24 bits describe 24 socket types. 601 */ 602 603 #define _X86_SOCKET_VENDOR_SHIFT 24 604 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 605 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 606 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 607 608 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 609 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 610 611 #define X86_SOCKET_MATCH(s, mask) \ 612 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 613 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 614 615 #define X86_SOCKET_UNKNOWN 0x0 616 /* 617 * AMD socket types 618 */ 619 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 620 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 621 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 622 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 623 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 624 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 625 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 626 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 627 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 628 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 629 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 630 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 631 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 632 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 633 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 634 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 635 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 636 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 637 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 638 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 639 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 640 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 641 642 /* 643 * xgetbv/xsetbv support 644 */ 645 646 #define XFEATURE_ENABLED_MASK 0x0 647 /* 648 * XFEATURE_ENABLED_MASK values (eax) 649 */ 650 #define XFEATURE_LEGACY_FP 0x1 651 #define XFEATURE_SSE 0x2 652 #define XFEATURE_AVX 0x4 653 #define XFEATURE_MAX XFEATURE_AVX 654 #define XFEATURE_FP_ALL \ 655 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 656 657 #if !defined(_ASM) 658 659 #if defined(_KERNEL) || defined(_KMEMUSER) 660 661 #define NUM_X86_FEATURES 46 662 extern uchar_t x86_featureset[]; 663 664 extern void free_x86_featureset(void *featureset); 665 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 666 extern void add_x86_feature(void *featureset, uint_t feature); 667 extern void remove_x86_feature(void *featureset, uint_t feature); 668 extern boolean_t compare_x86_featureset(void *setA, void *setB); 669 extern void print_x86_featureset(void *featureset); 670 671 672 extern uint_t x86_type; 673 extern uint_t x86_vendor; 674 extern uint_t x86_clflush_size; 675 676 extern uint_t pentiumpro_bug4046376; 677 678 extern const char CyrixInstead[]; 679 680 #endif 681 682 #if defined(_KERNEL) 683 684 /* 685 * This structure is used to pass arguments and get return values back 686 * from the CPUID instruction in __cpuid_insn() routine. 687 */ 688 struct cpuid_regs { 689 uint32_t cp_eax; 690 uint32_t cp_ebx; 691 uint32_t cp_ecx; 692 uint32_t cp_edx; 693 }; 694 695 /* 696 * Utility functions to get/set extended control registers (XCR) 697 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 698 */ 699 extern uint64_t get_xcr(uint_t); 700 extern void set_xcr(uint_t, uint64_t); 701 702 extern uint64_t rdmsr(uint_t); 703 extern void wrmsr(uint_t, const uint64_t); 704 extern uint64_t xrdmsr(uint_t); 705 extern void xwrmsr(uint_t, const uint64_t); 706 extern int checked_rdmsr(uint_t, uint64_t *); 707 extern int checked_wrmsr(uint_t, uint64_t); 708 709 extern void invalidate_cache(void); 710 extern ulong_t getcr4(void); 711 extern void setcr4(ulong_t); 712 713 extern void mtrr_sync(void); 714 715 extern void cpu_fast_syscall_enable(void *); 716 extern void cpu_fast_syscall_disable(void *); 717 718 struct cpu; 719 720 extern int cpuid_checkpass(struct cpu *, int); 721 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 722 extern uint32_t __cpuid_insn(struct cpuid_regs *); 723 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 724 extern int cpuid_getidstr(struct cpu *, char *, size_t); 725 extern const char *cpuid_getvendorstr(struct cpu *); 726 extern uint_t cpuid_getvendor(struct cpu *); 727 extern uint_t cpuid_getfamily(struct cpu *); 728 extern uint_t cpuid_getmodel(struct cpu *); 729 extern uint_t cpuid_getstep(struct cpu *); 730 extern uint_t cpuid_getsig(struct cpu *); 731 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 732 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 733 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 734 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 735 extern int cpuid_get_chipid(struct cpu *); 736 extern id_t cpuid_get_coreid(struct cpu *); 737 extern int cpuid_get_pkgcoreid(struct cpu *); 738 extern int cpuid_get_clogid(struct cpu *); 739 extern int cpuid_get_cacheid(struct cpu *); 740 extern uint32_t cpuid_get_apicid(struct cpu *); 741 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 742 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 743 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 744 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 745 extern int cpuid_is_cmt(struct cpu *); 746 extern int cpuid_syscall32_insn(struct cpu *); 747 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 748 749 extern uint32_t cpuid_getchiprev(struct cpu *); 750 extern const char *cpuid_getchiprevstr(struct cpu *); 751 extern uint32_t cpuid_getsockettype(struct cpu *); 752 extern const char *cpuid_getsocketstr(struct cpu *); 753 754 extern int cpuid_have_cr8access(struct cpu *); 755 756 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 757 758 struct cpuid_info; 759 760 extern void setx86isalist(void); 761 extern void cpuid_alloc_space(struct cpu *); 762 extern void cpuid_free_space(struct cpu *); 763 extern void cpuid_pass1(struct cpu *, uchar_t *); 764 extern void cpuid_pass2(struct cpu *); 765 extern void cpuid_pass3(struct cpu *); 766 extern void cpuid_pass4(struct cpu *, uint_t *); 767 extern void cpuid_set_cpu_properties(void *, processorid_t, 768 struct cpuid_info *); 769 770 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 771 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 772 773 #if !defined(__xpv) 774 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 775 extern void cpuid_mwait_free(struct cpu *); 776 extern int cpuid_deep_cstates_supported(void); 777 extern int cpuid_arat_supported(void); 778 extern int cpuid_iepb_supported(struct cpu *); 779 extern int cpuid_deadline_tsc_supported(void); 780 extern void vmware_port(int, uint32_t *); 781 #endif 782 783 struct cpu_ucode_info; 784 785 extern void ucode_alloc_space(struct cpu *); 786 extern void ucode_free_space(struct cpu *); 787 extern void ucode_check(struct cpu *); 788 extern void ucode_cleanup(); 789 790 #if !defined(__xpv) 791 extern char _tsc_mfence_start; 792 extern char _tsc_mfence_end; 793 extern char _tscp_start; 794 extern char _tscp_end; 795 extern char _no_rdtsc_start; 796 extern char _no_rdtsc_end; 797 extern char _tsc_lfence_start; 798 extern char _tsc_lfence_end; 799 #endif 800 801 #if !defined(__xpv) 802 extern char bcopy_patch_start; 803 extern char bcopy_patch_end; 804 extern char bcopy_ck_size; 805 #endif 806 807 extern void post_startup_cpu_fixups(void); 808 809 extern uint_t workaround_errata(struct cpu *); 810 811 #if defined(OPTERON_ERRATUM_93) 812 extern int opteron_erratum_93; 813 #endif 814 815 #if defined(OPTERON_ERRATUM_91) 816 extern int opteron_erratum_91; 817 #endif 818 819 #if defined(OPTERON_ERRATUM_100) 820 extern int opteron_erratum_100; 821 #endif 822 823 #if defined(OPTERON_ERRATUM_121) 824 extern int opteron_erratum_121; 825 #endif 826 827 #if defined(OPTERON_WORKAROUND_6323525) 828 extern int opteron_workaround_6323525; 829 extern void patch_workaround_6323525(void); 830 #endif 831 832 #if !defined(__xpv) 833 extern void determine_platform(void); 834 #endif 835 extern int get_hwenv(void); 836 extern int is_controldom(void); 837 838 extern void xsave_setup_msr(struct cpu *); 839 840 /* 841 * Hypervisor signatures 842 */ 843 #define HVSIG_XEN_HVM "XenVMMXenVMM" 844 #define HVSIG_VMWARE "VMwareVMware" 845 #define HVSIG_KVM "KVMKVMKVM" 846 #define HVSIG_MICROSOFT "Microsoft Hv" 847 848 /* 849 * Defined hardware environments 850 */ 851 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 852 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 853 854 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 855 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 856 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 857 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 858 859 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT) 860 861 #endif /* _KERNEL */ 862 863 #endif /* !_ASM */ 864 865 /* 866 * VMware hypervisor related defines 867 */ 868 #define VMWARE_HVMAGIC 0x564d5868 869 #define VMWARE_HVPORT 0x5658 870 #define VMWARE_HVCMD_GETVERSION 0x0a 871 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 872 873 #ifdef __cplusplus 874 } 875 #endif 876 877 #endif /* _SYS_X86_ARCHEXT_H */ 878