1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_X86_ARCHEXT_H 27 #define _SYS_X86_ARCHEXT_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #if !defined(_ASM) 32 #include <sys/regset.h> 33 #include <sys/processor.h> 34 #include <vm/seg_enum.h> 35 #include <vm/page.h> 36 #endif /* _ASM */ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * cpuid instruction feature flags in %edx (standard function 1) 44 */ 45 46 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 47 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 48 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 49 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 50 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 51 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 52 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 53 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 54 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 55 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 56 /* 0x400 - reserved */ 57 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 58 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 59 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 60 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 61 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 62 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 63 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 64 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 65 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 66 /* 0x100000 - reserved */ 67 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 68 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 69 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 70 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 71 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 72 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 73 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 74 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 75 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 76 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 77 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 78 79 #define FMT_CPUID_INTC_EDX \ 80 "\20" \ 81 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 82 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 83 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 84 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 85 86 /* 87 * cpuid instruction feature flags in %ecx (standard function 1) 88 */ 89 90 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 91 /* 0x00000002 - reserved */ 92 /* 0x00000004 - reserved */ 93 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 94 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 95 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 96 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 97 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 98 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 99 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 100 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 101 /* 0x00000800 - reserved */ 102 /* 0x00001000 - reserved */ 103 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 104 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 105 /* 0x00008000 - reserved */ 106 /* 0x00010000 - reserved */ 107 /* 0x00020000 - reserved */ 108 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 109 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 110 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 111 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 112 113 #define FMT_CPUID_INTC_ECX \ 114 "\20" \ 115 "\30popcnt\25sse4.2\24sse4.1\23dca" \ 116 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 117 "\10est\7smx\6vmx\5dscpl\4mon\1sse3" 118 119 /* 120 * cpuid instruction feature flags in %edx (extended function 0x80000001) 121 */ 122 123 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 124 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 125 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 126 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 127 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 128 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 129 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 130 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 131 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 132 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 133 /* 0x00000400 - sysc on K6m6 */ 134 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 135 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 136 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 137 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 138 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 139 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 140 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 141 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 142 /* 0x00040000 - reserved */ 143 /* 0x00080000 - reserved */ 144 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 145 /* 0x00200000 - reserved */ 146 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 147 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 148 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 149 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 150 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 151 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 152 /* 0x10000000 - reserved */ 153 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 154 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 155 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 156 157 #define FMT_CPUID_AMD_EDX \ 158 "\20" \ 159 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 160 "\30mmx\27mmxext\25nx\22pse\21pat" \ 161 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 162 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 163 164 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 165 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 166 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 167 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 168 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 169 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 170 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 171 172 #define FMT_CPUID_AMD_ECX \ 173 "\20" \ 174 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 175 176 /* 177 * Intel now seems to have claimed part of the "extended" function 178 * space that we previously for non-Intel implementors to use. 179 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 180 * is available in long mode i.e. what AMD indicate using bit 0. 181 * On the other hand, everything else is labelled as reserved. 182 */ 183 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 184 185 186 #define P5_MCHADDR 0x0 187 #define P5_CESR 0x11 188 #define P5_CTR0 0x12 189 #define P5_CTR1 0x13 190 191 #define K5_MCHADDR 0x0 192 #define K5_MCHTYPE 0x01 193 #define K5_TSC 0x10 194 #define K5_TR12 0x12 195 196 #define REG_PAT 0x277 197 198 #define REG_MC0_CTL 0x400 199 #define REG_MC5_MISC 0x417 200 #define REG_PERFCTR0 0xc1 201 #define REG_PERFCTR1 0xc2 202 203 #define REG_PERFEVNT0 0x186 204 #define REG_PERFEVNT1 0x187 205 206 #define REG_TSC 0x10 /* timestamp counter */ 207 #define REG_APIC_BASE_MSR 0x1b 208 209 #define MSR_DEBUGCTL 0x1d9 210 211 #define DEBUGCTL_LBR 0x01 212 #define DEBUGCTL_BTF 0x02 213 214 /* Intel P6, AMD */ 215 #define MSR_LBR_FROM 0x1db 216 #define MSR_LBR_TO 0x1dc 217 #define MSR_LEX_FROM 0x1dd 218 #define MSR_LEX_TO 0x1de 219 220 /* Intel P4 (pre-Prescott, non P4 M) */ 221 #define MSR_P4_LBSTK_TOS 0x1da 222 #define MSR_P4_LBSTK_0 0x1db 223 #define MSR_P4_LBSTK_1 0x1dc 224 #define MSR_P4_LBSTK_2 0x1dd 225 #define MSR_P4_LBSTK_3 0x1de 226 227 /* Intel Pentium M */ 228 #define MSR_P6M_LBSTK_TOS 0x1c9 229 #define MSR_P6M_LBSTK_0 0x040 230 #define MSR_P6M_LBSTK_1 0x041 231 #define MSR_P6M_LBSTK_2 0x042 232 #define MSR_P6M_LBSTK_3 0x043 233 #define MSR_P6M_LBSTK_4 0x044 234 #define MSR_P6M_LBSTK_5 0x045 235 #define MSR_P6M_LBSTK_6 0x046 236 #define MSR_P6M_LBSTK_7 0x047 237 238 /* Intel P4 (Prescott) */ 239 #define MSR_PRP4_LBSTK_TOS 0x1da 240 #define MSR_PRP4_LBSTK_FROM_0 0x680 241 #define MSR_PRP4_LBSTK_FROM_1 0x681 242 #define MSR_PRP4_LBSTK_FROM_2 0x682 243 #define MSR_PRP4_LBSTK_FROM_3 0x683 244 #define MSR_PRP4_LBSTK_FROM_4 0x684 245 #define MSR_PRP4_LBSTK_FROM_5 0x685 246 #define MSR_PRP4_LBSTK_FROM_6 0x686 247 #define MSR_PRP4_LBSTK_FROM_7 0x687 248 #define MSR_PRP4_LBSTK_FROM_8 0x688 249 #define MSR_PRP4_LBSTK_FROM_9 0x689 250 #define MSR_PRP4_LBSTK_FROM_10 0x68a 251 #define MSR_PRP4_LBSTK_FROM_11 0x68b 252 #define MSR_PRP4_LBSTK_FROM_12 0x68c 253 #define MSR_PRP4_LBSTK_FROM_13 0x68d 254 #define MSR_PRP4_LBSTK_FROM_14 0x68e 255 #define MSR_PRP4_LBSTK_FROM_15 0x68f 256 #define MSR_PRP4_LBSTK_TO_0 0x6c0 257 #define MSR_PRP4_LBSTK_TO_1 0x6c1 258 #define MSR_PRP4_LBSTK_TO_2 0x6c2 259 #define MSR_PRP4_LBSTK_TO_3 0x6c3 260 #define MSR_PRP4_LBSTK_TO_4 0x6c4 261 #define MSR_PRP4_LBSTK_TO_5 0x6c5 262 #define MSR_PRP4_LBSTK_TO_6 0x6c6 263 #define MSR_PRP4_LBSTK_TO_7 0x6c7 264 #define MSR_PRP4_LBSTK_TO_8 0x6c8 265 #define MSR_PRP4_LBSTK_TO_9 0x6c9 266 #define MSR_PRP4_LBSTK_TO_10 0x6ca 267 #define MSR_PRP4_LBSTK_TO_11 0x6cb 268 #define MSR_PRP4_LBSTK_TO_12 0x6cc 269 #define MSR_PRP4_LBSTK_TO_13 0x6cd 270 #define MSR_PRP4_LBSTK_TO_14 0x6ce 271 #define MSR_PRP4_LBSTK_TO_15 0x6cf 272 273 #define MCI_CTL_VALUE 0xffffffff 274 275 #define MTRR_TYPE_UC 0 276 #define MTRR_TYPE_WC 1 277 #define MTRR_TYPE_WT 4 278 #define MTRR_TYPE_WP 5 279 #define MTRR_TYPE_WB 6 280 #define MTRR_TYPE_UC_ 7 281 282 /* 283 * For Solaris we set up the page attritubute table in the following way: 284 * PAT0 Write-Back 285 * PAT1 Write-Through 286 * PAT2 Unchacheable- 287 * PAT3 Uncacheable 288 * PAT4 Write-Back 289 * PAT5 Write-Through 290 * PAT6 Write-Combine 291 * PAT7 Uncacheable 292 * The only difference from h/w default is entry 6. 293 */ 294 #define PAT_DEFAULT_ATTRIBUTE \ 295 ((uint64_t)MTRR_TYPE_WB | \ 296 ((uint64_t)MTRR_TYPE_WT << 8) | \ 297 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 298 ((uint64_t)MTRR_TYPE_UC << 24) | \ 299 ((uint64_t)MTRR_TYPE_WB << 32) | \ 300 ((uint64_t)MTRR_TYPE_WT << 40) | \ 301 ((uint64_t)MTRR_TYPE_WC << 48) | \ 302 ((uint64_t)MTRR_TYPE_UC << 56)) 303 304 #define X86_LARGEPAGE 0x00000001 305 #define X86_TSC 0x00000002 306 #define X86_MSR 0x00000004 307 #define X86_MTRR 0x00000008 308 #define X86_PGE 0x00000010 309 #define X86_DE 0x00000020 310 #define X86_CMOV 0x00000040 311 #define X86_MMX 0x00000080 312 #define X86_MCA 0x00000100 313 #define X86_PAE 0x00000200 314 #define X86_CX8 0x00000400 315 #define X86_PAT 0x00000800 316 #define X86_SEP 0x00001000 317 #define X86_SSE 0x00002000 318 #define X86_SSE2 0x00004000 319 #define X86_HTT 0x00008000 320 #define X86_ASYSC 0x00010000 321 #define X86_NX 0x00020000 322 #define X86_SSE3 0x00040000 323 #define X86_CX16 0x00080000 324 #define X86_CMP 0x00100000 325 #define X86_TSCP 0x00200000 326 #define X86_MWAIT 0x00400000 327 #define X86_SSE4A 0x00800000 328 #define X86_CPUID 0x01000000 329 #define X86_SSSE3 0x02000000 330 #define X86_SSE4_1 0x04000000 331 #define X86_SSE4_2 0x08000000 332 #define X86_1GPG 0x10000000 333 334 /* 335 * flags to patch tsc_read routine. 336 */ 337 #define X86_NO_TSC 0x0 338 #define X86_HAVE_TSCP 0x1 339 #define X86_TSC_MFENCE 0x2 340 341 #define FMT_X86_FEATURE \ 342 "\20" \ 343 "\34sse4_2\33sse4_1\32ssse3\31cpuid" \ 344 "\30sse4a\27mwait\26tscp\25cmp\24cx16\23sse3\22nx\21asysc"\ 345 "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ 346 "\10mmx\7cmov\6de\5pge\4mtrr\3msr\2tsc\1lgpg" 347 348 /* 349 * x86_type is a legacy concept; this is supplanted 350 * for most purposes by x86_feature; modern CPUs 351 * should be X86_TYPE_OTHER 352 */ 353 #define X86_TYPE_OTHER 0 354 #define X86_TYPE_486 1 355 #define X86_TYPE_P5 2 356 #define X86_TYPE_P6 3 357 #define X86_TYPE_CYRIX_486 4 358 #define X86_TYPE_CYRIX_6x86L 5 359 #define X86_TYPE_CYRIX_6x86 6 360 #define X86_TYPE_CYRIX_GXm 7 361 #define X86_TYPE_CYRIX_6x86MX 8 362 #define X86_TYPE_CYRIX_MediaGX 9 363 #define X86_TYPE_CYRIX_MII 10 364 #define X86_TYPE_VIA_CYRIX_III 11 365 #define X86_TYPE_P4 12 366 367 /* 368 * x86_vendor allows us to select between 369 * implementation features and helps guide 370 * the interpretation of the cpuid instruction. 371 */ 372 #define X86_VENDOR_Intel 0 /* GenuineIntel */ 373 #define X86_VENDOR_IntelClone 1 /* (an Intel clone) */ 374 #define X86_VENDOR_AMD 2 /* AuthenticAMD */ 375 #define X86_VENDOR_Cyrix 3 /* CyrixInstead */ 376 #define X86_VENDOR_UMC 4 /* UMC UMC UMC */ 377 #define X86_VENDOR_NexGen 5 /* NexGenDriven */ 378 #define X86_VENDOR_Centaur 6 /* CentaurHauls */ 379 #define X86_VENDOR_Rise 7 /* RiseRiseRise */ 380 #define X86_VENDOR_SiS 8 /* SiS SiS SiS */ 381 #define X86_VENDOR_TM 9 /* GenuineTMx86 */ 382 #define X86_VENDOR_NSC 10 /* Geode by NSC */ 383 384 #define X86_VENDOR_STRLEN 13 /* vendor string max len + \0 */ 385 386 /* 387 * Some vendor/family/model/stepping ranges are commonly grouped under 388 * a single identifying banner by the vendor. The following encode 389 * that "revision" in a uint32_t with the 8 most significant bits 390 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 391 * family, and the remaining 16 typically forming a bitmask of revisions 392 * within that family with more significant bits indicating "later" revisions. 393 */ 394 395 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 396 #define _X86_CHIPREV_VENDOR_SHIFT 24 397 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 398 #define _X86_CHIPREV_FAMILY_SHIFT 16 399 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 400 401 #define _X86_CHIPREV_VENDOR(x) \ 402 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 403 #define _X86_CHIPREV_FAMILY(x) \ 404 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 405 #define _X86_CHIPREV_REV(x) \ 406 ((x) & _X86_CHIPREV_REV_MASK) 407 408 /* True if x matches in vendor and family and if x matches the given rev mask */ 409 #define X86_CHIPREV_MATCH(x, mask) \ 410 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 411 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 412 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 413 414 /* True if x matches in vendor and family and rev is at least minx */ 415 #define X86_CHIPREV_ATLEAST(x, minx) \ 416 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 417 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 418 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 419 420 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 421 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 422 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 423 424 /* Revision default */ 425 #define X86_CHIPREV_UNKNOWN 0x0 426 427 /* 428 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 429 * sufficiently different that we will distinguish them; in all other 430 * case we will identify the major revision. 431 */ 432 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 433 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 434 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 435 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 436 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 437 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 438 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 439 440 /* 441 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 442 */ 443 #define X86_CHIPREV_AMD_10_REV_A \ 444 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 445 #define X86_CHIPREV_AMD_10_REV_B \ 446 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 447 448 /* 449 * Various socket/package types, extended as the need to distinguish 450 * a new type arises. The top 8 byte identfies the vendor and the 451 * remaining 24 bits describe 24 socket types. 452 */ 453 454 #define _X86_SOCKET_VENDOR_SHIFT 24 455 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 456 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 457 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 458 459 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 460 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 461 462 #define X86_SOCKET_MATCH(s, mask) \ 463 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 464 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 465 466 #define X86_SOCKET_UNKNOWN 0x0 467 /* 468 * AMD socket types 469 */ 470 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 471 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 472 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 473 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 474 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 475 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 476 477 #if !defined(_ASM) 478 479 #if defined(_KERNEL) || defined(_KMEMUSER) 480 481 extern uint_t x86_feature; 482 extern uint_t x86_type; 483 extern uint_t x86_vendor; 484 485 extern uint_t pentiumpro_bug4046376; 486 extern uint_t pentiumpro_bug4064495; 487 488 extern uint_t enable486; 489 490 extern const char CyrixInstead[]; 491 492 #endif 493 494 #if defined(_KERNEL) 495 496 /* 497 * This structure is used to pass arguments and get return values back 498 * from the CPUID instruction in __cpuid_insn() routine. 499 */ 500 struct cpuid_regs { 501 uint32_t cp_eax; 502 uint32_t cp_ebx; 503 uint32_t cp_ecx; 504 uint32_t cp_edx; 505 }; 506 507 extern uint64_t rdmsr(uint_t); 508 extern void wrmsr(uint_t, const uint64_t); 509 extern uint64_t xrdmsr(uint_t); 510 extern void xwrmsr(uint_t, const uint64_t); 511 extern int checked_rdmsr(uint_t, uint64_t *); 512 extern int checked_wrmsr(uint_t, uint64_t); 513 514 extern void invalidate_cache(void); 515 extern ulong_t getcr4(void); 516 extern void setcr4(ulong_t); 517 518 extern void mtrr_sync(void); 519 520 extern void cpu_fast_syscall_enable(void *); 521 extern void cpu_fast_syscall_disable(void *); 522 523 struct cpu; 524 525 extern int cpuid_checkpass(struct cpu *, int); 526 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 527 extern uint32_t __cpuid_insn(struct cpuid_regs *); 528 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 529 extern int cpuid_getidstr(struct cpu *, char *, size_t); 530 extern const char *cpuid_getvendorstr(struct cpu *); 531 extern uint_t cpuid_getvendor(struct cpu *); 532 extern uint_t cpuid_getfamily(struct cpu *); 533 extern uint_t cpuid_getmodel(struct cpu *); 534 extern uint_t cpuid_getstep(struct cpu *); 535 extern uint_t cpuid_getsig(struct cpu *); 536 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 537 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 538 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 539 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 540 extern int cpuid_get_chipid(struct cpu *); 541 extern id_t cpuid_get_coreid(struct cpu *); 542 extern int cpuid_get_pkgcoreid(struct cpu *); 543 extern int cpuid_get_clogid(struct cpu *); 544 extern int cpuid_is_cmt(struct cpu *); 545 extern int cpuid_syscall32_insn(struct cpu *); 546 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 547 548 extern uint32_t cpuid_getchiprev(struct cpu *); 549 extern const char *cpuid_getchiprevstr(struct cpu *); 550 extern uint32_t cpuid_getsockettype(struct cpu *); 551 552 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 553 554 struct cpuid_info; 555 556 extern void setx86isalist(void); 557 extern void cpuid_alloc_space(struct cpu *); 558 extern void cpuid_free_space(struct cpu *); 559 extern uint_t cpuid_pass1(struct cpu *); 560 extern void cpuid_pass2(struct cpu *); 561 extern void cpuid_pass3(struct cpu *); 562 extern uint_t cpuid_pass4(struct cpu *); 563 extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); 564 565 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 566 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 567 568 #if !defined(__xpv) 569 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 570 extern void cpuid_mwait_free(struct cpu *); 571 #endif 572 573 struct cpu_ucode_info; 574 575 #if !defined(__xpv) 576 extern void ucode_alloc_space(struct cpu *); 577 extern void ucode_free_space(struct cpu *); 578 extern void ucode_check(struct cpu *); 579 extern void ucode_free(); 580 #endif 581 582 #if !defined(__xpv) 583 extern char _tsc_mfence_start; 584 extern char _tsc_mfence_end; 585 extern char _tscp_start; 586 extern char _tscp_end; 587 extern char _no_rdtsc_start; 588 extern char _no_rdtsc_end; 589 #endif 590 591 extern uint_t workaround_errata(struct cpu *); 592 593 #if defined(OPTERON_ERRATUM_93) 594 extern int opteron_erratum_93; 595 #endif 596 597 #if defined(OPTERON_ERRATUM_91) 598 extern int opteron_erratum_91; 599 #endif 600 601 #if defined(OPTERON_ERRATUM_100) 602 extern int opteron_erratum_100; 603 #endif 604 605 #if defined(OPTERON_ERRATUM_121) 606 extern int opteron_erratum_121; 607 #endif 608 609 #if defined(OPTERON_WORKAROUND_6323525) 610 extern int opteron_workaround_6323525; 611 extern void patch_workaround_6323525(void); 612 #endif 613 614 #endif /* _KERNEL */ 615 616 #endif 617 618 #ifdef __cplusplus 619 } 620 #endif 621 622 #endif /* _SYS_X86_ARCHEXT_H */ 623