1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2018 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 /* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108 /* 0x00010000 - reserved */ 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124 125 /* 126 * cpuid instruction feature flags in %edx (extended function 0x80000001) 127 */ 128 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 139 /* 0x00000400 - sysc on K6m6 */ 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 148 /* 0x00040000 - reserved */ 149 /* 0x00080000 - reserved */ 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 151 /* 0x00200000 - reserved */ 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 158 /* 0x10000000 - reserved */ 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 162 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 177 /* 0x00004000 - reserved */ 178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 180 /* 0x00020000 - reserved */ 181 /* 0x00040000 - reserved */ 182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 183 /* 0x00100000 - reserved */ 184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 186 187 /* 188 * Intel now seems to have claimed part of the "extended" function 189 * space that we previously for non-Intel implementors to use. 190 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 191 * is available in long mode i.e. what AMD indicate using bit 0. 192 * On the other hand, everything else is labelled as reserved. 193 */ 194 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 195 196 /* 197 * Intel also uses cpuid leaf 7 to have additional instructions and features. 198 * Like some other leaves, but unlike the current ones we care about, it 199 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 200 * with the potential use of additional sub-leaves in the future, we now 201 * specifically label the EBX features with their leaf and sub-leaf. 202 */ 203 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 204 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 205 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 206 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 207 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 208 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 209 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 210 211 #define REG_PAT 0x277 212 #define REG_TSC 0x10 /* timestamp counter */ 213 #define REG_APIC_BASE_MSR 0x1b 214 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 215 216 #if !defined(__xpv) 217 /* 218 * AMD C1E 219 */ 220 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 221 #define AMD_ACTONCMPHALT_SHIFT 27 222 #define AMD_ACTONCMPHALT_MASK 3 223 #endif 224 225 #define MSR_DEBUGCTL 0x1d9 226 227 #define DEBUGCTL_LBR 0x01 228 #define DEBUGCTL_BTF 0x02 229 230 /* Intel P6, AMD */ 231 #define MSR_LBR_FROM 0x1db 232 #define MSR_LBR_TO 0x1dc 233 #define MSR_LEX_FROM 0x1dd 234 #define MSR_LEX_TO 0x1de 235 236 /* Intel P4 (pre-Prescott, non P4 M) */ 237 #define MSR_P4_LBSTK_TOS 0x1da 238 #define MSR_P4_LBSTK_0 0x1db 239 #define MSR_P4_LBSTK_1 0x1dc 240 #define MSR_P4_LBSTK_2 0x1dd 241 #define MSR_P4_LBSTK_3 0x1de 242 243 /* Intel Pentium M */ 244 #define MSR_P6M_LBSTK_TOS 0x1c9 245 #define MSR_P6M_LBSTK_0 0x040 246 #define MSR_P6M_LBSTK_1 0x041 247 #define MSR_P6M_LBSTK_2 0x042 248 #define MSR_P6M_LBSTK_3 0x043 249 #define MSR_P6M_LBSTK_4 0x044 250 #define MSR_P6M_LBSTK_5 0x045 251 #define MSR_P6M_LBSTK_6 0x046 252 #define MSR_P6M_LBSTK_7 0x047 253 254 /* Intel P4 (Prescott) */ 255 #define MSR_PRP4_LBSTK_TOS 0x1da 256 #define MSR_PRP4_LBSTK_FROM_0 0x680 257 #define MSR_PRP4_LBSTK_FROM_1 0x681 258 #define MSR_PRP4_LBSTK_FROM_2 0x682 259 #define MSR_PRP4_LBSTK_FROM_3 0x683 260 #define MSR_PRP4_LBSTK_FROM_4 0x684 261 #define MSR_PRP4_LBSTK_FROM_5 0x685 262 #define MSR_PRP4_LBSTK_FROM_6 0x686 263 #define MSR_PRP4_LBSTK_FROM_7 0x687 264 #define MSR_PRP4_LBSTK_FROM_8 0x688 265 #define MSR_PRP4_LBSTK_FROM_9 0x689 266 #define MSR_PRP4_LBSTK_FROM_10 0x68a 267 #define MSR_PRP4_LBSTK_FROM_11 0x68b 268 #define MSR_PRP4_LBSTK_FROM_12 0x68c 269 #define MSR_PRP4_LBSTK_FROM_13 0x68d 270 #define MSR_PRP4_LBSTK_FROM_14 0x68e 271 #define MSR_PRP4_LBSTK_FROM_15 0x68f 272 #define MSR_PRP4_LBSTK_TO_0 0x6c0 273 #define MSR_PRP4_LBSTK_TO_1 0x6c1 274 #define MSR_PRP4_LBSTK_TO_2 0x6c2 275 #define MSR_PRP4_LBSTK_TO_3 0x6c3 276 #define MSR_PRP4_LBSTK_TO_4 0x6c4 277 #define MSR_PRP4_LBSTK_TO_5 0x6c5 278 #define MSR_PRP4_LBSTK_TO_6 0x6c6 279 #define MSR_PRP4_LBSTK_TO_7 0x6c7 280 #define MSR_PRP4_LBSTK_TO_8 0x6c8 281 #define MSR_PRP4_LBSTK_TO_9 0x6c9 282 #define MSR_PRP4_LBSTK_TO_10 0x6ca 283 #define MSR_PRP4_LBSTK_TO_11 0x6cb 284 #define MSR_PRP4_LBSTK_TO_12 0x6cc 285 #define MSR_PRP4_LBSTK_TO_13 0x6cd 286 #define MSR_PRP4_LBSTK_TO_14 0x6ce 287 #define MSR_PRP4_LBSTK_TO_15 0x6cf 288 289 #define MCI_CTL_VALUE 0xffffffff 290 291 #define MTRR_TYPE_UC 0 292 #define MTRR_TYPE_WC 1 293 #define MTRR_TYPE_WT 4 294 #define MTRR_TYPE_WP 5 295 #define MTRR_TYPE_WB 6 296 #define MTRR_TYPE_UC_ 7 297 298 /* 299 * For Solaris we set up the page attritubute table in the following way: 300 * PAT0 Write-Back 301 * PAT1 Write-Through 302 * PAT2 Unchacheable- 303 * PAT3 Uncacheable 304 * PAT4 Write-Back 305 * PAT5 Write-Through 306 * PAT6 Write-Combine 307 * PAT7 Uncacheable 308 * The only difference from h/w default is entry 6. 309 */ 310 #define PAT_DEFAULT_ATTRIBUTE \ 311 ((uint64_t)MTRR_TYPE_WB | \ 312 ((uint64_t)MTRR_TYPE_WT << 8) | \ 313 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 314 ((uint64_t)MTRR_TYPE_UC << 24) | \ 315 ((uint64_t)MTRR_TYPE_WB << 32) | \ 316 ((uint64_t)MTRR_TYPE_WT << 40) | \ 317 ((uint64_t)MTRR_TYPE_WC << 48) | \ 318 ((uint64_t)MTRR_TYPE_UC << 56)) 319 320 #define X86FSET_LARGEPAGE 0 321 #define X86FSET_TSC 1 322 #define X86FSET_MSR 2 323 #define X86FSET_MTRR 3 324 #define X86FSET_PGE 4 325 #define X86FSET_DE 5 326 #define X86FSET_CMOV 6 327 #define X86FSET_MMX 7 328 #define X86FSET_MCA 8 329 #define X86FSET_PAE 9 330 #define X86FSET_CX8 10 331 #define X86FSET_PAT 11 332 #define X86FSET_SEP 12 333 #define X86FSET_SSE 13 334 #define X86FSET_SSE2 14 335 #define X86FSET_HTT 15 336 #define X86FSET_ASYSC 16 337 #define X86FSET_NX 17 338 #define X86FSET_SSE3 18 339 #define X86FSET_CX16 19 340 #define X86FSET_CMP 20 341 #define X86FSET_TSCP 21 342 #define X86FSET_MWAIT 22 343 #define X86FSET_SSE4A 23 344 #define X86FSET_CPUID 24 345 #define X86FSET_SSSE3 25 346 #define X86FSET_SSE4_1 26 347 #define X86FSET_SSE4_2 27 348 #define X86FSET_1GPG 28 349 #define X86FSET_CLFSH 29 350 #define X86FSET_64 30 351 #define X86FSET_AES 31 352 #define X86FSET_PCLMULQDQ 32 353 #define X86FSET_XSAVE 33 354 #define X86FSET_AVX 34 355 #define X86FSET_VMX 35 356 #define X86FSET_SVM 36 357 #define X86FSET_TOPOEXT 37 358 #define X86FSET_F16C 38 359 #define X86FSET_RDRAND 39 360 #define X86FSET_X2APIC 40 361 #define X86FSET_AVX2 41 362 #define X86FSET_BMI1 42 363 #define X86FSET_BMI2 43 364 #define X86FSET_FMA 44 365 #define X86FSET_SMEP 45 366 #define X86FSET_ADX 47 367 #define X86FSET_RDSEED 48 368 369 /* 370 * Intel Deep C-State invariant TSC in leaf 0x80000007. 371 */ 372 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 373 374 /* 375 * Intel Deep C-state always-running local APIC timer 376 */ 377 #define CPUID_CSTATE_ARAT (0x4) 378 379 /* 380 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 381 */ 382 #define CPUID_EPB_SUPPORT (1 << 3) 383 384 /* 385 * Intel TSC deadline timer 386 */ 387 #define CPUID_DEADLINE_TSC (1 << 24) 388 389 /* 390 * x86_type is a legacy concept; this is supplanted 391 * for most purposes by x86_featureset; modern CPUs 392 * should be X86_TYPE_OTHER 393 */ 394 #define X86_TYPE_OTHER 0 395 #define X86_TYPE_486 1 396 #define X86_TYPE_P5 2 397 #define X86_TYPE_P6 3 398 #define X86_TYPE_CYRIX_486 4 399 #define X86_TYPE_CYRIX_6x86L 5 400 #define X86_TYPE_CYRIX_6x86 6 401 #define X86_TYPE_CYRIX_GXm 7 402 #define X86_TYPE_CYRIX_6x86MX 8 403 #define X86_TYPE_CYRIX_MediaGX 9 404 #define X86_TYPE_CYRIX_MII 10 405 #define X86_TYPE_VIA_CYRIX_III 11 406 #define X86_TYPE_P4 12 407 408 /* 409 * x86_vendor allows us to select between 410 * implementation features and helps guide 411 * the interpretation of the cpuid instruction. 412 */ 413 #define X86_VENDOR_Intel 0 414 #define X86_VENDORSTR_Intel "GenuineIntel" 415 416 #define X86_VENDOR_IntelClone 1 417 418 #define X86_VENDOR_AMD 2 419 #define X86_VENDORSTR_AMD "AuthenticAMD" 420 421 #define X86_VENDOR_Cyrix 3 422 #define X86_VENDORSTR_CYRIX "CyrixInstead" 423 424 #define X86_VENDOR_UMC 4 425 #define X86_VENDORSTR_UMC "UMC UMC UMC " 426 427 #define X86_VENDOR_NexGen 5 428 #define X86_VENDORSTR_NexGen "NexGenDriven" 429 430 #define X86_VENDOR_Centaur 6 431 #define X86_VENDORSTR_Centaur "CentaurHauls" 432 433 #define X86_VENDOR_Rise 7 434 #define X86_VENDORSTR_Rise "RiseRiseRise" 435 436 #define X86_VENDOR_SiS 8 437 #define X86_VENDORSTR_SiS "SiS SiS SiS " 438 439 #define X86_VENDOR_TM 9 440 #define X86_VENDORSTR_TM "GenuineTMx86" 441 442 #define X86_VENDOR_NSC 10 443 #define X86_VENDORSTR_NSC "Geode by NSC" 444 445 /* 446 * Vendor string max len + \0 447 */ 448 #define X86_VENDOR_STRLEN 13 449 450 /* 451 * Some vendor/family/model/stepping ranges are commonly grouped under 452 * a single identifying banner by the vendor. The following encode 453 * that "revision" in a uint32_t with the 8 most significant bits 454 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 455 * family, and the remaining 16 typically forming a bitmask of revisions 456 * within that family with more significant bits indicating "later" revisions. 457 */ 458 459 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 460 #define _X86_CHIPREV_VENDOR_SHIFT 24 461 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 462 #define _X86_CHIPREV_FAMILY_SHIFT 16 463 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 464 465 #define _X86_CHIPREV_VENDOR(x) \ 466 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 467 #define _X86_CHIPREV_FAMILY(x) \ 468 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 469 #define _X86_CHIPREV_REV(x) \ 470 ((x) & _X86_CHIPREV_REV_MASK) 471 472 /* True if x matches in vendor and family and if x matches the given rev mask */ 473 #define X86_CHIPREV_MATCH(x, mask) \ 474 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 475 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 476 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 477 478 /* True if x matches in vendor and family, and rev is at least minx */ 479 #define X86_CHIPREV_ATLEAST(x, minx) \ 480 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 481 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 482 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 483 484 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 485 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 486 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 487 488 /* True if x matches in vendor, and family is at least minx */ 489 #define X86_CHIPFAM_ATLEAST(x, minx) \ 490 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 491 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 492 493 /* Revision default */ 494 #define X86_CHIPREV_UNKNOWN 0x0 495 496 /* 497 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 498 * sufficiently different that we will distinguish them; in all other 499 * case we will identify the major revision. 500 */ 501 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 502 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 503 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 504 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 505 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 506 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 507 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 508 509 /* 510 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 511 */ 512 #define X86_CHIPREV_AMD_10_REV_A \ 513 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 514 #define X86_CHIPREV_AMD_10_REV_B \ 515 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 516 #define X86_CHIPREV_AMD_10_REV_C2 \ 517 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 518 #define X86_CHIPREV_AMD_10_REV_C3 \ 519 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 520 #define X86_CHIPREV_AMD_10_REV_D0 \ 521 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 522 #define X86_CHIPREV_AMD_10_REV_D1 \ 523 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 524 #define X86_CHIPREV_AMD_10_REV_E \ 525 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 526 527 /* 528 * Definitions for AMD Family 0x11. 529 */ 530 #define X86_CHIPREV_AMD_11_REV_B \ 531 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 532 533 /* 534 * Definitions for AMD Family 0x12. 535 */ 536 #define X86_CHIPREV_AMD_12_REV_B \ 537 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 538 539 /* 540 * Definitions for AMD Family 0x14. 541 */ 542 #define X86_CHIPREV_AMD_14_REV_B \ 543 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 544 #define X86_CHIPREV_AMD_14_REV_C \ 545 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 546 547 /* 548 * Definitions for AMD Family 0x15 549 */ 550 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 551 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 552 553 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 554 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 555 556 /* 557 * Various socket/package types, extended as the need to distinguish 558 * a new type arises. The top 8 byte identfies the vendor and the 559 * remaining 24 bits describe 24 socket types. 560 */ 561 562 #define _X86_SOCKET_VENDOR_SHIFT 24 563 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 564 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 565 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 566 567 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 568 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 569 570 #define X86_SOCKET_MATCH(s, mask) \ 571 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 572 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 573 574 #define X86_SOCKET_UNKNOWN 0x0 575 /* 576 * AMD socket types 577 */ 578 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 579 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 580 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 581 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 582 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 583 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 584 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 585 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 586 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 587 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 588 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 589 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 590 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 591 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 592 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 593 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 594 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 595 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 596 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 597 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 598 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 599 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 600 601 602 /* 603 * Definitions for Intel processor models. These are all for Family 6 604 * processors. This list and the Atom set below it are not exhuastive. 605 */ 606 #define INTC_MODEL_MEROM 0x0f 607 #define INTC_MODEL_PENRYN 0x17 608 #define INTC_MODEL_DUNNINGTON 0x1d 609 610 #define INTC_MODEL_NEHALEM 0x1e 611 #define INTC_MODEL_NEHALEM2 0x1f 612 #define INTC_MODEL_NEHALEM_EP 0x1a 613 #define INTC_MODEL_NEHALEM_EX 0x2e 614 615 #define INTC_MODEL_WESTMERE 0x25 616 #define INTC_MODEL_WESTMERE_EP 0x2c 617 #define INTC_MODEL_WESTMERE_EX 0x2f 618 619 #define INTC_MODEL_SANDYBRIDGE 0x2a 620 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 621 #define INTC_MODEL_IVYBRIDGE 0x3a 622 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 623 624 #define INTC_MODEL_HASWELL 0x3c 625 #define INTC_MODEL_HASWELL_ULT 0x45 626 #define INTC_MODEL_HASWELL_GT3E 0x46 627 #define INTC_MODEL_HASWELL_XEON 0x3f 628 629 #define INTC_MODEL_BROADWELL 0x3d 630 #define INTC_MODEL_BROADELL_2 0x47 631 #define INTC_MODEL_BROADWELL_XEON 0x4f 632 633 #define INCC_MODEL_SKYLAKE_MOBILE 0x4e 634 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 635 636 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 637 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 638 639 /* 640 * Atom Processors 641 */ 642 #define INTC_MODEL_SILVERTHORNE 0x1c 643 #define INTC_MODEL_LINCROFT 0x26 644 #define INTC_MODEL_PENWELL 0x27 645 #define INTC_MODEL_CLOVERVIEW 0x35 646 #define INTC_MODEL_CEDARVIEW 0x36 647 #define INTC_MODEL_BAY_TRAIL 0x37 648 #define INTC_MODEL_AVATON 0x4d 649 #define INTC_MODEL_AIRMONT 0x4c 650 #define INTC_MODEL_GOLDMONT 0x5c 651 #define INTC_MODEL_DENVERTON 0x5f 652 #define INTC_MODEL_GEMINI_LAKE 0x7a 653 654 /* 655 * xgetbv/xsetbv support 656 */ 657 658 #define XFEATURE_ENABLED_MASK 0x0 659 /* 660 * XFEATURE_ENABLED_MASK values (eax) 661 */ 662 #define XFEATURE_LEGACY_FP 0x1 663 #define XFEATURE_SSE 0x2 664 #define XFEATURE_AVX 0x4 665 #define XFEATURE_MAX XFEATURE_AVX 666 #define XFEATURE_FP_ALL \ 667 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 668 669 #if !defined(_ASM) 670 671 #if defined(_KERNEL) || defined(_KMEMUSER) 672 673 #define NUM_X86_FEATURES 49 674 extern uchar_t x86_featureset[]; 675 676 extern void free_x86_featureset(void *featureset); 677 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 678 extern void add_x86_feature(void *featureset, uint_t feature); 679 extern void remove_x86_feature(void *featureset, uint_t feature); 680 extern boolean_t compare_x86_featureset(void *setA, void *setB); 681 extern void print_x86_featureset(void *featureset); 682 683 684 extern uint_t x86_type; 685 extern uint_t x86_vendor; 686 extern uint_t x86_clflush_size; 687 688 extern uint_t pentiumpro_bug4046376; 689 690 extern const char CyrixInstead[]; 691 692 #endif 693 694 #if defined(_KERNEL) 695 696 /* 697 * This structure is used to pass arguments and get return values back 698 * from the CPUID instruction in __cpuid_insn() routine. 699 */ 700 struct cpuid_regs { 701 uint32_t cp_eax; 702 uint32_t cp_ebx; 703 uint32_t cp_ecx; 704 uint32_t cp_edx; 705 }; 706 707 /* 708 * Utility functions to get/set extended control registers (XCR) 709 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 710 */ 711 extern uint64_t get_xcr(uint_t); 712 extern void set_xcr(uint_t, uint64_t); 713 714 extern uint64_t rdmsr(uint_t); 715 extern void wrmsr(uint_t, const uint64_t); 716 extern uint64_t xrdmsr(uint_t); 717 extern void xwrmsr(uint_t, const uint64_t); 718 extern int checked_rdmsr(uint_t, uint64_t *); 719 extern int checked_wrmsr(uint_t, uint64_t); 720 721 extern void invalidate_cache(void); 722 extern ulong_t getcr4(void); 723 extern void setcr4(ulong_t); 724 725 extern void mtrr_sync(void); 726 727 extern void cpu_fast_syscall_enable(void *); 728 extern void cpu_fast_syscall_disable(void *); 729 730 struct cpu; 731 732 extern int cpuid_checkpass(struct cpu *, int); 733 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 734 extern uint32_t __cpuid_insn(struct cpuid_regs *); 735 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 736 extern int cpuid_getidstr(struct cpu *, char *, size_t); 737 extern const char *cpuid_getvendorstr(struct cpu *); 738 extern uint_t cpuid_getvendor(struct cpu *); 739 extern uint_t cpuid_getfamily(struct cpu *); 740 extern uint_t cpuid_getmodel(struct cpu *); 741 extern uint_t cpuid_getstep(struct cpu *); 742 extern uint_t cpuid_getsig(struct cpu *); 743 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 744 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 745 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 746 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 747 extern int cpuid_get_chipid(struct cpu *); 748 extern id_t cpuid_get_coreid(struct cpu *); 749 extern int cpuid_get_pkgcoreid(struct cpu *); 750 extern int cpuid_get_clogid(struct cpu *); 751 extern int cpuid_get_cacheid(struct cpu *); 752 extern uint32_t cpuid_get_apicid(struct cpu *); 753 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 754 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 755 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 756 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 757 extern int cpuid_is_cmt(struct cpu *); 758 extern int cpuid_syscall32_insn(struct cpu *); 759 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 760 761 extern uint32_t cpuid_getchiprev(struct cpu *); 762 extern const char *cpuid_getchiprevstr(struct cpu *); 763 extern uint32_t cpuid_getsockettype(struct cpu *); 764 extern const char *cpuid_getsocketstr(struct cpu *); 765 766 extern int cpuid_have_cr8access(struct cpu *); 767 768 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 769 770 struct cpuid_info; 771 772 extern void setx86isalist(void); 773 extern void cpuid_alloc_space(struct cpu *); 774 extern void cpuid_free_space(struct cpu *); 775 extern void cpuid_pass1(struct cpu *, uchar_t *); 776 extern void cpuid_pass2(struct cpu *); 777 extern void cpuid_pass3(struct cpu *); 778 extern void cpuid_pass4(struct cpu *, uint_t *); 779 extern void cpuid_set_cpu_properties(void *, processorid_t, 780 struct cpuid_info *); 781 782 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 783 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 784 785 #if !defined(__xpv) 786 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 787 extern void cpuid_mwait_free(struct cpu *); 788 extern int cpuid_deep_cstates_supported(void); 789 extern int cpuid_arat_supported(void); 790 extern int cpuid_iepb_supported(struct cpu *); 791 extern int cpuid_deadline_tsc_supported(void); 792 extern void vmware_port(int, uint32_t *); 793 #endif 794 795 struct cpu_ucode_info; 796 797 extern void ucode_alloc_space(struct cpu *); 798 extern void ucode_free_space(struct cpu *); 799 extern void ucode_check(struct cpu *); 800 extern void ucode_cleanup(); 801 802 #if !defined(__xpv) 803 extern char _tsc_mfence_start; 804 extern char _tsc_mfence_end; 805 extern char _tscp_start; 806 extern char _tscp_end; 807 extern char _no_rdtsc_start; 808 extern char _no_rdtsc_end; 809 extern char _tsc_lfence_start; 810 extern char _tsc_lfence_end; 811 #endif 812 813 #if !defined(__xpv) 814 extern char bcopy_patch_start; 815 extern char bcopy_patch_end; 816 extern char bcopy_ck_size; 817 #endif 818 819 extern void post_startup_cpu_fixups(void); 820 821 extern uint_t workaround_errata(struct cpu *); 822 823 #if defined(OPTERON_ERRATUM_93) 824 extern int opteron_erratum_93; 825 #endif 826 827 #if defined(OPTERON_ERRATUM_91) 828 extern int opteron_erratum_91; 829 #endif 830 831 #if defined(OPTERON_ERRATUM_100) 832 extern int opteron_erratum_100; 833 #endif 834 835 #if defined(OPTERON_ERRATUM_121) 836 extern int opteron_erratum_121; 837 #endif 838 839 #if defined(OPTERON_WORKAROUND_6323525) 840 extern int opteron_workaround_6323525; 841 extern void patch_workaround_6323525(void); 842 #endif 843 844 #if !defined(__xpv) 845 extern void determine_platform(void); 846 #endif 847 extern int get_hwenv(void); 848 extern int is_controldom(void); 849 850 extern void xsave_setup_msr(struct cpu *); 851 852 /* 853 * Hypervisor signatures 854 */ 855 #define HVSIG_XEN_HVM "XenVMMXenVMM" 856 #define HVSIG_VMWARE "VMwareVMware" 857 #define HVSIG_KVM "KVMKVMKVM" 858 #define HVSIG_MICROSOFT "Microsoft Hv" 859 860 /* 861 * Defined hardware environments 862 */ 863 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 864 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 865 866 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 867 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 868 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 869 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 870 871 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT) 872 873 #endif /* _KERNEL */ 874 875 #endif /* !_ASM */ 876 877 /* 878 * VMware hypervisor related defines 879 */ 880 #define VMWARE_HVMAGIC 0x564d5868 881 #define VMWARE_HVPORT 0x5658 882 #define VMWARE_HVCMD_GETVERSION 0x0a 883 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 884 885 #ifdef __cplusplus 886 } 887 #endif 888 889 #endif /* _SYS_X86_ARCHEXT_H */ 890