1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIE_ACPI_H 27 #define _SYS_PCIE_ACPI_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* revision id of _OSC for PCI/PCI-X/PCI-Exp hierarchy */ 34 #define PCIE_OSC_REVISION_ID 1 /* defined in PCI fw ver 3.0 */ 35 36 /* 37 * _OSC method Capabilities buffer bit definitions (from PCI FW 3.0) 38 */ 39 /* first DWORD: status from _OSC invocation (except bit 0) */ 40 #define OSC_STATUS_QUERY_ENABLE 0x1 /* Query Support Flag */ 41 #define OSC_STATUS_FAILED 0x2 /* _OSC failure */ 42 #define OSC_STATUS_INV_UUID 0x4 /* invalid UUID */ 43 #define OSC_STATUS_INV_REVID 0x8 /* invalid revision ID */ 44 #define OSC_STATUS_CAPS_MASKED 0x10 /* capabilities masked */ 45 46 #define OSC_STATUS_ERRORS \ 47 (OSC_STATUS_FAILED | OSC_STATUS_INV_UUID | OSC_STATUS_INV_REVID) 48 49 /* second DWORD: Support Field (set by OS) */ 50 #define OSC_SUPPORT_EXT_PCI_CFG 0x1 /* Extended PCI Config Ops supported */ 51 #define OSC_SUPPORT_ACT_PM 0x2 /* Active State PM supported */ 52 #define OSC_SUPPORT_CLK_PM_CAP 0x4 /* Clock PM Capability supported */ 53 #define OSC_SUPPORT_PCI_SEGS 0x8 /* PCI Segment Groups supported */ 54 #define OSC_SUPPORT_MSI 0x10 /* MSI supported */ 55 56 /* third DWORD: Control Field (set by OS/BIOS) */ 57 #define OSC_CONTROL_PCIE_NAT_HP 0x1 /* PCI Exp Native Hot Plug control */ 58 #define OSC_CONTROL_SHPC_NAT_HP 0x2 /* SHPC Native Hot Plug control */ 59 #define OSC_CONTROL_PCIE_NAT_PM 0x4 /* PCI Exp Native Power Mgmt. control */ 60 #define OSC_CONTROL_PCIE_ADV_ERR 0x8 /* PCIE Advanced Err. rep. control */ 61 #define OSC_CONTROL_PCIE_CAPS 0x10 /* PCIE Caps Structure control */ 62 63 #define OSC_CONTROL_FIELD_INIT \ 64 (OSC_CONTROL_PCIE_CAPS | OSC_CONTROL_PCIE_ADV_ERR) 65 66 #define OSC_SUPPORT_FIELD_INIT \ 67 (OSC_SUPPORT_EXT_PCI_CFG | \ 68 OSC_SUPPORT_ACT_PM | OSC_SUPPORT_CLK_PM_CAP | \ 69 OSC_SUPPORT_MSI | OSC_SUPPORT_PCI_SEGS) 70 71 typedef struct pcie_x86_priv { 72 /* _OSC related */ 73 boolean_t bus_osc; /* Has _OSC method been called */ 74 boolean_t bus_osc_hp; /* Was native HP control granted */ 75 boolean_t bus_osc_aer; /* Was AER control granted */ 76 } pcie_x86_priv_t; 77 78 extern int pcie_acpi_osc(dev_info_t *dip, uint32_t *osc_flags); 79 extern boolean_t pcie_is_osc(dev_info_t *dip); 80 81 #ifdef __cplusplus 82 } 83 #endif 84 85 #endif /* _SYS_PCIE_ACPI_H */ 86