1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MCA_AMD_H 28 #define _SYS_MCA_AMD_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * Constants the Memory Check Architecture as implemented on AMD CPUs. 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #define AMD_MSR_MCG_CAP 0x179 41 #define AMD_MSR_MCG_STATUS 0x17a 42 #define AMD_MSR_MCG_CTL 0x17b 43 44 #define AMD_MCA_BANK_DC 0 /* Data Cache */ 45 #define AMD_MCA_BANK_IC 1 /* Instruction Cache */ 46 #define AMD_MCA_BANK_BU 2 /* Bus Unit */ 47 #define AMD_MCA_BANK_LS 3 /* Load/Store Unit */ 48 #define AMD_MCA_BANK_NB 4 /* Northbridge */ 49 #define AMD_MCA_BANK_COUNT 5 50 51 #define AMD_MSR_DC_CTL 0x400 52 #define AMD_MSR_DC_MASK 0xc0010044 53 #define AMD_MSR_DC_STATUS 0x401 54 #define AMD_MSR_DC_ADDR 0x402 55 56 #define AMD_MSR_IC_CTL 0x404 57 #define AMD_MSR_IC_MASK 0xc0010045 58 #define AMD_MSR_IC_STATUS 0x405 59 #define AMD_MSR_IC_ADDR 0x406 60 61 #define AMD_MSR_BU_CTL 0x408 62 #define AMD_MSR_BU_MASK 0xc0010046 63 #define AMD_MSR_BU_STATUS 0x409 64 #define AMD_MSR_BU_ADDR 0x40a 65 66 #define AMD_MSR_LS_CTL 0x40c 67 #define AMD_MSR_LS_MASK 0xc0010047 68 #define AMD_MSR_LS_STATUS 0x40d 69 #define AMD_MSR_LS_ADDR 0x40e 70 71 #define AMD_MSR_NB_CTL 0x410 72 #define AMD_MSR_NB_MASK 0xc0010048 73 #define AMD_MSR_NB_STATUS 0x411 74 #define AMD_MSR_NB_ADDR 0x412 75 76 #define AMD_MCG_EN_DC 0x01 77 #define AMD_MCG_EN_IC 0x02 78 #define AMD_MCG_EN_BU 0x04 79 #define AMD_MCG_EN_LS 0x08 80 #define AMD_MCG_EN_NB 0x10 81 #define AMD_MCG_EN_ALL \ 82 (AMD_MCG_EN_DC | AMD_MCG_EN_IC | AMD_MCG_EN_BU | AMD_MCG_EN_LS | \ 83 AMD_MCG_EN_NB) 84 85 /* 86 * Data Cache (DC) bank error-detection enabling bits and CTL register 87 * initializer value. 88 */ 89 90 #define AMD_DC_EN_ECCI 0x00000001ULL 91 #define AMD_DC_EN_ECCM 0x00000002ULL 92 #define AMD_DC_EN_DECC 0x00000004ULL 93 #define AMD_DC_EN_DMTP 0x00000008ULL 94 #define AMD_DC_EN_DSTP 0x00000010ULL 95 #define AMD_DC_EN_L1TP 0x00000020ULL 96 #define AMD_DC_EN_L2TP 0x00000040ULL 97 98 #define AMD_DC_CTL_INIT \ 99 (AMD_DC_EN_ECCI | AMD_DC_EN_ECCM | AMD_DC_EN_DECC | AMD_DC_EN_DMTP | \ 100 AMD_DC_EN_DSTP | AMD_DC_EN_L1TP | AMD_DC_EN_L2TP) 101 102 /* 103 * Instruction Cache (IC) bank error-detection enabling bits and CTL register 104 * initializer value. 105 * 106 * The Northbridge will handle Read Data errors. Our initializer will enable 107 * all but the RDDE detector. 108 */ 109 110 #define AMD_IC_EN_ECCI 0x00000001ULL 111 #define AMD_IC_EN_ECCM 0x00000002ULL 112 #define AMD_IC_EN_IDP 0x00000004ULL 113 #define AMD_IC_EN_IMTP 0x00000008ULL 114 #define AMD_IC_EN_ISTP 0x00000010ULL 115 #define AMD_IC_EN_L1TP 0x00000020ULL 116 #define AMD_IC_EN_L2TP 0x00000040ULL 117 #define AMD_IC_EN_RDDE 0x00000200ULL 118 119 #define AMD_IC_CTL_INIT \ 120 (AMD_IC_EN_ECCI | AMD_IC_EN_ECCM | AMD_IC_EN_IDP | AMD_IC_EN_IMTP | \ 121 AMD_IC_EN_ISTP | AMD_IC_EN_L1TP | AMD_IC_EN_L2TP) 122 123 /* 124 * Bus Unit (BU) bank error-detection enabling bits and CTL register 125 * initializer value. 126 * 127 * The Northbridge will handle Read Data errors. Our initializer will enable 128 * all but the S_RDE_* detectors. 129 */ 130 131 #define AMD_BU_EN_S_RDE_HP 0x00000001ULL 132 #define AMD_BU_EN_S_RDE_TLB 0x00000002ULL 133 #define AMD_BU_EN_S_RDE_ALL 0x00000004ULL 134 #define AMD_BU_EN_S_ECC1_TLB 0x00000008ULL 135 #define AMD_BU_EN_S_ECC1_HP 0x00000010ULL 136 #define AMD_BU_EN_S_ECCM_TLB 0x00000020ULL 137 #define AMD_BU_EN_S_ECCM_HP 0x00000040ULL 138 #define AMD_BU_EN_L2T_PAR_ICDC 0x00000080ULL 139 #define AMD_BU_EN_L2T_PAR_TLB 0x00000100ULL 140 #define AMD_BU_EN_L2T_PAR_SNP 0x00000200ULL 141 #define AMD_BU_EN_L2T_PAR_CPB 0x00000400ULL 142 #define AMD_BU_EN_L2T_PAR_SCR 0x00000800ULL 143 #define AMD_BU_EN_L2D_ECC1_TLB 0x00001000ULL 144 #define AMD_BU_EN_L2D_ECC1_SNP 0x00002000ULL 145 #define AMD_BU_EN_L2D_ECC1_CPB 0x00004000ULL 146 #define AMD_BU_EN_L2D_ECCM_TLB 0x00008000ULL 147 #define AMD_BU_EN_L2D_ECCM_SNP 0x00010000ULL 148 #define AMD_BU_EN_L2D_ECCM_CPB 0x00020000ULL 149 #define AMD_BU_EN_L2T_ECC1_SCR 0x00040000ULL 150 #define AMD_BU_EN_L2T_ECCM_SCR 0x00080000ULL 151 152 #define AMD_BU_CTL_INIT \ 153 (AMD_BU_EN_S_ECC1_TLB | AMD_BU_EN_S_ECC1_HP | \ 154 AMD_BU_EN_S_ECCM_TLB | AMD_BU_EN_S_ECCM_HP | \ 155 AMD_BU_EN_L2T_PAR_ICDC | AMD_BU_EN_L2T_PAR_TLB | \ 156 AMD_BU_EN_L2T_PAR_SNP | AMD_BU_EN_L2T_PAR_CPB | \ 157 AMD_BU_EN_L2T_PAR_SCR | AMD_BU_EN_L2D_ECC1_TLB | \ 158 AMD_BU_EN_L2D_ECC1_SNP | AMD_BU_EN_L2D_ECC1_CPB | \ 159 AMD_BU_EN_L2D_ECCM_TLB | AMD_BU_EN_L2D_ECCM_SNP | \ 160 AMD_BU_EN_L2D_ECCM_CPB | AMD_BU_EN_L2T_ECC1_SCR | \ 161 AMD_BU_EN_L2T_ECCM_SCR) 162 163 /* 164 * Load/Store (LS) bank error-detection enabling bits and CTL register 165 * initializer value. 166 * 167 * The Northbridge will handle Read Data errors. That's the only type of 168 * error the LS unit can detect at present, so we won't be enabling any 169 * LS detectors. 170 */ 171 172 #define AMD_LS_EN_S_RDE_S 0x00000001ULL 173 #define AMD_LS_EN_S_RDE_L 0x00000002ULL 174 175 #define AMD_LS_CTL_INIT 0ULL 176 177 /* 178 * The Northbridge (NB) is configured using both the standard MCA CTL register 179 * and a NB-specific configuration register (NB CFG). The AMD_NB_EN_* macros 180 * are the detector enabling bits for the NB MCA CTL register. The 181 * AMD_NB_CFG_* bits are for the NB CFG register. 182 * 183 * The CTL register can be initialized statically, but portions of the NB CFG 184 * register must be initialized based on the current machine's configuration. 185 * 186 * The MCA NB Control Register maps to MC4_CTL[31:0]. 187 * 188 */ 189 #define AMD_NB_EN_CORRECC 0x00000001 190 #define AMD_NB_EN_UNCORRECC 0x00000002 191 #define AMD_NB_EN_CRCERR0 0x00000004 192 #define AMD_NB_EN_CRCERR1 0x00000008 193 #define AMD_NB_EN_CRCERR2 0x00000010 194 #define AMD_NB_EN_SYNCPKT0 0x00000020 195 #define AMD_NB_EN_SYNCPKT1 0x00000040 196 #define AMD_NB_EN_SYNCPKT2 0x00000080 197 #define AMD_NB_EN_MSTRABRT 0x00000100 198 #define AMD_NB_EN_TGTABRT 0x00000200 199 #define AMD_NB_EN_GARTTBLWK 0x00000400 200 #define AMD_NB_EN_ATOMICRMW 0x00000800 201 #define AMD_NB_EN_WCHDOGTMR 0x00001000 202 203 #define AMD_NB_CTL_INIT /* All but GARTTBLWK */ \ 204 (AMD_NB_EN_CORRECC | AMD_NB_EN_UNCORRECC | \ 205 AMD_NB_EN_CRCERR0 | AMD_NB_EN_CRCERR1 | AMD_NB_EN_CRCERR2 | \ 206 AMD_NB_EN_SYNCPKT0 | AMD_NB_EN_SYNCPKT1 | AMD_NB_EN_SYNCPKT2 | \ 207 AMD_NB_EN_MSTRABRT | AMD_NB_EN_TGTABRT | \ 208 AMD_NB_EN_ATOMICRMW | AMD_NB_EN_WCHDOGTMR) 209 210 #define AMD_NB_CFG_CPUECCERREN 0x00000001 211 #define AMD_NB_CFG_CPURDDATERREN 0x00000002 212 #define AMD_NB_CFG_SYNCONUCECCEN 0x00000004 213 #define AMD_NB_CFG_SYNCPKTGENDIS 0x00000008 214 #define AMD_NB_CFG_SYNCPKTPROPDIS 0x00000010 215 #define AMD_NB_CFG_IOMSTABORTDIS 0x00000020 216 #define AMD_NB_CFG_CPUERRDIS 0x00000040 217 #define AMD_NB_CFG_IOERRDIS 0x00000080 218 #define AMD_NB_CFG_WDOGTMRDIS 0x00000100 219 #define AMD_NB_CFG_SYNCONWDOGEN 0x00100000 220 #define AMD_NB_CFG_SYNCONANYERREN 0x00200000 221 #define AMD_NB_CFG_ECCEN 0x00400000 222 #define AMD_NB_CFG_CHIPKILLECCEN 0x00800000 223 #define AMD_NB_CFG_IORDDATERREN 0x01000000 224 #define AMD_NB_CFG_DISPCICFGCPUERRRSP 0x02000000 225 #define AMD_NB_CFG_NBMCATOMSTCPUEN 0x08000000 226 227 #define AMD_NB_CFG_WDOGTMRCNTSEL_4095 0x00000000 228 #define AMD_NB_CFG_WDOGTMRCNTSEL_2047 0x00000200 229 #define AMD_NB_CFG_WDOGTMRCNTSEL_1023 0x00000400 230 #define AMD_NB_CFG_WDOGTMRCNTSEL_511 0x00000600 231 #define AMD_NB_CFG_WDOGTMRCNTSEL_255 0x00000800 232 #define AMD_NB_CFG_WDOGTMRCNTSEL_127 0x00000a00 233 #define AMD_NB_CFG_WDOGTMRCNTSEL_63 0x00000c00 234 #define AMD_NB_CFG_WDOGTMRCNTSEL_31 0x00000e00 235 #define AMD_NB_CFG_WDOGTMRCNTSEL_MASK 0x00000e00 236 #define AMD_NB_CFG_WDOGTMRCNTSEL_SHIFT 9 237 238 #define AMD_NB_CFG_WDOGTMRBASESEL_1MS 0x00000000 239 #define AMD_NB_CFG_WDOGTMRBASESEL_1US 0x00001000 240 #define AMD_NB_CFG_WDOGTMRBASESEL_5NS 0x00002000 241 #define AMD_NB_CFG_WDOGTMRBASESEL_MASK 0x00003000 242 #define AMD_NB_CFG_WDOGTMRBASESEL_SHIFT 12 243 244 #define AMD_NB_CFG_LDTLINKSEL_MASK 0x0000c000 245 #define AMD_NB_CFG_LDTLINKSEL_SHIFT 14 246 247 #define AMD_NB_CFG_GENCRCERRBYTE0 0x00010000 248 #define AMD_NB_CFG_GENCRCERRBYTE1 0x00020000 249 250 /* Generic bank status register bits */ 251 #define AMD_BANK_STAT_VALID 0x8000000000000000ULL 252 #define AMD_BANK_STAT_OVER 0x4000000000000000ULL 253 #define AMD_BANK_STAT_UC 0x2000000000000000ULL 254 #define AMD_BANK_STAT_EN 0x1000000000000000ULL 255 #define AMD_BANK_STAT_MISCV 0x0800000000000000ULL 256 #define AMD_BANK_STAT_ADDRV 0x0400000000000000ULL 257 #define AMD_BANK_STAT_PCC 0x0200000000000000ULL 258 259 #define AMD_BANK_STAT_CECC 0x0000400000000000ULL 260 #define AMD_BANK_STAT_UECC 0x0000200000000000ULL 261 #define AMD_BANK_STAT_SCRUB 0x0000010000000000ULL 262 263 /* syndrome[7:0] */ 264 #define AMD_BANK_STAT_SYND_MASK 0x007f800000000000ULL 265 #define AMD_BANK_STAT_SYND_SHIFT 47 266 267 #define AMD_BANK_SYND(stat) \ 268 (((stat) & AMD_BANK_STAT_SYND_MASK) >> AMD_BANK_STAT_SYND_SHIFT) 269 #define AMD_BANK_MKSYND(synd) \ 270 (((uint64_t)(synd) << AMD_BANK_STAT_SYND_SHIFT) & \ 271 AMD_BANK_STAT_SYND_MASK) 272 273 /* northbridge (NB) status registers */ 274 275 #define AMD_NB_FUNC 3 276 #define AMD_NB_REG_CFG 0x44 277 #define AMD_NB_REG_STLO 0x48 /* alias: NB_STATUS[0:31] */ 278 #define AMD_NB_REG_STHI 0x4c /* alias: NB_STATUS[32:63] */ 279 #define AMD_NB_REG_ADDRLO 0x50 /* alias: NB_ADDR[0:31] */ 280 #define AMD_NB_REG_ADDRHI 0x54 /* alias: NB_ADDR[32:63] */ 281 282 #define AMD_NB_REG_SCRUBCTL 0x58 283 #define AMD_NB_REG_SCRUBADDR_LO 0x5c 284 #define AMD_NB_REG_SCRUBADDR_HI 0x60 285 286 #define AMD_NB_STAT_LDTLINK_MASK 0x0000007000000000 287 #define AMD_NB_STAT_LDTLINK_SHIFT 4 288 #define AMD_NB_STAT_ERRCPU1 0x0000000200000000 289 #define AMD_NB_STAT_ERRCPU0 0x0000000100000000 290 #define AMD_NB_STAT_CKSYND_MASK 0x00000000ff000000 /* syndrome[15:8] */ 291 #define AMD_NB_STAT_CKSYND_SHIFT (24 - 8) /* shift [31:24] to [15:8] */ 292 293 #define AMD_NB_STAT_CKSYND(stat) \ 294 ((((stat) & AMD_NB_STAT_CKSYND_MASK) >> AMD_NB_STAT_CKSYND_SHIFT) | \ 295 AMD_BANK_SYND((stat))) 296 297 #define AMD_NB_STAT_MKCKSYND(synd) \ 298 ((((uint64_t)(synd) << AMD_NB_STAT_CKSYND_SHIFT) & \ 299 AMD_NB_STAT_CKSYND_MASK) | AMD_BANK_MKSYND(synd)) 300 301 #define AMD_ERRCODE_MASK 0x000000000000ffff 302 #define AMD_ERREXT_MASK 0x00000000000f0000 303 #define AMD_ERREXT_SHIFT 16 304 305 #define AMD_ERRCODE_TT_MASK 0x000c 306 #define AMD_ERRCODE_TT_SHIFT 2 307 #define AMD_ERRCODE_TT_INSTR 0x0 308 #define AMD_ERRCODE_TT_DATA 0x1 309 #define AMD_ERRCODE_TT_GEN 0x2 310 311 #define AMD_ERRCODE_LL_MASK 0x0003 312 #define AMD_ERRCODE_LL_L0 0x0 313 #define AMD_ERRCODE_LL_L1 0x1 314 #define AMD_ERRCODE_LL_L2 0x2 315 #define AMD_ERRCODE_LL_LG 0x3 316 317 #define AMD_ERRCODE_R4_MASK 0x00f0 318 #define AMD_ERRCODE_R4_SHIFT 4 319 #define AMD_ERRCODE_R4_GEN 0x0 320 #define AMD_ERRCODE_R4_RD 0x1 321 #define AMD_ERRCODE_R4_WR 0x2 322 #define AMD_ERRCODE_R4_DRD 0x3 323 #define AMD_ERRCODE_R4_DWR 0x4 324 #define AMD_ERRCODE_R4_IRD 0x5 325 #define AMD_ERRCODE_R4_PREFETCH 0x6 326 #define AMD_ERRCODE_R4_EVICT 0x7 327 #define AMD_ERRCODE_R4_SNOOP 0x8 328 329 #define AMD_ERRCODE_PP_MASK 0x0600 330 #define AMD_ERRCODE_PP_SHIFT 9 331 #define AMD_ERRCODE_PP_SRC 0x0 332 #define AMD_ERRCODE_PP_RSP 0x1 333 #define AMD_ERRCODE_PP_OBS 0x2 334 #define AMD_ERRCODE_PP_GEN 0x3 335 336 #define AMD_ERRCODE_T_MASK 0x0100 337 #define AMD_ERRCODE_T_SHIFT 8 338 #define AMD_ERRCODE_T_NONE 0x0 339 #define AMD_ERRCODE_T_TIMEOUT 0x1 340 341 #define AMD_ERRCODE_II_MASK 0x000c 342 #define AMD_ERRCODE_II_SHIFT 2 343 #define AMD_ERRCODE_II_MEM 0x0 344 #define AMD_ERRCODE_II_IO 0x2 345 #define AMD_ERRCODE_II_GEN 0x3 346 347 #define AMD_ERRCODE_TLB_BIT 4 348 #define AMD_ERRCODE_MEM_BIT 8 349 #define AMD_ERRCODE_BUS_BIT 11 350 351 #define AMD_ERRCODE_TLB_MASK 0xfff0 352 #define AMD_ERRCODE_TLB_VAL 0x0010 353 #define AMD_ERRCODE_MEM_MASK 0xff00 354 #define AMD_ERRCODE_MEM_VAL 0x0100 355 #define AMD_ERRCODE_BUS_MASK 0xf800 356 #define AMD_ERRCODE_BUS_VAL 0x0800 357 358 #define AMD_ERRCODE_MKTLB(tt, ll) \ 359 (AMD_ERRCODE_TLB_VAL | \ 360 (((tt) << AMD_ERRCODE_TT_SHIFT) & AMD_ERRCODE_TT_MASK) | \ 361 ((ll) & AMD_ERRCODE_LL_MASK)) 362 #define AMD_ERRCODE_ISTLB(code) \ 363 (((code) & AMD_ERRCODE_TLB_MASK) == AMD_ERRCODE_TLB_VAL) 364 365 #define AMD_ERRCODE_MKMEM(r4, tt, ll) \ 366 (AMD_ERRCODE_MEM_VAL | \ 367 (((r4) << AMD_ERRCODE_R4_SHIFT) & AMD_ERRCODE_R4_MASK) | \ 368 (((tt) << AMD_ERRCODE_TT_SHIFT) & AMD_ERRCODE_TT_MASK) | \ 369 ((ll) & AMD_ERRCODE_LL_MASK)) 370 #define AMD_ERRCODE_ISMEM(code) \ 371 (((code) & AMD_ERRCODE_MEM_MASK) == AMD_ERRCODE_MEM_VAL) 372 373 #define AMD_ERRCODE_MKBUS(pp, t, r4, ii, ll) \ 374 (AMD_ERRCODE_BUS_VAL | \ 375 (((pp) << AMD_ERRCODE_PP_SHIFT) & AMD_ERRCODE_PP_MASK) | \ 376 (((t) << AMD_ERRCODE_T_SHIFT) & AMD_ERRCODE_T_MASK) | \ 377 (((r4) << AMD_ERRCODE_R4_SHIFT) & AMD_ERRCODE_R4_MASK) | \ 378 (((ii) << AMD_ERRCODE_II_SHIFT) & AMD_ERRCODE_II_MASK) | \ 379 ((ll) & AMD_ERRCODE_LL_MASK)) 380 #define AMD_ERRCODE_ISBUS(code) \ 381 (((code) & AMD_ERRCODE_BUS_MASK) == AMD_ERRCODE_BUS_VAL) 382 383 #define AMD_NB_ADDRLO_MASK 0xfffffff8 384 #define AMD_NB_ADDRHI_MASK 0x000000ff 385 386 #define AMD_SYNDTYPE_ECC 0 387 #define AMD_SYNDTYPE_CHIPKILL 1 388 389 #define AMD_NB_SCRUBCTL_DRAM_MASK 0x0000001f 390 #define AMD_NB_SCRUBCTL_DRAM_SHIFT 0 391 #define AMD_NB_SCRUBCTL_L2_MASK 0x00001f00 392 #define AMD_NB_SCRUBCTL_L2_SHIFT 8 393 #define AMD_NB_SCRUBCTL_DC_MASK 0x001f0000 394 #define AMD_NB_SCRUBCTL_DC_SHIFT 16 395 396 #define AMD_NB_SCRUBCTL_RATE_NONE 0 397 #define AMD_NB_SCRUBCTL_RATE_MAX 0x16 398 399 #define AMD_NB_SCRUBADDR_LO_MASK 0xffffffc0 400 #define AMD_NB_SCRUBADDR_LO_SCRUBREDIREN 0x1 401 #define AMD_NB_SCRUBADDR_HI_MASK 0x000000ff 402 403 #define AMD_NB_SCRUBADDR_MKLO(addr) \ 404 ((addr) & AMD_NB_SCRUBADDR_LO_MASK) 405 406 #define AMD_NB_SCRUBADDR_MKHI(addr) \ 407 (((addr) >> 32) & AMD_NB_SCRUBADDR_HI_MASK) 408 409 #define AMD_NB_MKSCRUBCTL(dc, l2, dr) ( \ 410 (((dc) << AMD_NB_SCRUBCTL_DC_SHIFT) & AMD_NB_SCRUBCTL_DC_MASK) | \ 411 (((l2) << AMD_NB_SCRUBCTL_L2_SHIFT) & AMD_NB_SCRUBCTL_L2_MASK) | \ 412 (((dr) << AMD_NB_SCRUBCTL_DRAM_SHIFT) & AMD_NB_SCRUBCTL_DRAM_MASK)) 413 414 #ifdef __cplusplus 415 } 416 #endif 417 418 #endif /* _SYS_MCA_AMD_H */ 419