1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _PCIEX_PCI_NVIDIA_H 28 #define _PCIEX_PCI_NVIDIA_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * PCI Configuration (Nvidia, PCIe) related library functions 38 */ 39 boolean_t check_if_device_is_pciex(dev_info_t *, uchar_t, uchar_t, 40 uchar_t, ushort_t *, ushort_t *); 41 boolean_t create_pcie_root_bus(uchar_t, dev_info_t *); 42 void add_nvidia_isa_bridge_props(dev_info_t *, uchar_t, uchar_t, 43 uchar_t); 44 45 /* Generic Nvidia chipset IDs and defines */ 46 #define NVIDIA_VENDOR_ID 0x10de /* Nvidia Vendor Id */ 47 #define NVIDIA_INTR_BCR_OFF 0x3C /* NV_XVR_INTR_BCR */ 48 #define NVIDIA_INTR_BCR_SERR_FORWARD_BIT 0x02 /* SERR_FORWARD bit */ 49 50 /* CK8-04 PCIe RC and LPC-PCI Bridge device IDs */ 51 #define NVIDIA_CK804_DEVICE_ID 0x5d /* ck8-04 dev id */ 52 #define NVIDIA_CK804_DEFAULT_ISA_BRIDGE_DEVID 0x50 /* LPC Default Bridge */ 53 #define NVIDIA_CK804_PRO_ISA_BRIDGE_DEVID 0x51 /* LPC Bridge */ 54 #define NVIDIA_CK804_SLAVE_ISA_BRIDGE_DEVID 0xd3 /* Slave LPC Bridge */ 55 #define NVIDIA_CK804_AER_VALID_REVID 0xa3 /* RID w/ AER enabled */ 56 57 #define NVIDIA_CK804_LPC2PCI_DEVICE_ID(did) \ 58 (((did) == NVIDIA_CK804_DEFAULT_ISA_BRIDGE_DEVID) || \ 59 ((did) == NVIDIA_CK804_PRO_ISA_BRIDGE_DEVID) || \ 60 ((did) == NVIDIA_CK804_SLAVE_ISA_BRIDGE_DEVID)) 61 62 /* 63 * Only for Nvidia's CrushK 8-04 chipsets: 64 * To enable hotplug; we need to map in two I/O BARs 65 * from ISA bridge's config space 66 */ 67 #define NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF 0x64 /* System Control BAR */ 68 #define NVIDIA_CK804_ISA_ANALOG_BAR_OFF 0x68 /* Analog BAR */ 69 70 /* NV_XVR_VEND_CYA1 related defines */ 71 #define NVIDIA_CK804_VEND_CYA1_OFF 0xf40 /* NV_XVR_VEND_CYA1 */ 72 #define NVIDIA_CK804_VEND_CYA1_ERPT_VAL 0x2000 /* enable CYA1 ERPT */ 73 #define NVIDIA_CK804_VEND_CYA1_ERPT_MASK 0xdfff /* CYA1 ERPT mask */ 74 75 /* 76 * C51 related defines 77 */ 78 79 /* C51 PCIe Root Complex Device ID defines */ 80 #define NVIDIA_C51_DEVICE_ID_XVR16 0x2fb 81 #define NVIDIA_C51_DEVICE_ID_XVR1_0 0x2fc 82 #define NVIDIA_C51_DEVICE_ID_XVR1_1 0x2fd 83 84 #define NVIDIA_C51_DEVICE_ID(did) \ 85 (((did) == NVIDIA_C51_DEVICE_ID_XVR16) || \ 86 ((did) == NVIDIA_C51_DEVICE_ID_XVR1_0) || \ 87 ((did) == NVIDIA_C51_DEVICE_ID_XVR1_1)) 88 89 /* 90 * MCP55 related defines 91 */ 92 93 /* MCP55 PCIe Root Complex Device ID defines */ 94 #define NVIDIA_MCP55_DEVICE_ID_XVR4 0x374 95 #define NVIDIA_MCP55_DEVICE_ID_XVR8 0x375 96 #define NVIDIA_MCP55_DEVICE_ID_XVR8_VC1 0x376 97 #define NVIDIA_MCP55_DEVICE_ID_XVR16 0x377 98 #define NVIDIA_MCP55_DEVICE_ID_XVR4_VC1 0x378 99 100 #define NVIDIA_MCP55_DEVICE_ID(did) \ 101 (((did) == NVIDIA_MCP55_DEVICE_ID_XVR4) || \ 102 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR8) || \ 103 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR16) || \ 104 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR4_VC1) || \ 105 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR8_VC1)) 106 107 /* MCP55 LPC-PCI Bridge Device ID defines */ 108 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP0 0x360 109 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP1 0x361 110 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP2 0x362 111 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP3 0x363 112 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP4 0x364 113 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP5 0x365 114 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP6 0x366 115 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP7 0x367 116 117 #define NVIDIA_MCP55_LPC2PCI_DEVICE_ID(did) \ 118 (((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP0) || \ 119 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP1) || \ 120 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP2) || \ 121 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP3) || \ 122 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP4) || \ 123 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP5) || \ 124 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP6) || \ 125 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP7)) 126 127 /* 128 * MCP61 related defines 129 */ 130 131 /* MCP61 PCIe Root Complex Device ID defines */ 132 #define NVIDIA_MCP61_DEVICE_ID_XVR4 0x3e8 133 #define NVIDIA_MCP61_DEVICE_ID_XVR8 0x3e9 134 135 #define NVIDIA_MCP61_DEVICE_ID(did) \ 136 (((did) == NVIDIA_MCP61_DEVICE_ID_XVR4) || \ 137 ((did) == NVIDIA_MCP61_DEVICE_ID_XVR8)) 138 139 /* 140 * MCP65 related defines 141 */ 142 143 /* MCP65 PCIe Root Complex Device ID defines */ 144 #define NVIDIA_MCP65_DEVICE_ID_XVR4 0x458 145 #define NVIDIA_MCP65_DEVICE_ID_XVR8 0x459 146 #define NVIDIA_MCP65_DEVICE_ID_XVR16 0x45a 147 148 #define NVIDIA_MCP65_DEVICE_ID(did) \ 149 (((did) == NVIDIA_MCP65_DEVICE_ID_XVR4) || \ 150 ((did) == NVIDIA_MCP65_DEVICE_ID_XVR8) || \ 151 ((did) == NVIDIA_MCP65_DEVICE_ID_XVR16)) 152 153 /* 154 * Check if the given device is a Nvidia's LPC bridge 155 */ 156 #define NVIDIA_IS_LPC_BRIDGE(vid, did) \ 157 (((vid) == NVIDIA_VENDOR_ID) && \ 158 (NVIDIA_CK804_LPC2PCI_DEVICE_ID(did) || \ 159 NVIDIA_MCP55_LPC2PCI_DEVICE_ID(did))) 160 161 /* Check for PCIe RC Device ID */ 162 #define NVIDIA_PCIE_RC_DEV_ID(did) \ 163 (((did) == NVIDIA_CK804_DEVICE_ID) || \ 164 NVIDIA_C51_DEVICE_ID(did) || \ 165 NVIDIA_MCP55_DEVICE_ID(did) || \ 166 NVIDIA_MCP61_DEVICE_ID(did) || \ 167 NVIDIA_MCP65_DEVICE_ID(did)) 168 169 /* 170 * Defines to figure out what kind of hotplug is supported 171 */ 172 #define INBAND_HPC_NONE 0x0 /* No hotplug supported */ 173 #define INBAND_HPC_PCIE 0x1 /* PCIe based hotplug supported */ 174 #define INBAND_HPC_SHPC 0x2 /* SHPC based hotplug supported */ 175 176 #ifdef __cplusplus 177 } 178 #endif 179 180 #endif /* _PCIEX_PCI_NVIDIA_H */ 181