xref: /titanic_51/usr/src/uts/intel/io/pci/pci_pci.c (revision 837c1ac4e72b7d86278cca88b1075af557f7d161)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*
27  * PCI to PCI bus bridge nexus driver
28  */
29 
30 #include <sys/conf.h>
31 #include <sys/kmem.h>
32 #include <sys/debug.h>
33 #include <sys/modctl.h>
34 #include <sys/autoconf.h>
35 #include <sys/ddi_impldefs.h>
36 #include <sys/pci.h>
37 #include <sys/pci_impl.h>
38 #include <sys/pcie_impl.h>
39 #include <sys/ddi.h>
40 #include <sys/sunddi.h>
41 #include <sys/sunndi.h>
42 #include <sys/ddifm.h>
43 #include <sys/ndifm.h>
44 #include <sys/fm/protocol.h>
45 #include <sys/hotplug/pci/pcie_hp.h>
46 #include <sys/hotplug/pci/pcihp.h>
47 #include <sys/pci_intr_lib.h>
48 #include <sys/psm.h>
49 #include <sys/pci_cap.h>
50 
51 /*
52  * The variable controls the default setting of the command register
53  * for pci devices.  See ppb_initchild() for details.
54  */
55 static ushort_t ppb_command_default = PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO;
56 
57 
58 static int	ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *,
59 		    off_t, off_t, caddr_t *);
60 static int	ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t,
61 		    void *, void *);
62 static int	ppb_fm_init(dev_info_t *, dev_info_t *, int,
63 		    ddi_iblock_cookie_t *);
64 static int	ppb_fm_callback(dev_info_t *, ddi_fm_error_t *, const void *);
65 static int	ppb_intr_ops(dev_info_t *, dev_info_t *, ddi_intr_op_t,
66 		    ddi_intr_handle_impl_t *, void *);
67 
68 /*
69  * ppb_support_msi: Flag that controls MSI support across P2P Bridges.
70  * By default, MSI is not supported except for special cases like HT
71  * bridges/tunnels that have HT MSI mapping enabled.
72  *
73  * However, MSI support behavior can be patched on a system by changing
74  * the value of this flag as shown below:-
75  *	 0 = default value, MSI is allowed by this driver for special cases
76  *	 1 = MSI supported without any checks for this driver
77  *	-1 = MSI not supported at all
78  */
79 int ppb_support_msi = 0;
80 
81 /*
82  * Controls the usage of the Hypertransport MSI mapping capability
83  *	0 = default value, leave hardware function as it is
84  *	1 = always enable HT MSI mapping
85  *     -1 = always disable HT MSI mapping
86  */
87 int ppb_support_ht_msimap = 0;
88 
89 struct bus_ops ppb_bus_ops = {
90 	BUSO_REV,
91 	ppb_bus_map,
92 	0,
93 	0,
94 	0,
95 	i_ddi_map_fault,
96 	ddi_dma_map,
97 	ddi_dma_allochdl,
98 	ddi_dma_freehdl,
99 	ddi_dma_bindhdl,
100 	ddi_dma_unbindhdl,
101 	ddi_dma_flush,
102 	ddi_dma_win,
103 	ddi_dma_mctl,
104 	ppb_ctlops,
105 	ddi_bus_prop_op,
106 	0,			/* (*bus_get_eventcookie)();	*/
107 	0,			/* (*bus_add_eventcall)();	*/
108 	0,			/* (*bus_remove_eventcall)();	*/
109 	0,			/* (*bus_post_event)();		*/
110 	0,			/* (*bus_intr_ctl)();		*/
111 	0,			/* (*bus_config)(); 		*/
112 	0,			/* (*bus_unconfig)(); 		*/
113 	ppb_fm_init,		/* (*bus_fm_init)(); 		*/
114 	NULL,			/* (*bus_fm_fini)(); 		*/
115 	NULL,			/* (*bus_fm_access_enter)(); 	*/
116 	NULL,			/* (*bus_fm_access_exit)(); 	*/
117 	NULL,			/* (*bus_power)(); 	*/
118 	ppb_intr_ops,		/* (*bus_intr_op)(); 		*/
119 	pcie_hp_common_ops	/* (*bus_hp_op)(); 		*/
120 };
121 
122 /*
123  * The goal here is to leverage off of the pcihp.c source without making
124  * changes to it.  Call into it's cb_ops directly if needed.
125  */
126 static int	ppb_open(dev_t *, int, int, cred_t *);
127 static int	ppb_close(dev_t, int, int, cred_t *);
128 static int	ppb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
129 static int	ppb_prop_op(dev_t, dev_info_t *, ddi_prop_op_t, int, char *,
130 		    caddr_t, int *);
131 static int	ppb_info(dev_info_t *, ddi_info_cmd_t, void *, void **);
132 static void	ppb_peekpoke_cb(dev_info_t *, ddi_fm_error_t *);
133 
134 struct cb_ops ppb_cb_ops = {
135 	ppb_open,			/* open */
136 	ppb_close,			/* close */
137 	nodev,				/* strategy */
138 	nodev,				/* print */
139 	nodev,				/* dump */
140 	nodev,				/* read */
141 	nodev,				/* write */
142 	ppb_ioctl,			/* ioctl */
143 	nodev,				/* devmap */
144 	nodev,				/* mmap */
145 	nodev,				/* segmap */
146 	nochpoll,			/* poll */
147 	ppb_prop_op,			/* cb_prop_op */
148 	NULL,				/* streamtab */
149 	D_NEW | D_MP | D_HOTPLUG,	/* Driver compatibility flag */
150 	CB_REV,				/* rev */
151 	nodev,				/* int (*cb_aread)() */
152 	nodev				/* int (*cb_awrite)() */
153 };
154 
155 
156 static int ppb_probe(dev_info_t *);
157 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
158 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
159 
160 struct dev_ops ppb_ops = {
161 	DEVO_REV,		/* devo_rev */
162 	0,			/* refcnt  */
163 	ppb_info,		/* info */
164 	nulldev,		/* identify */
165 	ppb_probe,		/* probe */
166 	ppb_attach,		/* attach */
167 	ppb_detach,		/* detach */
168 	nulldev,		/* reset */
169 	&ppb_cb_ops,		/* driver operations */
170 	&ppb_bus_ops,		/* bus operations */
171 	NULL,			/* power */
172 	ddi_quiesce_not_needed,		/* quiesce */
173 };
174 
175 /*
176  * Module linkage information for the kernel.
177  */
178 
179 static struct modldrv modldrv = {
180 	&mod_driverops, /* Type of module */
181 	"Standard PCI to PCI bridge nexus driver",
182 	&ppb_ops,	/* driver ops */
183 };
184 
185 static struct modlinkage modlinkage = {
186 	MODREV_1,
187 	(void *)&modldrv,
188 	NULL
189 };
190 
191 /*
192  * soft state pointer and structure template:
193  */
194 static void *ppb_state;
195 
196 typedef struct {
197 	dev_info_t *dip;
198 	int ppb_fmcap;
199 	ddi_iblock_cookie_t ppb_fm_ibc;
200 	kmutex_t ppb_mutex;
201 	kmutex_t ppb_peek_poke_mutex;
202 	kmutex_t ppb_err_mutex;
203 
204 	/*
205 	 * cpr support:
206 	 */
207 	uint_t config_state_index;
208 	struct {
209 		dev_info_t *dip;
210 		ushort_t command;
211 		uchar_t cache_line_size;
212 		uchar_t latency_timer;
213 		uchar_t header_type;
214 		uchar_t sec_latency_timer;
215 		ushort_t bridge_control;
216 	} config_state[PCI_MAX_CHILDREN];
217 
218 	uint16_t parent_bus;
219 } ppb_devstate_t;
220 
221 
222 /*
223  * forward function declarations:
224  */
225 static void	ppb_removechild(dev_info_t *);
226 static int	ppb_initchild(dev_info_t *child);
227 static void	ppb_save_config_regs(ppb_devstate_t *ppb_p);
228 static void	ppb_restore_config_regs(ppb_devstate_t *ppb_p);
229 static boolean_t	ppb_ht_msimap_check(ddi_acc_handle_t cfg_hdl);
230 static int	ppb_ht_msimap_set(ddi_acc_handle_t cfg_hdl, int cmd);
231 
232 /*
233  * for <cmd> in ppb_ht_msimap_set
234  */
235 #define	HT_MSIMAP_ENABLE	1
236 #define	HT_MSIMAP_DISABLE	0
237 
238 
239 int
240 _init(void)
241 {
242 	int e;
243 
244 	if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t),
245 	    1)) == 0 && (e = mod_install(&modlinkage)) != 0)
246 		ddi_soft_state_fini(&ppb_state);
247 	return (e);
248 }
249 
250 int
251 _fini(void)
252 {
253 	int e;
254 
255 	if ((e = mod_remove(&modlinkage)) == 0)
256 		ddi_soft_state_fini(&ppb_state);
257 	return (e);
258 }
259 
260 int
261 _info(struct modinfo *modinfop)
262 {
263 	return (mod_info(&modlinkage, modinfop));
264 }
265 
266 /*ARGSUSED*/
267 static int
268 ppb_probe(dev_info_t *devi)
269 {
270 	return (DDI_PROBE_SUCCESS);
271 }
272 
273 /*ARGSUSED*/
274 static int
275 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
276 {
277 	dev_info_t *root = ddi_root_node();
278 	int instance;
279 	ppb_devstate_t *ppb;
280 	dev_info_t *pdip;
281 	ddi_acc_handle_t config_handle;
282 	char *bus;
283 	int ret;
284 
285 	switch (cmd) {
286 	case DDI_ATTACH:
287 
288 		/*
289 		 * Make sure the "device_type" property exists.
290 		 */
291 		(void) ddi_prop_update_string(DDI_DEV_T_NONE, devi,
292 		    "device_type", "pci");
293 
294 		/*
295 		 * Allocate and get soft state structure.
296 		 */
297 		instance = ddi_get_instance(devi);
298 		if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS)
299 			return (DDI_FAILURE);
300 		ppb = ddi_get_soft_state(ppb_state, instance);
301 		ppb->dip = devi;
302 
303 		/*
304 		 * don't enable ereports if immediate child of npe
305 		 */
306 		if (strcmp(ddi_driver_name(ddi_get_parent(devi)), "npe") == 0)
307 			ppb->ppb_fmcap = DDI_FM_ERRCB_CAPABLE |
308 			    DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE;
309 		else
310 			ppb->ppb_fmcap = DDI_FM_EREPORT_CAPABLE |
311 			    DDI_FM_ERRCB_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
312 			    DDI_FM_DMACHK_CAPABLE;
313 
314 		ddi_fm_init(devi, &ppb->ppb_fmcap, &ppb->ppb_fm_ibc);
315 		mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL);
316 		mutex_init(&ppb->ppb_err_mutex, NULL, MUTEX_DRIVER,
317 		    (void *)ppb->ppb_fm_ibc);
318 		mutex_init(&ppb->ppb_peek_poke_mutex, NULL, MUTEX_DRIVER,
319 		    (void *)ppb->ppb_fm_ibc);
320 
321 		if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE |
322 		    DDI_FM_EREPORT_CAPABLE))
323 			pci_ereport_setup(devi);
324 		if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE)
325 			ddi_fm_handler_register(devi, ppb_fm_callback, NULL);
326 
327 		if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) {
328 			if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE)
329 				ddi_fm_handler_unregister(devi);
330 			if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE |
331 			    DDI_FM_EREPORT_CAPABLE))
332 				pci_ereport_teardown(devi);
333 			ddi_fm_fini(devi);
334 			ddi_soft_state_free(ppb_state, instance);
335 			return (DDI_FAILURE);
336 		}
337 
338 		ppb->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO;
339 		for (pdip = ddi_get_parent(devi); pdip && (pdip != root) &&
340 		    (ppb->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV);
341 		    pdip = ddi_get_parent(pdip)) {
342 			if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip,
343 			    DDI_PROP_DONTPASS, "device_type", &bus) !=
344 			    DDI_PROP_SUCCESS)
345 				break;
346 
347 			if (strcmp(bus, "pciex") == 0)
348 				ppb->parent_bus =
349 				    PCIE_PCIECAP_DEV_TYPE_PCIE_DEV;
350 
351 			ddi_prop_free(bus);
352 		}
353 
354 		if (ppb_support_ht_msimap == 1)
355 			(void) ppb_ht_msimap_set(config_handle,
356 			    HT_MSIMAP_ENABLE);
357 		else if (ppb_support_ht_msimap == -1)
358 			(void) ppb_ht_msimap_set(config_handle,
359 			    HT_MSIMAP_DISABLE);
360 
361 		pci_config_teardown(&config_handle);
362 
363 		/*
364 		 * Initialize hotplug support on this bus.
365 		 */
366 		if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
367 			ret = pcie_init(devi, NULL);
368 		else
369 			ret = pcihp_init(devi);
370 
371 		if (ret != DDI_SUCCESS) {
372 			cmn_err(CE_WARN,
373 			    "pci: Failed to setup hotplug framework");
374 			(void) ppb_detach(devi, DDI_DETACH);
375 			return (ret);
376 		}
377 
378 		ddi_report_dev(devi);
379 		return (DDI_SUCCESS);
380 
381 	case DDI_RESUME:
382 
383 		/*
384 		 * Get the soft state structure for the bridge.
385 		 */
386 		ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
387 		ppb_restore_config_regs(ppb);
388 		return (DDI_SUCCESS);
389 
390 	default:
391 		break;
392 	}
393 	return (DDI_FAILURE);
394 }
395 
396 /*ARGSUSED*/
397 static int
398 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
399 {
400 	ppb_devstate_t *ppb;
401 	int		ret;
402 
403 	switch (cmd) {
404 	case DDI_DETACH:
405 		(void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type");
406 
407 		ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
408 		if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE)
409 			ddi_fm_handler_unregister(devi);
410 		if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE |
411 		    DDI_FM_EREPORT_CAPABLE))
412 			pci_ereport_teardown(devi);
413 
414 		/*
415 		 * Uninitialize hotplug support on this bus.
416 		 */
417 		ret = (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) ?
418 		    pcie_uninit(devi) : pcihp_uninit(devi);
419 		if (ret != DDI_SUCCESS)
420 			return (DDI_FAILURE);
421 
422 		mutex_destroy(&ppb->ppb_peek_poke_mutex);
423 		mutex_destroy(&ppb->ppb_err_mutex);
424 		mutex_destroy(&ppb->ppb_mutex);
425 		ddi_fm_fini(devi);
426 
427 		/*
428 		 * And finally free the per-pci soft state.
429 		 */
430 		ddi_soft_state_free(ppb_state, ddi_get_instance(devi));
431 
432 		return (DDI_SUCCESS);
433 
434 	case DDI_SUSPEND:
435 		ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
436 		ppb_save_config_regs(ppb);
437 		return (DDI_SUCCESS);
438 
439 	default:
440 		break;
441 	}
442 	return (DDI_FAILURE);
443 }
444 
445 /*ARGSUSED*/
446 static int
447 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
448 	off_t offset, off_t len, caddr_t *vaddrp)
449 {
450 	dev_info_t *pdip;
451 	ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state,
452 	    ddi_get_instance(dip));
453 
454 	if (strcmp(ddi_driver_name(ddi_get_parent(dip)), "npe") == 0) {
455 		ddi_acc_impl_t *hdlp =
456 		    (ddi_acc_impl_t *)(mp->map_handlep)->ah_platform_private;
457 		hdlp->ahi_err_mutexp = &ppb->ppb_err_mutex;
458 		hdlp->ahi_peekpoke_mutexp = &ppb->ppb_peek_poke_mutex;
459 		hdlp->ahi_scan_dip = dip;
460 		hdlp->ahi_scan = ppb_peekpoke_cb;
461 	}
462 	pdip = (dev_info_t *)DEVI(dip)->devi_parent;
463 	return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip,
464 	    rdip, mp, offset, len, vaddrp));
465 }
466 
467 /*ARGSUSED*/
468 static int
469 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip,
470 	ddi_ctl_enum_t ctlop, void *arg, void *result)
471 {
472 	pci_regspec_t *drv_regp;
473 	int	reglen;
474 	int	rn;
475 	int	totreg;
476 	ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state,
477 	    ddi_get_instance(dip));
478 	struct detachspec *dsp;
479 	struct attachspec *asp;
480 
481 	switch (ctlop) {
482 	case DDI_CTLOPS_REPORTDEV:
483 		if (rdip == (dev_info_t *)0)
484 			return (DDI_FAILURE);
485 		cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n",
486 		    ddi_node_name(rdip), ddi_get_name_addr(rdip),
487 		    ddi_driver_name(rdip),
488 		    ddi_get_instance(rdip));
489 		return (DDI_SUCCESS);
490 
491 	case DDI_CTLOPS_INITCHILD:
492 		return (ppb_initchild((dev_info_t *)arg));
493 
494 	case DDI_CTLOPS_UNINITCHILD:
495 		ppb_removechild((dev_info_t *)arg);
496 		return (DDI_SUCCESS);
497 
498 	case DDI_CTLOPS_SIDDEV:
499 		return (DDI_SUCCESS);
500 
501 	case DDI_CTLOPS_REGSIZE:
502 	case DDI_CTLOPS_NREGS:
503 		if (rdip == (dev_info_t *)0)
504 			return (DDI_FAILURE);
505 		break;
506 
507 	/* X86 systems support PME wakeup from suspend */
508 	case DDI_CTLOPS_ATTACH:
509 		if (!pcie_is_child(dip, rdip))
510 			return (DDI_SUCCESS);
511 
512 		asp = (struct attachspec *)arg;
513 		if ((ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) &&
514 		    (asp->when == DDI_POST) && (asp->result == DDI_SUCCESS))
515 			pf_init(rdip, (void *)ppb->ppb_fm_ibc, asp->cmd);
516 
517 		if (asp->cmd == DDI_RESUME && asp->when == DDI_PRE)
518 			if (pci_pre_resume(rdip) != DDI_SUCCESS)
519 				return (DDI_FAILURE);
520 
521 		return (DDI_SUCCESS);
522 
523 	case DDI_CTLOPS_DETACH:
524 		if (!pcie_is_child(dip, rdip))
525 			return (DDI_SUCCESS);
526 
527 		dsp = (struct detachspec *)arg;
528 		if ((ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) &&
529 		    (dsp->when == DDI_PRE))
530 			pf_fini(rdip, dsp->cmd);
531 
532 		if (dsp->cmd == DDI_SUSPEND && dsp->when == DDI_POST)
533 			if (pci_post_suspend(rdip) != DDI_SUCCESS)
534 				return (DDI_FAILURE);
535 
536 		return (DDI_SUCCESS);
537 
538 	case DDI_CTLOPS_PEEK:
539 	case DDI_CTLOPS_POKE:
540 		if (strcmp(ddi_driver_name(ddi_get_parent(dip)), "npe") != 0)
541 			return (ddi_ctlops(dip, rdip, ctlop, arg, result));
542 		return (pci_peekpoke_check(dip, rdip, ctlop, arg, result,
543 		    ddi_ctlops, &ppb->ppb_err_mutex,
544 		    &ppb->ppb_peek_poke_mutex, ppb_peekpoke_cb));
545 
546 	default:
547 		return (ddi_ctlops(dip, rdip, ctlop, arg, result));
548 	}
549 
550 	*(int *)result = 0;
551 	if (ddi_getlongprop(DDI_DEV_T_ANY, rdip,
552 	    DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg",
553 	    (caddr_t)&drv_regp, &reglen) != DDI_SUCCESS)
554 		return (DDI_FAILURE);
555 
556 	totreg = reglen / sizeof (pci_regspec_t);
557 	if (ctlop == DDI_CTLOPS_NREGS)
558 		*(int *)result = totreg;
559 	else if (ctlop == DDI_CTLOPS_REGSIZE) {
560 		rn = *(int *)arg;
561 		if (rn >= totreg) {
562 			kmem_free(drv_regp, reglen);
563 			return (DDI_FAILURE);
564 		}
565 		*(off_t *)result = drv_regp[rn].pci_size_low;
566 	}
567 
568 	kmem_free(drv_regp, reglen);
569 	return (DDI_SUCCESS);
570 }
571 
572 static int
573 ppb_name_child(dev_info_t *child, char *name, int namelen)
574 {
575 	pci_regspec_t *pci_rp;
576 	uint_t slot, func;
577 	char **unit_addr;
578 	uint_t n;
579 
580 	/*
581 	 * For .conf nodes, use unit-address property as name
582 	 */
583 	if (ndi_dev_is_persistent_node(child) == 0) {
584 		if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child,
585 		    DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) !=
586 		    DDI_PROP_SUCCESS) {
587 			cmn_err(CE_WARN,
588 			    "cannot find unit-address in %s.conf",
589 			    ddi_driver_name(child));
590 			return (DDI_FAILURE);
591 		}
592 		if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
593 			cmn_err(CE_WARN, "unit-address property in %s.conf"
594 			    " not well-formed", ddi_driver_name(child));
595 			ddi_prop_free(unit_addr);
596 			return (DDI_SUCCESS);
597 		}
598 		(void) snprintf(name, namelen, "%s", *unit_addr);
599 		ddi_prop_free(unit_addr);
600 		return (DDI_SUCCESS);
601 	}
602 
603 	/* get child "reg" property */
604 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child,
605 	    DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) {
606 		return (DDI_FAILURE);
607 	}
608 
609 	/* copy the device identifications */
610 	slot = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
611 	func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
612 
613 	if (func != 0)
614 		(void) snprintf(name, namelen, "%x,%x", slot, func);
615 	else
616 		(void) snprintf(name, namelen, "%x", slot);
617 
618 	ddi_prop_free(pci_rp);
619 	return (DDI_SUCCESS);
620 }
621 
622 static int
623 ppb_initchild(dev_info_t *child)
624 {
625 	struct ddi_parent_private_data *pdptr;
626 	ppb_devstate_t *ppb;
627 	char name[MAXNAMELEN];
628 	ddi_acc_handle_t config_handle;
629 	ushort_t command_preserve, command;
630 
631 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
632 	    ddi_get_instance(ddi_get_parent(child)));
633 
634 	if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS)
635 		return (DDI_FAILURE);
636 	ddi_set_name_addr(child, name);
637 
638 	/*
639 	 * Pseudo nodes indicate a prototype node with per-instance
640 	 * properties to be merged into the real h/w device node.
641 	 * The interpretation of the unit-address is DD[,F]
642 	 * where DD is the device id and F is the function.
643 	 */
644 	if (ndi_dev_is_persistent_node(child) == 0) {
645 		extern int pci_allow_pseudo_children;
646 
647 		ddi_set_parent_data(child, NULL);
648 
649 		/*
650 		 * Try to merge the properties from this prototype
651 		 * node into real h/w nodes.
652 		 */
653 		if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) {
654 			/*
655 			 * Merged ok - return failure to remove the node.
656 			 */
657 			ddi_set_name_addr(child, NULL);
658 			return (DDI_FAILURE);
659 		}
660 
661 		/* workaround for ddivs to run under PCI */
662 		if (pci_allow_pseudo_children)
663 			return (DDI_SUCCESS);
664 
665 		/*
666 		 * The child was not merged into a h/w node,
667 		 * but there's not much we can do with it other
668 		 * than return failure to cause the node to be removed.
669 		 */
670 		cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged",
671 		    ddi_driver_name(child), ddi_get_name_addr(child),
672 		    ddi_driver_name(child));
673 		ddi_set_name_addr(child, NULL);
674 		return (DDI_NOT_WELL_FORMED);
675 	}
676 
677 	ddi_set_parent_data(child, NULL);
678 
679 	/*
680 	 * PCIe FMA specific
681 	 *
682 	 * Note: parent_data for parent is created only if this is PCI-E
683 	 * platform, for which, SG take a different route to handle device
684 	 * errors.
685 	 */
686 	if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
687 		if (pcie_init_bus(child) == NULL)
688 			return (DDI_FAILURE);
689 	}
690 
691 	/* transfer select properties from PROM to kernel */
692 	if (ddi_getprop(DDI_DEV_T_NONE, child, DDI_PROP_DONTPASS,
693 	    "interrupts", -1) != -1) {
694 		pdptr = kmem_zalloc((sizeof (struct ddi_parent_private_data) +
695 		    sizeof (struct intrspec)), KM_SLEEP);
696 		pdptr->par_intr = (struct intrspec *)(pdptr + 1);
697 		pdptr->par_nintr = 1;
698 		ddi_set_parent_data(child, pdptr);
699 	} else
700 		ddi_set_parent_data(child, NULL);
701 
702 	if (pci_config_setup(child, &config_handle) != DDI_SUCCESS)
703 		return (DDI_FAILURE);
704 
705 	/*
706 	 * Support for the "command-preserve" property.
707 	 */
708 	command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child,
709 	    DDI_PROP_DONTPASS, "command-preserve", 0);
710 	command = pci_config_get16(config_handle, PCI_CONF_COMM);
711 	command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB);
712 	command |= (ppb_command_default & ~command_preserve);
713 	pci_config_put16(config_handle, PCI_CONF_COMM, command);
714 
715 	pci_config_teardown(&config_handle);
716 	return (DDI_SUCCESS);
717 }
718 
719 static void
720 ppb_removechild(dev_info_t *dip)
721 {
722 	struct ddi_parent_private_data *pdptr;
723 	ppb_devstate_t *ppb;
724 
725 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
726 	    ddi_get_instance(ddi_get_parent(dip)));
727 
728 	if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
729 		pcie_fini_bus(dip);
730 	else if ((pdptr = ddi_get_parent_data(dip)) != NULL) {
731 		kmem_free(pdptr, (sizeof (*pdptr) + sizeof (struct intrspec)));
732 		ddi_set_parent_data(dip, NULL);
733 	}
734 	ddi_set_name_addr(dip, NULL);
735 
736 	/*
737 	 * Strip the node to properly convert it back to prototype form
738 	 */
739 	ddi_remove_minor_node(dip, NULL);
740 
741 	impl_rem_dev_props(dip);
742 }
743 
744 /*
745  * ppb_save_config_regs
746  *
747  * This routine saves the state of the configuration registers of all
748  * the child nodes of each PBM.
749  *
750  * used by: ppb_detach() on suspends
751  *
752  * return value: none
753  */
754 static void
755 ppb_save_config_regs(ppb_devstate_t *ppb_p)
756 {
757 	int i;
758 	dev_info_t *dip;
759 	ddi_acc_handle_t config_handle;
760 
761 	for (i = 0, dip = ddi_get_child(ppb_p->dip); dip != NULL;
762 	    i++, dip = ddi_get_next_sibling(dip)) {
763 
764 		if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) {
765 			cmn_err(CE_WARN, "%s%d: can't config space for %s%d\n",
766 			    ddi_driver_name(ppb_p->dip),
767 			    ddi_get_instance(ppb_p->dip),
768 			    ddi_driver_name(dip),
769 			    ddi_get_instance(dip));
770 			continue;
771 		}
772 
773 		ppb_p->config_state[i].dip = dip;
774 		ppb_p->config_state[i].command =
775 		    pci_config_get16(config_handle, PCI_CONF_COMM);
776 		pci_config_teardown(&config_handle);
777 	}
778 	ppb_p->config_state_index = i;
779 }
780 
781 
782 /*
783  * ppb_restore_config_regs
784  *
785  * This routine restores the state of the configuration registers of all
786  * the child nodes of each PBM.
787  *
788  * used by: ppb_attach() on resume
789  *
790  * return value: none
791  */
792 static void
793 ppb_restore_config_regs(ppb_devstate_t *ppb_p)
794 {
795 	int i;
796 	dev_info_t *dip;
797 	ddi_acc_handle_t config_handle;
798 
799 	for (i = 0; i < ppb_p->config_state_index; i++) {
800 		dip = ppb_p->config_state[i].dip;
801 		if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) {
802 			cmn_err(CE_WARN, "%s%d: can't config space for %s%d\n",
803 			    ddi_driver_name(ppb_p->dip),
804 			    ddi_get_instance(ppb_p->dip),
805 			    ddi_driver_name(dip),
806 			    ddi_get_instance(dip));
807 			continue;
808 		}
809 		pci_config_put16(config_handle, PCI_CONF_COMM,
810 		    ppb_p->config_state[i].command);
811 		pci_config_teardown(&config_handle);
812 	}
813 }
814 
815 
816 static boolean_t
817 ppb_ht_msimap_check(ddi_acc_handle_t cfg_hdl)
818 {
819 	uint16_t ptr;
820 
821 	if (pci_htcap_locate(cfg_hdl,
822 	    PCI_HTCAP_TYPE_MASK | PCI_HTCAP_MSIMAP_ENABLE_MASK,
823 	    PCI_HTCAP_MSIMAP_TYPE | PCI_HTCAP_MSIMAP_ENABLE, &ptr) !=
824 	    DDI_SUCCESS)
825 		return (B_FALSE);
826 
827 	return (B_TRUE);
828 }
829 
830 
831 static int
832 ppb_ht_msimap_set(ddi_acc_handle_t cfg_hdl, int cmd)
833 {
834 	uint16_t ptr;
835 	uint16_t reg;
836 
837 	if (pci_htcap_locate(cfg_hdl, PCI_HTCAP_TYPE_MASK,
838 	    PCI_HTCAP_MSIMAP_TYPE, &ptr) != DDI_SUCCESS)
839 		return (0);
840 
841 	reg = pci_config_get16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF);
842 	switch (cmd) {
843 	case HT_MSIMAP_ENABLE:
844 		reg |= PCI_HTCAP_MSIMAP_ENABLE;
845 		break;
846 	case HT_MSIMAP_DISABLE:
847 	default:
848 		reg &= ~(uint16_t)PCI_HTCAP_MSIMAP_ENABLE;
849 	}
850 
851 	pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg);
852 	return (1);
853 }
854 
855 
856 /*
857  * intercept certain interrupt services to handle special cases
858  */
859 static int
860 ppb_intr_ops(dev_info_t *pdip, dev_info_t *rdip, ddi_intr_op_t intr_op,
861     ddi_intr_handle_impl_t *hdlp, void *result)
862 {
863 	ddi_acc_handle_t cfg_hdl;
864 	int rv = DDI_SUCCESS;
865 
866 	if (intr_op != DDI_INTROP_SUPPORTED_TYPES)
867 		return (i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result));
868 
869 	DDI_INTR_NEXDBG((CE_CONT,
870 	    "ppb_intr_ops: pdip 0x%p, rdip 0x%p, op %x handle 0x%p\n",
871 	    (void *)pdip, (void *)rdip, intr_op, (void *)hdlp));
872 
873 	/* Fixed interrupt is supported by default */
874 	*(int *)result = DDI_INTR_TYPE_FIXED;
875 
876 	if (ppb_support_msi == -1) {
877 		DDI_INTR_NEXDBG((CE_CONT,
878 		    "ppb_intr_ops: MSI is not allowed\n"));
879 		goto OUT;
880 	}
881 
882 	if (ppb_support_msi == 1) {
883 		DDI_INTR_NEXDBG((CE_CONT,
884 		    "ppb_intr_ops: MSI is always allowed\n"));
885 		rv = i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result);
886 		goto OUT;
887 	}
888 
889 	if (pci_config_setup(pdip, &cfg_hdl) != DDI_SUCCESS) {
890 		DDI_INTR_NEXDBG((CE_CONT,
891 		    "ppb_intr_ops: pci_config_setup() failed\n"));
892 		goto OUT;
893 	}
894 
895 	/*
896 	 * check for hypertransport msi mapping capability
897 	 */
898 	if (ppb_ht_msimap_check(cfg_hdl)) {
899 		DDI_INTR_NEXDBG((CE_CONT,
900 		    "ppb_intr_ops: HT MSI mapping enabled\n"));
901 		rv = i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result);
902 	}
903 
904 	/*
905 	 * if we add failure conditions after pci_config_setup, move this to
906 	 * OUT and use an extra flag to indicate the need to teardown cfg_hdl
907 	 */
908 	pci_config_teardown(&cfg_hdl);
909 
910 OUT:
911 	DDI_INTR_NEXDBG((CE_CONT,
912 	    "ppb_intr_ops: rdip 0x%p, returns supported types: 0x%x\n",
913 	    (void *)rdip, *(int *)result));
914 	return (rv);
915 }
916 
917 /* ARGSUSED */
918 static int
919 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
920 {
921 	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(*devp));
922 	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
923 	int	rv;
924 
925 	if (ppb_p == NULL)
926 		return (ENXIO);
927 
928 	/*
929 	 * Ioctls will be handled by PCI Express framework for all
930 	 * PCIe platforms
931 	 */
932 	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
933 		mutex_enter(&ppb_p->ppb_mutex);
934 		rv = pcie_open(ppb_p->dip, devp, flags, otyp, credp);
935 		mutex_exit(&ppb_p->ppb_mutex);
936 		return (rv);
937 	}
938 
939 	return ((pcihp_get_cb_ops())->cb_open(devp, flags, otyp, credp));
940 }
941 
942 /* ARGSUSED */
943 static int
944 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp)
945 {
946 	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
947 	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
948 	int	rv;
949 
950 	if (ppb_p == NULL)
951 		return (ENXIO);
952 
953 	mutex_enter(&ppb_p->ppb_mutex);
954 	/*
955 	 * Ioctls will be handled by PCI Express framework for all
956 	 * PCIe platforms
957 	 */
958 	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
959 		rv = pcie_close(ppb_p->dip, dev, flags, otyp, credp);
960 		mutex_exit(&ppb_p->ppb_mutex);
961 		return (rv);
962 	}
963 
964 	mutex_exit(&ppb_p->ppb_mutex);
965 	return ((pcihp_get_cb_ops())->cb_close(dev, flags, otyp, credp));
966 }
967 
968 /*
969  * ppb_ioctl: devctl hotplug controls
970  */
971 /* ARGSUSED */
972 static int
973 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
974 	int *rvalp)
975 {
976 	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
977 	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
978 
979 	if (ppb_p == NULL)
980 		return (ENXIO);
981 
982 	/*
983 	 * Ioctls will be handled by PCI Express framework for all
984 	 * PCIe platforms
985 	 */
986 	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
987 		return (pcie_ioctl(ppb_p->dip, dev, cmd, arg, mode, credp,
988 		    rvalp));
989 
990 	return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, arg, mode, credp,
991 	    rvalp));
992 }
993 
994 static int
995 ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, int flags,
996     char *name, caddr_t valuep, int *lengthp)
997 {
998 	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
999 	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
1000 
1001 	if (ppb_p == NULL)
1002 		return (ENXIO);
1003 
1004 	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
1005 		return (pcie_prop_op(dev, dip, prop_op, flags, name,
1006 		    valuep, lengthp));
1007 
1008 	return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, flags,
1009 	    name, valuep, lengthp));
1010 }
1011 
1012 static int
1013 ppb_info(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result)
1014 {
1015 	minor_t		minor = getminor((dev_t)arg);
1016 	int		instance = PCI_MINOR_NUM_TO_INSTANCE(minor);
1017 	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
1018 
1019 	if (ppb_p == NULL)
1020 		return (DDI_FAILURE);
1021 
1022 	if (ppb_p->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
1023 		return (pcihp_info(dip, cmd, arg, result));
1024 
1025 	switch (cmd) {
1026 	default:
1027 		return (DDI_FAILURE);
1028 
1029 	case DDI_INFO_DEVT2INSTANCE:
1030 		*result = (void *)(uintptr_t)instance;
1031 		return (DDI_SUCCESS);
1032 
1033 	case DDI_INFO_DEVT2DEVINFO:
1034 		if (ppb_p == NULL)
1035 			return (DDI_FAILURE);
1036 		*result = (void *)ppb_p->dip;
1037 		return (DDI_SUCCESS);
1038 	}
1039 }
1040 
1041 void ppb_peekpoke_cb(dev_info_t *dip, ddi_fm_error_t *derr) {
1042 	(void) pci_ereport_post(dip, derr, NULL);
1043 }
1044 
1045 /*ARGSUSED*/
1046 static int
1047 ppb_fm_init(dev_info_t *dip, dev_info_t *tdip, int cap,
1048     ddi_iblock_cookie_t *ibc)
1049 {
1050 	ppb_devstate_t  *ppb = ddi_get_soft_state(ppb_state,
1051 	    ddi_get_instance(dip));
1052 
1053 	ASSERT(ibc != NULL);
1054 	*ibc = ppb->ppb_fm_ibc;
1055 
1056 	return (ppb->ppb_fmcap);
1057 }
1058 
1059 /*ARGSUSED*/
1060 static int
1061 ppb_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *no_used)
1062 {
1063 	ppb_devstate_t  *ppb = ddi_get_soft_state(ppb_state,
1064 	    ddi_get_instance(dip));
1065 
1066 	mutex_enter(&ppb->ppb_err_mutex);
1067 	pci_ereport_post(dip, derr, NULL);
1068 	mutex_exit(&ppb->ppb_err_mutex);
1069 	return (derr->fme_status);
1070 }
1071