xref: /titanic_51/usr/src/uts/intel/io/pci/pci_boot.c (revision d7e6a9b10c50c7907635aeb61c4d1fe8bec9069a)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #include <sys/types.h>
27 #include <sys/stat.h>
28 #include <sys/sunndi.h>
29 #include <sys/pci.h>
30 #include <sys/pci_impl.h>
31 #include <sys/pci_cfgspace.h>
32 #include <sys/memlist.h>
33 #include <sys/bootconf.h>
34 #include <io/pci/mps_table.h>
35 #include <sys/pci_cfgspace.h>
36 #include <sys/pci_cfgspace_impl.h>
37 #include <sys/psw.h>
38 #include "../../../../common/pci/pci_strings.h"
39 #include <sys/apic.h>
40 #include <io/pciex/pcie_nvidia.h>
41 #include <io/hotplug/pciehpc/pciehpc_acpi.h>
42 #include <sys/acpi/acpi.h>
43 #include <sys/acpica.h>
44 #include <sys/intel_iommu.h>
45 #include <sys/iommulib.h>
46 
47 #define	pci_getb	(*pci_getb_func)
48 #define	pci_getw	(*pci_getw_func)
49 #define	pci_getl	(*pci_getl_func)
50 #define	pci_putb	(*pci_putb_func)
51 #define	pci_putw	(*pci_putw_func)
52 #define	pci_putl	(*pci_putl_func)
53 #define	dcmn_err	if (pci_boot_debug) cmn_err
54 
55 #define	CONFIG_INFO	0
56 #define	CONFIG_UPDATE	1
57 #define	CONFIG_NEW	2
58 #define	CONFIG_FIX	3
59 #define	COMPAT_BUFSIZE	512
60 
61 #define	PPB_IO_ALIGNMENT	0x1000		/* 4K aligned */
62 #define	PPB_MEM_ALIGNMENT	0x100000	/* 1M aligned */
63 
64 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */
65 #define	LPC_IO_CONTROL_REG_1	0x40
66 #define	AMD8111_ENABLENMI	(uint8_t)0x80
67 #define	DEVID_AMD8111_LPC	0x7468
68 
69 struct pci_fixundo {
70 	uint8_t			bus;
71 	uint8_t			dev;
72 	uint8_t			fn;
73 	void			(*undofn)(uint8_t, uint8_t, uint8_t);
74 	struct pci_fixundo	*next;
75 };
76 
77 struct pci_devfunc {
78 	struct pci_devfunc *next;
79 	dev_info_t *dip;
80 	uchar_t dev;
81 	uchar_t func;
82 	boolean_t reprogram;	/* this device needs to be reprogrammed */
83 };
84 
85 extern int pci_bios_nbus;
86 static uchar_t max_dev_pci = 32;	/* PCI standard */
87 int pci_boot_debug = 0;
88 extern struct memlist *find_bus_res(int, int);
89 static struct pci_fixundo *undolist = NULL;
90 static int num_root_bus = 0;	/* count of root buses */
91 extern volatile int acpi_resource_discovery;
92 
93 /*
94  * Module prototypes
95  */
96 static void enumerate_bus_devs(uchar_t bus, int config_op);
97 static void create_root_bus_dip(uchar_t bus);
98 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t,
99     ushort_t, int);
100 static void add_compatible(dev_info_t *, ushort_t, ushort_t,
101     ushort_t, ushort_t, uchar_t, uint_t, int);
102 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int);
103 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int,
104     ushort_t);
105 static void add_model_prop(dev_info_t *, uint_t);
106 static void add_bus_range_prop(int);
107 static void add_bus_slot_names_prop(int);
108 static void add_ranges_prop(int, int);
109 static void add_bus_available_prop(int);
110 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id);
111 static void fix_ppb_res(uchar_t, boolean_t);
112 static void alloc_res_array();
113 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
114     ushort_t deviceid);
115 static void pciex_slot_names_prop(dev_info_t *, ushort_t);
116 static void populate_bus_res(uchar_t bus);
117 static void memlist_remove_list(struct memlist **list,
118     struct memlist *remove_list);
119 
120 extern int pci_slot_names_prop(int, char *, int);
121 
122 /* set non-zero to force PCI peer-bus renumbering */
123 int pci_bus_always_renumber = 0;
124 
125 /*
126  * Enumerate all PCI devices
127  */
128 void
129 pci_setup_tree()
130 {
131 	uint_t i, root_bus_addr = 0;
132 
133 	alloc_res_array();
134 	for (i = 0; i <= pci_bios_nbus; i++) {
135 		pci_bus_res[i].par_bus = (uchar_t)-1;
136 		pci_bus_res[i].root_addr = (uchar_t)-1;
137 		pci_bus_res[i].sub_bus = i;
138 	}
139 
140 	pci_bus_res[0].root_addr = root_bus_addr++;
141 	create_root_bus_dip(0);
142 	enumerate_bus_devs(0, CONFIG_INFO);
143 
144 	/*
145 	 * Now enumerate peer busses
146 	 *
147 	 * We loop till pci_bios_nbus. On most systems, there is
148 	 * one more bus at the high end, which implements the ISA
149 	 * compatibility bus. We don't care about that.
150 	 *
151 	 * Note: In the old (bootconf) enumeration, the peer bus
152 	 *	address did not use the bus number, and there were
153 	 *	too many peer busses created. The root_bus_addr is
154 	 *	used to maintain the old peer bus address assignment.
155 	 *	However, we stop enumerating phantom peers with no
156 	 *	device below.
157 	 */
158 	for (i = 1; i <= pci_bios_nbus; i++) {
159 		if (pci_bus_res[i].dip == NULL) {
160 			pci_bus_res[i].root_addr = root_bus_addr++;
161 		}
162 		enumerate_bus_devs(i, CONFIG_INFO);
163 
164 		/* add slot-names property for named pci hot-plug slots */
165 		add_bus_slot_names_prop(i);
166 	}
167 
168 }
169 
170 /*
171  * >0 = present, 0 = not present, <0 = error
172  */
173 static int
174 pci_bbn_present(int bus)
175 {
176 	ACPI_HANDLE	hdl;
177 	int	rv;
178 
179 	/* no dip means no _BBN */
180 	if (pci_bus_res[bus].dip == NULL)
181 		return (0);
182 
183 	rv = -1;	/* default return value in case of error below */
184 	if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) {
185 		switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) {
186 		case AE_OK:
187 			rv = 1;
188 			break;
189 		case AE_NOT_FOUND:
190 			rv = 0;
191 			break;
192 		default:
193 			break;
194 		}
195 	}
196 
197 	return (rv);
198 }
199 
200 /*
201  * Return non-zero if any PCI bus in the system has an associated
202  * _BBN object, 0 otherwise.
203  */
204 static int
205 pci_roots_have_bbn(void)
206 {
207 	int	i;
208 
209 	/*
210 	 * Scan the PCI busses and look for at least 1 _BBN
211 	 */
212 	for (i = 0; i <= pci_bios_nbus; i++) {
213 		/* skip non-root (peer) PCI busses */
214 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
215 			continue;
216 
217 		if (pci_bbn_present(i) > 0)
218 			return (1);
219 	}
220 	return (0);
221 
222 }
223 
224 /*
225  * return non-zero if the machine is one on which we renumber
226  * the internal pci unit-addresses
227  */
228 static int
229 pci_bus_renumber()
230 {
231 	ACPI_TABLE_HEADER *fadt;
232 
233 	if (pci_bus_always_renumber)
234 		return (1);
235 
236 	/* get the FADT */
237 	if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) !=
238 	    AE_OK)
239 		return (0);
240 
241 	/* compare OEM Table ID to "SUNm31" */
242 	if (strncmp("SUNm31", fadt->OemId, 6))
243 		return (0);
244 	else
245 		return (1);
246 }
247 
248 /*
249  * Initial enumeration of the physical PCI bus hierarchy can
250  * leave 'gaps' in the order of peer PCI bus unit-addresses.
251  * Systems with more than one peer PCI bus *must* have an ACPI
252  * _BBN object associated with each peer bus; use the presence
253  * of this object to remove gaps in the numbering of the peer
254  * PCI bus unit-addresses - only peer busses with an associated
255  * _BBN are counted.
256  */
257 static void
258 pci_renumber_root_busses(void)
259 {
260 	int pci_regs[] = {0, 0, 0};
261 	int	i, root_addr = 0;
262 
263 	/*
264 	 * Currently, we only enable the re-numbering on specific
265 	 * Sun machines; this is a work-around for the more complicated
266 	 * issue of upgrade changing physical device paths
267 	 */
268 	if (!pci_bus_renumber())
269 		return;
270 
271 	/*
272 	 * If we find no _BBN objects at all, we either don't need
273 	 * to do anything or can't do anything anyway
274 	 */
275 	if (!pci_roots_have_bbn())
276 		return;
277 
278 	for (i = 0; i <= pci_bios_nbus; i++) {
279 		/* skip non-root (peer) PCI busses */
280 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
281 			continue;
282 
283 		if (pci_bbn_present(i) < 1) {
284 			pci_bus_res[i].root_addr = (uchar_t)-1;
285 			continue;
286 		}
287 
288 		ASSERT(pci_bus_res[i].dip != NULL);
289 		if (pci_bus_res[i].root_addr != root_addr) {
290 			/* update reg property for node */
291 			pci_bus_res[i].root_addr = root_addr;
292 			pci_regs[0] = pci_bus_res[i].root_addr;
293 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
294 			    pci_bus_res[i].dip, "reg", (int *)pci_regs, 3);
295 		}
296 		root_addr++;
297 	}
298 }
299 
300 static void
301 remove_resource_range(struct memlist **list, int *ranges, int range_count)
302 {
303 	struct range {
304 		uint32_t base;
305 		uint32_t len;
306 	};
307 	int index;
308 
309 	for (index = 0; index < range_count; index++) {
310 		/* all done if list is or has become empty */
311 		if (*list == NULL)
312 			break;
313 		(void) memlist_remove(list,
314 		    (uint64_t)((struct range *)ranges)[index].base,
315 		    (uint64_t)((struct range *)ranges)[index].len);
316 	}
317 }
318 
319 static void
320 remove_used_resources()
321 {
322 	dev_info_t *used;
323 	int	*narray;
324 	uint_t	ncount;
325 	int	status;
326 	int	bus;
327 
328 	used = ddi_find_devinfo("used-resources", -1, 0);
329 	if (used == NULL)
330 		return;
331 
332 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
333 	    DDI_PROP_DONTPASS, "io-space", &narray, &ncount);
334 	if (status == DDI_PROP_SUCCESS) {
335 		for (bus = 0; bus <= pci_bios_nbus; bus++)
336 			remove_resource_range(&pci_bus_res[bus].io_ports,
337 			    narray, ncount / 2);
338 		ddi_prop_free(narray);
339 	}
340 
341 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
342 	    DDI_PROP_DONTPASS, "device-memory", &narray, &ncount);
343 	if (status == DDI_PROP_SUCCESS) {
344 		for (bus = 0; bus <= pci_bios_nbus; bus++)
345 			remove_resource_range(&pci_bus_res[bus].mem_space,
346 			    narray, ncount / 2);
347 		ddi_prop_free(narray);
348 	}
349 }
350 
351 /*
352  * Remove the resources which are already used by devices under a subtractive
353  * bridge from the bus's resources lists, because they're not available, and
354  * shouldn't be allocated to other buses.  This is necessary because tracking
355  * resources for subtractive bridges is not complete.  (Subtractive bridges only
356  * track some of their claimed resources, not "the rest of the address space" as
357  * they should, so that allocation to peer non-subtractive PPBs is easier.  We
358  * need a fully-capable global resource allocator).
359  */
360 static void
361 remove_subtractive_res()
362 {
363 	int i, j;
364 	struct memlist *list;
365 
366 	for (i = 0; i <= pci_bios_nbus; i++) {
367 		if (pci_bus_res[i].subtractive) {
368 			/* remove used io ports */
369 			list = pci_bus_res[i].io_ports_used;
370 			while (list) {
371 				for (j = 0; j <= pci_bios_nbus; j++)
372 					(void) memlist_remove(
373 					    &pci_bus_res[j].io_ports,
374 					    list->address, list->size);
375 				list = list->next;
376 			}
377 			/* remove used mem resource */
378 			list = pci_bus_res[i].mem_space_used;
379 			while (list) {
380 				for (j = 0; j <= pci_bios_nbus; j++) {
381 					(void) memlist_remove(
382 					    &pci_bus_res[j].mem_space,
383 					    list->address, list->size);
384 					(void) memlist_remove(
385 					    &pci_bus_res[j].pmem_space,
386 					    list->address, list->size);
387 				}
388 				list = list->next;
389 			}
390 			/* remove used prefetchable mem resource */
391 			list = pci_bus_res[i].pmem_space_used;
392 			while (list) {
393 				for (j = 0; j <= pci_bios_nbus; j++) {
394 					(void) memlist_remove(
395 					    &pci_bus_res[j].pmem_space,
396 					    list->address, list->size);
397 					(void) memlist_remove(
398 					    &pci_bus_res[j].mem_space,
399 					    list->address, list->size);
400 				}
401 				list = list->next;
402 			}
403 		}
404 	}
405 }
406 
407 /*
408  * Set-up (or complete the set-up) of the bus_space resource list
409  */
410 static void
411 setup_bus_res(int bus)
412 {
413 	uchar_t par_bus;
414 
415 	if (pci_bus_res[bus].dip == NULL)	/* unused bus */
416 		return;
417 
418 	/*
419 	 * Setup bus_space if not already filled-in by populate_bus_res();
420 	 */
421 	if (pci_bus_res[bus].bus_space == NULL) {
422 		ASSERT(pci_bus_res[bus].sub_bus >= bus);
423 		memlist_insert(&pci_bus_res[bus].bus_space, bus,
424 		    pci_bus_res[bus].sub_bus - bus + 1);
425 	}
426 
427 	ASSERT(pci_bus_res[bus].bus_space != NULL);
428 
429 	/*
430 	 * Remove resources from parent bus node if this is not a
431 	 * root bus.
432 	 */
433 	par_bus = pci_bus_res[bus].par_bus;
434 	if (par_bus != (uchar_t)-1) {
435 		ASSERT(pci_bus_res[par_bus].bus_space != NULL);
436 		memlist_remove_list(&pci_bus_res[par_bus].bus_space,
437 		    pci_bus_res[bus].bus_space);
438 	}
439 
440 	/* remove self from bus_space */;
441 	(void) memlist_remove(&pci_bus_res[bus].bus_space, bus, 1);
442 }
443 
444 static uint64_t
445 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
446 {
447 	uint64_t addr = 0;
448 	uchar_t res_bus;
449 
450 	/*
451 	 * Skip root(peer) buses in multiple-root-bus systems when
452 	 * ACPI resource discovery was not successfully done.
453 	 */
454 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
455 	    (num_root_bus > 1) && (acpi_resource_discovery <= 0))
456 		return (0);
457 
458 	res_bus = parbus;
459 	while (pci_bus_res[res_bus].subtractive) {
460 		if (pci_bus_res[res_bus].io_ports)
461 			break;
462 		res_bus = pci_bus_res[res_bus].par_bus;
463 		if (res_bus == (uchar_t)-1)
464 			break; /* root bus already */
465 	}
466 
467 	if (pci_bus_res[res_bus].io_ports) {
468 		addr = memlist_find(&pci_bus_res[res_bus].io_ports,
469 		    size, align);
470 		if (addr) {
471 			memlist_insert(&pci_bus_res[res_bus].io_ports_used,
472 			    addr, size);
473 
474 			/* free the old resource */
475 			memlist_free_all(&pci_bus_res[bus].io_ports);
476 			memlist_free_all(&pci_bus_res[bus].io_ports_used);
477 
478 			/* add the new resource */
479 			memlist_insert(&pci_bus_res[bus].io_ports, addr, size);
480 		}
481 	}
482 
483 	return (addr);
484 }
485 
486 static uint64_t
487 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
488 {
489 	uint64_t addr = 0;
490 	uchar_t res_bus;
491 
492 	/*
493 	 * Skip root(peer) buses in multiple-root-bus systems when
494 	 * ACPI resource discovery was not successfully done.
495 	 */
496 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
497 	    (num_root_bus > 1) && (acpi_resource_discovery <= 0))
498 		return (0);
499 
500 	res_bus = parbus;
501 	while (pci_bus_res[res_bus].subtractive) {
502 		if (pci_bus_res[res_bus].mem_space)
503 			break;
504 		res_bus = pci_bus_res[res_bus].par_bus;
505 		if (res_bus == (uchar_t)-1)
506 			break; /* root bus already */
507 	}
508 
509 	if (pci_bus_res[res_bus].mem_space) {
510 		addr = memlist_find(&pci_bus_res[res_bus].mem_space,
511 		    size, align);
512 		if (addr) {
513 			memlist_insert(&pci_bus_res[res_bus].mem_space_used,
514 			    addr, size);
515 			(void) memlist_remove(&pci_bus_res[res_bus].pmem_space,
516 			    addr, size);
517 
518 			/* free the old resource */
519 			memlist_free_all(&pci_bus_res[bus].mem_space);
520 			memlist_free_all(&pci_bus_res[bus].mem_space_used);
521 
522 			/* add the new resource */
523 			memlist_insert(&pci_bus_res[bus].mem_space, addr, size);
524 		}
525 	}
526 
527 	return (addr);
528 }
529 
530 /*
531  * given a cap_id, return its cap_id location in config space
532  */
533 static int
534 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id)
535 {
536 	uint8_t curcap, cap_id_loc;
537 	uint16_t status;
538 	int location = -1;
539 
540 	/*
541 	 * Need to check the Status register for ECP support first.
542 	 * Also please note that for type 1 devices, the
543 	 * offset could change. Should support type 1 next.
544 	 */
545 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
546 	if (!(status & PCI_STAT_CAP)) {
547 		return (-1);
548 	}
549 	cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
550 
551 	/* Walk the list of capabilities */
552 	while (cap_id_loc && cap_id_loc != (uint8_t)-1) {
553 		curcap = pci_getb(bus, dev, func, cap_id_loc);
554 
555 		if (curcap == cap_id) {
556 			location = cap_id_loc;
557 			break;
558 		}
559 		cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1);
560 	}
561 	return (location);
562 }
563 
564 /*
565  * Assign valid resources to unconfigured pci(e) bridges. We are trying
566  * to reprogram the bridge when its
567  * 		i)   SECBUS == SUBBUS	||
568  * 		ii)  IOBASE > IOLIM	||
569  * 		iii) MEMBASE > MEMLIM
570  * This must be done after one full pass through the PCI tree to collect
571  * all BIOS-configured resources, so that we know what resources are
572  * free and available to assign to the unconfigured PPBs.
573  */
574 static void
575 fix_ppb_res(uchar_t secbus, boolean_t prog_sub)
576 {
577 	uchar_t bus, dev, func;
578 	uchar_t parbus, subbus;
579 	uint_t io_base, io_limit, mem_base, mem_limit;
580 	uint_t io_size, mem_size;
581 	uint64_t addr = 0;
582 	int *regp = NULL;
583 	uint_t reglen;
584 	int rv, cap_ptr, physhi;
585 	dev_info_t *dip;
586 	uint16_t cmd_reg;
587 	struct memlist *list;
588 
589 	/* skip root (peer) PCI busses */
590 	if (pci_bus_res[secbus].par_bus == (uchar_t)-1)
591 		return;
592 
593 	/* skip subtractive PPB when prog_sub is not TRUE */
594 	if (pci_bus_res[secbus].subtractive && !prog_sub)
595 		return;
596 
597 	/* some entries may be empty due to discontiguous bus numbering */
598 	dip = pci_bus_res[secbus].dip;
599 	if (dip == NULL)
600 		return;
601 
602 	rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
603 	    "reg", &regp, &reglen);
604 	ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0);
605 	physhi = regp[0];
606 	ddi_prop_free(regp);
607 
608 	func = (uchar_t)PCI_REG_FUNC_G(physhi);
609 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
610 	bus = (uchar_t)PCI_REG_BUS_G(physhi);
611 
612 	/*
613 	 * If pcie bridge, check to see if link is enabled
614 	 */
615 	cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E);
616 	if (cap_ptr != -1) {
617 		cmd_reg = pci_getw(bus, dev, func,
618 		    (uint16_t)cap_ptr + PCIE_LINKCTL);
619 		if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
620 			dcmn_err(CE_NOTE,
621 			    "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n",
622 			    bus, dev, func);
623 			return;
624 		}
625 	}
626 
627 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
628 	parbus = pci_bus_res[secbus].par_bus;
629 	ASSERT(parbus == bus);
630 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
631 
632 	/*
633 	 * If we have a Cardbus bridge, but no bus space
634 	 */
635 	if (pci_bus_res[secbus].num_cbb != 0 &&
636 	    pci_bus_res[secbus].bus_space == NULL) {
637 		uchar_t range;
638 
639 		/* normally there are 2 buses under a cardbus bridge */
640 		range = pci_bus_res[secbus].num_cbb * 2;
641 
642 		/*
643 		 * Try to find and allocate a bus-range starting at subbus+1
644 		 * from the parent of the PPB.
645 		 */
646 		for (; range != 0; range--) {
647 			if (memlist_find_with_startaddr(
648 			    &pci_bus_res[parbus].bus_space,
649 			    subbus + 1, range, 1) != NULL)
650 				break; /* find bus range resource at parent */
651 		}
652 		if (range != 0) {
653 			memlist_insert(&pci_bus_res[secbus].bus_space,
654 			    subbus + 1, range);
655 			subbus = subbus + range;
656 			pci_bus_res[secbus].sub_bus = subbus;
657 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
658 			add_bus_range_prop(secbus);
659 
660 			cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
661 			    "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
662 			    secbus, subbus);
663 		}
664 	}
665 
666 	/*
667 	 * Calculate required IO size
668 	 * We are going to assign 512 bytes per bus. The size needs to be
669 	 * 4K aligned and the maximum size is 16K.
670 	 */
671 	io_size = (subbus - secbus + 1) * 0x200;
672 	io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1));
673 	if (io_size > 0x4 * PPB_IO_ALIGNMENT)
674 		io_size = 0x4 * PPB_IO_ALIGNMENT;
675 	/*
676 	 * Calculate required MEM size
677 	 * We are going to assign 1M bytes per bus. The size needs to be
678 	 * 1M aligned and the maximum size is 8M.
679 	 */
680 	mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT;
681 	if (mem_size > 0x8 * PPB_MEM_ALIGNMENT)
682 		mem_size = 0x8 * PPB_MEM_ALIGNMENT;
683 
684 	/* Subtractive bridge */
685 	if (pci_bus_res[secbus].subtractive && prog_sub) {
686 		/*
687 		 * We program an arbitrary amount of I/O and memory resource
688 		 * for the subtractive bridge so that child dynamic-resource-
689 		 * allocating devices (such as Cardbus bridges) have a chance
690 		 * of success.  Until we have full-tree resource rebalancing,
691 		 * dynamic resource allocation (thru busra) only looks at the
692 		 * parent bridge, so all PPBs must have some allocatable
693 		 * resource.  For non-subtractive bridges, the resources come
694 		 * from the base/limit register "windows", but subtractive
695 		 * bridges often don't program those (since they don't need to).
696 		 * If we put all the remaining resources on the subtractive
697 		 * bridge, then peer non-subtractive bridges can't allocate
698 		 * more space (even though this is probably most correct).
699 		 * If we put the resources only on the parent, then allocations
700 		 * from children of subtractive bridges will fail without
701 		 * special-case code for bypassing the subtractive bridge.
702 		 * This solution is the middle-ground temporary solution until
703 		 * we have fully-capable resource allocation.
704 		 */
705 
706 		/*
707 		 * Add an arbitrary I/O resource to the subtractive PPB
708 		 */
709 		if (pci_bus_res[secbus].io_ports == NULL) {
710 			addr = get_parbus_io_res(parbus, secbus, io_size,
711 			    PPB_IO_ALIGNMENT);
712 			if (addr) {
713 				add_ranges_prop(secbus, 1);
714 				pci_bus_res[secbus].io_reprogram =
715 				    pci_bus_res[parbus].io_reprogram;
716 
717 				cmn_err(CE_NOTE, "!add io-range on subtractive"
718 				    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
719 				    bus, dev, func, (uint32_t)addr,
720 				    (uint32_t)addr + io_size - 1);
721 			}
722 		}
723 		/*
724 		 * Add an arbitrary memory resource to the subtractive PPB
725 		 */
726 		if (pci_bus_res[secbus].mem_space == NULL) {
727 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
728 			    PPB_MEM_ALIGNMENT);
729 			if (addr) {
730 				add_ranges_prop(secbus, 1);
731 				pci_bus_res[secbus].mem_reprogram =
732 				    pci_bus_res[parbus].mem_reprogram;
733 
734 				cmn_err(CE_NOTE, "!add mem-range on "
735 				    "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
736 				    bus, dev, func, (uint32_t)addr,
737 				    (uint32_t)addr + mem_size - 1);
738 			}
739 		}
740 
741 		goto cmd_enable;
742 	}
743 
744 	/*
745 	 * Check to see if we need to reprogram I/O space, either because the
746 	 * parent bus needed reprogramming and so do we, or because I/O space is
747 	 * disabled in base/limit or command register.
748 	 */
749 	io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
750 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
751 	io_base = (io_base & 0xf0) << 8;
752 	io_limit = ((io_limit & 0xf0) << 8) | 0xfff;
753 
754 	if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) ||
755 	    (!(cmd_reg & PCI_COMM_IO))) {
756 		if (pci_bus_res[secbus].io_ports_used) {
757 			memlist_merge(&pci_bus_res[secbus].io_ports_used,
758 			    &pci_bus_res[secbus].io_ports);
759 		}
760 		if (pci_bus_res[secbus].io_ports &&
761 		    (!pci_bus_res[parbus].io_reprogram) &&
762 		    (!pci_bus_res[parbus].subtractive)) {
763 			/* rechoose old io ports info */
764 			list = pci_bus_res[secbus].io_ports;
765 			io_base = (uint_t)list->address;
766 			/* 4K aligned */
767 			io_base = io_base & (~(PPB_IO_ALIGNMENT - 1));
768 			io_limit = (uint_t)(list->address + list->size);
769 			while (list->next) {
770 				list = list->next;
771 				if ((list->address + list->size) > io_limit)
772 					io_limit = (uint_t)
773 					    (list->address + list->size);
774 			}
775 			io_limit = io_limit - 1;
776 			/* 4K aligned */
777 			io_limit = (io_limit + PPB_IO_ALIGNMENT) &
778 			    (~(PPB_IO_ALIGNMENT - 1));
779 			io_size = io_limit - io_base;
780 			io_limit = io_limit - 1;
781 			ASSERT(io_base <= io_limit);
782 			memlist_free_all(&pci_bus_res[secbus].io_ports);
783 			memlist_insert(&pci_bus_res[secbus].io_ports,
784 			    io_base, io_size);
785 			memlist_insert(&pci_bus_res[parbus].io_ports_used,
786 			    io_base, io_size);
787 			(void) memlist_remove(&pci_bus_res[parbus].io_ports,
788 			    io_base, io_size);
789 			pci_bus_res[secbus].io_reprogram = B_TRUE;
790 		} else {
791 			/* get new io ports from parent bus */
792 			addr = get_parbus_io_res(parbus, secbus, io_size,
793 			    PPB_IO_ALIGNMENT);
794 			if (addr) {
795 				io_base = addr;
796 				io_limit = addr + io_size - 1;
797 				pci_bus_res[secbus].io_reprogram = B_TRUE;
798 			}
799 		}
800 		if (pci_bus_res[secbus].io_reprogram) {
801 			/* reprogram PPB regs */
802 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
803 			    (uchar_t)((io_base>>8) & 0xf0));
804 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
805 			    (uchar_t)((io_limit>>8) & 0xf0));
806 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
807 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
808 			add_ranges_prop(secbus, 1);
809 
810 			cmn_err(CE_NOTE, "!reprogram io-range on"
811 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
812 			    bus, dev, func, io_base, io_limit);
813 		}
814 	}
815 
816 	/*
817 	 * Check memory space as we did I/O space.
818 	 */
819 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
820 	mem_base = (mem_base & 0xfff0) << 16;
821 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
822 	mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff;
823 
824 	if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) ||
825 	    (!(cmd_reg & PCI_COMM_MAE))) {
826 		if (pci_bus_res[secbus].mem_space_used) {
827 			memlist_merge(&pci_bus_res[secbus].mem_space_used,
828 			    &pci_bus_res[secbus].mem_space);
829 		}
830 		if (pci_bus_res[secbus].mem_space &&
831 		    (!pci_bus_res[parbus].mem_reprogram) &&
832 		    (!pci_bus_res[parbus].subtractive)) {
833 			/* rechoose old mem resource */
834 			list = pci_bus_res[secbus].mem_space;
835 			mem_base = (uint_t)list->address;
836 			/* 1M aligned */
837 			mem_base = mem_base & (~0xfffff);
838 			mem_limit = (uint_t)(list->address + list->size);
839 			while (list->next) {
840 				list = list->next;
841 				if ((list->address + list->size) > mem_limit)
842 					mem_limit = (uint_t)
843 					    (list->address + list->size);
844 			}
845 			mem_limit = mem_limit - 1;
846 			/* 1M aligned */
847 			mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) &
848 			    (~(PPB_MEM_ALIGNMENT - 1));
849 			mem_size = mem_limit - mem_base;
850 			mem_limit = mem_limit - 1;
851 			ASSERT(mem_base <= mem_limit);
852 			memlist_free_all(&pci_bus_res[secbus].mem_space);
853 			memlist_insert(&pci_bus_res[secbus].mem_space,
854 			    mem_base, mem_size);
855 			memlist_insert(&pci_bus_res[parbus].mem_space_used,
856 			    mem_base, mem_size);
857 			(void) memlist_remove(&pci_bus_res[parbus].mem_space,
858 			    mem_base, mem_size);
859 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
860 		} else {
861 			/* get new mem resource from parent bus */
862 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
863 			    PPB_MEM_ALIGNMENT);
864 			if (addr) {
865 				mem_base = addr;
866 				mem_limit = addr + mem_size - 1;
867 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
868 			}
869 		}
870 
871 		if (pci_bus_res[secbus].mem_reprogram) {
872 			/* reprogram PPB regs */
873 			pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
874 			    (uint16_t)((mem_base>>16) & 0xfff0));
875 			pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
876 			    (uint16_t)((mem_limit>>16) & 0xfff0));
877 			add_ranges_prop(secbus, 1);
878 
879 			cmn_err(CE_NOTE, "!reprogram mem-range on"
880 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
881 			    bus, dev, func, mem_base, mem_limit);
882 		}
883 	}
884 
885 cmd_enable:
886 	if (pci_bus_res[secbus].io_ports)
887 		cmd_reg |= PCI_COMM_IO | PCI_COMM_ME;
888 	if (pci_bus_res[secbus].mem_space)
889 		cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME;
890 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
891 }
892 
893 void
894 pci_reprogram(void)
895 {
896 	int i, pci_reconfig = 1;
897 	char *onoff;
898 	int bus;
899 
900 	/*
901 	 * Excise phantom roots if possible
902 	 */
903 	pci_renumber_root_busses();
904 
905 	/*
906 	 * Do root-bus resource discovery
907 	 */
908 	for (bus = 0; bus <= pci_bios_nbus; bus++) {
909 		/* skip non-root (peer) PCI busses */
910 		if (pci_bus_res[bus].par_bus != (uchar_t)-1)
911 			continue;
912 
913 		/*
914 		 * 1. find resources associated with this root bus
915 		 */
916 		populate_bus_res(bus);
917 
918 
919 		/*
920 		 * 2. Remove the used resource lists from the bus resources
921 		 */
922 
923 		memlist_remove_list(&pci_bus_res[bus].io_ports,
924 		    pci_bus_res[bus].io_ports_used);
925 		memlist_remove_list(&pci_bus_res[bus].mem_space,
926 		    pci_bus_res[bus].mem_space_used);
927 		memlist_remove_list(&pci_bus_res[bus].pmem_space,
928 		    pci_bus_res[bus].pmem_space_used);
929 		memlist_remove_list(&pci_bus_res[bus].mem_space,
930 		    pci_bus_res[bus].pmem_space_used);
931 		memlist_remove_list(&pci_bus_res[bus].pmem_space,
932 		    pci_bus_res[bus].mem_space_used);
933 	}
934 
935 
936 	/* add bus-range property for root/peer bus nodes */
937 	for (i = 0; i <= pci_bios_nbus; i++) {
938 		/* create bus-range property on root/peer buses */
939 		if (pci_bus_res[i].par_bus == (uchar_t)-1)
940 			add_bus_range_prop(i);
941 
942 		/* setup bus range resource on each bus */
943 		setup_bus_res(i);
944 	}
945 
946 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(),
947 	    DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) {
948 		if (strcmp(onoff, "off") == 0) {
949 			pci_reconfig = 0;
950 			cmn_err(CE_NOTE, "pci device reprogramming disabled");
951 		}
952 		ddi_prop_free(onoff);
953 	}
954 
955 	/* remove used-resources from PCI resource maps */
956 	remove_used_resources();
957 	remove_subtractive_res();
958 
959 	/* reprogram the non-subtractive PPB */
960 	if (pci_reconfig)
961 		for (i = 0; i <= pci_bios_nbus; i++)
962 			fix_ppb_res(i, B_FALSE);
963 
964 	for (i = 0; i <= pci_bios_nbus; i++) {
965 		/* configure devices not configured by BIOS */
966 		if (pci_reconfig) {
967 			/*
968 			 * Reprogram the subtractive PPB. At this time, all its
969 			 * siblings should have got their resources already.
970 			 */
971 			if (pci_bus_res[i].subtractive)
972 				fix_ppb_res(i, B_TRUE);
973 			enumerate_bus_devs(i, CONFIG_NEW);
974 		}
975 	}
976 
977 	/* All dev programmed, so we can create available prop */
978 	for (i = 0; i <= pci_bios_nbus; i++)
979 		add_bus_available_prop(i);
980 }
981 
982 /*
983  * populate bus resources
984  */
985 static void
986 populate_bus_res(uchar_t bus)
987 {
988 
989 	/* scan BIOS structures */
990 	pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE);
991 	pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE);
992 	pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE);
993 	pci_bus_res[bus].bus_space = find_bus_res(bus, BUSRANGE_TYPE);
994 
995 	/*
996 	 * attempt to initialize sub_bus from the largest range-end
997 	 * in the bus_space list
998 	 */
999 	if (pci_bus_res[bus].bus_space != NULL) {
1000 		struct memlist *entry;
1001 		int current;
1002 
1003 		entry = pci_bus_res[bus].bus_space;
1004 		while (entry != NULL) {
1005 			current = entry->address + entry->size - 1;
1006 			if (current > pci_bus_res[bus].sub_bus)
1007 				pci_bus_res[bus].sub_bus = current;
1008 			entry = entry->next;
1009 		}
1010 	}
1011 
1012 	if (bus == 0) {
1013 		/*
1014 		 * Special treatment of bus 0:
1015 		 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy
1016 		 * pcimem from boot and make I/O space the entire range
1017 		 * starting at 0x100.
1018 		 */
1019 		if (pci_bus_res[0].mem_space == NULL)
1020 			pci_bus_res[0].mem_space =
1021 			    memlist_dup(bootops->boot_mem->pcimem);
1022 		/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
1023 		if (pci_bus_res[0].io_ports == NULL)
1024 			memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff);
1025 	}
1026 
1027 	/*
1028 	 * Create 'ranges' property here before any resources are
1029 	 * removed from the resource lists
1030 	 */
1031 	add_ranges_prop(bus, 0);
1032 }
1033 
1034 
1035 /*
1036  * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
1037  */
1038 static void
1039 create_root_bus_dip(uchar_t bus)
1040 {
1041 	int pci_regs[] = {0, 0, 0};
1042 	dev_info_t *dip;
1043 
1044 	ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
1045 
1046 	num_root_bus++;
1047 	ndi_devi_alloc_sleep(ddi_root_node(), "pci",
1048 	    (pnode_t)DEVI_SID_NODEID, &dip);
1049 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1050 	    "#address-cells", 3);
1051 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1052 	    "#size-cells", 2);
1053 	pci_regs[0] = pci_bus_res[bus].root_addr;
1054 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1055 	    "reg", (int *)pci_regs, 3);
1056 
1057 	/*
1058 	 * If system has PCIe bus, then create different properties
1059 	 */
1060 	if (create_pcie_root_bus(bus, dip) == B_FALSE)
1061 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1062 		    "device_type", "pci");
1063 
1064 	(void) ndi_devi_bind_driver(dip, 0);
1065 	pci_bus_res[bus].dip = dip;
1066 }
1067 
1068 /*
1069  * For any fixed configuration (often compatability) pci devices
1070  * and those with their own expansion rom, create device nodes
1071  * to hold the already configured device details.
1072  */
1073 void
1074 enumerate_bus_devs(uchar_t bus, int config_op)
1075 {
1076 	uchar_t dev, func, nfunc, header;
1077 	ushort_t venid;
1078 	struct pci_devfunc *devlist = NULL, *entry;
1079 
1080 	if (config_op == CONFIG_NEW) {
1081 		dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1082 	} else if (config_op == CONFIG_FIX) {
1083 		dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus);
1084 	} else
1085 		dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
1086 
1087 	if (config_op == CONFIG_NEW) {
1088 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1089 		while (devlist) {
1090 			entry = devlist;
1091 			devlist = entry->next;
1092 			if (entry->reprogram ||
1093 			    pci_bus_res[bus].io_reprogram ||
1094 			    pci_bus_res[bus].mem_reprogram) {
1095 				/* reprogram device(s) */
1096 				(void) add_reg_props(entry->dip, bus,
1097 				    entry->dev, entry->func, CONFIG_NEW, 0);
1098 			}
1099 			kmem_free(entry, sizeof (*entry));
1100 		}
1101 		pci_bus_res[bus].privdata = NULL;
1102 		return;
1103 	}
1104 
1105 	for (dev = 0; dev < max_dev_pci; dev++) {
1106 		nfunc = 1;
1107 		for (func = 0; func < nfunc; func++) {
1108 
1109 			dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x",
1110 			    dev, func);
1111 
1112 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1113 
1114 			if ((venid == 0xffff) || (venid == 0)) {
1115 				/* no function at this address */
1116 				continue;
1117 			}
1118 
1119 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1120 			if (header == 0xff) {
1121 				continue; /* illegal value */
1122 			}
1123 
1124 			/*
1125 			 * according to some mail from Microsoft posted
1126 			 * to the pci-drivers alias, their only requirement
1127 			 * for a multifunction device is for the 1st
1128 			 * function to have to PCI_HEADER_MULTI bit set.
1129 			 */
1130 			if ((func == 0) && (header & PCI_HEADER_MULTI)) {
1131 				nfunc = 8;
1132 			}
1133 
1134 			if (config_op == CONFIG_FIX ||
1135 			    config_op == CONFIG_INFO) {
1136 				/*
1137 				 * Create the node, unconditionally, on the
1138 				 * first pass only.  It may still need
1139 				 * resource assignment, which will be
1140 				 * done on the second, CONFIG_NEW, pass.
1141 				 */
1142 				process_devfunc(bus, dev, func, header,
1143 				    venid, config_op);
1144 
1145 			}
1146 		}
1147 	}
1148 
1149 	/* percolate bus used resources up through parents to root */
1150 	if (config_op == CONFIG_INFO) {
1151 		int	par_bus;
1152 
1153 		par_bus = pci_bus_res[bus].par_bus;
1154 		while (par_bus != (uchar_t)-1) {
1155 
1156 			if (pci_bus_res[bus].io_ports_used)
1157 				memlist_merge(&pci_bus_res[bus].io_ports_used,
1158 				    &pci_bus_res[par_bus].io_ports_used);
1159 
1160 			if (pci_bus_res[bus].mem_space_used)
1161 				memlist_merge(&pci_bus_res[bus].mem_space_used,
1162 				    &pci_bus_res[par_bus].mem_space_used);
1163 
1164 			if (pci_bus_res[bus].pmem_space_used)
1165 				memlist_merge(&pci_bus_res[bus].pmem_space_used,
1166 				    &pci_bus_res[par_bus].pmem_space_used);
1167 
1168 			par_bus = pci_bus_res[par_bus].par_bus;
1169 		}
1170 	}
1171 }
1172 
1173 static int
1174 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid,
1175     ushort_t subvenid, ushort_t subdevid)
1176 {
1177 	static int prop_exist = -1;
1178 	static char *pciide_str;
1179 	char compat[32];
1180 
1181 	if (prop_exist == -1) {
1182 		prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY,
1183 		    ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide",
1184 		    &pciide_str) == DDI_SUCCESS);
1185 	}
1186 
1187 	if (!prop_exist)
1188 		return (0);
1189 
1190 	/* compare property value against various forms of compatible */
1191 	if (subvenid) {
1192 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x",
1193 		    venid, devid, subvenid, subdevid, revid);
1194 		if (strcmp(pciide_str, compat) == 0)
1195 			return (1);
1196 
1197 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x",
1198 		    venid, devid, subvenid, subdevid);
1199 		if (strcmp(pciide_str, compat) == 0)
1200 			return (1);
1201 
1202 		(void) snprintf(compat, sizeof (compat), "pci%x,%x",
1203 		    subvenid, subdevid);
1204 		if (strcmp(pciide_str, compat) == 0)
1205 			return (1);
1206 	}
1207 	(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x",
1208 	    venid, devid, revid);
1209 	if (strcmp(pciide_str, compat) == 0)
1210 		return (1);
1211 
1212 	(void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid);
1213 	if (strcmp(pciide_str, compat) == 0)
1214 		return (1);
1215 
1216 	return (0);
1217 }
1218 
1219 static int
1220 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid,
1221     ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid)
1222 {
1223 	struct ide_table {	/* table for PCI_MASS_OTHER */
1224 		ushort_t venid;
1225 		ushort_t devid;
1226 	} *entry;
1227 
1228 	/* XXX SATA and other devices: need a way to add dynamically */
1229 	static struct ide_table ide_other[] = {
1230 		{0x1095, 0x3112},
1231 		{0x1095, 0x3114},
1232 		{0x1095, 0x3512},
1233 		{0x1095, 0x680},	/* Sil0680 */
1234 		{0x1283, 0x8211},	/* ITE 8211F is subcl PCI_MASS_OTHER */
1235 		{0, 0}
1236 	};
1237 
1238 	if (basecl != PCI_CLASS_MASS)
1239 		return (0);
1240 
1241 	if (subcl == PCI_MASS_IDE) {
1242 		return (1);
1243 	}
1244 
1245 	if (check_pciide_prop(revid, venid, devid, subvenid, subdevid))
1246 		return (1);
1247 
1248 	if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) {
1249 		return (0);
1250 	}
1251 
1252 	entry = &ide_other[0];
1253 	while (entry->venid) {
1254 		if (entry->venid == venid && entry->devid == devid)
1255 			return (1);
1256 		entry++;
1257 	}
1258 	return (0);
1259 }
1260 
1261 static int
1262 is_display(uint_t classcode)
1263 {
1264 	static uint_t disp_classes[] = {
1265 		0x000100,
1266 		0x030000,
1267 		0x030001
1268 	};
1269 	int i, nclasses = sizeof (disp_classes) / sizeof (uint_t);
1270 
1271 	for (i = 0; i < nclasses; i++) {
1272 		if (classcode == disp_classes[i])
1273 			return (1);
1274 	}
1275 	return (0);
1276 }
1277 
1278 static void
1279 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1280     void (*undofn)(uint8_t, uint8_t, uint8_t))
1281 {
1282 	struct pci_fixundo *newundo;
1283 
1284 	newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP);
1285 
1286 	/*
1287 	 * Adding an item to this list means that we must turn its NMIENABLE
1288 	 * bit back on at a later time.
1289 	 */
1290 	newundo->bus = bus;
1291 	newundo->dev = dev;
1292 	newundo->fn = fn;
1293 	newundo->undofn = undofn;
1294 	newundo->next = undolist;
1295 
1296 	/* add to the undo list in LIFO order */
1297 	undolist = newundo;
1298 }
1299 
1300 void
1301 add_pci_fixes(void)
1302 {
1303 	int i;
1304 
1305 	for (i = 0; i <= pci_bios_nbus; i++) {
1306 		/*
1307 		 * For each bus, apply needed fixes to the appropriate devices.
1308 		 * This must be done before the main enumeration loop because
1309 		 * some fixes must be applied to devices normally encountered
1310 		 * later in the pci scan (e.g. if a fix to device 7 must be
1311 		 * applied before scanning device 6, applying fixes in the
1312 		 * normal enumeration loop would obviously be too late).
1313 		 */
1314 		enumerate_bus_devs(i, CONFIG_FIX);
1315 	}
1316 }
1317 
1318 void
1319 undo_pci_fixes(void)
1320 {
1321 	struct pci_fixundo *nextundo;
1322 	uint8_t bus, dev, fn;
1323 
1324 	/*
1325 	 * All fixes in the undo list are performed unconditionally.  Future
1326 	 * fixes may require selective undo.
1327 	 */
1328 	while (undolist != NULL) {
1329 
1330 		bus = undolist->bus;
1331 		dev = undolist->dev;
1332 		fn = undolist->fn;
1333 
1334 		(*(undolist->undofn))(bus, dev, fn);
1335 
1336 		nextundo = undolist->next;
1337 		kmem_free(undolist, sizeof (struct pci_fixundo));
1338 		undolist = nextundo;
1339 	}
1340 }
1341 
1342 static void
1343 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1344 {
1345 	uint8_t val8;
1346 
1347 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1348 	/*
1349 	 * The NMIONERR bit is turned back on to allow the SMM BIOS
1350 	 * to handle more critical PCI errors (e.g. PERR#).
1351 	 */
1352 	val8 |= AMD8111_ENABLENMI;
1353 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1354 }
1355 
1356 static void
1357 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1358 {
1359 	uint8_t val8;
1360 
1361 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1362 
1363 	if ((val8 & AMD8111_ENABLENMI) == 0)
1364 		return;
1365 
1366 	/*
1367 	 * We reset NMIONERR in the LPC because master-abort on the PCI
1368 	 * bridge side of the 8111 will cause NMI, which might cause SMI,
1369 	 * which sometimes prevents all devices from being enumerated.
1370 	 */
1371 	val8 &= ~AMD8111_ENABLENMI;
1372 
1373 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1374 
1375 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1376 }
1377 
1378 static void
1379 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1380 {
1381 	uint16_t status;
1382 	uint8_t header;
1383 	uint8_t cap_ptr;
1384 	uint8_t cap_id;
1385 	uint16_t pmcsr;
1386 
1387 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1388 	if (!(status & PCI_STAT_CAP))
1389 		return;	/* No capabilities list */
1390 
1391 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1392 	if (header == PCI_HEADER_CARDBUS)
1393 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_RESERVED1);
1394 	else
1395 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1396 	/*
1397 	 * Walk the capabilities list searching for a PM entry.
1398 	 */
1399 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {
1400 		cap_ptr &= PCI_CAP_PTR_MASK;
1401 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1402 		if (cap_id == PCI_CAP_ID_PM) {
1403 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1404 			pmcsr &= ~(PCI_PMCSR_STATE_MASK);
1405 			pmcsr |= PCI_PMCSR_D0; /* D0 state */
1406 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1407 			break;
1408 		}
1409 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1410 	}
1411 
1412 }
1413 
1414 static void
1415 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
1416     ushort_t vendorid, int config_op)
1417 {
1418 	char nodename[32], unitaddr[5];
1419 	dev_info_t *dip;
1420 	uchar_t basecl, subcl, progcl, intr, revid;
1421 	ushort_t subvenid, subdevid, status;
1422 	ushort_t slot_num;
1423 	uint_t classcode, revclass;
1424 	int reprogram = 0, pciide = 0;
1425 	int power[2] = {1, 1};
1426 	int pciex = 0;
1427 	ushort_t is_pci_bridge = 0;
1428 	struct pci_devfunc *devlist = NULL, *entry = NULL;
1429 	iommu_private_t *private;
1430 	gfx_entry_t *gfxp;
1431 
1432 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
1433 
1434 	switch (header & PCI_HEADER_TYPE_M) {
1435 	case PCI_HEADER_ZERO:
1436 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
1437 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
1438 		break;
1439 	case PCI_HEADER_CARDBUS:
1440 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
1441 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
1442 		/* Record the # of cardbus bridges found on the bus */
1443 		if (config_op == CONFIG_INFO)
1444 			pci_bus_res[bus].num_cbb++;
1445 		break;
1446 	default:
1447 		subvenid = 0;
1448 		subdevid = 0;
1449 		break;
1450 	}
1451 
1452 	if (config_op == CONFIG_FIX) {
1453 		if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) {
1454 			pci_fix_amd8111(bus, dev, func);
1455 		}
1456 		return;
1457 	}
1458 
1459 	/* XXX should be use generic names? derive from class? */
1460 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
1461 	classcode = revclass >> 8;
1462 	revid = revclass & 0xff;
1463 
1464 	/* figure out if this is pci-ide */
1465 	basecl = classcode >> 16;
1466 	subcl = (classcode >> 8) & 0xff;
1467 	progcl = classcode & 0xff;
1468 
1469 
1470 	if (is_display(classcode))
1471 		(void) snprintf(nodename, sizeof (nodename), "display");
1472 	else if (subvenid != 0)
1473 		(void) snprintf(nodename, sizeof (nodename),
1474 		    "pci%x,%x", subvenid, subdevid);
1475 	else
1476 		(void) snprintf(nodename, sizeof (nodename),
1477 		    "pci%x,%x", vendorid, deviceid);
1478 
1479 	/* make sure parent bus dip has been created */
1480 	if (pci_bus_res[bus].dip == NULL)
1481 		create_root_bus_dip(bus);
1482 
1483 	ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
1484 	    DEVI_SID_NODEID, &dip);
1485 
1486 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num,
1487 	    &is_pci_bridge) == B_TRUE)
1488 		pciex = 1;
1489 
1490 	/* add properties */
1491 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid);
1492 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid);
1493 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid);
1494 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1495 	    "class-code", classcode);
1496 	if (func == 0)
1497 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
1498 	else
1499 		(void) snprintf(unitaddr, sizeof (unitaddr),
1500 		    "%x,%x", dev, func);
1501 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1502 	    "unit-address", unitaddr);
1503 
1504 	/* add device_type for display nodes */
1505 	if (is_display(classcode)) {
1506 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1507 		    "device_type", "display");
1508 	}
1509 	/* add special stuff for header type */
1510 	if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
1511 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
1512 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
1513 
1514 		if (subvenid != 0) {
1515 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1516 			    "subsystem-id", subdevid);
1517 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1518 			    "subsystem-vendor-id", subvenid);
1519 		}
1520 		if (!pciex)
1521 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1522 			    "min-grant", mingrant);
1523 		if (!pciex)
1524 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1525 			    "max-latency", maxlatency);
1526 	}
1527 
1528 	/* interrupt, record if not 0 */
1529 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
1530 	if (intr != 0)
1531 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1532 		    "interrupts", intr);
1533 
1534 	/*
1535 	 * Add support for 133 mhz pci eventually
1536 	 */
1537 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1538 
1539 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1540 	    "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9);
1541 	if (!pciex && (status & PCI_STAT_FBBC))
1542 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1543 		    "fast-back-to-back");
1544 	if (!pciex && (status & PCI_STAT_66MHZ))
1545 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1546 		    "66mhz-capable");
1547 	if (status & PCI_STAT_UDF)
1548 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1549 		    "udf-supported");
1550 	if (pciex && slot_num) {
1551 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1552 		    "physical-slot#", slot_num);
1553 		if (!is_pci_bridge)
1554 			pciex_slot_names_prop(dip, slot_num);
1555 	}
1556 
1557 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1558 	    "power-consumption", power, 2);
1559 
1560 	/* Set the device PM state to D0 */
1561 	set_devpm_d0(bus, dev, func);
1562 
1563 	if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI))
1564 		add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge);
1565 	else {
1566 		/*
1567 		 * Record the non-PPB devices on the bus for possible
1568 		 * reprogramming at 2nd bus enumeration.
1569 		 * Note: PPB reprogramming is done in fix_ppb_res()
1570 		 */
1571 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1572 		entry = kmem_zalloc(sizeof (*entry), KM_SLEEP);
1573 		entry->dip = dip;
1574 		entry->dev = dev;
1575 		entry->func = func;
1576 		entry->next = devlist;
1577 		pci_bus_res[bus].privdata = entry;
1578 	}
1579 
1580 	if (config_op == CONFIG_INFO &&
1581 	    IS_CLASS_IOAPIC(basecl, subcl, progcl)) {
1582 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
1583 	}
1584 
1585 	/* check for ck8-04 based PCI ISA bridge only */
1586 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
1587 	    (func == 0))
1588 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
1589 
1590 	if (pciex && is_pci_bridge)
1591 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
1592 		    (char *)"PCIe-PCI bridge");
1593 	else
1594 		add_model_prop(dip, classcode);
1595 
1596 	add_compatible(dip, subvenid, subdevid, vendorid, deviceid,
1597 	    revid, classcode, pciex);
1598 
1599 	/*
1600 	 * See if this device is a controller that advertises
1601 	 * itself to be a standard ATA task file controller, or one that
1602 	 * has been hard coded.
1603 	 *
1604 	 * If it is, check if any other higher precedence driver listed in
1605 	 * driver_aliases will claim the node by calling
1606 	 * ddi_compatibile_driver_major.  If so, clear pciide and do not
1607 	 * create a pci-ide node or any other special handling.
1608 	 *
1609 	 * If another driver does not bind, set the node name to pci-ide
1610 	 * and then let the special pci-ide handling for registers and
1611 	 * child pci-ide nodes proceed below.
1612 	 */
1613 	if (is_pciide(basecl, subcl, revid, vendorid, deviceid,
1614 	    subvenid, subdevid) == 1) {
1615 		if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) {
1616 			(void) ndi_devi_set_nodename(dip, "pci-ide", 0);
1617 			pciide = 1;
1618 		}
1619 	}
1620 
1621 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
1622 	(void) ndi_devi_bind_driver(dip, 0);
1623 
1624 	/* special handling for pci-ide */
1625 	if (pciide) {
1626 		dev_info_t *cdip;
1627 
1628 		/*
1629 		 * Create properties specified by P1275 Working Group
1630 		 * Proposal #414 Version 1
1631 		 */
1632 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1633 		    "device_type", "pci-ide");
1634 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1635 		    "#address-cells", 1);
1636 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1637 		    "#size-cells", 0);
1638 
1639 		/* allocate two child nodes */
1640 		ndi_devi_alloc_sleep(dip, "ide",
1641 		    (pnode_t)DEVI_SID_NODEID, &cdip);
1642 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
1643 		    "reg", 0);
1644 		(void) ndi_devi_bind_driver(cdip, 0);
1645 		ndi_devi_alloc_sleep(dip, "ide",
1646 		    (pnode_t)DEVI_SID_NODEID, &cdip);
1647 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
1648 		    "reg", 1);
1649 		(void) ndi_devi_bind_driver(cdip, 0);
1650 
1651 		reprogram = 0;	/* don't reprogram pci-ide bridge */
1652 	}
1653 
1654 	/* allocate and set up iommu private */
1655 	private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP);
1656 	private->idp_seg = 0;
1657 	private->idp_bus = bus;
1658 	private->idp_devfn = (dev << 3) | func;
1659 	private->idp_sec = 0;
1660 	private->idp_sub = 0;
1661 	private->idp_bbp_type = IOMMU_PPB_NONE;
1662 	/* record the bridge */
1663 	private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) &&
1664 	    (subcl == PCI_BRIDGE_PCI));
1665 	if (private->idp_is_bridge) {
1666 		private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
1667 		private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
1668 		if (pciex && is_pci_bridge)
1669 			private->idp_bbp_type = IOMMU_PPB_PCIE_PCI;
1670 		else if (pciex)
1671 			private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE;
1672 		else
1673 			private->idp_bbp_type = IOMMU_PPB_PCI_PCI;
1674 	}
1675 	/* record the special devices */
1676 	private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE);
1677 	private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) &&
1678 	    (subcl == PCI_BRIDGE_ISA));
1679 	private->idp_intel_domain = NULL;
1680 	/* hook the private to dip */
1681 	DEVI(dip)->devi_iommu_private = private;
1682 
1683 	if (private->idp_is_display == B_TRUE) {
1684 		gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP);
1685 		gfxp->g_dip = dip;
1686 		gfxp->g_prev = NULL;
1687 		gfxp->g_next = gfx_devinfo_list;
1688 		gfx_devinfo_list = gfxp;
1689 		if (gfxp->g_next)
1690 			gfxp->g_next->g_prev = gfxp;
1691 	}
1692 
1693 	if (reprogram && (entry != NULL))
1694 		entry->reprogram = B_TRUE;
1695 }
1696 
1697 /*
1698  * Set the compatible property to a value compliant with
1699  * rev 2.1 of the IEEE1275 PCI binding.
1700  * (Also used for PCI-Express devices).
1701  *
1702  *   pciVVVV,DDDD.SSSS.ssss.RR	(0)
1703  *   pciVVVV,DDDD.SSSS.ssss	(1)
1704  *   pciSSSS,ssss		(2)
1705  *   pciVVVV,DDDD.RR		(3)
1706  *   pciVVVV,DDDD		(4)
1707  *   pciclass,CCSSPP		(5)
1708  *   pciclass,CCSS		(6)
1709  *
1710  * The Subsystem (SSSS) forms are not inserted if
1711  * subsystem-vendor-id is 0.
1712  *
1713  * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
1714  * property 2 is not created as per "1275 bindings for PCI Express Interconnect"
1715  *
1716  * Set with setprop and \x00 between each
1717  * to generate the encoded string array form.
1718  */
1719 void
1720 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid,
1721     ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode,
1722     int pciex)
1723 {
1724 	int i = 0;
1725 	int size = COMPAT_BUFSIZE;
1726 	char *compat[13];
1727 	char *buf, *curr;
1728 
1729 	curr = buf = kmem_alloc(size, KM_SLEEP);
1730 
1731 	if (pciex) {
1732 		if (subvenid) {
1733 			compat[i++] = curr;	/* form 0 */
1734 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x",
1735 			    vendorid, deviceid, subvenid, subdevid, revid);
1736 			size -= strlen(curr) + 1;
1737 			curr += strlen(curr) + 1;
1738 
1739 			compat[i++] = curr;	/* form 1 */
1740 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x",
1741 			    vendorid, deviceid, subvenid, subdevid);
1742 			size -= strlen(curr) + 1;
1743 			curr += strlen(curr) + 1;
1744 
1745 		}
1746 		compat[i++] = curr;	/* form 3 */
1747 		(void) snprintf(curr, size, "pciex%x,%x.%x",
1748 		    vendorid, deviceid, revid);
1749 		size -= strlen(curr) + 1;
1750 		curr += strlen(curr) + 1;
1751 
1752 		compat[i++] = curr;	/* form 4 */
1753 		(void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid);
1754 		size -= strlen(curr) + 1;
1755 		curr += strlen(curr) + 1;
1756 
1757 		compat[i++] = curr;	/* form 5 */
1758 		(void) snprintf(curr, size, "pciexclass,%06x", classcode);
1759 		size -= strlen(curr) + 1;
1760 		curr += strlen(curr) + 1;
1761 
1762 		compat[i++] = curr;	/* form 6 */
1763 		(void) snprintf(curr, size, "pciexclass,%04x",
1764 		    (classcode >> 8));
1765 		size -= strlen(curr) + 1;
1766 		curr += strlen(curr) + 1;
1767 	}
1768 
1769 	if (subvenid) {
1770 		compat[i++] = curr;	/* form 0 */
1771 		(void) snprintf(curr, size, "pci%x,%x.%x.%x.%x",
1772 		    vendorid, deviceid, subvenid, subdevid, revid);
1773 		size -= strlen(curr) + 1;
1774 		curr += strlen(curr) + 1;
1775 
1776 		compat[i++] = curr;	/* form 1 */
1777 		(void) snprintf(curr, size, "pci%x,%x.%x.%x",
1778 		    vendorid, deviceid, subvenid, subdevid);
1779 		size -= strlen(curr) + 1;
1780 		curr += strlen(curr) + 1;
1781 
1782 		compat[i++] = curr;	/* form 2 */
1783 		(void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid);
1784 		size -= strlen(curr) + 1;
1785 		curr += strlen(curr) + 1;
1786 	}
1787 	compat[i++] = curr;	/* form 3 */
1788 	(void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid);
1789 	size -= strlen(curr) + 1;
1790 	curr += strlen(curr) + 1;
1791 
1792 	compat[i++] = curr;	/* form 4 */
1793 	(void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid);
1794 	size -= strlen(curr) + 1;
1795 	curr += strlen(curr) + 1;
1796 
1797 	compat[i++] = curr;	/* form 5 */
1798 	(void) snprintf(curr, size, "pciclass,%06x", classcode);
1799 	size -= strlen(curr) + 1;
1800 	curr += strlen(curr) + 1;
1801 
1802 	compat[i++] = curr;	/* form 6 */
1803 	(void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8));
1804 	size -= strlen(curr) + 1;
1805 	curr += strlen(curr) + 1;
1806 
1807 	(void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
1808 	    "compatible", compat, i);
1809 	kmem_free(buf, COMPAT_BUFSIZE);
1810 }
1811 
1812 /*
1813  * Adjust the reg properties for a dual channel PCI-IDE device.
1814  *
1815  * NOTE: don't do anything that changes the order of the hard-decodes
1816  * and programmed BARs. The kernel driver depends on these values
1817  * being in this order regardless of whether they're for a 'native'
1818  * mode BAR or not.
1819  */
1820 /*
1821  * config info for pci-ide devices
1822  */
1823 static struct {
1824 	uchar_t  native_mask;	/* 0 == 'compatibility' mode, 1 == native */
1825 	uchar_t  bar_offset;	/* offset for alt status register */
1826 	ushort_t addr;		/* compatibility mode base address */
1827 	ushort_t length;	/* number of ports for this BAR */
1828 } pciide_bar[] = {
1829 	{ 0x01, 0, 0x1f0, 8 },	/* primary lower BAR */
1830 	{ 0x01, 2, 0x3f6, 1 },	/* primary upper BAR */
1831 	{ 0x04, 0, 0x170, 8 },	/* secondary lower BAR */
1832 	{ 0x04, 2, 0x376, 1 }	/* secondary upper BAR */
1833 };
1834 
1835 static int
1836 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp)
1837 {
1838 	int hard_decode = 0;
1839 
1840 	/*
1841 	 * Adjust the base and len for the BARs of the PCI-IDE
1842 	 * device's primary and secondary controllers. The first
1843 	 * two BARs are for the primary controller and the next
1844 	 * two BARs are for the secondary controller. The fifth
1845 	 * and sixth bars are never adjusted.
1846 	 */
1847 	if (index >= 0 && index <= 3) {
1848 		*lenp = pciide_bar[index].length;
1849 
1850 		if (progcl & pciide_bar[index].native_mask) {
1851 			*basep += pciide_bar[index].bar_offset;
1852 		} else {
1853 			*basep = pciide_bar[index].addr;
1854 			hard_decode = 1;
1855 		}
1856 	}
1857 
1858 	/*
1859 	 * if either base or len is zero make certain both are zero
1860 	 */
1861 	if (*basep == 0 || *lenp == 0) {
1862 		*basep = 0;
1863 		*lenp = 0;
1864 		hard_decode = 0;
1865 	}
1866 
1867 	return (hard_decode);
1868 }
1869 
1870 
1871 /*
1872  * Add the "reg" and "assigned-addresses" property
1873  */
1874 static int
1875 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
1876     int config_op, int pciide)
1877 {
1878 	uchar_t baseclass, subclass, progclass, header;
1879 	ushort_t bar_sz;
1880 	uint_t value = 0, len, devloc;
1881 	uint_t base, base_hi, type;
1882 	ushort_t offset, end;
1883 	int max_basereg, j, reprogram = 0;
1884 	uint_t phys_hi;
1885 	struct memlist **io_res, **io_res_used;
1886 	struct memlist **mem_res, **mem_res_used;
1887 	struct memlist **pmem_res, **pmem_res_used;
1888 	uchar_t res_bus;
1889 
1890 	pci_regspec_t regs[16] = {{0}};
1891 	pci_regspec_t assigned[15] = {{0}};
1892 	int nreg, nasgn;
1893 
1894 	io_res = &pci_bus_res[bus].io_ports;
1895 	io_res_used = &pci_bus_res[bus].io_ports_used;
1896 	mem_res = &pci_bus_res[bus].mem_space;
1897 	mem_res_used = &pci_bus_res[bus].mem_space_used;
1898 	pmem_res = &pci_bus_res[bus].pmem_space;
1899 	pmem_res_used = &pci_bus_res[bus].pmem_space_used;
1900 
1901 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
1902 	regs[0].pci_phys_hi = devloc;
1903 	nreg = 1;	/* rest of regs[0] is all zero */
1904 	nasgn = 0;
1905 
1906 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
1907 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
1908 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
1909 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1910 
1911 	switch (header) {
1912 	case PCI_HEADER_ZERO:
1913 		max_basereg = PCI_BASE_NUM;
1914 		break;
1915 	case PCI_HEADER_PPB:
1916 		max_basereg = PCI_BCNF_BASE_NUM;
1917 		break;
1918 	case PCI_HEADER_CARDBUS:
1919 		max_basereg = PCI_CBUS_BASE_NUM;
1920 		break;
1921 	default:
1922 		max_basereg = 0;
1923 		break;
1924 	}
1925 
1926 	/*
1927 	 * Create the register property by saving the current
1928 	 * value of the base register. Write 0xffffffff to the
1929 	 * base register.  Read the value back to determine the
1930 	 * required size of the address space.  Restore the base
1931 	 * register contents.
1932 	 *
1933 	 * Do not disable I/O and memory access; this isn't necessary
1934 	 * since no driver is yet attached to this device, and disabling
1935 	 * I/O and memory access has the side-effect of disabling PCI-PCI
1936 	 * bridge mappings, which makes the bridge transparent to secondary-
1937 	 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge
1938 	 * Spec V1.2).
1939 	 */
1940 	end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
1941 	for (j = 0, offset = PCI_CONF_BASE0; offset < end;
1942 	    j++, offset += bar_sz) {
1943 		int hard_decode = 0;
1944 
1945 		/* determine the size of the address space */
1946 		base = pci_getl(bus, dev, func, offset);
1947 		pci_putl(bus, dev, func, offset, 0xffffffff);
1948 		value = pci_getl(bus, dev, func, offset);
1949 		pci_putl(bus, dev, func, offset, base);
1950 
1951 		/* construct phys hi,med.lo, size hi, lo */
1952 		if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) {
1953 			/* i/o space */
1954 			bar_sz = PCI_BAR_SZ_32;
1955 			value &= PCI_BASE_IO_ADDR_M;
1956 			len = ((value ^ (value-1)) + 1) >> 1;
1957 
1958 			/* XXX Adjust first 4 IDE registers */
1959 			if (pciide) {
1960 				if (subclass != PCI_MASS_IDE)
1961 					progclass = (PCI_IDE_IF_NATIVE_PRI |
1962 					    PCI_IDE_IF_NATIVE_SEC);
1963 				hard_decode = pciIdeAdjustBAR(progclass, j,
1964 				    &base, &len);
1965 			} else if (value == 0) {
1966 				/* skip base regs with size of 0 */
1967 				continue;
1968 			}
1969 
1970 			regs[nreg].pci_size_low =
1971 			    assigned[nasgn].pci_size_low = len;
1972 			if (!hard_decode) {
1973 				regs[nreg].pci_phys_hi =
1974 				    (PCI_ADDR_IO | devloc) + offset;
1975 			} else {
1976 				regs[nreg].pci_phys_hi =
1977 				    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) +
1978 				    offset;
1979 				regs[nreg].pci_phys_low =
1980 				    base & PCI_BASE_IO_ADDR_M;
1981 			}
1982 			assigned[nasgn].pci_phys_hi =
1983 			    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset;
1984 			type = base & (~PCI_BASE_IO_ADDR_M);
1985 			base &= PCI_BASE_IO_ADDR_M;
1986 			/*
1987 			 * A device under a subtractive PPB can allocate
1988 			 * resources from its parent bus if there is no resource
1989 			 * available on its own bus.
1990 			 */
1991 			if ((config_op == CONFIG_NEW) && (*io_res == NULL)) {
1992 				res_bus = bus;
1993 				while (pci_bus_res[res_bus].subtractive) {
1994 					res_bus = pci_bus_res[res_bus].par_bus;
1995 					if (res_bus == (uchar_t)-1)
1996 						break; /* root bus already */
1997 					if (pci_bus_res[res_bus].io_ports) {
1998 						io_res = &pci_bus_res
1999 						    [res_bus].io_ports;
2000 						break;
2001 					}
2002 				}
2003 			}
2004 
2005 			/*
2006 			 * first pass - gather what's there
2007 			 * update/second pass - adjust/allocate regions
2008 			 *	config - allocate regions
2009 			 */
2010 			if (config_op == CONFIG_INFO) {	/* first pass */
2011 				/* take out of the resource map of the bus */
2012 				if (base != 0) {
2013 					(void) memlist_remove(io_res, base,
2014 					    len);
2015 					memlist_insert(io_res_used, base, len);
2016 				} else
2017 					reprogram = 1;
2018 			} else if ((*io_res && base == 0) ||
2019 			    pci_bus_res[bus].io_reprogram) {
2020 				base = (uint_t)memlist_find(io_res, len, len);
2021 				if (base != 0) {
2022 					memlist_insert(io_res_used, base, len);
2023 					/* XXX need to worry about 64-bit? */
2024 					pci_putl(bus, dev, func, offset,
2025 					    base | type);
2026 					base = pci_getl(bus, dev, func, offset);
2027 					base &= PCI_BASE_IO_ADDR_M;
2028 				}
2029 				if (base == 0) {
2030 					cmn_err(CE_WARN, "failed to program"
2031 					    " IO space [%d/%d/%d] BAR@0x%x"
2032 					    " length 0x%x",
2033 					    bus, dev, func, offset, len);
2034 				}
2035 			}
2036 			assigned[nasgn].pci_phys_low = base;
2037 			nreg++, nasgn++;
2038 
2039 		} else {
2040 			/* memory space */
2041 			if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) {
2042 				bar_sz = PCI_BAR_SZ_64;
2043 				base_hi = pci_getl(bus, dev, func, offset + 4);
2044 				phys_hi = PCI_ADDR_MEM64;
2045 			} else {
2046 				bar_sz = PCI_BAR_SZ_32;
2047 				base_hi = 0;
2048 				phys_hi = PCI_ADDR_MEM32;
2049 			}
2050 
2051 			/* skip base regs with size of 0 */
2052 			value &= PCI_BASE_M_ADDR_M;
2053 
2054 			if (value == 0)
2055 				continue;
2056 
2057 			len = ((value ^ (value-1)) + 1) >> 1;
2058 			regs[nreg].pci_size_low =
2059 			    assigned[nasgn].pci_size_low = len;
2060 
2061 			phys_hi |= (devloc | offset);
2062 			if (base & PCI_BASE_PREF_M)
2063 				phys_hi |= PCI_PREFETCH_B;
2064 
2065 			/*
2066 			 * A device under a subtractive PPB can allocate
2067 			 * resources from its parent bus if there is no resource
2068 			 * available on its own bus.
2069 			 */
2070 			if ((config_op == CONFIG_NEW) && (*mem_res == NULL)) {
2071 				res_bus = bus;
2072 				while (pci_bus_res[res_bus].subtractive) {
2073 					res_bus = pci_bus_res[res_bus].par_bus;
2074 					if (res_bus == (uchar_t)-1)
2075 						break; /* root bus already */
2076 					mem_res =
2077 					    &pci_bus_res[res_bus].mem_space;
2078 					pmem_res =
2079 					    &pci_bus_res [res_bus].pmem_space;
2080 					/*
2081 					 * Break out as long as at least
2082 					 * mem_res is available
2083 					 */
2084 					if ((*pmem_res &&
2085 					    (phys_hi & PCI_PREFETCH_B)) ||
2086 					    *mem_res)
2087 						break;
2088 				}
2089 			}
2090 
2091 			regs[nreg].pci_phys_hi =
2092 			    assigned[nasgn].pci_phys_hi = phys_hi;
2093 			assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
2094 			assigned[nasgn].pci_phys_mid = base_hi;
2095 			type = base & ~PCI_BASE_M_ADDR_M;
2096 			base &= PCI_BASE_M_ADDR_M;
2097 
2098 			if (config_op == CONFIG_INFO) {
2099 				/* take out of the resource map of the bus */
2100 				if (base != NULL) {
2101 					/* remove from PMEM and MEM space */
2102 					(void) memlist_remove(mem_res,
2103 					    base, len);
2104 					(void) memlist_remove(pmem_res,
2105 					    base, len);
2106 					/* only note as used in correct map */
2107 					if (phys_hi & PCI_PREFETCH_B)
2108 						memlist_insert(pmem_res_used,
2109 						    base, len);
2110 					else
2111 						memlist_insert(mem_res_used,
2112 						    base, len);
2113 				} else
2114 					reprogram = 1;
2115 			} else if ((*mem_res && base == NULL) ||
2116 			    pci_bus_res[bus].mem_reprogram) {
2117 				/*
2118 				 * When desired, attempt a prefetchable
2119 				 * allocation first
2120 				 */
2121 				if (phys_hi & PCI_PREFETCH_B) {
2122 					base = (uint_t)memlist_find(pmem_res,
2123 					    len, len);
2124 					if (base != NULL) {
2125 						memlist_insert(pmem_res_used,
2126 						    base, len);
2127 						(void) memlist_remove(mem_res,
2128 						    base, len);
2129 					}
2130 				}
2131 				/*
2132 				 * If prefetchable allocation was not
2133 				 * desired, or failed, attempt ordinary
2134 				 * memory allocation
2135 				 */
2136 				if (base == NULL) {
2137 					base = (uint_t)memlist_find(mem_res,
2138 					    len, len);
2139 					if (base != NULL) {
2140 						memlist_insert(mem_res_used,
2141 						    base, len);
2142 						(void) memlist_remove(pmem_res,
2143 						    base, len);
2144 					}
2145 				}
2146 				if (base != NULL) {
2147 					pci_putl(bus, dev, func, offset,
2148 					    base | type);
2149 					base = pci_getl(bus, dev, func, offset);
2150 					base &= PCI_BASE_M_ADDR_M;
2151 				} else
2152 					cmn_err(CE_WARN, "failed to program "
2153 					    "mem space [%d/%d/%d] BAR@0x%x"
2154 					    " length 0x%x",
2155 					    bus, dev, func, offset, len);
2156 			}
2157 			assigned[nasgn].pci_phys_low = base;
2158 			nreg++, nasgn++;
2159 		}
2160 	}
2161 	switch (header) {
2162 	case PCI_HEADER_ZERO:
2163 		offset = PCI_CONF_ROM;
2164 		break;
2165 	case PCI_HEADER_PPB:
2166 		offset = PCI_BCNF_ROM;
2167 		break;
2168 	default: /* including PCI_HEADER_CARDBUS */
2169 		goto done;
2170 	}
2171 
2172 	/*
2173 	 * Add the expansion rom memory space
2174 	 * Determine the size of the ROM base reg; don't write reserved bits
2175 	 * ROM isn't in the PCI memory space.
2176 	 */
2177 	base = pci_getl(bus, dev, func, offset);
2178 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2179 	value = pci_getl(bus, dev, func, offset);
2180 	pci_putl(bus, dev, func, offset, base);
2181 	if (value & PCI_BASE_ROM_ENABLE)
2182 		value &= PCI_BASE_ROM_ADDR_M;
2183 	else
2184 		value = 0;
2185 
2186 	if (value != 0) {
2187 		regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
2188 		assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
2189 		    PCI_ADDR_MEM32 | devloc) + offset;
2190 		base &= PCI_BASE_ROM_ADDR_M;
2191 		assigned[nasgn].pci_phys_low = base;
2192 		len = ((value ^ (value-1)) + 1) >> 1;
2193 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len;
2194 		nreg++, nasgn++;
2195 		/* take it out of the memory resource */
2196 		if (base != NULL) {
2197 			(void) memlist_remove(mem_res, base, len);
2198 			memlist_insert(mem_res_used, base, len);
2199 		}
2200 	}
2201 
2202 	/*
2203 	 * Account for "legacy" (alias) video adapter resources
2204 	 */
2205 
2206 	/* add the three hard-decode, aliased address spaces for VGA */
2207 	if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) ||
2208 	    (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) {
2209 
2210 		/* VGA hard decode 0x3b0-0x3bb */
2211 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2212 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2213 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0;
2214 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc;
2215 		nreg++, nasgn++;
2216 		(void) memlist_remove(io_res, 0x3b0, 0xc);
2217 		memlist_insert(io_res_used, 0x3b0, 0xc);
2218 
2219 		/* VGA hard decode 0x3c0-0x3df */
2220 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2221 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2222 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0;
2223 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20;
2224 		nreg++, nasgn++;
2225 		(void) memlist_remove(io_res, 0x3c0, 0x20);
2226 		memlist_insert(io_res_used, 0x3c0, 0x20);
2227 
2228 		/* Video memory */
2229 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2230 		    (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc);
2231 		regs[nreg].pci_phys_low =
2232 		    assigned[nasgn].pci_phys_low = 0xa0000;
2233 		regs[nreg].pci_size_low =
2234 		    assigned[nasgn].pci_size_low = 0x20000;
2235 		nreg++, nasgn++;
2236 		/* remove from MEM and PMEM space */
2237 		(void) memlist_remove(mem_res, 0xa0000, 0x20000);
2238 		(void) memlist_remove(pmem_res, 0xa0000, 0x20000);
2239 		memlist_insert(mem_res_used, 0xa0000, 0x20000);
2240 	}
2241 
2242 	/* add the hard-decode, aliased address spaces for 8514 */
2243 	if ((baseclass == PCI_CLASS_DISPLAY) &&
2244 	    (subclass == PCI_DISPLAY_VGA) &&
2245 	    (progclass & PCI_DISPLAY_IF_8514)) {
2246 
2247 		/* hard decode 0x2e8 */
2248 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2249 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2250 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8;
2251 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1;
2252 		nreg++, nasgn++;
2253 		(void) memlist_remove(io_res, 0x2e8, 0x1);
2254 		memlist_insert(io_res_used, 0x2e8, 0x1);
2255 
2256 		/* hard decode 0x2ea-0x2ef */
2257 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2258 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2259 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea;
2260 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6;
2261 		nreg++, nasgn++;
2262 		(void) memlist_remove(io_res, 0x2ea, 0x6);
2263 		memlist_insert(io_res_used, 0x2ea, 0x6);
2264 	}
2265 
2266 done:
2267 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
2268 	    (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int));
2269 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
2270 	    "assigned-addresses",
2271 	    (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int));
2272 
2273 	return (reprogram);
2274 }
2275 
2276 static void
2277 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2278     int pciex, ushort_t is_pci_bridge)
2279 {
2280 	char *dev_type;
2281 	int i;
2282 	uint_t val, io_range[2], mem_range[2], pmem_range[2];
2283 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2284 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2285 	uchar_t progclass;
2286 
2287 	ASSERT(secbus <= subbus);
2288 
2289 	/*
2290 	 * Check if it's a subtractive PPB.
2291 	 */
2292 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2293 	if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
2294 		pci_bus_res[secbus].subtractive = B_TRUE;
2295 
2296 	/*
2297 	 * Some BIOSes lie about max pci busses, we allow for
2298 	 * such mistakes here
2299 	 */
2300 	if (subbus > pci_bios_nbus) {
2301 		pci_bios_nbus = subbus;
2302 		alloc_res_array();
2303 	}
2304 
2305 	ASSERT(pci_bus_res[secbus].dip == NULL);
2306 	pci_bus_res[secbus].dip = dip;
2307 	pci_bus_res[secbus].par_bus = bus;
2308 
2309 	dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci";
2310 
2311 	/* setup bus number hierarchy */
2312 	pci_bus_res[secbus].sub_bus = subbus;
2313 	/*
2314 	 * Keep track of the largest subordinate bus number (this is essential
2315 	 * for peer busses because there is no other way of determining its
2316 	 * subordinate bus number).
2317 	 */
2318 	if (subbus > pci_bus_res[bus].sub_bus)
2319 		pci_bus_res[bus].sub_bus = subbus;
2320 	/*
2321 	 * Loop through subordinate busses, initializing their parent bus
2322 	 * field to this bridge's parent.  The subordinate busses' parent
2323 	 * fields may very well be further refined later, as child bridges
2324 	 * are enumerated.  (The value is to note that the subordinate busses
2325 	 * are not peer busses by changing their par_bus fields to anything
2326 	 * other than -1.)
2327 	 */
2328 	for (i = secbus + 1; i <= subbus; i++)
2329 		pci_bus_res[i].par_bus = bus;
2330 
2331 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2332 	    "device_type", dev_type);
2333 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2334 	    "#address-cells", 3);
2335 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2336 	    "#size-cells", 2);
2337 
2338 	/*
2339 	 * According to PPB spec, the base register should be programmed
2340 	 * with a value bigger than the limit register when there are
2341 	 * no resources available. This applies to io, memory, and
2342 	 * prefetchable memory.
2343 	 */
2344 
2345 	/*
2346 	 * io range
2347 	 * We determine i/o windows that are left unconfigured by BIOS
2348 	 * through its i/o enable bit as Microsoft recommends OEMs to do.
2349 	 * If it is unset, we disable i/o and mark it for reconfiguration in
2350 	 * later passes by setting the base > limit
2351 	 */
2352 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
2353 	if (val & PCI_COMM_IO) {
2354 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
2355 		io_range[0] = ((val & 0xf0) << 8);
2356 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
2357 		io_range[1]  = ((val & 0xf0) << 8) | 0xFFF;
2358 	} else {
2359 		io_range[0] = 0x9fff;
2360 		io_range[1] = 0x1000;
2361 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
2362 		    (uint8_t)((io_range[0] >> 8) & 0xf0));
2363 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
2364 		    (uint8_t)((io_range[1] >> 8) & 0xf0));
2365 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
2366 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
2367 	}
2368 
2369 	if (io_range[0] != 0 && io_range[0] < io_range[1]) {
2370 		memlist_insert(&pci_bus_res[secbus].io_ports,
2371 		    (uint64_t)io_range[0],
2372 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2373 		memlist_insert(&pci_bus_res[bus].io_ports_used,
2374 		    (uint64_t)io_range[0],
2375 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2376 		if (pci_bus_res[bus].io_ports != NULL) {
2377 			(void) memlist_remove(&pci_bus_res[bus].io_ports,
2378 			    (uint64_t)io_range[0],
2379 			    (uint64_t)(io_range[1] - io_range[0] + 1));
2380 		}
2381 		dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x",
2382 		    secbus, io_range[0], io_range[1]);
2383 		/* if 32-bit supported, make sure upper bits are not set */
2384 		if ((val & 0xf) == 1 &&
2385 		    pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) {
2386 			cmn_err(CE_NOTE, "unsupported 32-bit IO address on"
2387 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2388 		}
2389 	}
2390 
2391 	/* mem range */
2392 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
2393 	mem_range[0] = ((val & 0xFFF0) << 16);
2394 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
2395 	mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2396 	if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) {
2397 		memlist_insert(&pci_bus_res[secbus].mem_space,
2398 		    (uint64_t)mem_range[0],
2399 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2400 		memlist_insert(&pci_bus_res[bus].mem_space_used,
2401 		    (uint64_t)mem_range[0],
2402 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2403 		/* remove from parent resource list */
2404 		(void) memlist_remove(&pci_bus_res[bus].mem_space,
2405 		    (uint64_t)mem_range[0],
2406 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2407 		(void) memlist_remove(&pci_bus_res[bus].pmem_space,
2408 		    (uint64_t)mem_range[0],
2409 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2410 		dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x",
2411 		    secbus, mem_range[0], mem_range[1]);
2412 	}
2413 
2414 	/* prefetchable memory range */
2415 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
2416 	pmem_range[0] = ((val & 0xFFF0) << 16);
2417 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
2418 	pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2419 	if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) {
2420 		memlist_insert(&pci_bus_res[secbus].pmem_space,
2421 		    (uint64_t)pmem_range[0],
2422 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2423 		memlist_insert(&pci_bus_res[bus].pmem_space_used,
2424 		    (uint64_t)pmem_range[0],
2425 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2426 		/* remove from parent resource list */
2427 		(void) memlist_remove(&pci_bus_res[bus].pmem_space,
2428 		    (uint64_t)pmem_range[0],
2429 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2430 		(void) memlist_remove(&pci_bus_res[bus].mem_space,
2431 		    (uint64_t)pmem_range[0],
2432 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2433 		dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x",
2434 		    secbus, pmem_range[0], pmem_range[1]);
2435 		/* if 64-bit supported, make sure upper bits are not set */
2436 		if ((val & 0xf) == 1 &&
2437 		    pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) {
2438 			cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on"
2439 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2440 		}
2441 	}
2442 
2443 	add_bus_range_prop(secbus);
2444 	add_ranges_prop(secbus, 1);
2445 }
2446 
2447 extern const struct pci_class_strings_s class_pci[];
2448 extern int class_pci_items;
2449 
2450 static void
2451 add_model_prop(dev_info_t *dip, uint_t classcode)
2452 {
2453 	const char *desc;
2454 	int i;
2455 	uchar_t baseclass = classcode >> 16;
2456 	uchar_t subclass = (classcode >> 8) & 0xff;
2457 	uchar_t progclass = classcode & 0xff;
2458 
2459 	if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) {
2460 		desc = "IDE controller";
2461 	} else {
2462 		for (desc = 0, i = 0; i < class_pci_items; i++) {
2463 			if ((baseclass == class_pci[i].base_class) &&
2464 			    (subclass == class_pci[i].sub_class) &&
2465 			    (progclass == class_pci[i].prog_class)) {
2466 				desc = class_pci[i].actual_desc;
2467 				break;
2468 			}
2469 		}
2470 		if (i == class_pci_items)
2471 			desc = "Unknown class of pci/pnpbios device";
2472 	}
2473 
2474 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
2475 	    (char *)desc);
2476 }
2477 
2478 static void
2479 add_bus_range_prop(int bus)
2480 {
2481 	int bus_range[2];
2482 
2483 	if (pci_bus_res[bus].dip == NULL)
2484 		return;
2485 	bus_range[0] = bus;
2486 	bus_range[1] = pci_bus_res[bus].sub_bus;
2487 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2488 	    "bus-range", (int *)bus_range, 2);
2489 }
2490 
2491 /*
2492  * Add slot-names property for any named pci hot-plug slots
2493  */
2494 static void
2495 add_bus_slot_names_prop(int bus)
2496 {
2497 	char slotprop[256];
2498 	int len;
2499 
2500 	if (pci_bus_res[bus].dip != NULL) {
2501 		/* simply return if the property is already defined */
2502 		if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip,
2503 		    DDI_PROP_DONTPASS, "slot-names"))
2504 			return;
2505 	}
2506 
2507 	len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop));
2508 	if (len > 0) {
2509 		/*
2510 		 * Only create a peer bus node if this bus may be a peer bus.
2511 		 * It may be a peer bus if the dip is NULL and if par_bus is
2512 		 * -1 (par_bus is -1 if this bus was not found to be
2513 		 * subordinate to any PCI-PCI bridge).
2514 		 * If it's not a peer bus, then the ACPI BBN-handling code
2515 		 * will remove it later.
2516 		 */
2517 		if (pci_bus_res[bus].par_bus == (uchar_t)-1 &&
2518 		    pci_bus_res[bus].dip == NULL) {
2519 
2520 			create_root_bus_dip(bus);
2521 		}
2522 		if (pci_bus_res[bus].dip != NULL) {
2523 			ASSERT((len % sizeof (int)) == 0);
2524 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
2525 			    pci_bus_res[bus].dip, "slot-names",
2526 			    (int *)slotprop, len / sizeof (int));
2527 		} else {
2528 			cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI "
2529 			    "IRQ routing table; Not adding slot-names "
2530 			    "property for incorrect bus %d", bus);
2531 		}
2532 	}
2533 }
2534 
2535 /*
2536  * Handle both PCI root and PCI-PCI bridge range properties;
2537  * non-zero 'ppb' argument select PCI-PCI bridges versus root.
2538  */
2539 static void
2540 memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb)
2541 {
2542 	ppb_ranges_t *ppb_rp = *rp;
2543 	pci_ranges_t *pci_rp = *rp;
2544 
2545 	while (entry != NULL) {
2546 		if (ppb) {
2547 			ppb_rp->child_high = ppb_rp->parent_high = type;
2548 			ppb_rp->child_mid = ppb_rp->parent_mid =
2549 			    (uint32_t)(entry->address >> 32); /* XXX */
2550 			ppb_rp->child_low = ppb_rp->parent_low =
2551 			    (uint32_t)entry->address;
2552 			ppb_rp->size_high =
2553 			    (uint32_t)(entry->size >> 32); /* XXX */
2554 			ppb_rp->size_low = (uint32_t)entry->size;
2555 			*rp = ++ppb_rp;
2556 		} else {
2557 			pci_rp->child_high = type;
2558 			pci_rp->child_mid = pci_rp->parent_high =
2559 			    (uint32_t)(entry->address >> 32); /* XXX */
2560 			pci_rp->child_low = pci_rp->parent_low =
2561 			    (uint32_t)entry->address;
2562 			pci_rp->size_high =
2563 			    (uint32_t)(entry->size >> 32); /* XXX */
2564 			pci_rp->size_low = (uint32_t)entry->size;
2565 			*rp = ++pci_rp;
2566 		}
2567 		entry = entry->next;
2568 	}
2569 }
2570 
2571 static void
2572 add_ranges_prop(int bus, int ppb)
2573 {
2574 	int total, alloc_size;
2575 	void	*rp, *next_rp;
2576 
2577 	/* no devinfo node - unused bus, return */
2578 	if (pci_bus_res[bus].dip == NULL)
2579 		return;
2580 
2581 	total = memlist_count(pci_bus_res[bus].io_ports);
2582 	total += memlist_count(pci_bus_res[bus].mem_space);
2583 	total += memlist_count(pci_bus_res[bus].pmem_space);
2584 
2585 	/* no property is created if no ranges are present */
2586 	if (total == 0)
2587 		return;
2588 
2589 	alloc_size = total *
2590 	    (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t));
2591 
2592 	next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP);
2593 
2594 	memlist_to_ranges(&next_rp, pci_bus_res[bus].io_ports,
2595 	    PCI_ADDR_IO | PCI_REG_REL_M, ppb);
2596 	memlist_to_ranges(&next_rp, pci_bus_res[bus].mem_space,
2597 	    PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb);
2598 	memlist_to_ranges(&next_rp, pci_bus_res[bus].pmem_space,
2599 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb);
2600 
2601 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2602 	    "ranges", (int *)rp, alloc_size / sizeof (int));
2603 
2604 	kmem_free(rp, alloc_size);
2605 }
2606 
2607 static void
2608 memlist_remove_list(struct memlist **list, struct memlist *remove_list)
2609 {
2610 	while (list && *list && remove_list) {
2611 		(void) memlist_remove(list, remove_list->address,
2612 		    remove_list->size);
2613 		remove_list = remove_list->next;
2614 	}
2615 }
2616 
2617 static int
2618 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type)
2619 {
2620 	int i = 0;
2621 
2622 	while (list) {
2623 		/* assume 32-bit addresses */
2624 		sp->pci_phys_hi = type;
2625 		sp->pci_phys_mid = 0;
2626 		sp->pci_phys_low = (uint32_t)list->address;
2627 		sp->pci_size_hi = 0;
2628 		sp->pci_size_low = (uint32_t)list->size;
2629 
2630 		list = list->next;
2631 		sp++, i++;
2632 	}
2633 	return (i);
2634 }
2635 
2636 static void
2637 add_bus_available_prop(int bus)
2638 {
2639 	int i, count;
2640 	struct pci_phys_spec *sp;
2641 
2642 	/* no devinfo node - unused bus, return */
2643 	if (pci_bus_res[bus].dip == NULL)
2644 		return;
2645 
2646 	count = memlist_count(pci_bus_res[bus].io_ports) +
2647 	    memlist_count(pci_bus_res[bus].mem_space) +
2648 	    memlist_count(pci_bus_res[bus].pmem_space);
2649 
2650 	if (count == 0)		/* nothing available */
2651 		return;
2652 
2653 	sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP);
2654 	i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports,
2655 	    PCI_ADDR_IO | PCI_REG_REL_M);
2656 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space,
2657 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
2658 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space,
2659 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
2660 	ASSERT(i == count);
2661 
2662 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2663 	    "available", (int *)sp,
2664 	    i * sizeof (struct pci_phys_spec) / sizeof (int));
2665 	kmem_free(sp, count * sizeof (*sp));
2666 }
2667 
2668 static void
2669 alloc_res_array(void)
2670 {
2671 	static int array_max = 0;
2672 	int old_max;
2673 	void *old_res;
2674 
2675 	if (array_max > pci_bios_nbus + 1)
2676 		return;	/* array is big enough */
2677 
2678 	old_max = array_max;
2679 	old_res = pci_bus_res;
2680 
2681 	if (array_max == 0)
2682 		array_max = 16;	/* start with a reasonable number */
2683 
2684 	while (array_max < pci_bios_nbus + 1)
2685 		array_max <<= 1;
2686 	pci_bus_res = (struct pci_bus_resource *)kmem_zalloc(
2687 	    array_max * sizeof (struct pci_bus_resource), KM_SLEEP);
2688 
2689 	if (old_res) {	/* copy content and free old array */
2690 		bcopy(old_res, pci_bus_res,
2691 		    old_max * sizeof (struct pci_bus_resource));
2692 		kmem_free(old_res, old_max * sizeof (struct pci_bus_resource));
2693 	}
2694 }
2695 
2696 static void
2697 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
2698     ushort_t deviceid)
2699 {
2700 	static dev_info_t *ioapicsnode = NULL;
2701 	static int numioapics = 0;
2702 	dev_info_t *ioapic_node;
2703 	uint64_t physaddr;
2704 	uint32_t lobase, hibase = 0;
2705 
2706 	/* BAR 0 contains the IOAPIC's memory-mapped I/O address */
2707 	lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
2708 
2709 	/* We (and the rest of the world) only support memory-mapped IOAPICs */
2710 	if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM)
2711 		return;
2712 
2713 	if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL)
2714 		hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
2715 
2716 	lobase &= PCI_BASE_M_ADDR_M;
2717 
2718 	physaddr = (((uint64_t)hibase) << 32) | lobase;
2719 
2720 	/*
2721 	 * Create a nexus node for all IOAPICs under the root node.
2722 	 */
2723 	if (ioapicsnode == NULL) {
2724 		if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME,
2725 		    (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) {
2726 			return;
2727 		}
2728 		(void) ndi_devi_online(ioapicsnode, 0);
2729 	}
2730 
2731 	/*
2732 	 * Create a child node for this IOAPIC
2733 	 */
2734 	ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME,
2735 	    DEVI_SID_NODEID, numioapics++);
2736 	if (ioapic_node == NULL) {
2737 		return;
2738 	}
2739 
2740 	/* Vendor and Device ID */
2741 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2742 	    IOAPICS_PROP_VENID, vendorid);
2743 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2744 	    IOAPICS_PROP_DEVID, deviceid);
2745 
2746 	/* device_type */
2747 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node,
2748 	    "device_type", IOAPICS_DEV_TYPE);
2749 
2750 	/* reg */
2751 	(void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node,
2752 	    "reg", physaddr);
2753 }
2754 
2755 /*
2756  * NOTE: For PCIe slots, the name is generated from the slot number
2757  * information obtained from Slot Capabilities register.
2758  * For non-PCIe slots, it is generated based on the slot number
2759  * information in the PCI IRQ table.
2760  */
2761 static void
2762 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num)
2763 {
2764 	char slotprop[256];
2765 	int len;
2766 
2767 	bzero(slotprop, sizeof (slotprop));
2768 
2769 	/* set mask to 1 as there is only one slot (i.e dev 0) */
2770 	*(uint32_t *)slotprop = 1;
2771 	len = 4;
2772 	(void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d",
2773 	    slot_num);
2774 	len += strlen(slotprop + len) + 1;
2775 	len += len % 4;
2776 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names",
2777 	    (int *)slotprop, len / sizeof (int));
2778 }
2779