1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/stat.h> 28 #include <sys/sunndi.h> 29 #include <sys/pci.h> 30 #include <sys/pci_impl.h> 31 #include <sys/pci_cfgspace.h> 32 #include <sys/memlist.h> 33 #include <sys/bootconf.h> 34 #include <io/pci/mps_table.h> 35 #include <sys/pci_cfgspace.h> 36 #include <sys/pci_cfgspace_impl.h> 37 #include <sys/psw.h> 38 #include "../../../../common/pci/pci_strings.h" 39 #include <sys/apic.h> 40 #include <io/pciex/pcie_nvidia.h> 41 #include <io/hotplug/pciehpc/pciehpc_acpi.h> 42 #include <sys/acpi/acpi.h> 43 #include <sys/acpica.h> 44 #include <sys/intel_iommu.h> 45 46 #define pci_getb (*pci_getb_func) 47 #define pci_getw (*pci_getw_func) 48 #define pci_getl (*pci_getl_func) 49 #define pci_putb (*pci_putb_func) 50 #define pci_putw (*pci_putw_func) 51 #define pci_putl (*pci_putl_func) 52 #define dcmn_err if (pci_boot_debug) cmn_err 53 54 #define CONFIG_INFO 0 55 #define CONFIG_UPDATE 1 56 #define CONFIG_NEW 2 57 #define CONFIG_FIX 3 58 #define COMPAT_BUFSIZE 512 59 60 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 61 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 62 63 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 64 #define LPC_IO_CONTROL_REG_1 0x40 65 #define AMD8111_ENABLENMI (uint8_t)0x80 66 #define DEVID_AMD8111_LPC 0x7468 67 68 struct pci_fixundo { 69 uint8_t bus; 70 uint8_t dev; 71 uint8_t fn; 72 void (*undofn)(uint8_t, uint8_t, uint8_t); 73 struct pci_fixundo *next; 74 }; 75 76 struct pci_devfunc { 77 struct pci_devfunc *next; 78 dev_info_t *dip; 79 uchar_t dev; 80 uchar_t func; 81 boolean_t reprogram; /* this device needs to be reprogrammed */ 82 }; 83 84 extern int pci_bios_nbus; 85 static uchar_t max_dev_pci = 32; /* PCI standard */ 86 int pci_boot_debug = 0; 87 extern struct memlist *find_bus_res(int, int); 88 static struct pci_fixundo *undolist = NULL; 89 static int num_root_bus = 0; /* count of root buses */ 90 91 /* 92 * Module prototypes 93 */ 94 static void enumerate_bus_devs(uchar_t bus, int config_op); 95 static void create_root_bus_dip(uchar_t bus); 96 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 97 ushort_t, int); 98 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 99 ushort_t, ushort_t, uchar_t, uint_t, int); 100 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 101 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 102 static void add_model_prop(dev_info_t *, uint_t); 103 static void add_bus_range_prop(int); 104 static void add_bus_slot_names_prop(int); 105 static void add_ppb_ranges_prop(int); 106 static void add_bus_available_prop(int); 107 static void fix_ppb_res(uchar_t, boolean_t); 108 static void alloc_res_array(); 109 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 110 ushort_t deviceid); 111 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 112 113 extern int pci_slot_names_prop(int, char *, int); 114 115 /* set non-zero to force PCI peer-bus renumbering */ 116 int pci_bus_always_renumber = 0; 117 118 /* get the subordinate bus # for a root/peer bus */ 119 static int 120 pci_root_subbus(int bus, uchar_t *subbus) 121 { 122 ACPI_HANDLE hdl; 123 ACPI_BUFFER rb; 124 ACPI_RESOURCE *rp; 125 int rv; 126 127 if (pci_bus_res[bus].dip == NULL) { 128 /* non-used bus # */ 129 return (AE_ERROR); 130 } 131 if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) { 132 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 133 return (AE_ERROR); 134 } 135 136 rb.Length = ACPI_ALLOCATE_BUFFER; 137 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 138 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 139 return (AE_ERROR); 140 } 141 142 rv = AE_ERROR; 143 144 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 145 rp = ACPI_NEXT_RESOURCE(rp)) { 146 147 switch (rp->Type) { 148 case ACPI_RESOURCE_TYPE_ADDRESS16: 149 if (rp->Data.Address.ResourceType != 150 ACPI_BUS_NUMBER_RANGE) 151 continue; 152 *subbus = (uchar_t)rp->Data.Address16.Maximum; 153 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 154 break; 155 case ACPI_RESOURCE_TYPE_ADDRESS32: 156 if (rp->Data.Address.ResourceType != 157 ACPI_BUS_NUMBER_RANGE) 158 continue; 159 *subbus = (uchar_t)rp->Data.Address32.Maximum; 160 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 161 break; 162 case ACPI_RESOURCE_TYPE_ADDRESS64: 163 if (rp->Data.Address.ResourceType != 164 ACPI_BUS_NUMBER_RANGE) 165 continue; 166 *subbus = (uchar_t)rp->Data.Address64.Maximum; 167 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 168 break; 169 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 170 if (rp->Data.Address.ResourceType != 171 ACPI_BUS_NUMBER_RANGE) 172 continue; 173 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 174 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 175 break; 176 default: 177 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 178 continue; 179 } 180 181 /* found the bus-range resource */ 182 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 183 rv = AE_OK; 184 185 /* This breaks out of the resource scanning loop */ 186 break; 187 } 188 189 AcpiOsFree(rb.Pointer); 190 if (rv != AE_OK) 191 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 192 193 return (rv); 194 195 } 196 197 /* 198 * Enumerate all PCI devices 199 */ 200 void 201 pci_setup_tree() 202 { 203 uchar_t i, root_bus_addr = 0; 204 205 alloc_res_array(); 206 for (i = 0; i <= pci_bios_nbus; i++) { 207 pci_bus_res[i].par_bus = (uchar_t)-1; 208 pci_bus_res[i].root_addr = (uchar_t)-1; 209 pci_bus_res[i].sub_bus = i; 210 } 211 212 pci_bus_res[0].root_addr = root_bus_addr++; 213 create_root_bus_dip(0); 214 enumerate_bus_devs(0, CONFIG_INFO); 215 216 /* 217 * Now enumerate peer busses 218 * 219 * We loop till pci_bios_nbus. On most systems, there is 220 * one more bus at the high end, which implements the ISA 221 * compatibility bus. We don't care about that. 222 * 223 * Note: In the old (bootconf) enumeration, the peer bus 224 * address did not use the bus number, and there were 225 * too many peer busses created. The root_bus_addr is 226 * used to maintain the old peer bus address assignment. 227 * However, we stop enumerating phantom peers with no 228 * device below. 229 */ 230 for (i = 1; i <= pci_bios_nbus; i++) { 231 if (pci_bus_res[i].dip == NULL) { 232 pci_bus_res[i].root_addr = root_bus_addr++; 233 } 234 enumerate_bus_devs(i, CONFIG_INFO); 235 236 /* add slot-names property for named pci hot-plug slots */ 237 add_bus_slot_names_prop(i); 238 } 239 240 } 241 242 /* 243 * >0 = present, 0 = not present, <0 = error 244 */ 245 static int 246 pci_bbn_present(int bus) 247 { 248 ACPI_HANDLE hdl; 249 ACPI_BUFFER rb; 250 int rv; 251 252 /* no dip means no _BBN */ 253 if (pci_bus_res[bus].dip == NULL) 254 return (0); 255 256 rv = acpica_get_handle(pci_bus_res[bus].dip, &hdl); 257 if (rv != AE_OK) 258 return (-1); 259 260 rb.Length = ACPI_ALLOCATE_BUFFER; 261 262 rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 263 264 if (rb.Length > 0) 265 AcpiOsFree(rb.Pointer); 266 267 if (rv == AE_OK) 268 return (1); 269 else if (rv == AE_NOT_FOUND) 270 return (0); 271 else 272 return (-1); 273 } 274 275 /* 276 * Return non-zero if any PCI bus in the system has an associated 277 * _BBN object, 0 otherwise. 278 */ 279 static int 280 pci_roots_have_bbn(void) 281 { 282 int i; 283 284 /* 285 * Scan the PCI busses and look for at least 1 _BBN 286 */ 287 for (i = 0; i <= pci_bios_nbus; i++) { 288 /* skip non-root (peer) PCI busses */ 289 if (pci_bus_res[i].par_bus != (uchar_t)-1) 290 continue; 291 292 if (pci_bbn_present(i) > 0) 293 return (1); 294 } 295 return (0); 296 297 } 298 299 /* 300 * return non-zero if the machine is one on which we renumber 301 * the internal pci unit-addresses 302 */ 303 static int 304 pci_bus_renumber() 305 { 306 ACPI_TABLE_HEADER *fadt; 307 308 if (pci_bus_always_renumber) 309 return (1); 310 311 /* get the FADT */ 312 if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 313 (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 314 return (0); 315 316 /* compare OEM Table ID to "SUNm31" */ 317 if (strncmp("SUNm31", fadt->OemId, 6)) 318 return (0); 319 else 320 return (1); 321 } 322 323 /* 324 * Initial enumeration of the physical PCI bus hierarchy can 325 * leave 'gaps' in the order of peer PCI bus unit-addresses. 326 * Systems with more than one peer PCI bus *must* have an ACPI 327 * _BBN object associated with each peer bus; use the presence 328 * of this object to remove gaps in the numbering of the peer 329 * PCI bus unit-addresses - only peer busses with an associated 330 * _BBN are counted. 331 */ 332 static void 333 pci_renumber_root_busses(void) 334 { 335 int pci_regs[] = {0, 0, 0}; 336 int i, root_addr = 0; 337 338 /* 339 * Currently, we only enable the re-numbering on specific 340 * Sun machines; this is a work-around for the more complicated 341 * issue of upgrade changing physical device paths 342 */ 343 if (!pci_bus_renumber()) 344 return; 345 346 /* 347 * If we find no _BBN objects at all, we either don't need 348 * to do anything or can't do anything anyway 349 */ 350 if (!pci_roots_have_bbn()) 351 return; 352 353 for (i = 0; i <= pci_bios_nbus; i++) { 354 /* skip non-root (peer) PCI busses */ 355 if (pci_bus_res[i].par_bus != (uchar_t)-1) 356 continue; 357 358 if (pci_bbn_present(i) < 1) { 359 pci_bus_res[i].root_addr = (uchar_t)-1; 360 continue; 361 } 362 363 ASSERT(pci_bus_res[i].dip != NULL); 364 if (pci_bus_res[i].root_addr != root_addr) { 365 /* update reg property for node */ 366 pci_bus_res[i].root_addr = root_addr; 367 pci_regs[0] = pci_bus_res[i].root_addr; 368 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 369 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 370 } 371 root_addr++; 372 } 373 } 374 375 static void 376 remove_resource_range(struct memlist **list, int *ranges, int range_count) 377 { 378 struct range { 379 uint32_t base; 380 uint32_t len; 381 }; 382 int index; 383 384 for (index = 0; index < range_count; index++) { 385 /* all done if list is or has become empty */ 386 if (*list == NULL) 387 break; 388 (void) memlist_remove(list, 389 (uint64_t)((struct range *)ranges)[index].base, 390 (uint64_t)((struct range *)ranges)[index].len); 391 } 392 } 393 394 static void 395 remove_used_resources() 396 { 397 dev_info_t *used; 398 int *narray; 399 uint_t ncount; 400 int status; 401 int bus; 402 403 used = ddi_find_devinfo("used-resources", -1, 0); 404 if (used == NULL) 405 return; 406 407 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 408 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 409 if (status == DDI_PROP_SUCCESS) { 410 for (bus = 0; bus <= pci_bios_nbus; bus++) 411 remove_resource_range(&pci_bus_res[bus].io_ports, 412 narray, ncount / 2); 413 ddi_prop_free(narray); 414 } 415 416 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 417 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 418 if (status == DDI_PROP_SUCCESS) { 419 for (bus = 0; bus <= pci_bios_nbus; bus++) 420 remove_resource_range(&pci_bus_res[bus].mem_space, 421 narray, ncount / 2); 422 ddi_prop_free(narray); 423 } 424 } 425 426 /* 427 * Remove the resources which are already used by devices under a subtractive 428 * bridge from the bus's resources lists, because they're not available, and 429 * shouldn't be allocated to other buses. This is necessary because tracking 430 * resources for subtractive bridges is not complete. (Subtractive bridges only 431 * track some of their claimed resources, not "the rest of the address space" as 432 * they should, so that allocation to peer non-subtractive PPBs is easier. We 433 * need a fully-capable global resource allocator). 434 */ 435 static void 436 remove_subtractive_res() 437 { 438 int i, j; 439 struct memlist *list; 440 441 for (i = 0; i <= pci_bios_nbus; i++) { 442 if (pci_bus_res[i].subtractive) { 443 /* remove used io ports */ 444 list = pci_bus_res[i].io_ports_used; 445 while (list) { 446 for (j = 0; j <= pci_bios_nbus; j++) { 447 if (pci_bus_res[j].io_ports) 448 (void) memlist_remove( 449 &pci_bus_res[j].io_ports, 450 list->address, list->size); 451 } 452 list = list->next; 453 } 454 /* remove used mem resource */ 455 list = pci_bus_res[i].mem_space_used; 456 while (list) { 457 for (j = 0; j <= pci_bios_nbus; j++) { 458 if (pci_bus_res[j].mem_space) 459 (void) memlist_remove( 460 &pci_bus_res[j].mem_space, 461 list->address, list->size); 462 } 463 list = list->next; 464 } 465 /* remove used prefetchable mem resource */ 466 list = pci_bus_res[i].pmem_space_used; 467 while (list) { 468 for (j = 0; j <= pci_bios_nbus; j++) { 469 if (pci_bus_res[j].pmem_space) 470 (void) memlist_remove( 471 &pci_bus_res[j].pmem_space, 472 list->address, list->size); 473 } 474 list = list->next; 475 } 476 } 477 } 478 } 479 480 /* Set up this bus's "bus_space" resource list */ 481 static void 482 setup_bus_res(int bus) 483 { 484 uchar_t par_bus; 485 uchar_t sub_bus; 486 487 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 488 return; 489 490 sub_bus = pci_bus_res[bus].sub_bus; 491 ASSERT(sub_bus >= bus); 492 ASSERT(pci_bus_res[bus].bus_space == NULL); 493 if (sub_bus > bus) { 494 /* 495 * Keep the remaining available bus range in bus_space. 496 * ('bus' is already allocated) 497 */ 498 memlist_insert(&pci_bus_res[bus].bus_space, bus + 1, 499 sub_bus - bus); 500 } 501 502 /* 503 * Remove resources from parent bus node if this is not a 504 * root bus. 505 */ 506 par_bus = pci_bus_res[bus].par_bus; 507 if (par_bus != (uchar_t)-1) { 508 ASSERT(pci_bus_res[par_bus].bus_space != NULL); 509 (void) memlist_remove(&pci_bus_res[par_bus].bus_space, 510 bus, sub_bus - bus + 1); 511 } 512 } 513 514 static uint64_t 515 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 516 { 517 uint64_t addr = 0; 518 uchar_t res_bus; 519 520 /* 521 * Skip root(peer) buses in multiple-root-bus systems, as currently 522 * the initial resources set on each root bus might not be correctly 523 * accounted for. (We need to read resources from ACPI as well as 524 * the MP tables and hotplug tables.) 525 */ 526 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 527 (num_root_bus > 1)) 528 return (0); 529 530 res_bus = parbus; 531 while (pci_bus_res[res_bus].subtractive) { 532 if (pci_bus_res[res_bus].io_ports) 533 break; 534 res_bus = pci_bus_res[res_bus].par_bus; 535 if (res_bus == (uchar_t)-1) 536 break; /* root bus already */ 537 } 538 539 if (pci_bus_res[res_bus].io_ports) { 540 addr = memlist_find(&pci_bus_res[res_bus].io_ports, 541 size, align); 542 if (addr) { 543 memlist_insert(&pci_bus_res[res_bus].io_ports_used, 544 addr, size); 545 /* free the old resource */ 546 memlist_free_all(&pci_bus_res[bus].io_ports); 547 /* add the new resource */ 548 memlist_insert(&pci_bus_res[bus].io_ports, addr, size); 549 } 550 } 551 552 return (addr); 553 } 554 555 static uint64_t 556 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 557 { 558 uint64_t addr = 0; 559 uchar_t res_bus; 560 561 /* 562 * Skip root(peer) buses in multiple-root-bus systems, as currently 563 * the initial resources set on each root bus might not be correctly 564 * accounted for. (We need to read resources from ACPI as well as 565 * the MP tables and hotplug tables.) 566 */ 567 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 568 (num_root_bus > 1)) 569 return (0); 570 571 res_bus = parbus; 572 while (pci_bus_res[res_bus].subtractive) { 573 if (pci_bus_res[res_bus].mem_space) 574 break; 575 res_bus = pci_bus_res[res_bus].par_bus; 576 if (res_bus == (uchar_t)-1) 577 break; /* root bus already */ 578 } 579 580 if (pci_bus_res[res_bus].mem_space) { 581 addr = memlist_find(&pci_bus_res[res_bus].mem_space, 582 size, align); 583 if (addr) { 584 memlist_insert(&pci_bus_res[res_bus].mem_space_used, 585 addr, size); 586 /* free the old resource */ 587 memlist_free_all(&pci_bus_res[bus].mem_space); 588 /* add the new resource */ 589 memlist_insert(&pci_bus_res[bus].mem_space, addr, size); 590 } 591 } 592 593 return (addr); 594 } 595 596 /* 597 * Assign valid resources to unconfigured pci(e) bridges. We are trying 598 * to reprogram the bridge when its 599 * i) SECBUS == SUBBUS || 600 * ii) IOBASE > IOLIM || 601 * iii) MEMBASE > MEMLIM 602 * This must be done after one full pass through the PCI tree to collect 603 * all BIOS-configured resources, so that we know what resources are 604 * free and available to assign to the unconfigured PPBs. 605 */ 606 static void 607 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 608 { 609 uchar_t bus, dev, func; 610 uchar_t parbus, subbus; 611 uint_t io_base, io_limit, mem_base, mem_limit; 612 uint_t io_size, mem_size; 613 uint64_t addr = 0; 614 int *regp = NULL; 615 uint_t reglen; 616 int rv, cap_ptr, physhi; 617 dev_info_t *dip; 618 uint16_t cmd_reg; 619 struct memlist *list; 620 621 /* skip root (peer) PCI busses */ 622 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 623 return; 624 625 /* skip subtractive PPB when prog_sub is not TRUE */ 626 if (pci_bus_res[secbus].subtractive && !prog_sub) 627 return; 628 629 /* some entries may be empty due to discontiguous bus numbering */ 630 dip = pci_bus_res[secbus].dip; 631 if (dip == NULL) 632 return; 633 634 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 635 "reg", ®p, ®len); 636 ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 637 physhi = regp[0]; 638 ddi_prop_free(regp); 639 640 func = (uchar_t)PCI_REG_FUNC_G(physhi); 641 dev = (uchar_t)PCI_REG_DEV_G(physhi); 642 bus = (uchar_t)PCI_REG_BUS_G(physhi); 643 644 /* 645 * If pcie bridge, check to see if link is enabled 646 */ 647 cap_ptr = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 648 "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL); 649 if (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 650 cmd_reg = pci_getw(bus, dev, func, 651 (uint16_t)cap_ptr + PCIE_LINKCTL); 652 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 653 dcmn_err(CE_NOTE, 654 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 655 bus, dev, func); 656 return; 657 } 658 } 659 660 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 661 parbus = pci_bus_res[secbus].par_bus; 662 ASSERT(parbus == bus); 663 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 664 665 /* 666 * If we have a Cardbus bridge, but no bus space 667 */ 668 if (pci_bus_res[secbus].num_cbb != 0 && 669 pci_bus_res[secbus].bus_space == NULL) { 670 uchar_t range; 671 672 /* normally there are 2 buses under a cardbus bridge */ 673 range = pci_bus_res[secbus].num_cbb * 2; 674 675 /* 676 * Try to find and allocate a bus-range starting at subbus+1 677 * from the parent of the PPB. 678 */ 679 for (; range != 0; range--) { 680 if (memlist_find_with_startaddr( 681 &pci_bus_res[parbus].bus_space, 682 subbus + 1, range, 1) != NULL) 683 break; /* find bus range resource at parent */ 684 } 685 if (range != 0) { 686 memlist_insert(&pci_bus_res[secbus].bus_space, 687 subbus + 1, range); 688 subbus = subbus + range; 689 pci_bus_res[secbus].sub_bus = subbus; 690 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 691 add_bus_range_prop(secbus); 692 693 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 694 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 695 secbus, subbus); 696 } 697 } 698 699 /* 700 * Calculate required IO size 701 * We are going to assign 512 bytes per bus. The size needs to be 702 * 4K aligned and the maximum size is 16K. 703 */ 704 io_size = (subbus - secbus + 1) * 0x200; 705 io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1)); 706 if (io_size > 0x4 * PPB_IO_ALIGNMENT) 707 io_size = 0x4 * PPB_IO_ALIGNMENT; 708 /* 709 * Calculate required MEM size 710 * We are going to assign 1M bytes per bus. The size needs to be 711 * 1M aligned and the maximum size is 8M. 712 */ 713 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 714 if (mem_size > 0x8 * PPB_MEM_ALIGNMENT) 715 mem_size = 0x8 * PPB_MEM_ALIGNMENT; 716 717 /* Subtractive bridge */ 718 if (pci_bus_res[secbus].subtractive && prog_sub) { 719 /* 720 * We program an arbitrary amount of I/O and memory resource 721 * for the subtractive bridge so that child dynamic-resource- 722 * allocating devices (such as Cardbus bridges) have a chance 723 * of success. Until we have full-tree resource rebalancing, 724 * dynamic resource allocation (thru busra) only looks at the 725 * parent bridge, so all PPBs must have some allocatable 726 * resource. For non-subtractive bridges, the resources come 727 * from the base/limit register "windows", but subtractive 728 * bridges often don't program those (since they don't need to). 729 * If we put all the remaining resources on the subtractive 730 * bridge, then peer non-subtractive bridges can't allocate 731 * more space (even though this is probably most correct). 732 * If we put the resources only on the parent, then allocations 733 * from children of subtractive bridges will fail without 734 * special-case code for bypassing the subtractive bridge. 735 * This solution is the middle-ground temporary solution until 736 * we have fully-capable resource allocation. 737 */ 738 739 /* 740 * Add an arbitrary I/O resource to the subtractive PPB 741 */ 742 if (pci_bus_res[secbus].io_ports == NULL) { 743 addr = get_parbus_io_res(parbus, secbus, io_size, 744 PPB_IO_ALIGNMENT); 745 if (addr) { 746 add_ppb_ranges_prop(secbus); 747 pci_bus_res[secbus].io_reprogram = 748 pci_bus_res[parbus].io_reprogram; 749 750 cmn_err(CE_NOTE, "!add io-range on subtractive" 751 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 752 bus, dev, func, (uint32_t)addr, 753 (uint32_t)addr + io_size - 1); 754 } 755 } 756 /* 757 * Add an arbitrary memory resource to the subtractive PPB 758 */ 759 if (pci_bus_res[secbus].mem_space == NULL) { 760 addr = get_parbus_mem_res(parbus, secbus, mem_size, 761 PPB_MEM_ALIGNMENT); 762 if (addr) { 763 add_ppb_ranges_prop(secbus); 764 pci_bus_res[secbus].mem_reprogram = 765 pci_bus_res[parbus].mem_reprogram; 766 767 cmn_err(CE_NOTE, "!add mem-range on " 768 "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 769 bus, dev, func, (uint32_t)addr, 770 (uint32_t)addr + mem_size - 1); 771 } 772 } 773 774 goto cmd_enable; 775 } 776 777 /* 778 * Check to see if we need to reprogram I/O space, either because the 779 * parent bus needed reprogramming and so do we, or because I/O space is 780 * disabled in base/limit or command register. 781 */ 782 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 783 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 784 io_base = (io_base & 0xf0) << 8; 785 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 786 787 if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) || 788 (!(cmd_reg & PCI_COMM_IO))) { 789 if (pci_bus_res[secbus].io_ports_used) { 790 memlist_merge(&pci_bus_res[secbus].io_ports_used, 791 &pci_bus_res[secbus].io_ports); 792 } 793 if (pci_bus_res[secbus].io_ports && 794 (!pci_bus_res[parbus].io_reprogram) && 795 (!pci_bus_res[parbus].subtractive)) { 796 /* rechoose old io ports info */ 797 list = pci_bus_res[secbus].io_ports; 798 io_base = (uint_t)list->address; 799 /* 4K aligned */ 800 io_base = io_base & (~(PPB_IO_ALIGNMENT - 1)); 801 io_limit = (uint_t)(list->address + list->size); 802 while (list->next) { 803 list = list->next; 804 if ((list->address + list->size) > io_limit) 805 io_limit = (uint_t) 806 (list->address + list->size); 807 } 808 io_limit = io_limit - 1; 809 /* 4K aligned */ 810 io_limit = (io_limit + PPB_IO_ALIGNMENT) & 811 (~(PPB_IO_ALIGNMENT - 1)); 812 io_size = io_limit - io_base; 813 io_limit = io_limit - 1; 814 ASSERT(io_base <= io_limit); 815 memlist_free_all(&pci_bus_res[secbus].io_ports); 816 memlist_insert(&pci_bus_res[secbus].io_ports, 817 io_base, io_size); 818 memlist_insert(&pci_bus_res[parbus].io_ports_used, 819 io_base, io_size); 820 if (pci_bus_res[parbus].io_ports) 821 (void) memlist_remove( 822 &pci_bus_res[parbus].io_ports, 823 io_base, io_size); 824 pci_bus_res[secbus].io_reprogram = B_TRUE; 825 } else { 826 /* get new io ports from parent bus */ 827 addr = get_parbus_io_res(parbus, secbus, io_size, 828 PPB_IO_ALIGNMENT); 829 if (addr) { 830 io_base = addr; 831 io_limit = addr + io_size - 1; 832 pci_bus_res[secbus].io_reprogram = B_TRUE; 833 } 834 } 835 if (pci_bus_res[secbus].io_reprogram) { 836 /* reprogram PPB regs */ 837 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 838 (uchar_t)((io_base>>8) & 0xf0)); 839 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 840 (uchar_t)((io_limit>>8) & 0xf0)); 841 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 842 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 843 add_ppb_ranges_prop(secbus); 844 845 cmn_err(CE_NOTE, "!reprogram io-range on" 846 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 847 bus, dev, func, io_base, io_limit); 848 } 849 } 850 851 /* 852 * Check memory space as we did I/O space. 853 */ 854 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 855 mem_base = (mem_base & 0xfff0) << 16; 856 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 857 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 858 859 if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) || 860 (!(cmd_reg & PCI_COMM_MAE))) { 861 if (pci_bus_res[secbus].mem_space_used) { 862 memlist_merge(&pci_bus_res[secbus].mem_space_used, 863 &pci_bus_res[secbus].mem_space); 864 } 865 if (pci_bus_res[secbus].mem_space && 866 (!pci_bus_res[parbus].mem_reprogram) && 867 (!pci_bus_res[parbus].subtractive)) { 868 /* rechoose old mem resource */ 869 list = pci_bus_res[secbus].mem_space; 870 mem_base = (uint_t)list->address; 871 /* 1M aligned */ 872 mem_base = mem_base & (~0xfffff); 873 mem_limit = (uint_t)(list->address + list->size); 874 while (list->next) { 875 list = list->next; 876 if ((list->address + list->size) > mem_limit) 877 mem_limit = (uint_t) 878 (list->address + list->size); 879 } 880 mem_limit = mem_limit - 1; 881 /* 1M aligned */ 882 mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) & 883 (~(PPB_MEM_ALIGNMENT - 1)); 884 mem_size = mem_limit - mem_base; 885 mem_limit = mem_limit - 1; 886 ASSERT(mem_base <= mem_limit); 887 memlist_free_all(&pci_bus_res[secbus].mem_space); 888 memlist_insert(&pci_bus_res[secbus].mem_space, 889 mem_base, mem_size); 890 memlist_insert(&pci_bus_res[parbus].mem_space_used, 891 mem_base, mem_size); 892 if (pci_bus_res[parbus].mem_space) 893 (void) memlist_remove( 894 &pci_bus_res[parbus].mem_space, 895 mem_base, mem_size); 896 pci_bus_res[secbus].mem_reprogram = B_TRUE; 897 } else { 898 /* get new mem resource from parent bus */ 899 addr = get_parbus_mem_res(parbus, secbus, mem_size, 900 PPB_MEM_ALIGNMENT); 901 if (addr) { 902 mem_base = addr; 903 mem_limit = addr + mem_size - 1; 904 pci_bus_res[secbus].mem_reprogram = B_TRUE; 905 } 906 } 907 908 if (pci_bus_res[secbus].mem_reprogram) { 909 /* reprogram PPB regs */ 910 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 911 (uint16_t)((mem_base>>16) & 0xfff0)); 912 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 913 (uint16_t)((mem_limit>>16) & 0xfff0)); 914 add_ppb_ranges_prop(secbus); 915 916 cmn_err(CE_NOTE, "!reprogram mem-range on" 917 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 918 bus, dev, func, mem_base, mem_limit); 919 } 920 } 921 922 cmd_enable: 923 if (pci_bus_res[secbus].io_ports) 924 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 925 if (pci_bus_res[secbus].mem_space) 926 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 927 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 928 } 929 930 void 931 pci_reprogram(void) 932 { 933 int i, pci_reconfig = 1; 934 char *onoff; 935 936 /* 937 * Excise phantom roots if possible 938 */ 939 pci_renumber_root_busses(); 940 941 /* add bus-range property for root/peer bus nodes */ 942 for (i = 0; i <= pci_bios_nbus; i++) { 943 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 944 uchar_t subbus; 945 if (pci_root_subbus(i, &subbus) == AE_OK) 946 pci_bus_res[i].sub_bus = subbus; 947 add_bus_range_prop(i); 948 } 949 /* setup bus range resource on each bus */ 950 setup_bus_res(i); 951 } 952 953 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 954 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 955 if (strcmp(onoff, "off") == 0) { 956 pci_reconfig = 0; 957 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 958 } 959 ddi_prop_free(onoff); 960 } 961 962 /* remove used-resources from PCI resource maps */ 963 remove_used_resources(); 964 remove_subtractive_res(); 965 966 /* reprogram the non-subtractive PPB */ 967 if (pci_reconfig) 968 for (i = 0; i <= pci_bios_nbus; i++) 969 fix_ppb_res(i, B_FALSE); 970 971 for (i = 0; i <= pci_bios_nbus; i++) { 972 /* configure devices not configured by BIOS */ 973 if (pci_reconfig) { 974 /* 975 * Reprogram the subtractive PPB. At this time, all its 976 * siblings should have got their resources already. 977 */ 978 if (pci_bus_res[i].subtractive) 979 fix_ppb_res(i, B_TRUE); 980 enumerate_bus_devs(i, CONFIG_NEW); 981 } 982 /* All dev programmed, so we can create available prop */ 983 add_bus_available_prop(i); 984 } 985 } 986 987 /* 988 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 989 */ 990 static void 991 create_root_bus_dip(uchar_t bus) 992 { 993 int pci_regs[] = {0, 0, 0}; 994 dev_info_t *dip; 995 996 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 997 998 num_root_bus++; 999 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1000 (pnode_t)DEVI_SID_NODEID, &dip); 1001 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1002 "#address-cells", 3); 1003 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1004 "#size-cells", 2); 1005 pci_regs[0] = pci_bus_res[bus].root_addr; 1006 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1007 "reg", (int *)pci_regs, 3); 1008 1009 /* 1010 * If system has PCIe bus, then create different properties 1011 */ 1012 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1013 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1014 "device_type", "pci"); 1015 1016 (void) ndi_devi_bind_driver(dip, 0); 1017 pci_bus_res[bus].dip = dip; 1018 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 1019 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 1020 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 1021 1022 if (bus != 0) 1023 return; 1024 1025 /* 1026 * Special treatment of bus 0: 1027 * If no resource from MPSPEC/HRT, copy pcimem from boot 1028 * and make I/O space the entire range starting at 0x100. There 1029 * is no difference between prefetchable memory or not. 1030 */ 1031 if (pci_bus_res[0].mem_space == NULL) 1032 pci_bus_res[0].mem_space = 1033 memlist_dup(bootops->boot_mem->pcimem); 1034 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1035 if (pci_bus_res[0].io_ports == NULL) 1036 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 1037 } 1038 1039 /* 1040 * For any fixed configuration (often compatability) pci devices 1041 * and those with their own expansion rom, create device nodes 1042 * to hold the already configured device details. 1043 */ 1044 void 1045 enumerate_bus_devs(uchar_t bus, int config_op) 1046 { 1047 uchar_t dev, func, nfunc, header; 1048 ushort_t venid; 1049 struct pci_devfunc *devlist = NULL, *entry; 1050 1051 if (config_op == CONFIG_NEW) { 1052 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1053 } else if (config_op == CONFIG_FIX) { 1054 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 1055 } else 1056 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1057 1058 for (dev = 0; dev < max_dev_pci; dev++) { 1059 nfunc = 1; 1060 for (func = 0; func < nfunc; func++) { 1061 1062 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 1063 dev, func); 1064 1065 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1066 1067 if ((venid == 0xffff) || (venid == 0)) { 1068 /* no function at this address */ 1069 continue; 1070 } 1071 1072 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1073 if (header == 0xff) { 1074 continue; /* illegal value */ 1075 } 1076 1077 /* 1078 * according to some mail from Microsoft posted 1079 * to the pci-drivers alias, their only requirement 1080 * for a multifunction device is for the 1st 1081 * function to have to PCI_HEADER_MULTI bit set. 1082 */ 1083 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1084 nfunc = 8; 1085 } 1086 1087 if (config_op == CONFIG_FIX || 1088 config_op == CONFIG_INFO) { 1089 /* 1090 * Create the node, unconditionally, on the 1091 * first pass only. It may still need 1092 * resource assignment, which will be 1093 * done on the second, CONFIG_NEW, pass. 1094 */ 1095 process_devfunc(bus, dev, func, header, 1096 venid, config_op); 1097 1098 } 1099 } 1100 } 1101 1102 if (config_op == CONFIG_NEW) { 1103 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1104 while (devlist) { 1105 entry = devlist; 1106 devlist = entry->next; 1107 if (entry->reprogram || 1108 pci_bus_res[bus].io_reprogram || 1109 pci_bus_res[bus].mem_reprogram) { 1110 /* reprogram device(s) */ 1111 (void) add_reg_props(entry->dip, bus, 1112 entry->dev, entry->func, CONFIG_NEW, 0); 1113 } 1114 kmem_free(entry, sizeof (*entry)); 1115 } 1116 pci_bus_res[bus].privdata = NULL; 1117 } 1118 } 1119 1120 static int 1121 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1122 ushort_t subvenid, ushort_t subdevid) 1123 { 1124 static int prop_exist = -1; 1125 static char *pciide_str; 1126 char compat[32]; 1127 1128 if (prop_exist == -1) { 1129 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1130 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1131 &pciide_str) == DDI_SUCCESS); 1132 } 1133 1134 if (!prop_exist) 1135 return (0); 1136 1137 /* compare property value against various forms of compatible */ 1138 if (subvenid) { 1139 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1140 venid, devid, subvenid, subdevid, revid); 1141 if (strcmp(pciide_str, compat) == 0) 1142 return (1); 1143 1144 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1145 venid, devid, subvenid, subdevid); 1146 if (strcmp(pciide_str, compat) == 0) 1147 return (1); 1148 1149 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1150 subvenid, subdevid); 1151 if (strcmp(pciide_str, compat) == 0) 1152 return (1); 1153 } 1154 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1155 venid, devid, revid); 1156 if (strcmp(pciide_str, compat) == 0) 1157 return (1); 1158 1159 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1160 if (strcmp(pciide_str, compat) == 0) 1161 return (1); 1162 1163 return (0); 1164 } 1165 1166 static int 1167 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1168 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1169 { 1170 struct ide_table { /* table for PCI_MASS_OTHER */ 1171 ushort_t venid; 1172 ushort_t devid; 1173 } *entry; 1174 1175 /* XXX SATA and other devices: need a way to add dynamically */ 1176 static struct ide_table ide_other[] = { 1177 {0x1095, 0x3112}, 1178 {0x1095, 0x3114}, 1179 {0x1095, 0x3512}, 1180 {0x1095, 0x680}, /* Sil0680 */ 1181 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1182 {0, 0} 1183 }; 1184 1185 if (basecl != PCI_CLASS_MASS) 1186 return (0); 1187 1188 if (subcl == PCI_MASS_IDE) { 1189 return (1); 1190 } 1191 1192 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1193 return (1); 1194 1195 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1196 return (0); 1197 } 1198 1199 entry = &ide_other[0]; 1200 while (entry->venid) { 1201 if (entry->venid == venid && entry->devid == devid) 1202 return (1); 1203 entry++; 1204 } 1205 return (0); 1206 } 1207 1208 static int 1209 is_display(uint_t classcode) 1210 { 1211 static uint_t disp_classes[] = { 1212 0x000100, 1213 0x030000, 1214 0x030001 1215 }; 1216 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1217 1218 for (i = 0; i < nclasses; i++) { 1219 if (classcode == disp_classes[i]) 1220 return (1); 1221 } 1222 return (0); 1223 } 1224 1225 static void 1226 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1227 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1228 { 1229 struct pci_fixundo *newundo; 1230 1231 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1232 1233 /* 1234 * Adding an item to this list means that we must turn its NMIENABLE 1235 * bit back on at a later time. 1236 */ 1237 newundo->bus = bus; 1238 newundo->dev = dev; 1239 newundo->fn = fn; 1240 newundo->undofn = undofn; 1241 newundo->next = undolist; 1242 1243 /* add to the undo list in LIFO order */ 1244 undolist = newundo; 1245 } 1246 1247 void 1248 add_pci_fixes(void) 1249 { 1250 int i; 1251 1252 for (i = 0; i <= pci_bios_nbus; i++) { 1253 /* 1254 * For each bus, apply needed fixes to the appropriate devices. 1255 * This must be done before the main enumeration loop because 1256 * some fixes must be applied to devices normally encountered 1257 * later in the pci scan (e.g. if a fix to device 7 must be 1258 * applied before scanning device 6, applying fixes in the 1259 * normal enumeration loop would obviously be too late). 1260 */ 1261 enumerate_bus_devs(i, CONFIG_FIX); 1262 } 1263 } 1264 1265 void 1266 undo_pci_fixes(void) 1267 { 1268 struct pci_fixundo *nextundo; 1269 uint8_t bus, dev, fn; 1270 1271 /* 1272 * All fixes in the undo list are performed unconditionally. Future 1273 * fixes may require selective undo. 1274 */ 1275 while (undolist != NULL) { 1276 1277 bus = undolist->bus; 1278 dev = undolist->dev; 1279 fn = undolist->fn; 1280 1281 (*(undolist->undofn))(bus, dev, fn); 1282 1283 nextundo = undolist->next; 1284 kmem_free(undolist, sizeof (struct pci_fixundo)); 1285 undolist = nextundo; 1286 } 1287 } 1288 1289 static void 1290 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1291 { 1292 uint8_t val8; 1293 1294 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1295 /* 1296 * The NMIONERR bit is turned back on to allow the SMM BIOS 1297 * to handle more critical PCI errors (e.g. PERR#). 1298 */ 1299 val8 |= AMD8111_ENABLENMI; 1300 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1301 } 1302 1303 static void 1304 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1305 { 1306 uint8_t val8; 1307 1308 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1309 1310 if ((val8 & AMD8111_ENABLENMI) == 0) 1311 return; 1312 1313 /* 1314 * We reset NMIONERR in the LPC because master-abort on the PCI 1315 * bridge side of the 8111 will cause NMI, which might cause SMI, 1316 * which sometimes prevents all devices from being enumerated. 1317 */ 1318 val8 &= ~AMD8111_ENABLENMI; 1319 1320 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1321 1322 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1323 } 1324 1325 static void 1326 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1327 { 1328 uint16_t status; 1329 uint8_t header; 1330 uint8_t cap_ptr; 1331 uint8_t cap_id; 1332 uint16_t pmcsr; 1333 1334 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1335 if (!(status & PCI_STAT_CAP)) 1336 return; /* No capabilities list */ 1337 1338 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1339 if (header == PCI_HEADER_CARDBUS) 1340 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_RESERVED1); 1341 else 1342 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1343 /* 1344 * Walk the capabilities list searching for a PM entry. 1345 */ 1346 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1347 cap_ptr &= PCI_CAP_PTR_MASK; 1348 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1349 if (cap_id == PCI_CAP_ID_PM) { 1350 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1351 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1352 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1353 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1354 break; 1355 } 1356 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1357 } 1358 1359 } 1360 1361 static void 1362 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1363 ushort_t vendorid, int config_op) 1364 { 1365 char nodename[32], unitaddr[5]; 1366 dev_info_t *dip; 1367 uchar_t basecl, subcl, progcl, intr, revid; 1368 ushort_t subvenid, subdevid, status; 1369 ushort_t slot_num; 1370 uint_t classcode, revclass; 1371 int reprogram = 0, pciide = 0; 1372 int power[2] = {1, 1}; 1373 int pciex = 0; 1374 ushort_t is_pci_bridge = 0; 1375 struct pci_devfunc *devlist = NULL, *entry = NULL; 1376 iommu_private_t *private; 1377 1378 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 1379 1380 switch (header & PCI_HEADER_TYPE_M) { 1381 case PCI_HEADER_ZERO: 1382 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 1383 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 1384 break; 1385 case PCI_HEADER_CARDBUS: 1386 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 1387 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 1388 /* Record the # of cardbus bridges found on the bus */ 1389 if (config_op == CONFIG_INFO) 1390 pci_bus_res[bus].num_cbb++; 1391 break; 1392 default: 1393 subvenid = 0; 1394 subdevid = 0; 1395 break; 1396 } 1397 1398 if (config_op == CONFIG_FIX) { 1399 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1400 pci_fix_amd8111(bus, dev, func); 1401 } 1402 return; 1403 } 1404 1405 /* XXX should be use generic names? derive from class? */ 1406 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1407 classcode = revclass >> 8; 1408 revid = revclass & 0xff; 1409 1410 /* figure out if this is pci-ide */ 1411 basecl = classcode >> 16; 1412 subcl = (classcode >> 8) & 0xff; 1413 progcl = classcode & 0xff; 1414 1415 1416 if (is_display(classcode)) 1417 (void) snprintf(nodename, sizeof (nodename), "display"); 1418 else if (subvenid != 0) 1419 (void) snprintf(nodename, sizeof (nodename), 1420 "pci%x,%x", subvenid, subdevid); 1421 else 1422 (void) snprintf(nodename, sizeof (nodename), 1423 "pci%x,%x", vendorid, deviceid); 1424 1425 /* make sure parent bus dip has been created */ 1426 if (pci_bus_res[bus].dip == NULL) { 1427 create_root_bus_dip(bus); 1428 } 1429 1430 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1431 DEVI_SID_NODEID, &dip); 1432 1433 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1434 &is_pci_bridge) == B_TRUE) 1435 pciex = 1; 1436 1437 /* add properties */ 1438 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1439 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1440 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1441 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1442 "class-code", classcode); 1443 if (func == 0) 1444 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1445 else 1446 (void) snprintf(unitaddr, sizeof (unitaddr), 1447 "%x,%x", dev, func); 1448 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1449 "unit-address", unitaddr); 1450 1451 /* add device_type for display nodes */ 1452 if (is_display(classcode)) { 1453 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1454 "device_type", "display"); 1455 } 1456 /* add special stuff for header type */ 1457 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1458 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1459 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1460 1461 if (subvenid != 0) { 1462 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1463 "subsystem-id", subdevid); 1464 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1465 "subsystem-vendor-id", subvenid); 1466 } 1467 if (!pciex) 1468 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1469 "min-grant", mingrant); 1470 if (!pciex) 1471 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1472 "max-latency", maxlatency); 1473 } 1474 1475 /* interrupt, record if not 0 */ 1476 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1477 if (intr != 0) 1478 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1479 "interrupts", intr); 1480 1481 /* 1482 * Add support for 133 mhz pci eventually 1483 */ 1484 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1485 1486 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1487 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1488 if (!pciex && (status & PCI_STAT_FBBC)) 1489 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1490 "fast-back-to-back"); 1491 if (!pciex && (status & PCI_STAT_66MHZ)) 1492 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1493 "66mhz-capable"); 1494 if (status & PCI_STAT_UDF) 1495 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1496 "udf-supported"); 1497 if (pciex && slot_num) { 1498 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1499 "physical-slot#", slot_num); 1500 if (!is_pci_bridge) 1501 pciex_slot_names_prop(dip, slot_num); 1502 } 1503 1504 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1505 "power-consumption", power, 2); 1506 1507 /* Set the device PM state to D0 */ 1508 set_devpm_d0(bus, dev, func); 1509 1510 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1511 add_ppb_props(dip, bus, dev, func, pciex); 1512 else { 1513 /* 1514 * Record the non-PPB devices on the bus for possible 1515 * reprogramming at 2nd bus enumeration. 1516 * Note: PPB reprogramming is done in fix_ppb_res() 1517 */ 1518 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1519 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 1520 entry->dip = dip; 1521 entry->dev = dev; 1522 entry->func = func; 1523 entry->next = devlist; 1524 pci_bus_res[bus].privdata = entry; 1525 } 1526 1527 if (config_op == CONFIG_INFO && 1528 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1529 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1530 } 1531 1532 /* check for ck8-04 based PCI ISA bridge only */ 1533 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1534 (func == 0)) 1535 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1536 1537 if (pciex && is_pci_bridge) 1538 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1539 (char *)"PCIe-PCI bridge"); 1540 else 1541 add_model_prop(dip, classcode); 1542 1543 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1544 revid, classcode, pciex); 1545 1546 /* 1547 * See if this device is a controller that advertises 1548 * itself to be a standard ATA task file controller, or one that 1549 * has been hard coded. 1550 * 1551 * If it is, check if any other higher precedence driver listed in 1552 * driver_aliases will claim the node by calling 1553 * ddi_compatibile_driver_major. If so, clear pciide and do not 1554 * create a pci-ide node or any other special handling. 1555 * 1556 * If another driver does not bind, set the node name to pci-ide 1557 * and then let the special pci-ide handling for registers and 1558 * child pci-ide nodes proceed below. 1559 */ 1560 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 1561 subvenid, subdevid) == 1) { 1562 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 1563 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 1564 pciide = 1; 1565 } 1566 } 1567 1568 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1569 (void) ndi_devi_bind_driver(dip, 0); 1570 1571 /* special handling for pci-ide */ 1572 if (pciide) { 1573 dev_info_t *cdip; 1574 1575 /* 1576 * Create properties specified by P1275 Working Group 1577 * Proposal #414 Version 1 1578 */ 1579 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1580 "device_type", "pci-ide"); 1581 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1582 "#address-cells", 1); 1583 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1584 "#size-cells", 0); 1585 1586 /* allocate two child nodes */ 1587 ndi_devi_alloc_sleep(dip, "ide", 1588 (pnode_t)DEVI_SID_NODEID, &cdip); 1589 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1590 "reg", 0); 1591 (void) ndi_devi_bind_driver(cdip, 0); 1592 ndi_devi_alloc_sleep(dip, "ide", 1593 (pnode_t)DEVI_SID_NODEID, &cdip); 1594 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1595 "reg", 1); 1596 (void) ndi_devi_bind_driver(cdip, 0); 1597 1598 reprogram = 0; /* don't reprogram pci-ide bridge */ 1599 } 1600 1601 /* allocate and set up iommu private */ 1602 private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP); 1603 private->idp_seg = 0; 1604 private->idp_bus = bus; 1605 private->idp_devfn = (dev << 3) | func; 1606 private->idp_sec = 0; 1607 private->idp_sub = 0; 1608 private->idp_bbp_type = IOMMU_PPB_NONE; 1609 /* record the bridge */ 1610 private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) && 1611 (subcl == PCI_BRIDGE_PCI)); 1612 if (private->idp_is_bridge) { 1613 private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1614 private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1615 if (pciex && is_pci_bridge) 1616 private->idp_bbp_type = IOMMU_PPB_PCIE_PCI; 1617 else if (pciex) 1618 private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE; 1619 else 1620 private->idp_bbp_type = IOMMU_PPB_PCI_PCI; 1621 } 1622 /* record the special devices */ 1623 private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE); 1624 private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) && 1625 (subcl == PCI_BRIDGE_ISA)); 1626 private->idp_domain = NULL; 1627 /* hook the private to dip */ 1628 DEVI(dip)->devi_iommu_private = private; 1629 1630 if (reprogram && (entry != NULL)) 1631 entry->reprogram = B_TRUE; 1632 } 1633 1634 /* 1635 * Set the compatible property to a value compliant with 1636 * rev 2.1 of the IEEE1275 PCI binding. 1637 * (Also used for PCI-Express devices). 1638 * 1639 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1640 * pciVVVV,DDDD.SSSS.ssss (1) 1641 * pciSSSS,ssss (2) 1642 * pciVVVV,DDDD.RR (3) 1643 * pciVVVV,DDDD (4) 1644 * pciclass,CCSSPP (5) 1645 * pciclass,CCSS (6) 1646 * 1647 * The Subsystem (SSSS) forms are not inserted if 1648 * subsystem-vendor-id is 0. 1649 * 1650 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1651 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1652 * 1653 * Set with setprop and \x00 between each 1654 * to generate the encoded string array form. 1655 */ 1656 void 1657 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1658 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1659 int pciex) 1660 { 1661 int i = 0; 1662 int size = COMPAT_BUFSIZE; 1663 char *compat[13]; 1664 char *buf, *curr; 1665 1666 curr = buf = kmem_alloc(size, KM_SLEEP); 1667 1668 if (pciex) { 1669 if (subvenid) { 1670 compat[i++] = curr; /* form 0 */ 1671 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1672 vendorid, deviceid, subvenid, subdevid, revid); 1673 size -= strlen(curr) + 1; 1674 curr += strlen(curr) + 1; 1675 1676 compat[i++] = curr; /* form 1 */ 1677 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1678 vendorid, deviceid, subvenid, subdevid); 1679 size -= strlen(curr) + 1; 1680 curr += strlen(curr) + 1; 1681 1682 } 1683 compat[i++] = curr; /* form 3 */ 1684 (void) snprintf(curr, size, "pciex%x,%x.%x", 1685 vendorid, deviceid, revid); 1686 size -= strlen(curr) + 1; 1687 curr += strlen(curr) + 1; 1688 1689 compat[i++] = curr; /* form 4 */ 1690 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1691 size -= strlen(curr) + 1; 1692 curr += strlen(curr) + 1; 1693 1694 compat[i++] = curr; /* form 5 */ 1695 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1696 size -= strlen(curr) + 1; 1697 curr += strlen(curr) + 1; 1698 1699 compat[i++] = curr; /* form 6 */ 1700 (void) snprintf(curr, size, "pciexclass,%04x", 1701 (classcode >> 8)); 1702 size -= strlen(curr) + 1; 1703 curr += strlen(curr) + 1; 1704 } 1705 1706 if (subvenid) { 1707 compat[i++] = curr; /* form 0 */ 1708 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1709 vendorid, deviceid, subvenid, subdevid, revid); 1710 size -= strlen(curr) + 1; 1711 curr += strlen(curr) + 1; 1712 1713 compat[i++] = curr; /* form 1 */ 1714 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1715 vendorid, deviceid, subvenid, subdevid); 1716 size -= strlen(curr) + 1; 1717 curr += strlen(curr) + 1; 1718 1719 compat[i++] = curr; /* form 2 */ 1720 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1721 size -= strlen(curr) + 1; 1722 curr += strlen(curr) + 1; 1723 } 1724 compat[i++] = curr; /* form 3 */ 1725 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1726 size -= strlen(curr) + 1; 1727 curr += strlen(curr) + 1; 1728 1729 compat[i++] = curr; /* form 4 */ 1730 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1731 size -= strlen(curr) + 1; 1732 curr += strlen(curr) + 1; 1733 1734 compat[i++] = curr; /* form 5 */ 1735 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1736 size -= strlen(curr) + 1; 1737 curr += strlen(curr) + 1; 1738 1739 compat[i++] = curr; /* form 6 */ 1740 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1741 size -= strlen(curr) + 1; 1742 curr += strlen(curr) + 1; 1743 1744 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1745 "compatible", compat, i); 1746 kmem_free(buf, COMPAT_BUFSIZE); 1747 } 1748 1749 /* 1750 * Adjust the reg properties for a dual channel PCI-IDE device. 1751 * 1752 * NOTE: don't do anything that changes the order of the hard-decodes 1753 * and programmed BARs. The kernel driver depends on these values 1754 * being in this order regardless of whether they're for a 'native' 1755 * mode BAR or not. 1756 */ 1757 /* 1758 * config info for pci-ide devices 1759 */ 1760 static struct { 1761 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1762 uchar_t bar_offset; /* offset for alt status register */ 1763 ushort_t addr; /* compatibility mode base address */ 1764 ushort_t length; /* number of ports for this BAR */ 1765 } pciide_bar[] = { 1766 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1767 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1768 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1769 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1770 }; 1771 1772 static int 1773 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1774 { 1775 int hard_decode = 0; 1776 1777 /* 1778 * Adjust the base and len for the BARs of the PCI-IDE 1779 * device's primary and secondary controllers. The first 1780 * two BARs are for the primary controller and the next 1781 * two BARs are for the secondary controller. The fifth 1782 * and sixth bars are never adjusted. 1783 */ 1784 if (index >= 0 && index <= 3) { 1785 *lenp = pciide_bar[index].length; 1786 1787 if (progcl & pciide_bar[index].native_mask) { 1788 *basep += pciide_bar[index].bar_offset; 1789 } else { 1790 *basep = pciide_bar[index].addr; 1791 hard_decode = 1; 1792 } 1793 } 1794 1795 /* 1796 * if either base or len is zero make certain both are zero 1797 */ 1798 if (*basep == 0 || *lenp == 0) { 1799 *basep = 0; 1800 *lenp = 0; 1801 hard_decode = 0; 1802 } 1803 1804 return (hard_decode); 1805 } 1806 1807 1808 /* 1809 * Add the "reg" and "assigned-addresses" property 1810 */ 1811 static int 1812 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1813 int config_op, int pciide) 1814 { 1815 uchar_t baseclass, subclass, progclass, header; 1816 ushort_t bar_sz; 1817 uint_t value = 0, len, devloc; 1818 uint_t base, base_hi, type; 1819 ushort_t offset, end; 1820 int max_basereg, j, reprogram = 0; 1821 uint_t phys_hi; 1822 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1823 struct memlist **io_res_used, **mres_used; 1824 struct memlist **mem_res_used, **pmem_res_used; 1825 uchar_t res_bus; 1826 1827 pci_regspec_t regs[16] = {{0}}; 1828 pci_regspec_t assigned[15] = {{0}}; 1829 int nreg, nasgn; 1830 1831 io_res = &pci_bus_res[bus].io_ports; 1832 io_res_used = &pci_bus_res[bus].io_ports_used; 1833 mem_res = &pci_bus_res[bus].mem_space; 1834 mem_res_used = &pci_bus_res[bus].mem_space_used; 1835 if (bus == 0) { /* for bus 0, there is only mem_space */ 1836 pmem_res = mem_res; 1837 pmem_res_used = mem_res_used; 1838 } else { 1839 pmem_res = &pci_bus_res[bus].pmem_space; 1840 pmem_res_used = &pci_bus_res[bus].pmem_space_used; 1841 } 1842 1843 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1844 regs[0].pci_phys_hi = devloc; 1845 nreg = 1; /* rest of regs[0] is all zero */ 1846 nasgn = 0; 1847 1848 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1849 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1850 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1851 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1852 1853 switch (header) { 1854 case PCI_HEADER_ZERO: 1855 max_basereg = PCI_BASE_NUM; 1856 break; 1857 case PCI_HEADER_PPB: 1858 max_basereg = PCI_BCNF_BASE_NUM; 1859 break; 1860 case PCI_HEADER_CARDBUS: 1861 max_basereg = PCI_CBUS_BASE_NUM; 1862 break; 1863 default: 1864 max_basereg = 0; 1865 break; 1866 } 1867 1868 /* 1869 * Create the register property by saving the current 1870 * value of the base register. Write 0xffffffff to the 1871 * base register. Read the value back to determine the 1872 * required size of the address space. Restore the base 1873 * register contents. 1874 * 1875 * Do not disable I/O and memory access; this isn't necessary 1876 * since no driver is yet attached to this device, and disabling 1877 * I/O and memory access has the side-effect of disabling PCI-PCI 1878 * bridge mappings, which makes the bridge transparent to secondary- 1879 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1880 * Spec V1.2). 1881 */ 1882 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1883 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1884 j++, offset += bar_sz) { 1885 int hard_decode = 0; 1886 1887 /* determine the size of the address space */ 1888 base = pci_getl(bus, dev, func, offset); 1889 pci_putl(bus, dev, func, offset, 0xffffffff); 1890 value = pci_getl(bus, dev, func, offset); 1891 pci_putl(bus, dev, func, offset, base); 1892 1893 /* construct phys hi,med.lo, size hi, lo */ 1894 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1895 /* i/o space */ 1896 bar_sz = PCI_BAR_SZ_32; 1897 value &= PCI_BASE_IO_ADDR_M; 1898 len = ((value ^ (value-1)) + 1) >> 1; 1899 1900 /* XXX Adjust first 4 IDE registers */ 1901 if (pciide) { 1902 if (subclass != PCI_MASS_IDE) 1903 progclass = (PCI_IDE_IF_NATIVE_PRI | 1904 PCI_IDE_IF_NATIVE_SEC); 1905 hard_decode = pciIdeAdjustBAR(progclass, j, 1906 &base, &len); 1907 } else if (value == 0) { 1908 /* skip base regs with size of 0 */ 1909 continue; 1910 } 1911 1912 regs[nreg].pci_size_low = 1913 assigned[nasgn].pci_size_low = len; 1914 if (!hard_decode) { 1915 regs[nreg].pci_phys_hi = 1916 (PCI_ADDR_IO | devloc) + offset; 1917 } else { 1918 regs[nreg].pci_phys_hi = 1919 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1920 offset; 1921 regs[nreg].pci_phys_low = 1922 base & PCI_BASE_IO_ADDR_M; 1923 } 1924 assigned[nasgn].pci_phys_hi = 1925 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1926 type = base & (~PCI_BASE_IO_ADDR_M); 1927 base &= PCI_BASE_IO_ADDR_M; 1928 /* 1929 * A device under a subtractive PPB can allocate 1930 * resources from its parent bus if there is no resource 1931 * available on its own bus. 1932 */ 1933 if ((config_op == CONFIG_NEW) && (*io_res == NULL)) { 1934 res_bus = bus; 1935 while (pci_bus_res[res_bus].subtractive) { 1936 res_bus = pci_bus_res[res_bus].par_bus; 1937 if (res_bus == (uchar_t)-1) 1938 break; /* root bus already */ 1939 if (pci_bus_res[res_bus].io_ports) { 1940 io_res = &pci_bus_res 1941 [res_bus].io_ports; 1942 break; 1943 } 1944 } 1945 } 1946 1947 /* 1948 * first pass - gather what's there 1949 * update/second pass - adjust/allocate regions 1950 * config - allocate regions 1951 */ 1952 if (config_op == CONFIG_INFO) { /* first pass */ 1953 /* take out of the resource map of the bus */ 1954 if (base != 0) { 1955 if (*io_res) 1956 (void) memlist_remove(io_res, 1957 base, len); 1958 memlist_insert(io_res_used, base, len); 1959 } else 1960 reprogram = 1; 1961 } else if ((*io_res && base == 0) || 1962 pci_bus_res[bus].io_reprogram) { 1963 base = (uint_t)memlist_find(io_res, len, len); 1964 if (base != 0) { 1965 memlist_insert(io_res_used, base, len); 1966 /* XXX need to worry about 64-bit? */ 1967 pci_putl(bus, dev, func, offset, 1968 base | type); 1969 base = pci_getl(bus, dev, func, offset); 1970 base &= PCI_BASE_IO_ADDR_M; 1971 } 1972 if (base == 0) { 1973 cmn_err(CE_WARN, "failed to program" 1974 " IO space [%d/%d/%d] BAR@0x%x" 1975 " length 0x%x", 1976 bus, dev, func, offset, len); 1977 } 1978 } 1979 assigned[nasgn].pci_phys_low = base; 1980 nreg++, nasgn++; 1981 1982 } else { 1983 /* memory space */ 1984 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 1985 bar_sz = PCI_BAR_SZ_64; 1986 base_hi = pci_getl(bus, dev, func, offset + 4); 1987 phys_hi = PCI_ADDR_MEM64; 1988 } else { 1989 bar_sz = PCI_BAR_SZ_32; 1990 base_hi = 0; 1991 phys_hi = PCI_ADDR_MEM32; 1992 } 1993 1994 /* skip base regs with size of 0 */ 1995 value &= PCI_BASE_M_ADDR_M; 1996 1997 if (value == 0) { 1998 continue; 1999 } 2000 len = ((value ^ (value-1)) + 1) >> 1; 2001 regs[nreg].pci_size_low = 2002 assigned[nasgn].pci_size_low = len; 2003 2004 phys_hi |= (devloc | offset); 2005 if (base & PCI_BASE_PREF_M) { 2006 mres = pmem_res; 2007 mres_used = pmem_res_used; 2008 phys_hi |= PCI_PREFETCH_B; 2009 } else { 2010 mres = mem_res; 2011 mres_used = mem_res_used; 2012 } 2013 /* 2014 * A device under a subtractive PPB can allocate 2015 * resources from its parent bus if there is no resource 2016 * available on its own bus. 2017 */ 2018 if ((config_op == CONFIG_NEW) && (*mres == NULL)) { 2019 res_bus = bus; 2020 while (pci_bus_res[res_bus].subtractive) { 2021 res_bus = pci_bus_res[res_bus].par_bus; 2022 if (res_bus == (uchar_t)-1) 2023 break; /* root bus already */ 2024 if ((phys_hi & PCI_PREFETCH_B) && 2025 (res_bus != 0)) 2026 mres = &pci_bus_res 2027 [res_bus].pmem_space; 2028 else 2029 mres = &pci_bus_res 2030 [res_bus].mem_space; 2031 if (*mres) 2032 break; 2033 } 2034 } 2035 2036 regs[nreg].pci_phys_hi = 2037 assigned[nasgn].pci_phys_hi = phys_hi; 2038 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2039 assigned[nasgn].pci_phys_mid = base_hi; 2040 type = base & ~PCI_BASE_M_ADDR_M; 2041 base &= PCI_BASE_M_ADDR_M; 2042 2043 if (config_op == CONFIG_INFO) { 2044 /* take out of the resource map of the bus */ 2045 if (base != 0) { 2046 if (*mres) 2047 (void) memlist_remove(mres, 2048 base, len); 2049 memlist_insert(mres_used, base, len); 2050 } else 2051 reprogram = 1; 2052 } else if ((*mres && base == 0) || 2053 pci_bus_res[bus].mem_reprogram) { 2054 base = (uint_t)memlist_find(mres, len, len); 2055 if (base != NULL) { 2056 memlist_insert(mres_used, base, len); 2057 pci_putl(bus, dev, func, offset, 2058 base | type); 2059 base = pci_getl(bus, dev, func, offset); 2060 base &= PCI_BASE_M_ADDR_M; 2061 } 2062 2063 if (base == 0) { 2064 cmn_err(CE_WARN, "failed to program " 2065 "mem space [%d/%d/%d] BAR@0x%x" 2066 " length 0x%x", 2067 bus, dev, func, offset, len); 2068 } 2069 } 2070 assigned[nasgn].pci_phys_low = base; 2071 nreg++, nasgn++; 2072 } 2073 } 2074 switch (header) { 2075 case PCI_HEADER_ZERO: 2076 offset = PCI_CONF_ROM; 2077 break; 2078 case PCI_HEADER_PPB: 2079 offset = PCI_BCNF_ROM; 2080 break; 2081 default: /* including PCI_HEADER_CARDBUS */ 2082 goto done; 2083 } 2084 2085 /* 2086 * Add the expansion rom memory space 2087 * Determine the size of the ROM base reg; don't write reserved bits 2088 * ROM isn't in the PCI memory space. 2089 */ 2090 base = pci_getl(bus, dev, func, offset); 2091 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2092 value = pci_getl(bus, dev, func, offset); 2093 pci_putl(bus, dev, func, offset, base); 2094 if (value & PCI_BASE_ROM_ENABLE) 2095 value &= PCI_BASE_ROM_ADDR_M; 2096 else 2097 value = 0; 2098 2099 if (value != 0) { 2100 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2101 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2102 PCI_ADDR_MEM32 | devloc) + offset; 2103 base &= PCI_BASE_ROM_ADDR_M; 2104 assigned[nasgn].pci_phys_low = base; 2105 len = ((value ^ (value-1)) + 1) >> 1; 2106 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2107 nreg++, nasgn++; 2108 /* take it out of the memory resource */ 2109 if (*mem_res && base != 0) 2110 (void) memlist_remove(mem_res, base, len); 2111 if (base != 0) 2112 memlist_insert(mem_res, base, len); 2113 } 2114 2115 /* 2116 * The following are ISA resources. There are not part 2117 * of the PCI local bus resources. So don't attempt to 2118 * do resource accounting against PCI. 2119 */ 2120 2121 /* add the three hard-decode, aliased address spaces for VGA */ 2122 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2123 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2124 2125 /* VGA hard decode 0x3b0-0x3bb */ 2126 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2127 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2128 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2129 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2130 nreg++, nasgn++; 2131 2132 /* VGA hard decode 0x3c0-0x3df */ 2133 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2134 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2135 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2136 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2137 nreg++, nasgn++; 2138 2139 /* Video memory */ 2140 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2141 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 2142 regs[nreg].pci_phys_low = 2143 assigned[nasgn].pci_phys_low = 0xa0000; 2144 regs[nreg].pci_size_low = 2145 assigned[nasgn].pci_size_low = 0x20000; 2146 nreg++, nasgn++; 2147 } 2148 2149 /* add the hard-decode, aliased address spaces for 8514 */ 2150 if ((baseclass == PCI_CLASS_DISPLAY) && 2151 (subclass == PCI_DISPLAY_VGA) && 2152 (progclass & PCI_DISPLAY_IF_8514)) { 2153 2154 /* hard decode 0x2e8 */ 2155 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2156 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2157 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2158 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2159 nreg++, nasgn++; 2160 2161 /* hard decode 0x2ea-0x2ef */ 2162 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2163 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2164 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2165 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2166 nreg++, nasgn++; 2167 } 2168 2169 done: 2170 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2171 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2172 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2173 "assigned-addresses", 2174 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2175 2176 return (reprogram); 2177 } 2178 2179 static void 2180 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2181 int pciex) 2182 { 2183 char *dev_type; 2184 int i; 2185 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 2186 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2187 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2188 uchar_t progclass; 2189 2190 ASSERT(secbus <= subbus); 2191 2192 /* 2193 * Check if it's a subtractive PPB. 2194 */ 2195 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2196 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 2197 pci_bus_res[secbus].subtractive = B_TRUE; 2198 2199 /* 2200 * Some BIOSes lie about max pci busses, we allow for 2201 * such mistakes here 2202 */ 2203 if (subbus > pci_bios_nbus) { 2204 pci_bios_nbus = subbus; 2205 alloc_res_array(); 2206 } 2207 2208 ASSERT(pci_bus_res[secbus].dip == NULL); 2209 pci_bus_res[secbus].dip = dip; 2210 pci_bus_res[secbus].par_bus = bus; 2211 2212 dev_type = pciex ? "pciex" : "pci"; 2213 2214 /* setup bus number hierarchy */ 2215 pci_bus_res[secbus].sub_bus = subbus; 2216 /* 2217 * Keep track of the largest subordinate bus number (this is essential 2218 * for peer busses because there is no other way of determining its 2219 * subordinate bus number). 2220 */ 2221 if (subbus > pci_bus_res[bus].sub_bus) 2222 pci_bus_res[bus].sub_bus = subbus; 2223 /* 2224 * Loop through subordinate busses, initializing their parent bus 2225 * field to this bridge's parent. The subordinate busses' parent 2226 * fields may very well be further refined later, as child bridges 2227 * are enumerated. (The value is to note that the subordinate busses 2228 * are not peer busses by changing their par_bus fields to anything 2229 * other than -1.) 2230 */ 2231 for (i = secbus + 1; i <= subbus; i++) 2232 pci_bus_res[i].par_bus = bus; 2233 2234 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2235 "device_type", dev_type); 2236 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2237 "#address-cells", 3); 2238 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2239 "#size-cells", 2); 2240 2241 /* 2242 * According to PPB spec, the base register should be programmed 2243 * with a value bigger than the limit register when there are 2244 * no resources available. This applies to io, memory, and 2245 * prefetchable memory. 2246 */ 2247 2248 /* 2249 * io range 2250 * We determine i/o windows that are left unconfigured by BIOS 2251 * through its i/o enable bit as Microsoft recommends OEMs to do. 2252 * If it is unset, we disable i/o and mark it for reconfiguration in 2253 * later passes by setting the base > limit 2254 */ 2255 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2256 if (val & PCI_COMM_IO) { 2257 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 2258 io_range[0] = ((val & 0xf0) << 8); 2259 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 2260 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 2261 } else { 2262 io_range[0] = 0x9fff; 2263 io_range[1] = 0x1000; 2264 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 2265 (uint8_t)((io_range[0] >> 8) & 0xf0)); 2266 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 2267 (uint8_t)((io_range[1] >> 8) & 0xf0)); 2268 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 2269 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 2270 } 2271 2272 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2273 memlist_insert(&pci_bus_res[secbus].io_ports, 2274 (uint64_t)io_range[0], 2275 (uint64_t)(io_range[1] - io_range[0] + 1)); 2276 memlist_insert(&pci_bus_res[bus].io_ports_used, 2277 (uint64_t)io_range[0], 2278 (uint64_t)(io_range[1] - io_range[0] + 1)); 2279 if (pci_bus_res[bus].io_ports != NULL) { 2280 (void) memlist_remove(&pci_bus_res[bus].io_ports, 2281 (uint64_t)io_range[0], 2282 (uint64_t)(io_range[1] - io_range[0] + 1)); 2283 } 2284 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 2285 secbus, io_range[0], io_range[1]); 2286 /* if 32-bit supported, make sure upper bits are not set */ 2287 if ((val & 0xf) == 1 && 2288 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 2289 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 2290 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2291 } 2292 } 2293 2294 /* mem range */ 2295 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 2296 mem_range[0] = ((val & 0xFFF0) << 16); 2297 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 2298 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2299 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2300 memlist_insert(&pci_bus_res[secbus].mem_space, 2301 (uint64_t)mem_range[0], 2302 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2303 memlist_insert(&pci_bus_res[bus].mem_space_used, 2304 (uint64_t)mem_range[0], 2305 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2306 /* remove from parent resouce list */ 2307 if (pci_bus_res[bus].mem_space != NULL) { 2308 (void) memlist_remove(&pci_bus_res[bus].mem_space, 2309 (uint64_t)mem_range[0], 2310 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2311 } 2312 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 2313 secbus, mem_range[0], mem_range[1]); 2314 } 2315 2316 /* prefetchable memory range */ 2317 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 2318 pmem_range[0] = ((val & 0xFFF0) << 16); 2319 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 2320 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2321 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2322 memlist_insert(&pci_bus_res[secbus].pmem_space, 2323 (uint64_t)pmem_range[0], 2324 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2325 memlist_insert(&pci_bus_res[bus].pmem_space_used, 2326 (uint64_t)pmem_range[0], 2327 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2328 if (pci_bus_res[bus].pmem_space != NULL) { 2329 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 2330 (uint64_t)pmem_range[0], 2331 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2332 } 2333 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 2334 secbus, pmem_range[0], pmem_range[1]); 2335 /* if 64-bit supported, make sure upper bits are not set */ 2336 if ((val & 0xf) == 1 && 2337 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 2338 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 2339 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2340 } 2341 } 2342 2343 add_bus_range_prop(secbus); 2344 add_ppb_ranges_prop(secbus); 2345 } 2346 2347 extern const struct pci_class_strings_s class_pci[]; 2348 extern int class_pci_items; 2349 2350 static void 2351 add_model_prop(dev_info_t *dip, uint_t classcode) 2352 { 2353 const char *desc; 2354 int i; 2355 uchar_t baseclass = classcode >> 16; 2356 uchar_t subclass = (classcode >> 8) & 0xff; 2357 uchar_t progclass = classcode & 0xff; 2358 2359 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 2360 desc = "IDE controller"; 2361 } else { 2362 for (desc = 0, i = 0; i < class_pci_items; i++) { 2363 if ((baseclass == class_pci[i].base_class) && 2364 (subclass == class_pci[i].sub_class) && 2365 (progclass == class_pci[i].prog_class)) { 2366 desc = class_pci[i].actual_desc; 2367 break; 2368 } 2369 } 2370 if (i == class_pci_items) 2371 desc = "Unknown class of pci/pnpbios device"; 2372 } 2373 2374 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2375 (char *)desc); 2376 } 2377 2378 static void 2379 add_bus_range_prop(int bus) 2380 { 2381 int bus_range[2]; 2382 2383 if (pci_bus_res[bus].dip == NULL) 2384 return; 2385 bus_range[0] = bus; 2386 bus_range[1] = pci_bus_res[bus].sub_bus; 2387 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2388 "bus-range", (int *)bus_range, 2); 2389 } 2390 2391 /* 2392 * Add slot-names property for any named pci hot-plug slots 2393 */ 2394 static void 2395 add_bus_slot_names_prop(int bus) 2396 { 2397 char slotprop[256]; 2398 int len; 2399 2400 if (pci_bus_res[bus].dip != NULL) { 2401 /* simply return if the property is already defined */ 2402 if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2403 DDI_PROP_DONTPASS, "slot-names")) 2404 return; 2405 } 2406 2407 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2408 if (len > 0) { 2409 /* 2410 * Only create a peer bus node if this bus may be a peer bus. 2411 * It may be a peer bus if the dip is NULL and if par_bus is 2412 * -1 (par_bus is -1 if this bus was not found to be 2413 * subordinate to any PCI-PCI bridge). 2414 * If it's not a peer bus, then the ACPI BBN-handling code 2415 * will remove it later. 2416 */ 2417 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 2418 pci_bus_res[bus].dip == NULL) { 2419 2420 create_root_bus_dip(bus); 2421 } 2422 if (pci_bus_res[bus].dip != NULL) { 2423 ASSERT((len % sizeof (int)) == 0); 2424 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2425 pci_bus_res[bus].dip, "slot-names", 2426 (int *)slotprop, len / sizeof (int)); 2427 } else { 2428 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 2429 "IRQ routing table; Not adding slot-names " 2430 "property for incorrect bus %d", bus); 2431 } 2432 } 2433 } 2434 2435 static int 2436 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 2437 { 2438 if (entry == NULL) 2439 return (0); 2440 2441 /* assume 32-bit addresses */ 2442 rp->child_high = rp->parent_high = type; 2443 rp->child_mid = rp->parent_mid = 0; 2444 rp->child_low = rp->parent_low = (uint32_t)entry->address; 2445 rp->size_high = 0; 2446 rp->size_low = (uint32_t)entry->size; 2447 return (1); 2448 } 2449 2450 static void 2451 add_ppb_ranges_prop(int bus) 2452 { 2453 int i = 0; 2454 ppb_ranges_t *rp; 2455 2456 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 2457 2458 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 2459 PCI_ADDR_IO | PCI_REG_REL_M); 2460 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 2461 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2462 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 2463 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2464 2465 if (i != 0) 2466 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2467 pci_bus_res[bus].dip, "ranges", (int *)rp, 2468 i * sizeof (ppb_ranges_t) / sizeof (int)); 2469 kmem_free(rp, 3 * sizeof (*rp)); 2470 } 2471 2472 static int 2473 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 2474 { 2475 int i = 0; 2476 2477 while (list) { 2478 /* assume 32-bit addresses */ 2479 sp->pci_phys_hi = type; 2480 sp->pci_phys_mid = 0; 2481 sp->pci_phys_low = (uint32_t)list->address; 2482 sp->pci_size_hi = 0; 2483 sp->pci_size_low = (uint32_t)list->size; 2484 2485 list = list->next; 2486 sp++, i++; 2487 } 2488 return (i); 2489 } 2490 2491 static void 2492 add_bus_available_prop(int bus) 2493 { 2494 int i, count; 2495 struct pci_phys_spec *sp; 2496 2497 count = memlist_count(pci_bus_res[bus].io_ports) + 2498 memlist_count(pci_bus_res[bus].mem_space) + 2499 memlist_count(pci_bus_res[bus].pmem_space); 2500 2501 if (count == 0) /* nothing available */ 2502 return; 2503 2504 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 2505 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 2506 PCI_ADDR_IO | PCI_REG_REL_M); 2507 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 2508 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2509 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 2510 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2511 ASSERT(i == count); 2512 2513 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2514 "available", (int *)sp, 2515 i * sizeof (struct pci_phys_spec) / sizeof (int)); 2516 kmem_free(sp, count * sizeof (*sp)); 2517 } 2518 2519 static void 2520 alloc_res_array(void) 2521 { 2522 static int array_max = 0; 2523 int old_max; 2524 void *old_res; 2525 2526 if (array_max > pci_bios_nbus + 1) 2527 return; /* array is big enough */ 2528 2529 old_max = array_max; 2530 old_res = pci_bus_res; 2531 2532 if (array_max == 0) 2533 array_max = 16; /* start with a reasonable number */ 2534 2535 while (array_max < pci_bios_nbus + 1) 2536 array_max <<= 1; 2537 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2538 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2539 2540 if (old_res) { /* copy content and free old array */ 2541 bcopy(old_res, pci_bus_res, 2542 old_max * sizeof (struct pci_bus_resource)); 2543 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2544 } 2545 } 2546 2547 static void 2548 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2549 ushort_t deviceid) 2550 { 2551 static dev_info_t *ioapicsnode = NULL; 2552 static int numioapics = 0; 2553 dev_info_t *ioapic_node; 2554 uint64_t physaddr; 2555 uint32_t lobase, hibase = 0; 2556 2557 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2558 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2559 2560 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2561 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2562 return; 2563 2564 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2565 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2566 2567 lobase &= PCI_BASE_M_ADDR_M; 2568 2569 physaddr = (((uint64_t)hibase) << 32) | lobase; 2570 2571 /* 2572 * Create a nexus node for all IOAPICs under the root node. 2573 */ 2574 if (ioapicsnode == NULL) { 2575 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2576 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2577 return; 2578 } 2579 (void) ndi_devi_online(ioapicsnode, 0); 2580 } 2581 2582 /* 2583 * Create a child node for this IOAPIC 2584 */ 2585 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2586 DEVI_SID_NODEID, numioapics++); 2587 if (ioapic_node == NULL) { 2588 return; 2589 } 2590 2591 /* Vendor and Device ID */ 2592 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2593 IOAPICS_PROP_VENID, vendorid); 2594 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2595 IOAPICS_PROP_DEVID, deviceid); 2596 2597 /* device_type */ 2598 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2599 "device_type", IOAPICS_DEV_TYPE); 2600 2601 /* reg */ 2602 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2603 "reg", physaddr); 2604 } 2605 2606 /* 2607 * NOTE: For PCIe slots, the name is generated from the slot number 2608 * information obtained from Slot Capabilities register. 2609 * For non-PCIe slots, it is generated based on the slot number 2610 * information in the PCI IRQ table. 2611 */ 2612 static void 2613 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2614 { 2615 char slotprop[256]; 2616 int len; 2617 2618 bzero(slotprop, sizeof (slotprop)); 2619 2620 /* set mask to 1 as there is only one slot (i.e dev 0) */ 2621 *(uint32_t *)slotprop = 1; 2622 len = 4; 2623 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2624 slot_num); 2625 len += strlen(slotprop + len) + 1; 2626 len += len % 4; 2627 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2628 (int *)slotprop, len / sizeof (int)); 2629 } 2630