1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/stat.h> 28 #include <sys/sunndi.h> 29 #include <sys/pci.h> 30 #include <sys/pci_impl.h> 31 #include <sys/pci_cfgspace.h> 32 #include <sys/memlist.h> 33 #include <sys/bootconf.h> 34 #include <io/pci/mps_table.h> 35 #include <sys/pci_cfgspace.h> 36 #include <sys/pci_cfgspace_impl.h> 37 #include <sys/psw.h> 38 #include "../../../../common/pci/pci_strings.h" 39 #include <sys/apic.h> 40 #include <io/pciex/pcie_nvidia.h> 41 #include <io/hotplug/pciehpc/pciehpc_acpi.h> 42 #include <sys/acpi/acpi.h> 43 #include <sys/acpica.h> 44 #include <sys/intel_iommu.h> 45 #include <sys/iommulib.h> 46 47 #define pci_getb (*pci_getb_func) 48 #define pci_getw (*pci_getw_func) 49 #define pci_getl (*pci_getl_func) 50 #define pci_putb (*pci_putb_func) 51 #define pci_putw (*pci_putw_func) 52 #define pci_putl (*pci_putl_func) 53 #define dcmn_err if (pci_boot_debug) cmn_err 54 55 #define CONFIG_INFO 0 56 #define CONFIG_UPDATE 1 57 #define CONFIG_NEW 2 58 #define CONFIG_FIX 3 59 #define COMPAT_BUFSIZE 512 60 61 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 62 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 63 64 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 65 #define LPC_IO_CONTROL_REG_1 0x40 66 #define AMD8111_ENABLENMI (uint8_t)0x80 67 #define DEVID_AMD8111_LPC 0x7468 68 69 struct pci_fixundo { 70 uint8_t bus; 71 uint8_t dev; 72 uint8_t fn; 73 void (*undofn)(uint8_t, uint8_t, uint8_t); 74 struct pci_fixundo *next; 75 }; 76 77 struct pci_devfunc { 78 struct pci_devfunc *next; 79 dev_info_t *dip; 80 uchar_t dev; 81 uchar_t func; 82 boolean_t reprogram; /* this device needs to be reprogrammed */ 83 }; 84 85 extern int pseudo_isa; 86 extern int pci_bios_nbus; 87 static uchar_t max_dev_pci = 32; /* PCI standard */ 88 int pci_boot_debug = 0; 89 extern struct memlist *find_bus_res(int, int); 90 static struct pci_fixundo *undolist = NULL; 91 static int num_root_bus = 0; /* count of root buses */ 92 extern volatile int acpi_resource_discovery; 93 94 /* 95 * Module prototypes 96 */ 97 static void enumerate_bus_devs(uchar_t bus, int config_op); 98 static void create_root_bus_dip(uchar_t bus); 99 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 100 ushort_t, int); 101 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 102 ushort_t, ushort_t, uchar_t, uint_t, int); 103 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 104 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 105 ushort_t); 106 static void add_model_prop(dev_info_t *, uint_t); 107 static void add_bus_range_prop(int); 108 static void add_bus_slot_names_prop(int); 109 static void add_ranges_prop(int, int); 110 static void add_bus_available_prop(int); 111 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 112 static void fix_ppb_res(uchar_t, boolean_t); 113 static void alloc_res_array(); 114 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 115 ushort_t deviceid); 116 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 117 static void populate_bus_res(uchar_t bus); 118 static void memlist_remove_list(struct memlist **list, 119 struct memlist *remove_list); 120 121 extern int pci_slot_names_prop(int, char *, int); 122 123 /* set non-zero to force PCI peer-bus renumbering */ 124 int pci_bus_always_renumber = 0; 125 126 /* 127 * used to register ISA resource usage which must not be made 128 * "available" from other PCI node' resource maps 129 */ 130 static struct { 131 struct memlist *io_ports_used; 132 struct memlist *mem_space_used; 133 } isa_res; 134 135 /* 136 * Enumerate all PCI devices 137 */ 138 void 139 pci_setup_tree() 140 { 141 uint_t i, root_bus_addr = 0; 142 143 alloc_res_array(); 144 for (i = 0; i <= pci_bios_nbus; i++) { 145 pci_bus_res[i].par_bus = (uchar_t)-1; 146 pci_bus_res[i].root_addr = (uchar_t)-1; 147 pci_bus_res[i].sub_bus = i; 148 } 149 150 pci_bus_res[0].root_addr = root_bus_addr++; 151 create_root_bus_dip(0); 152 enumerate_bus_devs(0, CONFIG_INFO); 153 154 /* 155 * Now enumerate peer busses 156 * 157 * We loop till pci_bios_nbus. On most systems, there is 158 * one more bus at the high end, which implements the ISA 159 * compatibility bus. We don't care about that. 160 * 161 * Note: In the old (bootconf) enumeration, the peer bus 162 * address did not use the bus number, and there were 163 * too many peer busses created. The root_bus_addr is 164 * used to maintain the old peer bus address assignment. 165 * However, we stop enumerating phantom peers with no 166 * device below. 167 */ 168 for (i = 1; i <= pci_bios_nbus; i++) { 169 if (pci_bus_res[i].dip == NULL) { 170 pci_bus_res[i].root_addr = root_bus_addr++; 171 } 172 enumerate_bus_devs(i, CONFIG_INFO); 173 174 /* add slot-names property for named pci hot-plug slots */ 175 add_bus_slot_names_prop(i); 176 } 177 178 } 179 180 /* 181 * >0 = present, 0 = not present, <0 = error 182 */ 183 static int 184 pci_bbn_present(int bus) 185 { 186 ACPI_HANDLE hdl; 187 int rv; 188 189 /* no dip means no _BBN */ 190 if (pci_bus_res[bus].dip == NULL) 191 return (0); 192 193 rv = -1; /* default return value in case of error below */ 194 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 195 switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 196 case AE_OK: 197 rv = 1; 198 break; 199 case AE_NOT_FOUND: 200 rv = 0; 201 break; 202 default: 203 break; 204 } 205 } 206 207 return (rv); 208 } 209 210 /* 211 * Return non-zero if any PCI bus in the system has an associated 212 * _BBN object, 0 otherwise. 213 */ 214 static int 215 pci_roots_have_bbn(void) 216 { 217 int i; 218 219 /* 220 * Scan the PCI busses and look for at least 1 _BBN 221 */ 222 for (i = 0; i <= pci_bios_nbus; i++) { 223 /* skip non-root (peer) PCI busses */ 224 if (pci_bus_res[i].par_bus != (uchar_t)-1) 225 continue; 226 227 if (pci_bbn_present(i) > 0) 228 return (1); 229 } 230 return (0); 231 232 } 233 234 /* 235 * return non-zero if the machine is one on which we renumber 236 * the internal pci unit-addresses 237 */ 238 static int 239 pci_bus_renumber() 240 { 241 ACPI_TABLE_HEADER *fadt; 242 243 if (pci_bus_always_renumber) 244 return (1); 245 246 /* get the FADT */ 247 if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 248 AE_OK) 249 return (0); 250 251 /* compare OEM Table ID to "SUNm31" */ 252 if (strncmp("SUNm31", fadt->OemId, 6)) 253 return (0); 254 else 255 return (1); 256 } 257 258 /* 259 * Initial enumeration of the physical PCI bus hierarchy can 260 * leave 'gaps' in the order of peer PCI bus unit-addresses. 261 * Systems with more than one peer PCI bus *must* have an ACPI 262 * _BBN object associated with each peer bus; use the presence 263 * of this object to remove gaps in the numbering of the peer 264 * PCI bus unit-addresses - only peer busses with an associated 265 * _BBN are counted. 266 */ 267 static void 268 pci_renumber_root_busses(void) 269 { 270 int pci_regs[] = {0, 0, 0}; 271 int i, root_addr = 0; 272 273 /* 274 * Currently, we only enable the re-numbering on specific 275 * Sun machines; this is a work-around for the more complicated 276 * issue of upgrade changing physical device paths 277 */ 278 if (!pci_bus_renumber()) 279 return; 280 281 /* 282 * If we find no _BBN objects at all, we either don't need 283 * to do anything or can't do anything anyway 284 */ 285 if (!pci_roots_have_bbn()) 286 return; 287 288 for (i = 0; i <= pci_bios_nbus; i++) { 289 /* skip non-root (peer) PCI busses */ 290 if (pci_bus_res[i].par_bus != (uchar_t)-1) 291 continue; 292 293 if (pci_bbn_present(i) < 1) { 294 pci_bus_res[i].root_addr = (uchar_t)-1; 295 continue; 296 } 297 298 ASSERT(pci_bus_res[i].dip != NULL); 299 if (pci_bus_res[i].root_addr != root_addr) { 300 /* update reg property for node */ 301 pci_bus_res[i].root_addr = root_addr; 302 pci_regs[0] = pci_bus_res[i].root_addr; 303 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 304 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 305 } 306 root_addr++; 307 } 308 } 309 310 void 311 pci_register_isa_resources(int type, uint32_t base, uint32_t size) 312 { 313 (void) memlist_insert( 314 (type == 1) ? &isa_res.io_ports_used : &isa_res.mem_space_used, 315 base, size); 316 } 317 318 /* 319 * Remove the resources which are already used by devices under a subtractive 320 * bridge from the bus's resources lists, because they're not available, and 321 * shouldn't be allocated to other buses. This is necessary because tracking 322 * resources for subtractive bridges is not complete. (Subtractive bridges only 323 * track some of their claimed resources, not "the rest of the address space" as 324 * they should, so that allocation to peer non-subtractive PPBs is easier. We 325 * need a fully-capable global resource allocator). 326 */ 327 static void 328 remove_subtractive_res() 329 { 330 int i, j; 331 struct memlist *list; 332 333 for (i = 0; i <= pci_bios_nbus; i++) { 334 if (pci_bus_res[i].subtractive) { 335 /* remove used io ports */ 336 list = pci_bus_res[i].io_ports_used; 337 while (list) { 338 for (j = 0; j <= pci_bios_nbus; j++) 339 (void) memlist_remove( 340 &pci_bus_res[j].io_ports, 341 list->address, list->size); 342 list = list->next; 343 } 344 /* remove used mem resource */ 345 list = pci_bus_res[i].mem_space_used; 346 while (list) { 347 for (j = 0; j <= pci_bios_nbus; j++) { 348 (void) memlist_remove( 349 &pci_bus_res[j].mem_space, 350 list->address, list->size); 351 (void) memlist_remove( 352 &pci_bus_res[j].pmem_space, 353 list->address, list->size); 354 } 355 list = list->next; 356 } 357 /* remove used prefetchable mem resource */ 358 list = pci_bus_res[i].pmem_space_used; 359 while (list) { 360 for (j = 0; j <= pci_bios_nbus; j++) { 361 (void) memlist_remove( 362 &pci_bus_res[j].pmem_space, 363 list->address, list->size); 364 (void) memlist_remove( 365 &pci_bus_res[j].mem_space, 366 list->address, list->size); 367 } 368 list = list->next; 369 } 370 } 371 } 372 } 373 374 /* 375 * Set-up (or complete the set-up) of the bus_space resource list 376 */ 377 static void 378 setup_bus_res(int bus) 379 { 380 uchar_t par_bus; 381 382 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 383 return; 384 385 /* 386 * Setup bus_space if not already filled-in by populate_bus_res(); 387 */ 388 if (pci_bus_res[bus].bus_space == NULL) { 389 ASSERT(pci_bus_res[bus].sub_bus >= bus); 390 memlist_insert(&pci_bus_res[bus].bus_space, bus, 391 pci_bus_res[bus].sub_bus - bus + 1); 392 } 393 394 ASSERT(pci_bus_res[bus].bus_space != NULL); 395 396 /* 397 * Remove resources from parent bus node if this is not a 398 * root bus. 399 */ 400 par_bus = pci_bus_res[bus].par_bus; 401 if (par_bus != (uchar_t)-1) { 402 ASSERT(pci_bus_res[par_bus].bus_space != NULL); 403 memlist_remove_list(&pci_bus_res[par_bus].bus_space, 404 pci_bus_res[bus].bus_space); 405 } 406 407 /* remove self from bus_space */; 408 (void) memlist_remove(&pci_bus_res[bus].bus_space, bus, 1); 409 } 410 411 static uint64_t 412 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 413 { 414 uint64_t addr = 0; 415 uchar_t res_bus; 416 417 /* 418 * Skip root(peer) buses in multiple-root-bus systems when 419 * ACPI resource discovery was not successfully done. 420 */ 421 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 422 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 423 return (0); 424 425 res_bus = parbus; 426 while (pci_bus_res[res_bus].subtractive) { 427 if (pci_bus_res[res_bus].io_ports) 428 break; 429 res_bus = pci_bus_res[res_bus].par_bus; 430 if (res_bus == (uchar_t)-1) 431 break; /* root bus already */ 432 } 433 434 if (pci_bus_res[res_bus].io_ports) { 435 addr = memlist_find(&pci_bus_res[res_bus].io_ports, 436 size, align); 437 if (addr) { 438 memlist_insert(&pci_bus_res[res_bus].io_ports_used, 439 addr, size); 440 441 /* free the old resource */ 442 memlist_free_all(&pci_bus_res[bus].io_ports); 443 memlist_free_all(&pci_bus_res[bus].io_ports_used); 444 445 /* add the new resource */ 446 memlist_insert(&pci_bus_res[bus].io_ports, addr, size); 447 } 448 } 449 450 return (addr); 451 } 452 453 static uint64_t 454 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 455 { 456 uint64_t addr = 0; 457 uchar_t res_bus; 458 459 /* 460 * Skip root(peer) buses in multiple-root-bus systems when 461 * ACPI resource discovery was not successfully done. 462 */ 463 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 464 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 465 return (0); 466 467 res_bus = parbus; 468 while (pci_bus_res[res_bus].subtractive) { 469 if (pci_bus_res[res_bus].mem_space) 470 break; 471 res_bus = pci_bus_res[res_bus].par_bus; 472 if (res_bus == (uchar_t)-1) 473 break; /* root bus already */ 474 } 475 476 if (pci_bus_res[res_bus].mem_space) { 477 addr = memlist_find(&pci_bus_res[res_bus].mem_space, 478 size, align); 479 if (addr) { 480 memlist_insert(&pci_bus_res[res_bus].mem_space_used, 481 addr, size); 482 (void) memlist_remove(&pci_bus_res[res_bus].pmem_space, 483 addr, size); 484 485 /* free the old resource */ 486 memlist_free_all(&pci_bus_res[bus].mem_space); 487 memlist_free_all(&pci_bus_res[bus].mem_space_used); 488 489 /* add the new resource */ 490 memlist_insert(&pci_bus_res[bus].mem_space, addr, size); 491 } 492 } 493 494 return (addr); 495 } 496 497 /* 498 * given a cap_id, return its cap_id location in config space 499 */ 500 static int 501 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 502 { 503 uint8_t curcap, cap_id_loc; 504 uint16_t status; 505 int location = -1; 506 507 /* 508 * Need to check the Status register for ECP support first. 509 * Also please note that for type 1 devices, the 510 * offset could change. Should support type 1 next. 511 */ 512 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 513 if (!(status & PCI_STAT_CAP)) { 514 return (-1); 515 } 516 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 517 518 /* Walk the list of capabilities */ 519 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 520 curcap = pci_getb(bus, dev, func, cap_id_loc); 521 522 if (curcap == cap_id) { 523 location = cap_id_loc; 524 break; 525 } 526 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 527 } 528 return (location); 529 } 530 531 /* 532 * Assign valid resources to unconfigured pci(e) bridges. We are trying 533 * to reprogram the bridge when its 534 * i) SECBUS == SUBBUS || 535 * ii) IOBASE > IOLIM || 536 * iii) MEMBASE > MEMLIM 537 * This must be done after one full pass through the PCI tree to collect 538 * all BIOS-configured resources, so that we know what resources are 539 * free and available to assign to the unconfigured PPBs. 540 */ 541 static void 542 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 543 { 544 uchar_t bus, dev, func; 545 uchar_t parbus, subbus; 546 uint_t io_base, io_limit, mem_base, mem_limit; 547 uint_t io_size, mem_size; 548 uint64_t addr = 0; 549 int *regp = NULL; 550 uint_t reglen; 551 int rv, cap_ptr, physhi; 552 dev_info_t *dip; 553 uint16_t cmd_reg; 554 struct memlist *list; 555 556 /* skip root (peer) PCI busses */ 557 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 558 return; 559 560 /* skip subtractive PPB when prog_sub is not TRUE */ 561 if (pci_bus_res[secbus].subtractive && !prog_sub) 562 return; 563 564 /* some entries may be empty due to discontiguous bus numbering */ 565 dip = pci_bus_res[secbus].dip; 566 if (dip == NULL) 567 return; 568 569 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 570 "reg", ®p, ®len); 571 ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 572 physhi = regp[0]; 573 ddi_prop_free(regp); 574 575 func = (uchar_t)PCI_REG_FUNC_G(physhi); 576 dev = (uchar_t)PCI_REG_DEV_G(physhi); 577 bus = (uchar_t)PCI_REG_BUS_G(physhi); 578 579 /* 580 * If pcie bridge, check to see if link is enabled 581 */ 582 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 583 if (cap_ptr != -1) { 584 cmd_reg = pci_getw(bus, dev, func, 585 (uint16_t)cap_ptr + PCIE_LINKCTL); 586 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 587 dcmn_err(CE_NOTE, 588 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 589 bus, dev, func); 590 return; 591 } 592 } 593 594 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 595 parbus = pci_bus_res[secbus].par_bus; 596 ASSERT(parbus == bus); 597 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 598 599 /* 600 * If we have a Cardbus bridge, but no bus space 601 */ 602 if (pci_bus_res[secbus].num_cbb != 0 && 603 pci_bus_res[secbus].bus_space == NULL) { 604 uchar_t range; 605 606 /* normally there are 2 buses under a cardbus bridge */ 607 range = pci_bus_res[secbus].num_cbb * 2; 608 609 /* 610 * Try to find and allocate a bus-range starting at subbus+1 611 * from the parent of the PPB. 612 */ 613 for (; range != 0; range--) { 614 if (memlist_find_with_startaddr( 615 &pci_bus_res[parbus].bus_space, 616 subbus + 1, range, 1) != NULL) 617 break; /* find bus range resource at parent */ 618 } 619 if (range != 0) { 620 memlist_insert(&pci_bus_res[secbus].bus_space, 621 subbus + 1, range); 622 subbus = subbus + range; 623 pci_bus_res[secbus].sub_bus = subbus; 624 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 625 add_bus_range_prop(secbus); 626 627 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 628 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 629 secbus, subbus); 630 } 631 } 632 633 /* 634 * Calculate required IO size 635 * We are going to assign 512 bytes per bus. The size needs to be 636 * 4K aligned and the maximum size is 16K. 637 */ 638 io_size = (subbus - secbus + 1) * 0x200; 639 io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1)); 640 if (io_size > 0x4 * PPB_IO_ALIGNMENT) 641 io_size = 0x4 * PPB_IO_ALIGNMENT; 642 /* 643 * Calculate required MEM size 644 * We are going to assign 1M bytes per bus. The size needs to be 645 * 1M aligned and the maximum size is 8M. 646 */ 647 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 648 if (mem_size > 0x8 * PPB_MEM_ALIGNMENT) 649 mem_size = 0x8 * PPB_MEM_ALIGNMENT; 650 651 /* Subtractive bridge */ 652 if (pci_bus_res[secbus].subtractive && prog_sub) { 653 /* 654 * We program an arbitrary amount of I/O and memory resource 655 * for the subtractive bridge so that child dynamic-resource- 656 * allocating devices (such as Cardbus bridges) have a chance 657 * of success. Until we have full-tree resource rebalancing, 658 * dynamic resource allocation (thru busra) only looks at the 659 * parent bridge, so all PPBs must have some allocatable 660 * resource. For non-subtractive bridges, the resources come 661 * from the base/limit register "windows", but subtractive 662 * bridges often don't program those (since they don't need to). 663 * If we put all the remaining resources on the subtractive 664 * bridge, then peer non-subtractive bridges can't allocate 665 * more space (even though this is probably most correct). 666 * If we put the resources only on the parent, then allocations 667 * from children of subtractive bridges will fail without 668 * special-case code for bypassing the subtractive bridge. 669 * This solution is the middle-ground temporary solution until 670 * we have fully-capable resource allocation. 671 */ 672 673 /* 674 * Add an arbitrary I/O resource to the subtractive PPB 675 */ 676 if (pci_bus_res[secbus].io_ports == NULL) { 677 addr = get_parbus_io_res(parbus, secbus, io_size, 678 PPB_IO_ALIGNMENT); 679 if (addr) { 680 add_ranges_prop(secbus, 1); 681 pci_bus_res[secbus].io_reprogram = 682 pci_bus_res[parbus].io_reprogram; 683 684 cmn_err(CE_NOTE, "!add io-range on subtractive" 685 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 686 bus, dev, func, (uint32_t)addr, 687 (uint32_t)addr + io_size - 1); 688 } 689 } 690 /* 691 * Add an arbitrary memory resource to the subtractive PPB 692 */ 693 if (pci_bus_res[secbus].mem_space == NULL) { 694 addr = get_parbus_mem_res(parbus, secbus, mem_size, 695 PPB_MEM_ALIGNMENT); 696 if (addr) { 697 add_ranges_prop(secbus, 1); 698 pci_bus_res[secbus].mem_reprogram = 699 pci_bus_res[parbus].mem_reprogram; 700 701 cmn_err(CE_NOTE, "!add mem-range on " 702 "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 703 bus, dev, func, (uint32_t)addr, 704 (uint32_t)addr + mem_size - 1); 705 } 706 } 707 708 goto cmd_enable; 709 } 710 711 /* 712 * Check to see if we need to reprogram I/O space, either because the 713 * parent bus needed reprogramming and so do we, or because I/O space is 714 * disabled in base/limit or command register. 715 */ 716 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 717 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 718 io_base = (io_base & 0xf0) << 8; 719 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 720 721 if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) || 722 (!(cmd_reg & PCI_COMM_IO))) { 723 if (pci_bus_res[secbus].io_ports_used) { 724 memlist_merge(&pci_bus_res[secbus].io_ports_used, 725 &pci_bus_res[secbus].io_ports); 726 } 727 if (pci_bus_res[secbus].io_ports && 728 (!pci_bus_res[parbus].io_reprogram) && 729 (!pci_bus_res[parbus].subtractive)) { 730 /* rechoose old io ports info */ 731 list = pci_bus_res[secbus].io_ports; 732 io_base = (uint_t)list->address; 733 /* 4K aligned */ 734 io_base = io_base & (~(PPB_IO_ALIGNMENT - 1)); 735 io_limit = (uint_t)(list->address + list->size); 736 while (list->next) { 737 list = list->next; 738 if ((list->address + list->size) > io_limit) 739 io_limit = (uint_t) 740 (list->address + list->size); 741 } 742 io_limit = io_limit - 1; 743 /* 4K aligned */ 744 io_limit = (io_limit + PPB_IO_ALIGNMENT) & 745 (~(PPB_IO_ALIGNMENT - 1)); 746 io_size = io_limit - io_base; 747 io_limit = io_limit - 1; 748 ASSERT(io_base <= io_limit); 749 memlist_free_all(&pci_bus_res[secbus].io_ports); 750 memlist_insert(&pci_bus_res[secbus].io_ports, 751 io_base, io_size); 752 memlist_insert(&pci_bus_res[parbus].io_ports_used, 753 io_base, io_size); 754 (void) memlist_remove(&pci_bus_res[parbus].io_ports, 755 io_base, io_size); 756 pci_bus_res[secbus].io_reprogram = B_TRUE; 757 } else { 758 /* get new io ports from parent bus */ 759 addr = get_parbus_io_res(parbus, secbus, io_size, 760 PPB_IO_ALIGNMENT); 761 if (addr) { 762 io_base = addr; 763 io_limit = addr + io_size - 1; 764 pci_bus_res[secbus].io_reprogram = B_TRUE; 765 } 766 } 767 if (pci_bus_res[secbus].io_reprogram) { 768 /* reprogram PPB regs */ 769 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 770 (uchar_t)((io_base>>8) & 0xf0)); 771 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 772 (uchar_t)((io_limit>>8) & 0xf0)); 773 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 774 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 775 add_ranges_prop(secbus, 1); 776 777 cmn_err(CE_NOTE, "!reprogram io-range on" 778 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 779 bus, dev, func, io_base, io_limit); 780 } 781 } 782 783 /* 784 * Check memory space as we did I/O space. 785 */ 786 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 787 mem_base = (mem_base & 0xfff0) << 16; 788 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 789 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 790 791 if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) || 792 (!(cmd_reg & PCI_COMM_MAE))) { 793 if (pci_bus_res[secbus].mem_space_used) { 794 memlist_merge(&pci_bus_res[secbus].mem_space_used, 795 &pci_bus_res[secbus].mem_space); 796 } 797 if (pci_bus_res[secbus].mem_space && 798 (!pci_bus_res[parbus].mem_reprogram) && 799 (!pci_bus_res[parbus].subtractive)) { 800 /* rechoose old mem resource */ 801 list = pci_bus_res[secbus].mem_space; 802 mem_base = (uint_t)list->address; 803 /* 1M aligned */ 804 mem_base = mem_base & (~0xfffff); 805 mem_limit = (uint_t)(list->address + list->size); 806 while (list->next) { 807 list = list->next; 808 if ((list->address + list->size) > mem_limit) 809 mem_limit = (uint_t) 810 (list->address + list->size); 811 } 812 mem_limit = mem_limit - 1; 813 /* 1M aligned */ 814 mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) & 815 (~(PPB_MEM_ALIGNMENT - 1)); 816 mem_size = mem_limit - mem_base; 817 mem_limit = mem_limit - 1; 818 ASSERT(mem_base <= mem_limit); 819 memlist_free_all(&pci_bus_res[secbus].mem_space); 820 memlist_insert(&pci_bus_res[secbus].mem_space, 821 mem_base, mem_size); 822 memlist_insert(&pci_bus_res[parbus].mem_space_used, 823 mem_base, mem_size); 824 (void) memlist_remove(&pci_bus_res[parbus].mem_space, 825 mem_base, mem_size); 826 pci_bus_res[secbus].mem_reprogram = B_TRUE; 827 } else { 828 /* get new mem resource from parent bus */ 829 addr = get_parbus_mem_res(parbus, secbus, mem_size, 830 PPB_MEM_ALIGNMENT); 831 if (addr) { 832 mem_base = addr; 833 mem_limit = addr + mem_size - 1; 834 pci_bus_res[secbus].mem_reprogram = B_TRUE; 835 } 836 } 837 838 if (pci_bus_res[secbus].mem_reprogram) { 839 /* reprogram PPB MEM regs */ 840 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 841 (uint16_t)((mem_base>>16) & 0xfff0)); 842 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 843 (uint16_t)((mem_limit>>16) & 0xfff0)); 844 /* 845 * Disable PMEM window by setting base > limit. 846 * We currently don't reprogram the PMEM like we've 847 * done for I/O and MEM. (Devices that support prefetch 848 * can use non-prefetch MEM.) Anyway, if the MEM access 849 * bit is initially disabled by BIOS, we disable the 850 * PMEM window manually by setting PMEM base > PMEM 851 * limit here, in case there are incorrect values in 852 * them from BIOS, so that we won't get in trouble once 853 * the MEM access bit is enabled at the end of this 854 * function. 855 */ 856 if (!(cmd_reg & PCI_COMM_MAE)) { 857 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 858 0xfff0); 859 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 860 0x0); 861 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 862 0xffffffff); 863 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 864 0x0); 865 } 866 867 add_ranges_prop(secbus, 1); 868 869 cmn_err(CE_NOTE, "!reprogram mem-range on" 870 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 871 bus, dev, func, mem_base, mem_limit); 872 } 873 } 874 875 cmd_enable: 876 if (pci_bus_res[secbus].io_ports) 877 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 878 if (pci_bus_res[secbus].mem_space) 879 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 880 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 881 } 882 883 void 884 pci_reprogram(void) 885 { 886 int i, pci_reconfig = 1; 887 char *onoff; 888 int bus; 889 890 /* 891 * Excise phantom roots if possible 892 */ 893 pci_renumber_root_busses(); 894 895 /* 896 * Do root-bus resource discovery 897 */ 898 for (bus = 0; bus <= pci_bios_nbus; bus++) { 899 /* skip non-root (peer) PCI busses */ 900 if (pci_bus_res[bus].par_bus != (uchar_t)-1) 901 continue; 902 903 /* 904 * 1. find resources associated with this root bus 905 */ 906 populate_bus_res(bus); 907 908 909 /* 910 * 2. Remove used PCI and ISA resources from bus resource map 911 */ 912 913 memlist_remove_list(&pci_bus_res[bus].io_ports, 914 pci_bus_res[bus].io_ports_used); 915 memlist_remove_list(&pci_bus_res[bus].mem_space, 916 pci_bus_res[bus].mem_space_used); 917 memlist_remove_list(&pci_bus_res[bus].pmem_space, 918 pci_bus_res[bus].pmem_space_used); 919 memlist_remove_list(&pci_bus_res[bus].mem_space, 920 pci_bus_res[bus].pmem_space_used); 921 memlist_remove_list(&pci_bus_res[bus].pmem_space, 922 pci_bus_res[bus].mem_space_used); 923 924 memlist_remove_list(&pci_bus_res[bus].io_ports, 925 isa_res.io_ports_used); 926 memlist_remove_list(&pci_bus_res[bus].mem_space, 927 isa_res.mem_space_used); 928 } 929 930 memlist_free_all(&isa_res.io_ports_used); 931 memlist_free_all(&isa_res.mem_space_used); 932 933 /* add bus-range property for root/peer bus nodes */ 934 for (i = 0; i <= pci_bios_nbus; i++) { 935 /* create bus-range property on root/peer buses */ 936 if (pci_bus_res[i].par_bus == (uchar_t)-1) 937 add_bus_range_prop(i); 938 939 /* setup bus range resource on each bus */ 940 setup_bus_res(i); 941 } 942 943 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 944 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 945 if (strcmp(onoff, "off") == 0) { 946 pci_reconfig = 0; 947 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 948 } 949 ddi_prop_free(onoff); 950 } 951 952 remove_subtractive_res(); 953 954 /* reprogram the non-subtractive PPB */ 955 if (pci_reconfig) 956 for (i = 0; i <= pci_bios_nbus; i++) 957 fix_ppb_res(i, B_FALSE); 958 959 for (i = 0; i <= pci_bios_nbus; i++) { 960 /* configure devices not configured by BIOS */ 961 if (pci_reconfig) { 962 /* 963 * Reprogram the subtractive PPB. At this time, all its 964 * siblings should have got their resources already. 965 */ 966 if (pci_bus_res[i].subtractive) 967 fix_ppb_res(i, B_TRUE); 968 enumerate_bus_devs(i, CONFIG_NEW); 969 } 970 } 971 972 /* All dev programmed, so we can create available prop */ 973 for (i = 0; i <= pci_bios_nbus; i++) 974 add_bus_available_prop(i); 975 } 976 977 /* 978 * populate bus resources 979 */ 980 static void 981 populate_bus_res(uchar_t bus) 982 { 983 984 /* scan BIOS structures */ 985 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 986 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 987 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 988 pci_bus_res[bus].bus_space = find_bus_res(bus, BUSRANGE_TYPE); 989 990 /* 991 * attempt to initialize sub_bus from the largest range-end 992 * in the bus_space list 993 */ 994 if (pci_bus_res[bus].bus_space != NULL) { 995 struct memlist *entry; 996 int current; 997 998 entry = pci_bus_res[bus].bus_space; 999 while (entry != NULL) { 1000 current = entry->address + entry->size - 1; 1001 if (current > pci_bus_res[bus].sub_bus) 1002 pci_bus_res[bus].sub_bus = current; 1003 entry = entry->next; 1004 } 1005 } 1006 1007 if (bus == 0) { 1008 /* 1009 * Special treatment of bus 0: 1010 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 1011 * pcimem from boot and make I/O space the entire range 1012 * starting at 0x100. 1013 */ 1014 if (pci_bus_res[0].mem_space == NULL) 1015 pci_bus_res[0].mem_space = 1016 memlist_dup(bootops->boot_mem->pcimem); 1017 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1018 if (pci_bus_res[0].io_ports == NULL) 1019 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 1020 } 1021 1022 /* 1023 * Create 'ranges' property here before any resources are 1024 * removed from the resource lists 1025 */ 1026 add_ranges_prop(bus, 0); 1027 } 1028 1029 1030 /* 1031 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1032 */ 1033 static void 1034 create_root_bus_dip(uchar_t bus) 1035 { 1036 int pci_regs[] = {0, 0, 0}; 1037 dev_info_t *dip; 1038 1039 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1040 1041 num_root_bus++; 1042 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1043 (pnode_t)DEVI_SID_NODEID, &dip); 1044 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1045 "#address-cells", 3); 1046 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1047 "#size-cells", 2); 1048 pci_regs[0] = pci_bus_res[bus].root_addr; 1049 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1050 "reg", (int *)pci_regs, 3); 1051 1052 /* 1053 * If system has PCIe bus, then create different properties 1054 */ 1055 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1056 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1057 "device_type", "pci"); 1058 1059 (void) ndi_devi_bind_driver(dip, 0); 1060 pci_bus_res[bus].dip = dip; 1061 } 1062 1063 /* 1064 * For any fixed configuration (often compatability) pci devices 1065 * and those with their own expansion rom, create device nodes 1066 * to hold the already configured device details. 1067 */ 1068 void 1069 enumerate_bus_devs(uchar_t bus, int config_op) 1070 { 1071 uchar_t dev, func, nfunc, header; 1072 ushort_t venid; 1073 struct pci_devfunc *devlist = NULL, *entry; 1074 1075 if (config_op == CONFIG_NEW) { 1076 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1077 } else if (config_op == CONFIG_FIX) { 1078 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 1079 } else 1080 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1081 1082 if (config_op == CONFIG_NEW) { 1083 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1084 while (devlist) { 1085 entry = devlist; 1086 devlist = entry->next; 1087 if (entry->reprogram || 1088 pci_bus_res[bus].io_reprogram || 1089 pci_bus_res[bus].mem_reprogram) { 1090 /* reprogram device(s) */ 1091 (void) add_reg_props(entry->dip, bus, 1092 entry->dev, entry->func, CONFIG_NEW, 0); 1093 } 1094 kmem_free(entry, sizeof (*entry)); 1095 } 1096 pci_bus_res[bus].privdata = NULL; 1097 return; 1098 } 1099 1100 for (dev = 0; dev < max_dev_pci; dev++) { 1101 nfunc = 1; 1102 for (func = 0; func < nfunc; func++) { 1103 1104 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 1105 dev, func); 1106 1107 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1108 1109 if ((venid == 0xffff) || (venid == 0)) { 1110 /* no function at this address */ 1111 continue; 1112 } 1113 1114 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1115 if (header == 0xff) { 1116 continue; /* illegal value */ 1117 } 1118 1119 /* 1120 * according to some mail from Microsoft posted 1121 * to the pci-drivers alias, their only requirement 1122 * for a multifunction device is for the 1st 1123 * function to have to PCI_HEADER_MULTI bit set. 1124 */ 1125 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1126 nfunc = 8; 1127 } 1128 1129 if (config_op == CONFIG_FIX || 1130 config_op == CONFIG_INFO) { 1131 /* 1132 * Create the node, unconditionally, on the 1133 * first pass only. It may still need 1134 * resource assignment, which will be 1135 * done on the second, CONFIG_NEW, pass. 1136 */ 1137 process_devfunc(bus, dev, func, header, 1138 venid, config_op); 1139 1140 } 1141 } 1142 } 1143 1144 /* percolate bus used resources up through parents to root */ 1145 if (config_op == CONFIG_INFO) { 1146 int par_bus; 1147 1148 par_bus = pci_bus_res[bus].par_bus; 1149 while (par_bus != (uchar_t)-1) { 1150 1151 if (pci_bus_res[bus].io_ports_used) 1152 memlist_merge(&pci_bus_res[bus].io_ports_used, 1153 &pci_bus_res[par_bus].io_ports_used); 1154 1155 if (pci_bus_res[bus].mem_space_used) 1156 memlist_merge(&pci_bus_res[bus].mem_space_used, 1157 &pci_bus_res[par_bus].mem_space_used); 1158 1159 if (pci_bus_res[bus].pmem_space_used) 1160 memlist_merge(&pci_bus_res[bus].pmem_space_used, 1161 &pci_bus_res[par_bus].pmem_space_used); 1162 1163 par_bus = pci_bus_res[par_bus].par_bus; 1164 } 1165 } 1166 } 1167 1168 static int 1169 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1170 ushort_t subvenid, ushort_t subdevid) 1171 { 1172 static int prop_exist = -1; 1173 static char *pciide_str; 1174 char compat[32]; 1175 1176 if (prop_exist == -1) { 1177 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1178 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1179 &pciide_str) == DDI_SUCCESS); 1180 } 1181 1182 if (!prop_exist) 1183 return (0); 1184 1185 /* compare property value against various forms of compatible */ 1186 if (subvenid) { 1187 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1188 venid, devid, subvenid, subdevid, revid); 1189 if (strcmp(pciide_str, compat) == 0) 1190 return (1); 1191 1192 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1193 venid, devid, subvenid, subdevid); 1194 if (strcmp(pciide_str, compat) == 0) 1195 return (1); 1196 1197 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1198 subvenid, subdevid); 1199 if (strcmp(pciide_str, compat) == 0) 1200 return (1); 1201 } 1202 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1203 venid, devid, revid); 1204 if (strcmp(pciide_str, compat) == 0) 1205 return (1); 1206 1207 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1208 if (strcmp(pciide_str, compat) == 0) 1209 return (1); 1210 1211 return (0); 1212 } 1213 1214 static int 1215 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1216 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1217 { 1218 struct ide_table { /* table for PCI_MASS_OTHER */ 1219 ushort_t venid; 1220 ushort_t devid; 1221 } *entry; 1222 1223 /* XXX SATA and other devices: need a way to add dynamically */ 1224 static struct ide_table ide_other[] = { 1225 {0x1095, 0x3112}, 1226 {0x1095, 0x3114}, 1227 {0x1095, 0x3512}, 1228 {0x1095, 0x680}, /* Sil0680 */ 1229 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1230 {0, 0} 1231 }; 1232 1233 if (basecl != PCI_CLASS_MASS) 1234 return (0); 1235 1236 if (subcl == PCI_MASS_IDE) { 1237 return (1); 1238 } 1239 1240 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1241 return (1); 1242 1243 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1244 return (0); 1245 } 1246 1247 entry = &ide_other[0]; 1248 while (entry->venid) { 1249 if (entry->venid == venid && entry->devid == devid) 1250 return (1); 1251 entry++; 1252 } 1253 return (0); 1254 } 1255 1256 static int 1257 is_display(uint_t classcode) 1258 { 1259 static uint_t disp_classes[] = { 1260 0x000100, 1261 0x030000, 1262 0x030001 1263 }; 1264 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1265 1266 for (i = 0; i < nclasses; i++) { 1267 if (classcode == disp_classes[i]) 1268 return (1); 1269 } 1270 return (0); 1271 } 1272 1273 static void 1274 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1275 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1276 { 1277 struct pci_fixundo *newundo; 1278 1279 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1280 1281 /* 1282 * Adding an item to this list means that we must turn its NMIENABLE 1283 * bit back on at a later time. 1284 */ 1285 newundo->bus = bus; 1286 newundo->dev = dev; 1287 newundo->fn = fn; 1288 newundo->undofn = undofn; 1289 newundo->next = undolist; 1290 1291 /* add to the undo list in LIFO order */ 1292 undolist = newundo; 1293 } 1294 1295 void 1296 add_pci_fixes(void) 1297 { 1298 int i; 1299 1300 for (i = 0; i <= pci_bios_nbus; i++) { 1301 /* 1302 * For each bus, apply needed fixes to the appropriate devices. 1303 * This must be done before the main enumeration loop because 1304 * some fixes must be applied to devices normally encountered 1305 * later in the pci scan (e.g. if a fix to device 7 must be 1306 * applied before scanning device 6, applying fixes in the 1307 * normal enumeration loop would obviously be too late). 1308 */ 1309 enumerate_bus_devs(i, CONFIG_FIX); 1310 } 1311 } 1312 1313 void 1314 undo_pci_fixes(void) 1315 { 1316 struct pci_fixundo *nextundo; 1317 uint8_t bus, dev, fn; 1318 1319 /* 1320 * All fixes in the undo list are performed unconditionally. Future 1321 * fixes may require selective undo. 1322 */ 1323 while (undolist != NULL) { 1324 1325 bus = undolist->bus; 1326 dev = undolist->dev; 1327 fn = undolist->fn; 1328 1329 (*(undolist->undofn))(bus, dev, fn); 1330 1331 nextundo = undolist->next; 1332 kmem_free(undolist, sizeof (struct pci_fixundo)); 1333 undolist = nextundo; 1334 } 1335 } 1336 1337 static void 1338 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1339 { 1340 uint8_t val8; 1341 1342 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1343 /* 1344 * The NMIONERR bit is turned back on to allow the SMM BIOS 1345 * to handle more critical PCI errors (e.g. PERR#). 1346 */ 1347 val8 |= AMD8111_ENABLENMI; 1348 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1349 } 1350 1351 static void 1352 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1353 { 1354 uint8_t val8; 1355 1356 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1357 1358 if ((val8 & AMD8111_ENABLENMI) == 0) 1359 return; 1360 1361 /* 1362 * We reset NMIONERR in the LPC because master-abort on the PCI 1363 * bridge side of the 8111 will cause NMI, which might cause SMI, 1364 * which sometimes prevents all devices from being enumerated. 1365 */ 1366 val8 &= ~AMD8111_ENABLENMI; 1367 1368 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1369 1370 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1371 } 1372 1373 static void 1374 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1375 { 1376 uint16_t status; 1377 uint8_t header; 1378 uint8_t cap_ptr; 1379 uint8_t cap_id; 1380 uint16_t pmcsr; 1381 1382 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1383 if (!(status & PCI_STAT_CAP)) 1384 return; /* No capabilities list */ 1385 1386 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1387 if (header == PCI_HEADER_CARDBUS) 1388 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1389 else 1390 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1391 /* 1392 * Walk the capabilities list searching for a PM entry. 1393 */ 1394 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1395 cap_ptr &= PCI_CAP_PTR_MASK; 1396 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1397 if (cap_id == PCI_CAP_ID_PM) { 1398 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1399 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1400 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1401 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1402 break; 1403 } 1404 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1405 } 1406 1407 } 1408 1409 #define is_isa(bc, sc) \ 1410 (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 1411 1412 static void 1413 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1414 ushort_t vendorid, int config_op) 1415 { 1416 char nodename[32], unitaddr[5]; 1417 dev_info_t *dip; 1418 uchar_t basecl, subcl, progcl, intr, revid; 1419 ushort_t subvenid, subdevid, status; 1420 ushort_t slot_num; 1421 uint_t classcode, revclass; 1422 int reprogram = 0, pciide = 0; 1423 int power[2] = {1, 1}; 1424 int pciex = 0; 1425 ushort_t is_pci_bridge = 0; 1426 struct pci_devfunc *devlist = NULL, *entry = NULL; 1427 iommu_private_t *private; 1428 gfx_entry_t *gfxp; 1429 1430 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 1431 1432 switch (header & PCI_HEADER_TYPE_M) { 1433 case PCI_HEADER_ZERO: 1434 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 1435 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 1436 break; 1437 case PCI_HEADER_CARDBUS: 1438 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 1439 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 1440 /* Record the # of cardbus bridges found on the bus */ 1441 if (config_op == CONFIG_INFO) 1442 pci_bus_res[bus].num_cbb++; 1443 break; 1444 default: 1445 subvenid = 0; 1446 subdevid = 0; 1447 break; 1448 } 1449 1450 if (config_op == CONFIG_FIX) { 1451 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1452 pci_fix_amd8111(bus, dev, func); 1453 } 1454 return; 1455 } 1456 1457 /* XXX should be use generic names? derive from class? */ 1458 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1459 classcode = revclass >> 8; 1460 revid = revclass & 0xff; 1461 1462 /* figure out if this is pci-ide */ 1463 basecl = classcode >> 16; 1464 subcl = (classcode >> 8) & 0xff; 1465 progcl = classcode & 0xff; 1466 1467 1468 if (is_display(classcode)) 1469 (void) snprintf(nodename, sizeof (nodename), "display"); 1470 else if (!pseudo_isa && is_isa(basecl, subcl)) 1471 (void) snprintf(nodename, sizeof (nodename), "isa"); 1472 else if (subvenid != 0) 1473 (void) snprintf(nodename, sizeof (nodename), 1474 "pci%x,%x", subvenid, subdevid); 1475 else 1476 (void) snprintf(nodename, sizeof (nodename), 1477 "pci%x,%x", vendorid, deviceid); 1478 1479 /* make sure parent bus dip has been created */ 1480 if (pci_bus_res[bus].dip == NULL) 1481 create_root_bus_dip(bus); 1482 1483 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1484 DEVI_SID_NODEID, &dip); 1485 1486 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1487 &is_pci_bridge) == B_TRUE) 1488 pciex = 1; 1489 1490 /* add properties */ 1491 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1492 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1493 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1494 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1495 "class-code", classcode); 1496 if (func == 0) 1497 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1498 else 1499 (void) snprintf(unitaddr, sizeof (unitaddr), 1500 "%x,%x", dev, func); 1501 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1502 "unit-address", unitaddr); 1503 1504 /* add device_type for display nodes */ 1505 if (is_display(classcode)) { 1506 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1507 "device_type", "display"); 1508 } 1509 /* add special stuff for header type */ 1510 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1511 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1512 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1513 1514 if (subvenid != 0) { 1515 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1516 "subsystem-id", subdevid); 1517 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1518 "subsystem-vendor-id", subvenid); 1519 } 1520 if (!pciex) 1521 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1522 "min-grant", mingrant); 1523 if (!pciex) 1524 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1525 "max-latency", maxlatency); 1526 } 1527 1528 /* interrupt, record if not 0 */ 1529 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1530 if (intr != 0) 1531 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1532 "interrupts", intr); 1533 1534 /* 1535 * Add support for 133 mhz pci eventually 1536 */ 1537 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1538 1539 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1540 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1541 if (!pciex && (status & PCI_STAT_FBBC)) 1542 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1543 "fast-back-to-back"); 1544 if (!pciex && (status & PCI_STAT_66MHZ)) 1545 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1546 "66mhz-capable"); 1547 if (status & PCI_STAT_UDF) 1548 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1549 "udf-supported"); 1550 if (pciex && slot_num) { 1551 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1552 "physical-slot#", slot_num); 1553 if (!is_pci_bridge) 1554 pciex_slot_names_prop(dip, slot_num); 1555 } 1556 1557 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1558 "power-consumption", power, 2); 1559 1560 /* Set the device PM state to D0 */ 1561 set_devpm_d0(bus, dev, func); 1562 1563 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1564 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 1565 else { 1566 /* 1567 * Record the non-PPB devices on the bus for possible 1568 * reprogramming at 2nd bus enumeration. 1569 * Note: PPB reprogramming is done in fix_ppb_res() 1570 */ 1571 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1572 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 1573 entry->dip = dip; 1574 entry->dev = dev; 1575 entry->func = func; 1576 entry->next = devlist; 1577 pci_bus_res[bus].privdata = entry; 1578 } 1579 1580 if (config_op == CONFIG_INFO && 1581 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1582 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1583 } 1584 1585 /* check for ck8-04 based PCI ISA bridge only */ 1586 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1587 (func == 0)) 1588 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1589 1590 if (pciex && is_pci_bridge) 1591 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1592 (char *)"PCIe-PCI bridge"); 1593 else 1594 add_model_prop(dip, classcode); 1595 1596 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1597 revid, classcode, pciex); 1598 1599 /* 1600 * See if this device is a controller that advertises 1601 * itself to be a standard ATA task file controller, or one that 1602 * has been hard coded. 1603 * 1604 * If it is, check if any other higher precedence driver listed in 1605 * driver_aliases will claim the node by calling 1606 * ddi_compatibile_driver_major. If so, clear pciide and do not 1607 * create a pci-ide node or any other special handling. 1608 * 1609 * If another driver does not bind, set the node name to pci-ide 1610 * and then let the special pci-ide handling for registers and 1611 * child pci-ide nodes proceed below. 1612 */ 1613 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 1614 subvenid, subdevid) == 1) { 1615 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 1616 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 1617 pciide = 1; 1618 } 1619 } 1620 1621 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1622 (void) ndi_devi_bind_driver(dip, 0); 1623 1624 /* special handling for pci-ide */ 1625 if (pciide) { 1626 dev_info_t *cdip; 1627 1628 /* 1629 * Create properties specified by P1275 Working Group 1630 * Proposal #414 Version 1 1631 */ 1632 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1633 "device_type", "pci-ide"); 1634 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1635 "#address-cells", 1); 1636 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1637 "#size-cells", 0); 1638 1639 /* allocate two child nodes */ 1640 ndi_devi_alloc_sleep(dip, "ide", 1641 (pnode_t)DEVI_SID_NODEID, &cdip); 1642 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1643 "reg", 0); 1644 (void) ndi_devi_bind_driver(cdip, 0); 1645 ndi_devi_alloc_sleep(dip, "ide", 1646 (pnode_t)DEVI_SID_NODEID, &cdip); 1647 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1648 "reg", 1); 1649 (void) ndi_devi_bind_driver(cdip, 0); 1650 1651 reprogram = 0; /* don't reprogram pci-ide bridge */ 1652 } 1653 1654 /* allocate and set up iommu private */ 1655 private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP); 1656 private->idp_seg = 0; 1657 private->idp_bus = bus; 1658 private->idp_devfn = (dev << 3) | func; 1659 private->idp_sec = 0; 1660 private->idp_sub = 0; 1661 private->idp_bbp_type = IOMMU_PPB_NONE; 1662 /* record the bridge */ 1663 private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) && 1664 (subcl == PCI_BRIDGE_PCI)); 1665 if (private->idp_is_bridge) { 1666 private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1667 private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1668 if (pciex && is_pci_bridge) 1669 private->idp_bbp_type = IOMMU_PPB_PCIE_PCI; 1670 else if (pciex) 1671 private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE; 1672 else 1673 private->idp_bbp_type = IOMMU_PPB_PCI_PCI; 1674 } 1675 /* record the special devices */ 1676 private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE); 1677 private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) && 1678 (subcl == PCI_BRIDGE_ISA)); 1679 private->idp_intel_domain = NULL; 1680 /* hook the private to dip */ 1681 DEVI(dip)->devi_iommu_private = private; 1682 1683 if (private->idp_is_display == B_TRUE) { 1684 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 1685 gfxp->g_dip = dip; 1686 gfxp->g_prev = NULL; 1687 gfxp->g_next = gfx_devinfo_list; 1688 gfx_devinfo_list = gfxp; 1689 if (gfxp->g_next) 1690 gfxp->g_next->g_prev = gfxp; 1691 } 1692 1693 /* special handling for isa */ 1694 if (!pseudo_isa && is_isa(basecl, subcl)) { 1695 /* add device_type */ 1696 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1697 "device_type", "isa"); 1698 } 1699 1700 if (reprogram && (entry != NULL)) 1701 entry->reprogram = B_TRUE; 1702 } 1703 1704 /* 1705 * Set the compatible property to a value compliant with 1706 * rev 2.1 of the IEEE1275 PCI binding. 1707 * (Also used for PCI-Express devices). 1708 * 1709 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1710 * pciVVVV,DDDD.SSSS.ssss (1) 1711 * pciSSSS,ssss (2) 1712 * pciVVVV,DDDD.RR (3) 1713 * pciVVVV,DDDD (4) 1714 * pciclass,CCSSPP (5) 1715 * pciclass,CCSS (6) 1716 * 1717 * The Subsystem (SSSS) forms are not inserted if 1718 * subsystem-vendor-id is 0. 1719 * 1720 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1721 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1722 * 1723 * Set with setprop and \x00 between each 1724 * to generate the encoded string array form. 1725 */ 1726 void 1727 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1728 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1729 int pciex) 1730 { 1731 int i = 0; 1732 int size = COMPAT_BUFSIZE; 1733 char *compat[13]; 1734 char *buf, *curr; 1735 1736 curr = buf = kmem_alloc(size, KM_SLEEP); 1737 1738 if (pciex) { 1739 if (subvenid) { 1740 compat[i++] = curr; /* form 0 */ 1741 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1742 vendorid, deviceid, subvenid, subdevid, revid); 1743 size -= strlen(curr) + 1; 1744 curr += strlen(curr) + 1; 1745 1746 compat[i++] = curr; /* form 1 */ 1747 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1748 vendorid, deviceid, subvenid, subdevid); 1749 size -= strlen(curr) + 1; 1750 curr += strlen(curr) + 1; 1751 1752 } 1753 compat[i++] = curr; /* form 3 */ 1754 (void) snprintf(curr, size, "pciex%x,%x.%x", 1755 vendorid, deviceid, revid); 1756 size -= strlen(curr) + 1; 1757 curr += strlen(curr) + 1; 1758 1759 compat[i++] = curr; /* form 4 */ 1760 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1761 size -= strlen(curr) + 1; 1762 curr += strlen(curr) + 1; 1763 1764 compat[i++] = curr; /* form 5 */ 1765 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1766 size -= strlen(curr) + 1; 1767 curr += strlen(curr) + 1; 1768 1769 compat[i++] = curr; /* form 6 */ 1770 (void) snprintf(curr, size, "pciexclass,%04x", 1771 (classcode >> 8)); 1772 size -= strlen(curr) + 1; 1773 curr += strlen(curr) + 1; 1774 } 1775 1776 if (subvenid) { 1777 compat[i++] = curr; /* form 0 */ 1778 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1779 vendorid, deviceid, subvenid, subdevid, revid); 1780 size -= strlen(curr) + 1; 1781 curr += strlen(curr) + 1; 1782 1783 compat[i++] = curr; /* form 1 */ 1784 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1785 vendorid, deviceid, subvenid, subdevid); 1786 size -= strlen(curr) + 1; 1787 curr += strlen(curr) + 1; 1788 1789 compat[i++] = curr; /* form 2 */ 1790 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1791 size -= strlen(curr) + 1; 1792 curr += strlen(curr) + 1; 1793 } 1794 compat[i++] = curr; /* form 3 */ 1795 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1796 size -= strlen(curr) + 1; 1797 curr += strlen(curr) + 1; 1798 1799 compat[i++] = curr; /* form 4 */ 1800 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1801 size -= strlen(curr) + 1; 1802 curr += strlen(curr) + 1; 1803 1804 compat[i++] = curr; /* form 5 */ 1805 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1806 size -= strlen(curr) + 1; 1807 curr += strlen(curr) + 1; 1808 1809 compat[i++] = curr; /* form 6 */ 1810 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1811 size -= strlen(curr) + 1; 1812 curr += strlen(curr) + 1; 1813 1814 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1815 "compatible", compat, i); 1816 kmem_free(buf, COMPAT_BUFSIZE); 1817 } 1818 1819 /* 1820 * Adjust the reg properties for a dual channel PCI-IDE device. 1821 * 1822 * NOTE: don't do anything that changes the order of the hard-decodes 1823 * and programmed BARs. The kernel driver depends on these values 1824 * being in this order regardless of whether they're for a 'native' 1825 * mode BAR or not. 1826 */ 1827 /* 1828 * config info for pci-ide devices 1829 */ 1830 static struct { 1831 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1832 uchar_t bar_offset; /* offset for alt status register */ 1833 ushort_t addr; /* compatibility mode base address */ 1834 ushort_t length; /* number of ports for this BAR */ 1835 } pciide_bar[] = { 1836 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1837 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1838 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1839 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1840 }; 1841 1842 static int 1843 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1844 { 1845 int hard_decode = 0; 1846 1847 /* 1848 * Adjust the base and len for the BARs of the PCI-IDE 1849 * device's primary and secondary controllers. The first 1850 * two BARs are for the primary controller and the next 1851 * two BARs are for the secondary controller. The fifth 1852 * and sixth bars are never adjusted. 1853 */ 1854 if (index >= 0 && index <= 3) { 1855 *lenp = pciide_bar[index].length; 1856 1857 if (progcl & pciide_bar[index].native_mask) { 1858 *basep += pciide_bar[index].bar_offset; 1859 } else { 1860 *basep = pciide_bar[index].addr; 1861 hard_decode = 1; 1862 } 1863 } 1864 1865 /* 1866 * if either base or len is zero make certain both are zero 1867 */ 1868 if (*basep == 0 || *lenp == 0) { 1869 *basep = 0; 1870 *lenp = 0; 1871 hard_decode = 0; 1872 } 1873 1874 return (hard_decode); 1875 } 1876 1877 1878 /* 1879 * Add the "reg" and "assigned-addresses" property 1880 */ 1881 static int 1882 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1883 int config_op, int pciide) 1884 { 1885 uchar_t baseclass, subclass, progclass, header; 1886 ushort_t bar_sz; 1887 uint_t value = 0, len, devloc; 1888 uint_t base, base_hi, type; 1889 ushort_t offset, end; 1890 int max_basereg, j, reprogram = 0; 1891 uint_t phys_hi; 1892 struct memlist **io_res, **io_res_used; 1893 struct memlist **mem_res, **mem_res_used; 1894 struct memlist **pmem_res, **pmem_res_used; 1895 uchar_t res_bus; 1896 1897 pci_regspec_t regs[16] = {{0}}; 1898 pci_regspec_t assigned[15] = {{0}}; 1899 int nreg, nasgn; 1900 1901 io_res = &pci_bus_res[bus].io_ports; 1902 io_res_used = &pci_bus_res[bus].io_ports_used; 1903 mem_res = &pci_bus_res[bus].mem_space; 1904 mem_res_used = &pci_bus_res[bus].mem_space_used; 1905 pmem_res = &pci_bus_res[bus].pmem_space; 1906 pmem_res_used = &pci_bus_res[bus].pmem_space_used; 1907 1908 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1909 regs[0].pci_phys_hi = devloc; 1910 nreg = 1; /* rest of regs[0] is all zero */ 1911 nasgn = 0; 1912 1913 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1914 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1915 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1916 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1917 1918 switch (header) { 1919 case PCI_HEADER_ZERO: 1920 max_basereg = PCI_BASE_NUM; 1921 break; 1922 case PCI_HEADER_PPB: 1923 max_basereg = PCI_BCNF_BASE_NUM; 1924 break; 1925 case PCI_HEADER_CARDBUS: 1926 max_basereg = PCI_CBUS_BASE_NUM; 1927 break; 1928 default: 1929 max_basereg = 0; 1930 break; 1931 } 1932 1933 /* 1934 * Create the register property by saving the current 1935 * value of the base register. Write 0xffffffff to the 1936 * base register. Read the value back to determine the 1937 * required size of the address space. Restore the base 1938 * register contents. 1939 * 1940 * Do not disable I/O and memory access; this isn't necessary 1941 * since no driver is yet attached to this device, and disabling 1942 * I/O and memory access has the side-effect of disabling PCI-PCI 1943 * bridge mappings, which makes the bridge transparent to secondary- 1944 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1945 * Spec V1.2). 1946 */ 1947 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1948 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1949 j++, offset += bar_sz) { 1950 int hard_decode = 0; 1951 1952 /* determine the size of the address space */ 1953 base = pci_getl(bus, dev, func, offset); 1954 pci_putl(bus, dev, func, offset, 0xffffffff); 1955 value = pci_getl(bus, dev, func, offset); 1956 pci_putl(bus, dev, func, offset, base); 1957 1958 /* construct phys hi,med.lo, size hi, lo */ 1959 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1960 /* i/o space */ 1961 bar_sz = PCI_BAR_SZ_32; 1962 value &= PCI_BASE_IO_ADDR_M; 1963 len = ((value ^ (value-1)) + 1) >> 1; 1964 1965 /* XXX Adjust first 4 IDE registers */ 1966 if (pciide) { 1967 if (subclass != PCI_MASS_IDE) 1968 progclass = (PCI_IDE_IF_NATIVE_PRI | 1969 PCI_IDE_IF_NATIVE_SEC); 1970 hard_decode = pciIdeAdjustBAR(progclass, j, 1971 &base, &len); 1972 } else if (value == 0) { 1973 /* skip base regs with size of 0 */ 1974 continue; 1975 } 1976 1977 regs[nreg].pci_size_low = 1978 assigned[nasgn].pci_size_low = len; 1979 if (!hard_decode) { 1980 regs[nreg].pci_phys_hi = 1981 (PCI_ADDR_IO | devloc) + offset; 1982 } else { 1983 regs[nreg].pci_phys_hi = 1984 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1985 offset; 1986 regs[nreg].pci_phys_low = 1987 base & PCI_BASE_IO_ADDR_M; 1988 } 1989 assigned[nasgn].pci_phys_hi = 1990 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1991 type = base & (~PCI_BASE_IO_ADDR_M); 1992 base &= PCI_BASE_IO_ADDR_M; 1993 /* 1994 * A device under a subtractive PPB can allocate 1995 * resources from its parent bus if there is no resource 1996 * available on its own bus. 1997 */ 1998 if ((config_op == CONFIG_NEW) && (*io_res == NULL)) { 1999 res_bus = bus; 2000 while (pci_bus_res[res_bus].subtractive) { 2001 res_bus = pci_bus_res[res_bus].par_bus; 2002 if (res_bus == (uchar_t)-1) 2003 break; /* root bus already */ 2004 if (pci_bus_res[res_bus].io_ports) { 2005 io_res = &pci_bus_res 2006 [res_bus].io_ports; 2007 break; 2008 } 2009 } 2010 } 2011 2012 /* 2013 * first pass - gather what's there 2014 * update/second pass - adjust/allocate regions 2015 * config - allocate regions 2016 */ 2017 if (config_op == CONFIG_INFO) { /* first pass */ 2018 /* take out of the resource map of the bus */ 2019 if (base != 0) { 2020 (void) memlist_remove(io_res, base, 2021 len); 2022 memlist_insert(io_res_used, base, len); 2023 } else 2024 reprogram = 1; 2025 } else if ((*io_res && base == 0) || 2026 pci_bus_res[bus].io_reprogram) { 2027 base = (uint_t)memlist_find(io_res, len, len); 2028 if (base != 0) { 2029 memlist_insert(io_res_used, base, len); 2030 /* XXX need to worry about 64-bit? */ 2031 pci_putl(bus, dev, func, offset, 2032 base | type); 2033 base = pci_getl(bus, dev, func, offset); 2034 base &= PCI_BASE_IO_ADDR_M; 2035 } 2036 if (base == 0) { 2037 cmn_err(CE_WARN, "failed to program" 2038 " IO space [%d/%d/%d] BAR@0x%x" 2039 " length 0x%x", 2040 bus, dev, func, offset, len); 2041 } 2042 } 2043 assigned[nasgn].pci_phys_low = base; 2044 nreg++, nasgn++; 2045 2046 } else { 2047 /* memory space */ 2048 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2049 bar_sz = PCI_BAR_SZ_64; 2050 base_hi = pci_getl(bus, dev, func, offset + 4); 2051 phys_hi = PCI_ADDR_MEM64; 2052 } else { 2053 bar_sz = PCI_BAR_SZ_32; 2054 base_hi = 0; 2055 phys_hi = PCI_ADDR_MEM32; 2056 } 2057 2058 /* skip base regs with size of 0 */ 2059 value &= PCI_BASE_M_ADDR_M; 2060 2061 if (value == 0) 2062 continue; 2063 2064 len = ((value ^ (value-1)) + 1) >> 1; 2065 regs[nreg].pci_size_low = 2066 assigned[nasgn].pci_size_low = len; 2067 2068 phys_hi |= (devloc | offset); 2069 if (base & PCI_BASE_PREF_M) 2070 phys_hi |= PCI_PREFETCH_B; 2071 2072 /* 2073 * A device under a subtractive PPB can allocate 2074 * resources from its parent bus if there is no resource 2075 * available on its own bus. 2076 */ 2077 if ((config_op == CONFIG_NEW) && (*mem_res == NULL)) { 2078 res_bus = bus; 2079 while (pci_bus_res[res_bus].subtractive) { 2080 res_bus = pci_bus_res[res_bus].par_bus; 2081 if (res_bus == (uchar_t)-1) 2082 break; /* root bus already */ 2083 mem_res = 2084 &pci_bus_res[res_bus].mem_space; 2085 pmem_res = 2086 &pci_bus_res [res_bus].pmem_space; 2087 /* 2088 * Break out as long as at least 2089 * mem_res is available 2090 */ 2091 if ((*pmem_res && 2092 (phys_hi & PCI_PREFETCH_B)) || 2093 *mem_res) 2094 break; 2095 } 2096 } 2097 2098 regs[nreg].pci_phys_hi = 2099 assigned[nasgn].pci_phys_hi = phys_hi; 2100 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2101 assigned[nasgn].pci_phys_mid = base_hi; 2102 type = base & ~PCI_BASE_M_ADDR_M; 2103 base &= PCI_BASE_M_ADDR_M; 2104 2105 if (config_op == CONFIG_INFO) { 2106 /* take out of the resource map of the bus */ 2107 if (base != NULL) { 2108 /* remove from PMEM and MEM space */ 2109 (void) memlist_remove(mem_res, 2110 base, len); 2111 (void) memlist_remove(pmem_res, 2112 base, len); 2113 /* only note as used in correct map */ 2114 if (phys_hi & PCI_PREFETCH_B) 2115 memlist_insert(pmem_res_used, 2116 base, len); 2117 else 2118 memlist_insert(mem_res_used, 2119 base, len); 2120 } else 2121 reprogram = 1; 2122 } else if ((*mem_res && base == NULL) || 2123 pci_bus_res[bus].mem_reprogram) { 2124 /* 2125 * When desired, attempt a prefetchable 2126 * allocation first 2127 */ 2128 if (phys_hi & PCI_PREFETCH_B) { 2129 base = (uint_t)memlist_find(pmem_res, 2130 len, len); 2131 if (base != NULL) { 2132 memlist_insert(pmem_res_used, 2133 base, len); 2134 (void) memlist_remove(mem_res, 2135 base, len); 2136 } 2137 } 2138 /* 2139 * If prefetchable allocation was not 2140 * desired, or failed, attempt ordinary 2141 * memory allocation 2142 */ 2143 if (base == NULL) { 2144 base = (uint_t)memlist_find(mem_res, 2145 len, len); 2146 if (base != NULL) { 2147 memlist_insert(mem_res_used, 2148 base, len); 2149 (void) memlist_remove(pmem_res, 2150 base, len); 2151 } 2152 } 2153 if (base != NULL) { 2154 pci_putl(bus, dev, func, offset, 2155 base | type); 2156 base = pci_getl(bus, dev, func, offset); 2157 base &= PCI_BASE_M_ADDR_M; 2158 } else 2159 cmn_err(CE_WARN, "failed to program " 2160 "mem space [%d/%d/%d] BAR@0x%x" 2161 " length 0x%x", 2162 bus, dev, func, offset, len); 2163 } 2164 assigned[nasgn].pci_phys_low = base; 2165 nreg++, nasgn++; 2166 } 2167 } 2168 switch (header) { 2169 case PCI_HEADER_ZERO: 2170 offset = PCI_CONF_ROM; 2171 break; 2172 case PCI_HEADER_PPB: 2173 offset = PCI_BCNF_ROM; 2174 break; 2175 default: /* including PCI_HEADER_CARDBUS */ 2176 goto done; 2177 } 2178 2179 /* 2180 * Add the expansion rom memory space 2181 * Determine the size of the ROM base reg; don't write reserved bits 2182 * ROM isn't in the PCI memory space. 2183 */ 2184 base = pci_getl(bus, dev, func, offset); 2185 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2186 value = pci_getl(bus, dev, func, offset); 2187 pci_putl(bus, dev, func, offset, base); 2188 if (value & PCI_BASE_ROM_ENABLE) 2189 value &= PCI_BASE_ROM_ADDR_M; 2190 else 2191 value = 0; 2192 2193 if (value != 0) { 2194 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2195 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2196 PCI_ADDR_MEM32 | devloc) + offset; 2197 base &= PCI_BASE_ROM_ADDR_M; 2198 assigned[nasgn].pci_phys_low = base; 2199 len = ((value ^ (value-1)) + 1) >> 1; 2200 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2201 nreg++, nasgn++; 2202 /* take it out of the memory resource */ 2203 if (base != NULL) { 2204 (void) memlist_remove(mem_res, base, len); 2205 memlist_insert(mem_res_used, base, len); 2206 } 2207 } 2208 2209 /* 2210 * Account for "legacy" (alias) video adapter resources 2211 */ 2212 2213 /* add the three hard-decode, aliased address spaces for VGA */ 2214 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2215 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2216 2217 /* VGA hard decode 0x3b0-0x3bb */ 2218 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2219 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2220 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2221 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2222 nreg++, nasgn++; 2223 (void) memlist_remove(io_res, 0x3b0, 0xc); 2224 memlist_insert(io_res_used, 0x3b0, 0xc); 2225 2226 /* VGA hard decode 0x3c0-0x3df */ 2227 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2228 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2229 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2230 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2231 nreg++, nasgn++; 2232 (void) memlist_remove(io_res, 0x3c0, 0x20); 2233 memlist_insert(io_res_used, 0x3c0, 0x20); 2234 2235 /* Video memory */ 2236 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2237 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 2238 regs[nreg].pci_phys_low = 2239 assigned[nasgn].pci_phys_low = 0xa0000; 2240 regs[nreg].pci_size_low = 2241 assigned[nasgn].pci_size_low = 0x20000; 2242 nreg++, nasgn++; 2243 /* remove from MEM and PMEM space */ 2244 (void) memlist_remove(mem_res, 0xa0000, 0x20000); 2245 (void) memlist_remove(pmem_res, 0xa0000, 0x20000); 2246 memlist_insert(mem_res_used, 0xa0000, 0x20000); 2247 } 2248 2249 /* add the hard-decode, aliased address spaces for 8514 */ 2250 if ((baseclass == PCI_CLASS_DISPLAY) && 2251 (subclass == PCI_DISPLAY_VGA) && 2252 (progclass & PCI_DISPLAY_IF_8514)) { 2253 2254 /* hard decode 0x2e8 */ 2255 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2256 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2257 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2258 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2259 nreg++, nasgn++; 2260 (void) memlist_remove(io_res, 0x2e8, 0x1); 2261 memlist_insert(io_res_used, 0x2e8, 0x1); 2262 2263 /* hard decode 0x2ea-0x2ef */ 2264 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2265 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2266 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2267 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2268 nreg++, nasgn++; 2269 (void) memlist_remove(io_res, 0x2ea, 0x6); 2270 memlist_insert(io_res_used, 0x2ea, 0x6); 2271 } 2272 2273 done: 2274 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2275 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2276 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2277 "assigned-addresses", 2278 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2279 2280 return (reprogram); 2281 } 2282 2283 static void 2284 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2285 int pciex, ushort_t is_pci_bridge) 2286 { 2287 char *dev_type; 2288 int i; 2289 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 2290 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2291 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2292 uchar_t progclass; 2293 2294 ASSERT(secbus <= subbus); 2295 2296 /* 2297 * Check if it's a subtractive PPB. 2298 */ 2299 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2300 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 2301 pci_bus_res[secbus].subtractive = B_TRUE; 2302 2303 /* 2304 * Some BIOSes lie about max pci busses, we allow for 2305 * such mistakes here 2306 */ 2307 if (subbus > pci_bios_nbus) { 2308 pci_bios_nbus = subbus; 2309 alloc_res_array(); 2310 } 2311 2312 ASSERT(pci_bus_res[secbus].dip == NULL); 2313 pci_bus_res[secbus].dip = dip; 2314 pci_bus_res[secbus].par_bus = bus; 2315 2316 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 2317 2318 /* setup bus number hierarchy */ 2319 pci_bus_res[secbus].sub_bus = subbus; 2320 /* 2321 * Keep track of the largest subordinate bus number (this is essential 2322 * for peer busses because there is no other way of determining its 2323 * subordinate bus number). 2324 */ 2325 if (subbus > pci_bus_res[bus].sub_bus) 2326 pci_bus_res[bus].sub_bus = subbus; 2327 /* 2328 * Loop through subordinate busses, initializing their parent bus 2329 * field to this bridge's parent. The subordinate busses' parent 2330 * fields may very well be further refined later, as child bridges 2331 * are enumerated. (The value is to note that the subordinate busses 2332 * are not peer busses by changing their par_bus fields to anything 2333 * other than -1.) 2334 */ 2335 for (i = secbus + 1; i <= subbus; i++) 2336 pci_bus_res[i].par_bus = bus; 2337 2338 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2339 "device_type", dev_type); 2340 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2341 "#address-cells", 3); 2342 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2343 "#size-cells", 2); 2344 2345 /* 2346 * According to PPB spec, the base register should be programmed 2347 * with a value bigger than the limit register when there are 2348 * no resources available. This applies to io, memory, and 2349 * prefetchable memory. 2350 */ 2351 2352 /* 2353 * io range 2354 * We determine i/o windows that are left unconfigured by BIOS 2355 * through its i/o enable bit as Microsoft recommends OEMs to do. 2356 * If it is unset, we disable i/o and mark it for reconfiguration in 2357 * later passes by setting the base > limit 2358 */ 2359 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2360 if (val & PCI_COMM_IO) { 2361 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 2362 io_range[0] = ((val & 0xf0) << 8); 2363 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 2364 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 2365 } else { 2366 io_range[0] = 0x9fff; 2367 io_range[1] = 0x1000; 2368 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 2369 (uint8_t)((io_range[0] >> 8) & 0xf0)); 2370 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 2371 (uint8_t)((io_range[1] >> 8) & 0xf0)); 2372 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 2373 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 2374 } 2375 2376 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2377 memlist_insert(&pci_bus_res[secbus].io_ports, 2378 (uint64_t)io_range[0], 2379 (uint64_t)(io_range[1] - io_range[0] + 1)); 2380 memlist_insert(&pci_bus_res[bus].io_ports_used, 2381 (uint64_t)io_range[0], 2382 (uint64_t)(io_range[1] - io_range[0] + 1)); 2383 if (pci_bus_res[bus].io_ports != NULL) { 2384 (void) memlist_remove(&pci_bus_res[bus].io_ports, 2385 (uint64_t)io_range[0], 2386 (uint64_t)(io_range[1] - io_range[0] + 1)); 2387 } 2388 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 2389 secbus, io_range[0], io_range[1]); 2390 /* if 32-bit supported, make sure upper bits are not set */ 2391 if ((val & 0xf) == 1 && 2392 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 2393 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 2394 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2395 } 2396 } 2397 2398 /* mem range */ 2399 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 2400 mem_range[0] = ((val & 0xFFF0) << 16); 2401 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 2402 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2403 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2404 memlist_insert(&pci_bus_res[secbus].mem_space, 2405 (uint64_t)mem_range[0], 2406 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2407 memlist_insert(&pci_bus_res[bus].mem_space_used, 2408 (uint64_t)mem_range[0], 2409 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2410 /* remove from parent resource list */ 2411 (void) memlist_remove(&pci_bus_res[bus].mem_space, 2412 (uint64_t)mem_range[0], 2413 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2414 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 2415 (uint64_t)mem_range[0], 2416 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2417 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 2418 secbus, mem_range[0], mem_range[1]); 2419 } 2420 2421 /* prefetchable memory range */ 2422 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 2423 pmem_range[0] = ((val & 0xFFF0) << 16); 2424 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 2425 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2426 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2427 memlist_insert(&pci_bus_res[secbus].pmem_space, 2428 (uint64_t)pmem_range[0], 2429 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2430 memlist_insert(&pci_bus_res[bus].pmem_space_used, 2431 (uint64_t)pmem_range[0], 2432 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2433 /* remove from parent resource list */ 2434 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 2435 (uint64_t)pmem_range[0], 2436 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2437 (void) memlist_remove(&pci_bus_res[bus].mem_space, 2438 (uint64_t)pmem_range[0], 2439 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2440 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 2441 secbus, pmem_range[0], pmem_range[1]); 2442 /* if 64-bit supported, make sure upper bits are not set */ 2443 if ((val & 0xf) == 1 && 2444 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 2445 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 2446 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2447 } 2448 } 2449 2450 add_bus_range_prop(secbus); 2451 add_ranges_prop(secbus, 1); 2452 } 2453 2454 extern const struct pci_class_strings_s class_pci[]; 2455 extern int class_pci_items; 2456 2457 static void 2458 add_model_prop(dev_info_t *dip, uint_t classcode) 2459 { 2460 const char *desc; 2461 int i; 2462 uchar_t baseclass = classcode >> 16; 2463 uchar_t subclass = (classcode >> 8) & 0xff; 2464 uchar_t progclass = classcode & 0xff; 2465 2466 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 2467 desc = "IDE controller"; 2468 } else { 2469 for (desc = 0, i = 0; i < class_pci_items; i++) { 2470 if ((baseclass == class_pci[i].base_class) && 2471 (subclass == class_pci[i].sub_class) && 2472 (progclass == class_pci[i].prog_class)) { 2473 desc = class_pci[i].actual_desc; 2474 break; 2475 } 2476 } 2477 if (i == class_pci_items) 2478 desc = "Unknown class of pci/pnpbios device"; 2479 } 2480 2481 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2482 (char *)desc); 2483 } 2484 2485 static void 2486 add_bus_range_prop(int bus) 2487 { 2488 int bus_range[2]; 2489 2490 if (pci_bus_res[bus].dip == NULL) 2491 return; 2492 bus_range[0] = bus; 2493 bus_range[1] = pci_bus_res[bus].sub_bus; 2494 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2495 "bus-range", (int *)bus_range, 2); 2496 } 2497 2498 /* 2499 * Add slot-names property for any named pci hot-plug slots 2500 */ 2501 static void 2502 add_bus_slot_names_prop(int bus) 2503 { 2504 char slotprop[256]; 2505 int len; 2506 2507 if (pci_bus_res[bus].dip != NULL) { 2508 /* simply return if the property is already defined */ 2509 if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2510 DDI_PROP_DONTPASS, "slot-names")) 2511 return; 2512 } 2513 2514 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2515 if (len > 0) { 2516 /* 2517 * Only create a peer bus node if this bus may be a peer bus. 2518 * It may be a peer bus if the dip is NULL and if par_bus is 2519 * -1 (par_bus is -1 if this bus was not found to be 2520 * subordinate to any PCI-PCI bridge). 2521 * If it's not a peer bus, then the ACPI BBN-handling code 2522 * will remove it later. 2523 */ 2524 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 2525 pci_bus_res[bus].dip == NULL) { 2526 2527 create_root_bus_dip(bus); 2528 } 2529 if (pci_bus_res[bus].dip != NULL) { 2530 ASSERT((len % sizeof (int)) == 0); 2531 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2532 pci_bus_res[bus].dip, "slot-names", 2533 (int *)slotprop, len / sizeof (int)); 2534 } else { 2535 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 2536 "IRQ routing table; Not adding slot-names " 2537 "property for incorrect bus %d", bus); 2538 } 2539 } 2540 } 2541 2542 /* 2543 * Handle both PCI root and PCI-PCI bridge range properties; 2544 * non-zero 'ppb' argument select PCI-PCI bridges versus root. 2545 */ 2546 static void 2547 memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) 2548 { 2549 ppb_ranges_t *ppb_rp = *rp; 2550 pci_ranges_t *pci_rp = *rp; 2551 2552 while (entry != NULL) { 2553 if (ppb) { 2554 ppb_rp->child_high = ppb_rp->parent_high = type; 2555 ppb_rp->child_mid = ppb_rp->parent_mid = 2556 (uint32_t)(entry->address >> 32); /* XXX */ 2557 ppb_rp->child_low = ppb_rp->parent_low = 2558 (uint32_t)entry->address; 2559 ppb_rp->size_high = 2560 (uint32_t)(entry->size >> 32); /* XXX */ 2561 ppb_rp->size_low = (uint32_t)entry->size; 2562 *rp = ++ppb_rp; 2563 } else { 2564 pci_rp->child_high = type; 2565 pci_rp->child_mid = pci_rp->parent_high = 2566 (uint32_t)(entry->address >> 32); /* XXX */ 2567 pci_rp->child_low = pci_rp->parent_low = 2568 (uint32_t)entry->address; 2569 pci_rp->size_high = 2570 (uint32_t)(entry->size >> 32); /* XXX */ 2571 pci_rp->size_low = (uint32_t)entry->size; 2572 *rp = ++pci_rp; 2573 } 2574 entry = entry->next; 2575 } 2576 } 2577 2578 static void 2579 add_ranges_prop(int bus, int ppb) 2580 { 2581 int total, alloc_size; 2582 void *rp, *next_rp; 2583 2584 /* no devinfo node - unused bus, return */ 2585 if (pci_bus_res[bus].dip == NULL) 2586 return; 2587 2588 total = memlist_count(pci_bus_res[bus].io_ports); 2589 total += memlist_count(pci_bus_res[bus].mem_space); 2590 total += memlist_count(pci_bus_res[bus].pmem_space); 2591 2592 /* no property is created if no ranges are present */ 2593 if (total == 0) 2594 return; 2595 2596 alloc_size = total * 2597 (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 2598 2599 next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 2600 2601 memlist_to_ranges(&next_rp, pci_bus_res[bus].io_ports, 2602 PCI_ADDR_IO | PCI_REG_REL_M, ppb); 2603 memlist_to_ranges(&next_rp, pci_bus_res[bus].mem_space, 2604 PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 2605 memlist_to_ranges(&next_rp, pci_bus_res[bus].pmem_space, 2606 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 2607 2608 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2609 "ranges", (int *)rp, alloc_size / sizeof (int)); 2610 2611 kmem_free(rp, alloc_size); 2612 } 2613 2614 static void 2615 memlist_remove_list(struct memlist **list, struct memlist *remove_list) 2616 { 2617 while (list && *list && remove_list) { 2618 (void) memlist_remove(list, remove_list->address, 2619 remove_list->size); 2620 remove_list = remove_list->next; 2621 } 2622 } 2623 2624 static int 2625 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 2626 { 2627 int i = 0; 2628 2629 while (list) { 2630 /* assume 32-bit addresses */ 2631 sp->pci_phys_hi = type; 2632 sp->pci_phys_mid = 0; 2633 sp->pci_phys_low = (uint32_t)list->address; 2634 sp->pci_size_hi = 0; 2635 sp->pci_size_low = (uint32_t)list->size; 2636 2637 list = list->next; 2638 sp++, i++; 2639 } 2640 return (i); 2641 } 2642 2643 static void 2644 add_bus_available_prop(int bus) 2645 { 2646 int i, count; 2647 struct pci_phys_spec *sp; 2648 2649 /* no devinfo node - unused bus, return */ 2650 if (pci_bus_res[bus].dip == NULL) 2651 return; 2652 2653 count = memlist_count(pci_bus_res[bus].io_ports) + 2654 memlist_count(pci_bus_res[bus].mem_space) + 2655 memlist_count(pci_bus_res[bus].pmem_space); 2656 2657 if (count == 0) /* nothing available */ 2658 return; 2659 2660 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 2661 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 2662 PCI_ADDR_IO | PCI_REG_REL_M); 2663 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 2664 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2665 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 2666 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2667 ASSERT(i == count); 2668 2669 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2670 "available", (int *)sp, 2671 i * sizeof (struct pci_phys_spec) / sizeof (int)); 2672 kmem_free(sp, count * sizeof (*sp)); 2673 } 2674 2675 static void 2676 alloc_res_array(void) 2677 { 2678 static int array_max = 0; 2679 int old_max; 2680 void *old_res; 2681 2682 if (array_max > pci_bios_nbus + 1) 2683 return; /* array is big enough */ 2684 2685 old_max = array_max; 2686 old_res = pci_bus_res; 2687 2688 if (array_max == 0) 2689 array_max = 16; /* start with a reasonable number */ 2690 2691 while (array_max < pci_bios_nbus + 1) 2692 array_max <<= 1; 2693 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2694 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2695 2696 if (old_res) { /* copy content and free old array */ 2697 bcopy(old_res, pci_bus_res, 2698 old_max * sizeof (struct pci_bus_resource)); 2699 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2700 } 2701 } 2702 2703 static void 2704 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2705 ushort_t deviceid) 2706 { 2707 static dev_info_t *ioapicsnode = NULL; 2708 static int numioapics = 0; 2709 dev_info_t *ioapic_node; 2710 uint64_t physaddr; 2711 uint32_t lobase, hibase = 0; 2712 2713 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2714 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2715 2716 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2717 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2718 return; 2719 2720 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2721 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2722 2723 lobase &= PCI_BASE_M_ADDR_M; 2724 2725 physaddr = (((uint64_t)hibase) << 32) | lobase; 2726 2727 /* 2728 * Create a nexus node for all IOAPICs under the root node. 2729 */ 2730 if (ioapicsnode == NULL) { 2731 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2732 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2733 return; 2734 } 2735 (void) ndi_devi_online(ioapicsnode, 0); 2736 } 2737 2738 /* 2739 * Create a child node for this IOAPIC 2740 */ 2741 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2742 DEVI_SID_NODEID, numioapics++); 2743 if (ioapic_node == NULL) { 2744 return; 2745 } 2746 2747 /* Vendor and Device ID */ 2748 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2749 IOAPICS_PROP_VENID, vendorid); 2750 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2751 IOAPICS_PROP_DEVID, deviceid); 2752 2753 /* device_type */ 2754 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2755 "device_type", IOAPICS_DEV_TYPE); 2756 2757 /* reg */ 2758 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2759 "reg", physaddr); 2760 } 2761 2762 /* 2763 * NOTE: For PCIe slots, the name is generated from the slot number 2764 * information obtained from Slot Capabilities register. 2765 * For non-PCIe slots, it is generated based on the slot number 2766 * information in the PCI IRQ table. 2767 */ 2768 static void 2769 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2770 { 2771 char slotprop[256]; 2772 int len; 2773 2774 bzero(slotprop, sizeof (slotprop)); 2775 2776 /* set mask to 1 as there is only one slot (i.e dev 0) */ 2777 *(uint32_t *)slotprop = 1; 2778 len = 4; 2779 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2780 slot_num); 2781 len += strlen(slotprop + len) + 1; 2782 len += len % 4; 2783 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2784 (int *)slotprop, len / sizeof (int)); 2785 } 2786