1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI configurator (pcicfg) 30 */ 31 32 #include <sys/sysmacros.h> 33 #include <sys/conf.h> 34 #include <sys/kmem.h> 35 #include <sys/debug.h> 36 #include <sys/modctl.h> 37 #include <sys/autoconf.h> 38 #include <sys/hwconf.h> 39 #include <sys/pcie.h> 40 #include <sys/ddi.h> 41 #include <sys/sunndi.h> 42 #include <sys/hotplug/pci/pcicfg.h> 43 #include <sys/ndi_impldefs.h> 44 45 /* 46 * ************************************************************************ 47 * *** Implementation specific local data structures/definitions. *** 48 * ************************************************************************ 49 */ 50 51 static int pcicfg_start_devno = 0; /* for Debug only */ 52 53 #define PCICFG_NODEVICE 42 54 #define PCICFG_NOMEMORY 43 55 #define PCICFG_NOMULTI 44 56 57 #define PCICFG_HIADDR(n) ((uint32_t)(((uint64_t)(n) & \ 58 0xFFFFFFFF00000000ULL)>> 32)) 59 #define PCICFG_LOADDR(n) ((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF)) 60 #define PCICFG_LADDR(lo, hi) (((uint64_t)(hi) << 32) | (uint32_t)(lo)) 61 62 #define PCICFG_HIWORD(n) ((uint16_t)(((uint32_t)(n) & 0xFFFF0000)>> 16)) 63 #define PCICFG_LOWORD(n) ((uint16_t)((uint32_t)(n) & 0x0000FFFF)) 64 #define PCICFG_HIBYTE(n) ((uint8_t)(((uint16_t)(n) & 0xFF00)>> 8)) 65 #define PCICFG_LOBYTE(n) ((uint8_t)((uint16_t)(n) & 0x00FF)) 66 67 #define PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1)))) 68 #define PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1))) 69 70 #define PCICFG_MEMGRAN 0x100000 71 #define PCICFG_IOGRAN 0x1000 72 #define PCICFG_4GIG_LIMIT 0xFFFFFFFFUL 73 74 #define PCICFG_MEM_MULT 4 75 #define PCICFG_IO_MULT 4 76 #define PCICFG_RANGE_LEN 3 /* Number of range entries */ 77 78 static int pcicfg_slot_busnums = 8; 79 static int pcicfg_slot_memsize = 32 * PCICFG_MEMGRAN; /* 32MB per slot */ 80 static int pcicfg_slot_pf_memsize = 32 * PCICFG_MEMGRAN; /* 32MB per slot */ 81 static int pcicfg_slot_iosize = 64 * PCICFG_IOGRAN; /* 64K per slot */ 82 static int pcicfg_sec_reset_delay = 3000000; 83 static int pcicfg_do_legacy_props = 1; /* create legacy compatible prop */ 84 85 typedef struct hole hole_t; 86 87 struct hole { 88 uint64_t start; 89 uint64_t len; 90 hole_t *next; 91 }; 92 93 typedef struct pcicfg_phdl pcicfg_phdl_t; 94 95 struct pcicfg_phdl { 96 97 dev_info_t *dip; /* Associated with the bridge */ 98 dev_info_t *top_dip; /* top node of the attach point */ 99 pcicfg_phdl_t *next; 100 101 /* non-prefetchable memory space */ 102 uint64_t memory_base; /* Memory base for this attach point */ 103 uint64_t memory_last; 104 uint64_t memory_len; 105 106 /* prefetchable memory space */ 107 uint64_t pf_memory_base; /* PF Memory base for this AP */ 108 uint64_t pf_memory_last; 109 uint64_t pf_memory_len; 110 111 /* io space */ 112 uint32_t io_base; /* I/O base for this attach point */ 113 uint32_t io_last; 114 uint32_t io_len; 115 116 int error; 117 uint_t highest_bus; /* Highest bus seen on the probe */ 118 119 hole_t mem_hole; /* Memory hole linked list. */ 120 hole_t pf_mem_hole; /* PF Memory hole linked list. */ 121 hole_t io_hole; /* IO hole linked list */ 122 123 ndi_ra_request_t mem_req; /* allocator request for memory */ 124 ndi_ra_request_t pf_mem_req; /* allocator request for PF memory */ 125 ndi_ra_request_t io_req; /* allocator request for I/O */ 126 }; 127 128 struct pcicfg_standard_prop_entry { 129 uchar_t *name; 130 uint_t config_offset; 131 uint_t size; 132 }; 133 134 135 struct pcicfg_name_entry { 136 uint32_t class_code; 137 char *name; 138 }; 139 140 struct pcicfg_find_ctrl { 141 uint_t device; 142 uint_t function; 143 dev_info_t *dip; 144 }; 145 146 /* 147 * List of Indirect Config Map Devices. At least the intent of the 148 * design is to look for a device in this list during the configure 149 * operation, and if the device is listed here, then it is a nontransparent 150 * bridge, hence load the driver and avail the config map services from 151 * the driver. Class and Subclass should be as defined in the PCI specs 152 * ie. class is 0x6, and subclass is 0x9. 153 */ 154 static struct { 155 uint8_t mem_range_bar_offset; 156 uint8_t io_range_bar_offset; 157 uint8_t prefetch_mem_range_bar_offset; 158 } pcicfg_indirect_map_devs[] = { 159 PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3, 160 0, 0, 0, 161 }; 162 163 #define PCICFG_MAKE_REG_HIGH(busnum, devnum, funcnum, register)\ 164 (\ 165 ((ulong_t)(busnum & 0xff) << 16) |\ 166 ((ulong_t)(devnum & 0x1f) << 11) |\ 167 ((ulong_t)(funcnum & 0x7) << 8) |\ 168 ((ulong_t)(register & 0x3f))) 169 170 /* 171 * debug macros: 172 */ 173 #if defined(DEBUG) 174 extern void prom_printf(const char *, ...); 175 176 /* 177 * Following values are defined for this debug flag. 178 * 179 * 1 = dump configuration header only. 180 * 2 = dump generic debug data only (no config header dumped) 181 * 3 = dump everything (both 1 and 2) 182 */ 183 int pcicfg_debug = 0; 184 185 static void debug(char *, uintptr_t, uintptr_t, 186 uintptr_t, uintptr_t, uintptr_t); 187 188 #define DEBUG0(fmt)\ 189 debug(fmt, 0, 0, 0, 0, 0); 190 #define DEBUG1(fmt, a1)\ 191 debug(fmt, (uintptr_t)(a1), 0, 0, 0, 0); 192 #define DEBUG2(fmt, a1, a2)\ 193 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0); 194 #define DEBUG3(fmt, a1, a2, a3)\ 195 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 196 (uintptr_t)(a3), 0, 0); 197 #define DEBUG4(fmt, a1, a2, a3, a4)\ 198 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 199 (uintptr_t)(a3), (uintptr_t)(a4), 0); 200 #define DEBUG5(fmt, a1, a2, a3, a4, a5)\ 201 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 202 (uintptr_t)(a3), (uintptr_t)(a4), (uintptr_t)(a5)); 203 #else 204 #define DEBUG0(fmt) 205 #define DEBUG1(fmt, a1) 206 #define DEBUG2(fmt, a1, a2) 207 #define DEBUG3(fmt, a1, a2, a3) 208 #define DEBUG4(fmt, a1, a2, a3, a4) 209 #define DEBUG5(fmt, a1, a2, a3, a4, a5) 210 #endif 211 212 /* 213 * forward declarations for routines defined in this module (called here) 214 */ 215 216 static int pcicfg_add_config_reg(dev_info_t *, 217 uint_t, uint_t, uint_t); 218 static int pcicfg_probe_children(dev_info_t *, uint_t, uint_t, uint_t, 219 uint_t *); 220 static int pcicfg_match_dev(dev_info_t *, void *); 221 static dev_info_t *pcicfg_devi_find(dev_info_t *, uint_t, uint_t); 222 static pcicfg_phdl_t *pcicfg_find_phdl(dev_info_t *); 223 static pcicfg_phdl_t *pcicfg_create_phdl(dev_info_t *); 224 static int pcicfg_destroy_phdl(dev_info_t *); 225 static int pcicfg_sum_resources(dev_info_t *, void *); 226 static int pcicfg_device_assign(dev_info_t *); 227 static int pcicfg_bridge_assign(dev_info_t *, void *); 228 static int pcicfg_free_resources(dev_info_t *); 229 static void pcicfg_setup_bridge(pcicfg_phdl_t *, ddi_acc_handle_t); 230 static void pcicfg_update_bridge(pcicfg_phdl_t *, ddi_acc_handle_t); 231 static int pcicfg_update_assigned_prop(dev_info_t *, pci_regspec_t *); 232 static void pcicfg_device_on(ddi_acc_handle_t); 233 static void pcicfg_device_off(ddi_acc_handle_t); 234 static int pcicfg_set_busnode_props(dev_info_t *, uint8_t); 235 static int pcicfg_free_bridge_resources(dev_info_t *); 236 static int pcicfg_free_device_resources(dev_info_t *); 237 static int pcicfg_teardown_device(dev_info_t *); 238 static void pcicfg_reparent_node(dev_info_t *, dev_info_t *); 239 static int pcicfg_config_setup(dev_info_t *, ddi_acc_handle_t *); 240 static void pcicfg_config_teardown(ddi_acc_handle_t *); 241 static void pcicfg_get_mem(pcicfg_phdl_t *, uint32_t, uint64_t *); 242 static void pcicfg_get_pf_mem(pcicfg_phdl_t *, uint32_t, uint64_t *); 243 static void pcicfg_get_io(pcicfg_phdl_t *, uint32_t, uint32_t *); 244 static int pcicfg_update_ranges_prop(dev_info_t *, ppb_ranges_t *); 245 static int pcicfg_configure_ntbridge(dev_info_t *, uint_t, uint_t); 246 static uint_t pcicfg_ntbridge_child(dev_info_t *); 247 static uint_t pcicfg_get_ntbridge_child_range(dev_info_t *, uint64_t *, 248 uint64_t *, uint_t); 249 static int pcicfg_is_ntbridge(dev_info_t *); 250 static int pcicfg_ntbridge_allocate_resources(dev_info_t *); 251 static int pcicfg_ntbridge_configure_done(dev_info_t *); 252 static int pcicfg_ntbridge_program_child(dev_info_t *); 253 static uint_t pcicfg_ntbridge_unconfigure(dev_info_t *); 254 static int pcicfg_ntbridge_unconfigure_child(dev_info_t *, uint_t); 255 static void pcicfg_free_hole(hole_t *); 256 static uint64_t pcicfg_alloc_hole(hole_t *, uint64_t *, uint32_t); 257 static int pcicfg_device_type(dev_info_t *, ddi_acc_handle_t *); 258 static void pcicfg_update_phdl(dev_info_t *, uint8_t, uint8_t); 259 static int pcicfg_get_cap(ddi_acc_handle_t, uint8_t); 260 static uint8_t pcicfg_get_nslots(dev_info_t *, ddi_acc_handle_t); 261 static int pcicfg_pcie_dev(dev_info_t *, ddi_acc_handle_t); 262 static int pcicfg_pcie_device_type(dev_info_t *, ddi_acc_handle_t); 263 static int pcicfg_pcie_port_type(dev_info_t *, ddi_acc_handle_t); 264 static int pcicfg_probe_bridge(dev_info_t *, ddi_acc_handle_t, uint_t, 265 uint_t *); 266 static int pcicfg_find_resource_end(dev_info_t *, void *); 267 268 #ifdef DEBUG 269 static void pcicfg_dump_common_config(ddi_acc_handle_t config_handle); 270 static void pcicfg_dump_device_config(ddi_acc_handle_t); 271 static void pcicfg_dump_bridge_config(ddi_acc_handle_t config_handle); 272 static uint64_t pcicfg_unused_space(hole_t *, uint32_t *); 273 274 #define PCICFG_DUMP_COMMON_CONFIG(hdl) (void)pcicfg_dump_common_config(hdl) 275 #define PCICFG_DUMP_DEVICE_CONFIG(hdl) (void)pcicfg_dump_device_config(hdl) 276 #define PCICFG_DUMP_BRIDGE_CONFIG(hdl) (void)pcicfg_dump_bridge_config(hdl) 277 #else 278 #define PCICFG_DUMP_COMMON_CONFIG(handle) 279 #define PCICFG_DUMP_DEVICE_CONFIG(handle) 280 #define PCICFG_DUMP_BRIDGE_CONFIG(handle) 281 #endif 282 283 static kmutex_t pcicfg_list_mutex; /* Protects the probe handle list */ 284 static pcicfg_phdl_t *pcicfg_phdl_list = NULL; 285 286 #ifndef _DONT_USE_1275_GENERIC_NAMES 287 /* 288 * Class code table 289 */ 290 static struct pcicfg_name_entry pcicfg_class_lookup [] = { 291 292 { 0x001, "display" }, 293 { 0x100, "scsi" }, 294 { 0x101, "ide" }, 295 { 0x102, "fdc" }, 296 { 0x103, "ipi" }, 297 { 0x104, "raid" }, 298 { 0x105, "ata" }, 299 { 0x106, "sata" }, 300 { 0x200, "ethernet" }, 301 { 0x201, "token-ring" }, 302 { 0x202, "fddi" }, 303 { 0x203, "atm" }, 304 { 0x204, "isdn" }, 305 { 0x206, "mcd" }, 306 { 0x300, "display" }, 307 { 0x400, "video" }, 308 { 0x401, "sound" }, 309 { 0x500, "memory" }, 310 { 0x501, "flash" }, 311 { 0x600, "host" }, 312 { 0x601, "isa" }, 313 { 0x602, "eisa" }, 314 { 0x603, "mca" }, 315 { 0x604, "pci" }, 316 { 0x605, "pcmcia" }, 317 { 0x606, "nubus" }, 318 { 0x607, "cardbus" }, 319 { 0x609, "pci" }, 320 { 0x60a, "ib-pci" }, 321 { 0x700, "serial" }, 322 { 0x701, "parallel" }, 323 { 0x800, "interrupt-controller" }, 324 { 0x801, "dma-controller" }, 325 { 0x802, "timer" }, 326 { 0x803, "rtc" }, 327 { 0x900, "keyboard" }, 328 { 0x901, "pen" }, 329 { 0x902, "mouse" }, 330 { 0xa00, "dock" }, 331 { 0xb00, "cpu" }, 332 { 0xb01, "cpu" }, 333 { 0xb02, "cpu" }, 334 { 0xb10, "cpu" }, 335 { 0xb20, "cpu" }, 336 { 0xb30, "cpu" }, 337 { 0xb40, "coproc" }, 338 { 0xc00, "firewire" }, 339 { 0xc01, "access-bus" }, 340 { 0xc02, "ssa" }, 341 { 0xc03, "usb" }, 342 { 0xc04, "fibre-channel" }, 343 { 0xc05, "smbus" }, 344 { 0xc06, "ib" }, 345 { 0xd00, "irda" }, 346 { 0xd01, "ir" }, 347 { 0xd10, "rf" }, 348 { 0xd11, "btooth" }, 349 { 0xd12, "brdband" }, 350 { 0xd20, "802.11a" }, 351 { 0xd21, "802.11b" }, 352 { 0xe00, "i2o" }, 353 { 0xf01, "tv" }, 354 { 0xf02, "audio" }, 355 { 0xf03, "voice" }, 356 { 0xf04, "data" }, 357 { 0, 0 } 358 }; 359 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 360 361 /* 362 * Module control operations 363 */ 364 365 extern struct mod_ops mod_miscops; 366 367 static struct modlmisc modlmisc = { 368 &mod_miscops, /* Type of module */ 369 "PCI configurator %I%" 370 }; 371 372 static struct modlinkage modlinkage = { 373 MODREV_1, (void *)&modlmisc, NULL 374 }; 375 376 377 #ifdef DEBUG 378 379 static void 380 pcicfg_dump_common_config(ddi_acc_handle_t config_handle) 381 { 382 if ((pcicfg_debug & 1) == 0) 383 return; 384 prom_printf(" Vendor ID = [0x%x]\n", 385 pci_config_get16(config_handle, PCI_CONF_VENID)); 386 prom_printf(" Device ID = [0x%x]\n", 387 pci_config_get16(config_handle, PCI_CONF_DEVID)); 388 prom_printf(" Command REG = [0x%x]\n", 389 pci_config_get16(config_handle, PCI_CONF_COMM)); 390 prom_printf(" Status REG = [0x%x]\n", 391 pci_config_get16(config_handle, PCI_CONF_STAT)); 392 prom_printf(" Revision ID = [0x%x]\n", 393 pci_config_get8(config_handle, PCI_CONF_REVID)); 394 prom_printf(" Prog Class = [0x%x]\n", 395 pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 396 prom_printf(" Dev Class = [0x%x]\n", 397 pci_config_get8(config_handle, PCI_CONF_SUBCLASS)); 398 prom_printf(" Base Class = [0x%x]\n", 399 pci_config_get8(config_handle, PCI_CONF_BASCLASS)); 400 prom_printf(" Device ID = [0x%x]\n", 401 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ)); 402 prom_printf(" Header Type = [0x%x]\n", 403 pci_config_get8(config_handle, PCI_CONF_HEADER)); 404 prom_printf(" BIST = [0x%x]\n", 405 pci_config_get8(config_handle, PCI_CONF_BIST)); 406 prom_printf(" BASE 0 = [0x%x]\n", 407 pci_config_get32(config_handle, PCI_CONF_BASE0)); 408 prom_printf(" BASE 1 = [0x%x]\n", 409 pci_config_get32(config_handle, PCI_CONF_BASE1)); 410 411 } 412 413 static void 414 pcicfg_dump_device_config(ddi_acc_handle_t config_handle) 415 { 416 if ((pcicfg_debug & 1) == 0) 417 return; 418 pcicfg_dump_common_config(config_handle); 419 420 prom_printf(" BASE 2 = [0x%x]\n", 421 pci_config_get32(config_handle, PCI_CONF_BASE2)); 422 prom_printf(" BASE 3 = [0x%x]\n", 423 pci_config_get32(config_handle, PCI_CONF_BASE3)); 424 prom_printf(" BASE 4 = [0x%x]\n", 425 pci_config_get32(config_handle, PCI_CONF_BASE4)); 426 prom_printf(" BASE 5 = [0x%x]\n", 427 pci_config_get32(config_handle, PCI_CONF_BASE5)); 428 prom_printf(" Cardbus CIS = [0x%x]\n", 429 pci_config_get32(config_handle, PCI_CONF_CIS)); 430 prom_printf(" Sub VID = [0x%x]\n", 431 pci_config_get16(config_handle, PCI_CONF_SUBVENID)); 432 prom_printf(" Sub SID = [0x%x]\n", 433 pci_config_get16(config_handle, PCI_CONF_SUBSYSID)); 434 prom_printf(" ROM = [0x%x]\n", 435 pci_config_get32(config_handle, PCI_CONF_ROM)); 436 prom_printf(" I Line = [0x%x]\n", 437 pci_config_get8(config_handle, PCI_CONF_ILINE)); 438 prom_printf(" I Pin = [0x%x]\n", 439 pci_config_get8(config_handle, PCI_CONF_IPIN)); 440 prom_printf(" Max Grant = [0x%x]\n", 441 pci_config_get8(config_handle, PCI_CONF_MIN_G)); 442 prom_printf(" Max Latent = [0x%x]\n", 443 pci_config_get8(config_handle, PCI_CONF_MAX_L)); 444 } 445 446 static void 447 pcicfg_dump_bridge_config(ddi_acc_handle_t config_handle) 448 { 449 if ((pcicfg_debug & 1) == 0) 450 return; 451 pcicfg_dump_common_config(config_handle); 452 453 prom_printf("........................................\n"); 454 455 prom_printf(" Pri Bus = [0x%x]\n", 456 pci_config_get8(config_handle, PCI_BCNF_PRIBUS)); 457 prom_printf(" Sec Bus = [0x%x]\n", 458 pci_config_get8(config_handle, PCI_BCNF_SECBUS)); 459 prom_printf(" Sub Bus = [0x%x]\n", 460 pci_config_get8(config_handle, PCI_BCNF_SUBBUS)); 461 prom_printf(" Latency = [0x%x]\n", 462 pci_config_get8(config_handle, PCI_BCNF_LATENCY_TIMER)); 463 prom_printf(" I/O Base LO = [0x%x]\n", 464 pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW)); 465 prom_printf(" I/O Lim LO = [0x%x]\n", 466 pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW)); 467 prom_printf(" Sec. Status = [0x%x]\n", 468 pci_config_get16(config_handle, PCI_BCNF_SEC_STATUS)); 469 prom_printf(" Mem Base = [0x%x]\n", 470 pci_config_get16(config_handle, PCI_BCNF_MEM_BASE)); 471 prom_printf(" Mem Limit = [0x%x]\n", 472 pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT)); 473 prom_printf(" PF Mem Base = [0x%x]\n", 474 pci_config_get16(config_handle, PCI_BCNF_PF_BASE_LOW)); 475 prom_printf(" PF Mem Lim = [0x%x]\n", 476 pci_config_get16(config_handle, PCI_BCNF_PF_LIMIT_LOW)); 477 prom_printf(" PF Base HI = [0x%x]\n", 478 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH)); 479 prom_printf(" PF Lim HI = [0x%x]\n", 480 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); 481 prom_printf(" I/O Base HI = [0x%x]\n", 482 pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI)); 483 prom_printf(" I/O Lim HI = [0x%x]\n", 484 pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI)); 485 prom_printf(" ROM addr = [0x%x]\n", 486 pci_config_get32(config_handle, PCI_BCNF_ROM)); 487 prom_printf(" Intr Line = [0x%x]\n", 488 pci_config_get8(config_handle, PCI_BCNF_ILINE)); 489 prom_printf(" Intr Pin = [0x%x]\n", 490 pci_config_get8(config_handle, PCI_BCNF_IPIN)); 491 prom_printf(" Bridge Ctrl = [0x%x]\n", 492 pci_config_get16(config_handle, PCI_BCNF_BCNTRL)); 493 } 494 #endif 495 496 int 497 _init() 498 { 499 DEBUG0(" PCI configurator installed\n"); 500 mutex_init(&pcicfg_list_mutex, NULL, MUTEX_DRIVER, NULL); 501 return (mod_install(&modlinkage)); 502 } 503 504 int 505 _fini(void) 506 { 507 int error; 508 509 error = mod_remove(&modlinkage); 510 if (error != 0) { 511 return (error); 512 } 513 mutex_destroy(&pcicfg_list_mutex); 514 return (0); 515 } 516 517 int 518 _info(struct modinfo *modinfop) 519 { 520 return (mod_info(&modlinkage, modinfop)); 521 } 522 523 /* 524 * In the following functions ndi_devi_enter() without holding the 525 * parent dip is sufficient. This is because pci dr is driven through 526 * opens on the nexus which is in the device tree path above the node 527 * being operated on, and implicitly held due to the open. 528 */ 529 530 /* 531 * This entry point is called to configure a device (and 532 * all its children) on the given bus. It is called when 533 * a new device is added to the PCI domain. This routine 534 * will create the device tree and program the devices 535 * registers. 536 */ 537 538 int 539 pcicfg_configure(dev_info_t *devi, uint_t device) 540 { 541 uint_t bus; 542 int len; 543 int func; 544 dev_info_t *new_device; 545 dev_info_t *attach_point; 546 pci_bus_range_t pci_bus_range; 547 int rv; 548 int circ; 549 uint_t highest_bus; 550 551 /* 552 * Start probing at the device specified in "device" on the 553 * "bus" specified. 554 */ 555 len = sizeof (pci_bus_range_t); 556 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, devi, 0, "bus-range", 557 (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) { 558 DEBUG0("no bus-range property\n"); 559 return (PCICFG_FAILURE); 560 } 561 562 bus = pci_bus_range.lo; /* primary bus number of this bus node */ 563 564 attach_point = devi; 565 566 ndi_devi_enter(devi, &circ); 567 for (func = 0; func < PCI_MAX_FUNCTIONS; func++) { 568 569 DEBUG3("Configuring [0x%x][0x%x][0x%x]\n", bus, device, func); 570 571 switch (rv = pcicfg_probe_children(attach_point, 572 bus, device, func, &highest_bus)) { 573 case PCICFG_FAILURE: 574 DEBUG2("configure failed: " 575 "bus [0x%x] device [0x%x]\n", 576 bus, device); 577 goto cleanup; 578 case PCICFG_NODEVICE: 579 DEBUG3("no device : bus " 580 "[0x%x] slot [0x%x] func [0x%x]\n", 581 bus, device, func); 582 continue; 583 default: 584 DEBUG3("configure: bus => [%d] " 585 "slot => [%d] func => [%d]\n", 586 bus, device, func); 587 break; 588 } 589 590 if (rv != PCICFG_SUCCESS) 591 break; 592 593 if ((new_device = pcicfg_devi_find(attach_point, 594 device, func)) == NULL) { 595 DEBUG0("Did'nt find device node just created\n"); 596 goto cleanup; 597 } 598 599 /* 600 * Up until now, we have detected a non transparent bridge 601 * (ntbridge) as a part of the generic probe code and 602 * configured only one configuration 603 * header which is the side facing the host bus. 604 * Now, configure the other side and create children. 605 * 606 * In order to make the process simpler, lets load the device 607 * driver for the non transparent bridge as this is a 608 * Solaris bundled driver, and use its configuration map 609 * services rather than programming it here. 610 * If the driver is not bundled into Solaris, it must be 611 * first loaded and configured before performing any 612 * hotplug operations. 613 * 614 * This not only makes the code here simpler but also more 615 * generic. 616 * 617 * So here we go. 618 */ 619 620 /* 621 * check if this is a bridge in nontransparent mode 622 */ 623 if (pcicfg_is_ntbridge(new_device) != DDI_FAILURE) { 624 625 int rc; 626 627 DEBUG0("pcicfg: Found nontransparent bridge.\n"); 628 629 rc = pcicfg_configure_ntbridge(new_device, bus, device); 630 if (rc == PCICFG_FAILURE) 631 goto cleanup; 632 } 633 } 634 635 ndi_devi_exit(devi, circ); 636 637 if (func == 0) 638 return (PCICFG_FAILURE); /* probe failed */ 639 else 640 return (PCICFG_SUCCESS); 641 642 cleanup: 643 /* 644 * Clean up a partially created "probe state" tree. 645 * There are no resources allocated to the in the 646 * probe state. 647 */ 648 649 for (func = 0; func < PCI_MAX_FUNCTIONS; func++) { 650 if ((new_device = pcicfg_devi_find(devi, 651 device, func)) == NULL) { 652 continue; 653 } 654 655 DEBUG2("Cleaning up device [0x%x] function [0x%x]\n", 656 device, func); 657 /* 658 * If this was a bridge device it will have a 659 * probe handle - if not, no harm in calling this. 660 */ 661 (void) pcicfg_destroy_phdl(new_device); 662 /* 663 * This will free up the node 664 */ 665 (void) ndi_devi_offline(new_device, NDI_DEVI_REMOVE); 666 } 667 ndi_devi_exit(devi, circ); 668 669 return (PCICFG_FAILURE); 670 } 671 672 /* 673 * configure the child nodes of ntbridge. new_device points to ntbridge itself 674 */ 675 /*ARGSUSED*/ 676 static int 677 pcicfg_configure_ntbridge(dev_info_t *new_device, uint_t bus, uint_t device) 678 { 679 int bus_range[2], rc = PCICFG_FAILURE, rc1, max_devs = 0; 680 int devno; 681 dev_info_t *new_ntbridgechild; 682 ddi_acc_handle_t config_handle; 683 uint16_t vid; 684 uint64_t next_bus; 685 uint64_t blen; 686 ndi_ra_request_t req; 687 uint8_t pcie_device_type = 0; 688 689 /* 690 * If we need to do indirect config, lets create a property here 691 * to let the child conf map routine know that it has to 692 * go through the DDI calls, and not assume the devices are 693 * mapped directly under the host. 694 */ 695 if ((rc = ndi_prop_update_int(DDI_DEV_T_NONE, new_device, 696 PCI_DEV_CONF_MAP_PROP, (int)DDI_SUCCESS)) 697 != DDI_SUCCESS) { 698 699 DEBUG0("Cannot create indirect conf map property.\n"); 700 return ((int)PCICFG_FAILURE); 701 } 702 703 if (pci_config_setup(new_device, &config_handle) != DDI_SUCCESS) 704 return (PCICFG_FAILURE); 705 /* check if we are PCIe device */ 706 if (pcicfg_pcie_device_type(new_device, config_handle) == DDI_SUCCESS) { 707 DEBUG0("PCIe device detected\n"); 708 pcie_device_type = 1; 709 } 710 pci_config_teardown(&config_handle); 711 /* create Bus node properties for ntbridge. */ 712 if (pcicfg_set_busnode_props(new_device, pcie_device_type) 713 != PCICFG_SUCCESS) { 714 DEBUG0("Failed to set busnode props\n"); 715 return (rc); 716 } 717 718 /* For now: Lets only support one layer of child */ 719 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 720 req.ra_len = 1; 721 if (ndi_ra_alloc(ddi_get_parent(new_device), &req, 722 &next_bus, &blen, NDI_RA_TYPE_PCI_BUSNUM, 723 NDI_RA_PASS) != NDI_SUCCESS) { 724 DEBUG0("ntbridge: Failed to get a bus number\n"); 725 return (rc); 726 } 727 728 DEBUG1("ntbridge bus range start ->[%d]\n", next_bus); 729 730 /* 731 * Following will change, as we detect more bridges 732 * on the way. 733 */ 734 bus_range[0] = (int)next_bus; 735 bus_range[1] = (int)next_bus; 736 737 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, new_device, 738 "bus-range", bus_range, 2) != DDI_SUCCESS) { 739 DEBUG0("Cannot set ntbridge bus-range property"); 740 return (rc); 741 } 742 743 /* 744 * The other interface (away from the host) will be 745 * initialized by the nexus driver when it loads. 746 * We just have to set the registers and the nexus driver 747 * figures out the rest. 748 */ 749 750 /* 751 * finally, lets load and attach the driver 752 * before configuring children of ntbridge. 753 */ 754 rc = ndi_devi_online(new_device, NDI_ONLINE_ATTACH|NDI_CONFIG); 755 if (rc != NDI_SUCCESS) { 756 cmn_err(CE_WARN, 757 "pcicfg: Fail:cant load nontransparent bridgd driver..\n"); 758 rc = PCICFG_FAILURE; 759 return (rc); 760 } 761 DEBUG0("pcicfg: Success loading nontransparent bridge nexus driver.."); 762 763 /* Now set aside pci resources for our children. */ 764 if (pcicfg_ntbridge_allocate_resources(new_device) != 765 PCICFG_SUCCESS) { 766 max_devs = 0; 767 rc = PCICFG_FAILURE; 768 } else 769 max_devs = PCI_MAX_DEVICES; 770 771 /* Probe devices on 2nd bus */ 772 for (devno = pcicfg_start_devno; devno < max_devs; devno++) { 773 774 ndi_devi_alloc_sleep(new_device, DEVI_PSEUDO_NEXNAME, 775 (pnode_t)DEVI_SID_NODEID, &new_ntbridgechild); 776 777 if (pcicfg_add_config_reg(new_ntbridgechild, next_bus, devno, 0) 778 != DDI_PROP_SUCCESS) { 779 cmn_err(CE_WARN, 780 "Failed to add conf reg for ntbridge child.\n"); 781 (void) ndi_devi_free(new_ntbridgechild); 782 rc = PCICFG_FAILURE; 783 break; 784 } 785 786 if (pci_config_setup(new_ntbridgechild, &config_handle) 787 != DDI_SUCCESS) { 788 cmn_err(CE_WARN, 789 "Cannot map ntbridge child %x\n", devno); 790 (void) ndi_devi_free(new_ntbridgechild); 791 rc = PCICFG_FAILURE; 792 break; 793 } 794 795 /* 796 * See if there is any PCI HW at this location 797 * by reading the Vendor ID. If it returns with 0xffff 798 * then there is no hardware at this location. 799 */ 800 vid = pci_config_get16(config_handle, PCI_CONF_VENID); 801 802 pci_config_teardown(&config_handle); 803 (void) ndi_devi_free(new_ntbridgechild); 804 if (vid == 0xffff) 805 continue; 806 807 /* Lets fake attachments points for each child, */ 808 if (pcicfg_configure(new_device, devno) != PCICFG_SUCCESS) { 809 int old_dev = pcicfg_start_devno; 810 811 cmn_err(CE_WARN, 812 "Error configuring ntbridge child dev=%d\n", devno); 813 814 rc = PCICFG_FAILURE; 815 while (old_dev != devno) { 816 if (pcicfg_ntbridge_unconfigure_child( 817 new_device, old_dev) == PCICFG_FAILURE) 818 819 cmn_err(CE_WARN, 820 "Unconfig Error ntbridge child " 821 "dev=%d\n", old_dev); 822 old_dev++; 823 } 824 break; 825 } 826 } /* devno loop */ 827 DEBUG1("ntbridge: finish probing 2nd bus, rc=%d\n", rc); 828 829 if (rc != PCICFG_FAILURE) 830 rc = pcicfg_ntbridge_configure_done(new_device); 831 else { 832 pcicfg_phdl_t *entry = pcicfg_find_phdl(new_device); 833 uint_t *bus; 834 int k; 835 836 if (ddi_getlongprop(DDI_DEV_T_ANY, new_device, 837 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 838 &k) != DDI_PROP_SUCCESS) { 839 DEBUG0("Failed to read bus-range property\n"); 840 rc = PCICFG_FAILURE; 841 return (rc); 842 } 843 844 DEBUG2("Need to free bus [%d] range [%d]\n", 845 bus[0], bus[1] - bus[0] + 1); 846 847 if (ndi_ra_free(ddi_get_parent(new_device), 848 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), 849 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 850 DEBUG0("Failed to free a bus number\n"); 851 rc = PCICFG_FAILURE; 852 return (rc); 853 } 854 855 /* 856 * Since no memory allocations are done for non transparent 857 * bridges (but instead we just set the handle with the 858 * already allocated memory, we just need to reset the 859 * following values before calling the destroy_phdl() 860 * function next, otherwise the it will try to free 861 * memory allocated as in case of a transparent bridge. 862 */ 863 entry->memory_len = 0; 864 entry->pf_memory_len = 0; 865 entry->io_len = 0; 866 /* the following will free hole data. */ 867 (void) pcicfg_destroy_phdl(new_device); 868 } 869 870 /* 871 * Unload driver just in case child configure failed! 872 */ 873 rc1 = ndi_devi_offline(new_device, 0); 874 DEBUG1("pcicfg: now unloading the ntbridge driver. rc1=%d\n", rc1); 875 if (rc1 != NDI_SUCCESS) { 876 cmn_err(CE_WARN, 877 "pcicfg: cant unload ntbridge driver..children.\n"); 878 rc = PCICFG_FAILURE; 879 } 880 881 return (rc); 882 } 883 884 static int 885 pcicfg_ntbridge_allocate_resources(dev_info_t *dip) 886 { 887 pcicfg_phdl_t *phdl; 888 ndi_ra_request_t *mem_request; 889 ndi_ra_request_t *pf_mem_request; 890 ndi_ra_request_t *io_request; 891 uint64_t boundbase, boundlen; 892 893 phdl = pcicfg_find_phdl(dip); 894 ASSERT(phdl); 895 896 mem_request = &phdl->mem_req; 897 pf_mem_request = &phdl->pf_mem_req; 898 io_request = &phdl->io_req; 899 900 phdl->error = PCICFG_SUCCESS; 901 902 /* Set Memory space handle for ntbridge */ 903 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 904 PCI_BASE_SPACE_MEM) != DDI_SUCCESS) { 905 cmn_err(CE_WARN, 906 "ntbridge: Mem resource information failure\n"); 907 phdl->memory_len = 0; 908 return (PCICFG_FAILURE); 909 } 910 mem_request->ra_boundbase = boundbase; 911 mem_request->ra_boundlen = boundbase + boundlen; 912 mem_request->ra_len = boundlen; 913 mem_request->ra_align_mask = 914 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 915 mem_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 916 917 /* 918 * mem_request->ra_len = 919 * PCICFG_ROUND_UP(mem_request->ra_len, PCICFG_MEMGRAN); 920 */ 921 922 phdl->memory_base = phdl->memory_last = boundbase; 923 phdl->memory_len = boundlen; 924 phdl->mem_hole.start = phdl->memory_base; 925 phdl->mem_hole.len = mem_request->ra_len; 926 phdl->mem_hole.next = (hole_t *)NULL; 927 928 DEBUG2("AP requested [0x%llx], needs [0x%llx] bytes of memory\n", 929 boundlen, mem_request->ra_len); 930 931 /* Set IO space handle for ntbridge */ 932 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 933 PCI_BASE_SPACE_IO) != DDI_SUCCESS) { 934 cmn_err(CE_WARN, "ntbridge: IO resource information failure\n"); 935 phdl->io_len = 0; 936 return (PCICFG_FAILURE); 937 } 938 io_request->ra_len = boundlen; 939 io_request->ra_align_mask = 940 PCICFG_IOGRAN - 1; /* 4K alignment on I/O space */ 941 io_request->ra_boundbase = boundbase; 942 io_request->ra_boundlen = boundbase + boundlen; 943 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 944 945 /* 946 * io_request->ra_len = 947 * PCICFG_ROUND_UP(io_request->ra_len, PCICFG_IOGRAN); 948 */ 949 950 phdl->io_base = phdl->io_last = (uint32_t)boundbase; 951 phdl->io_len = (uint32_t)boundlen; 952 phdl->io_hole.start = phdl->io_base; 953 phdl->io_hole.len = io_request->ra_len; 954 phdl->io_hole.next = (hole_t *)NULL; 955 956 DEBUG2("AP requested [0x%llx], needs [0x%llx] bytes of IO\n", 957 boundlen, io_request->ra_len); 958 959 /* Set Prefetchable Memory space handle for ntbridge */ 960 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 961 PCI_BASE_SPACE_MEM | PCI_BASE_PREF_M) != DDI_SUCCESS) { 962 cmn_err(CE_WARN, 963 "ntbridge: PF Mem resource information failure\n"); 964 phdl->pf_memory_len = 0; 965 return (PCICFG_FAILURE); 966 } 967 pf_mem_request->ra_boundbase = boundbase; 968 pf_mem_request->ra_boundlen = boundbase + boundlen; 969 pf_mem_request->ra_len = boundlen; 970 pf_mem_request->ra_align_mask = 971 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 972 pf_mem_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 973 974 /* 975 * pf_mem_request->ra_len = 976 * PCICFG_ROUND_UP(pf_mem_request->ra_len, PCICFG_MEMGRAN); 977 */ 978 979 phdl->pf_memory_base = phdl->pf_memory_last = boundbase; 980 phdl->pf_memory_len = boundlen; 981 phdl->pf_mem_hole.start = phdl->pf_memory_base; 982 phdl->pf_mem_hole.len = pf_mem_request->ra_len; 983 phdl->pf_mem_hole.next = (hole_t *)NULL; 984 985 DEBUG2("AP requested [0x%llx], needs [0x%llx] bytes of PF memory\n", 986 boundlen, pf_mem_request->ra_len); 987 988 DEBUG2("MEMORY BASE = [0x%lx] length [0x%lx]\n", 989 phdl->memory_base, phdl->memory_len); 990 DEBUG2("IO BASE = [0x%x] length [0x%x]\n", 991 phdl->io_base, phdl->io_len); 992 DEBUG2("PF MEMORY BASE = [0x%lx] length [0x%lx]\n", 993 phdl->pf_memory_base, phdl->pf_memory_len); 994 995 return (PCICFG_SUCCESS); 996 } 997 998 static int 999 pcicfg_ntbridge_configure_done(dev_info_t *dip) 1000 { 1001 ppb_ranges_t range[PCICFG_RANGE_LEN]; 1002 pcicfg_phdl_t *entry; 1003 uint_t len; 1004 pci_bus_range_t bus_range; 1005 int new_bus_range[2]; 1006 1007 DEBUG1("Configuring children for %p\n", dip); 1008 1009 entry = pcicfg_find_phdl(dip); 1010 ASSERT(entry); 1011 1012 bzero((caddr_t)range, 1013 sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 1014 range[1].child_high = range[1].parent_high |= 1015 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1016 range[1].child_low = range[1].parent_low = (uint32_t)entry->memory_base; 1017 1018 range[0].child_high = range[0].parent_high |= 1019 (PCI_REG_REL_M | PCI_ADDR_IO); 1020 range[0].child_low = range[0].parent_low = (uint32_t)entry->io_base; 1021 1022 range[2].child_high = range[2].parent_high |= 1023 (PCI_REG_REL_M | PCI_ADDR_MEM32 | PCI_REG_PF_M); 1024 range[2].child_low = range[2].parent_low = 1025 (uint32_t)entry->pf_memory_base; 1026 1027 len = sizeof (pci_bus_range_t); 1028 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1029 "bus-range", (caddr_t)&bus_range, (int *)&len) != DDI_SUCCESS) { 1030 DEBUG0("no bus-range property\n"); 1031 return (PCICFG_FAILURE); 1032 } 1033 1034 new_bus_range[0] = bus_range.lo; /* primary bus number */ 1035 if (entry->highest_bus) { /* secondary bus number */ 1036 if (entry->highest_bus < bus_range.lo) { 1037 cmn_err(CE_WARN, 1038 "ntbridge bus range invalid !(%d,%d)\n", 1039 bus_range.lo, entry->highest_bus); 1040 new_bus_range[1] = bus_range.lo + entry->highest_bus; 1041 } 1042 else 1043 new_bus_range[1] = entry->highest_bus; 1044 } 1045 else 1046 new_bus_range[1] = bus_range.hi; 1047 1048 DEBUG2("ntbridge: bus range lo=%x, hi=%x\n", 1049 new_bus_range[0], new_bus_range[1]); 1050 1051 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1052 "bus-range", new_bus_range, 2) != DDI_SUCCESS) { 1053 DEBUG0("Failed to set bus-range property"); 1054 entry->error = PCICFG_FAILURE; 1055 return (PCICFG_FAILURE); 1056 } 1057 1058 #ifdef DEBUG 1059 { 1060 uint64_t unused; 1061 unused = pcicfg_unused_space(&entry->io_hole, &len); 1062 DEBUG2("ntbridge: Unused IO space %llx bytes over %d holes\n", 1063 unused, len); 1064 } 1065 #endif 1066 1067 range[0].size_low = entry->io_len; 1068 if (pcicfg_update_ranges_prop(dip, &range[0])) { 1069 DEBUG0("Failed to update ranges (i/o)\n"); 1070 entry->error = PCICFG_FAILURE; 1071 return (PCICFG_FAILURE); 1072 } 1073 1074 #ifdef DEBUG 1075 { 1076 uint64_t unused; 1077 unused = pcicfg_unused_space(&entry->mem_hole, &len); 1078 DEBUG2("ntbridge: Unused Mem space %llx bytes over %d holes\n", 1079 unused, len); 1080 } 1081 #endif 1082 1083 range[1].size_low = entry->memory_len; 1084 if (pcicfg_update_ranges_prop(dip, &range[1])) { 1085 DEBUG0("Failed to update ranges (memory)\n"); 1086 entry->error = PCICFG_FAILURE; 1087 return (PCICFG_FAILURE); 1088 } 1089 1090 #ifdef DEBUG 1091 { 1092 uint64_t unused; 1093 unused = pcicfg_unused_space(&entry->pf_mem_hole, &len); 1094 DEBUG2("ntbridge: Unused PF Mem space %llx bytes over" 1095 " %d holes\n", unused, len); 1096 } 1097 #endif 1098 1099 range[2].size_low = entry->pf_memory_len; 1100 if (pcicfg_update_ranges_prop(dip, &range[2])) { 1101 DEBUG0("Failed to update ranges (PF memory)\n"); 1102 entry->error = PCICFG_FAILURE; 1103 return (PCICFG_FAILURE); 1104 } 1105 1106 return (PCICFG_SUCCESS); 1107 } 1108 1109 static int 1110 pcicfg_ntbridge_program_child(dev_info_t *dip) 1111 { 1112 pcicfg_phdl_t *entry; 1113 int rc = PCICFG_SUCCESS; 1114 dev_info_t *anode = dip; 1115 1116 /* Find the attachment point node */ 1117 while ((anode != NULL) && (strcmp(ddi_binding_name(anode), 1118 "hp_attachment") != 0)) { 1119 anode = ddi_get_parent(anode); 1120 } 1121 1122 if (anode == NULL) { 1123 DEBUG0("ntbridge child tree not in PROBE state\n"); 1124 return (PCICFG_FAILURE); 1125 } 1126 entry = pcicfg_find_phdl(ddi_get_parent(anode)); 1127 ASSERT(entry); 1128 1129 if (pcicfg_bridge_assign(dip, entry) == DDI_WALK_TERMINATE) { 1130 cmn_err(CE_WARN, 1131 "ntbridge: Error assigning range for child %s\n", 1132 ddi_get_name(dip)); 1133 rc = PCICFG_FAILURE; 1134 } 1135 return (rc); 1136 } 1137 1138 static int 1139 pcicfg_ntbridge_unconfigure_child(dev_info_t *new_device, uint_t devno) 1140 { 1141 1142 dev_info_t *new_ntbridgechild; 1143 int len, bus; 1144 uint16_t vid; 1145 ddi_acc_handle_t config_handle; 1146 pci_bus_range_t pci_bus_range; 1147 1148 len = sizeof (pci_bus_range_t); 1149 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, new_device, DDI_PROP_DONTPASS, 1150 "bus-range", (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) { 1151 DEBUG0("no bus-range property\n"); 1152 return (PCICFG_FAILURE); 1153 } 1154 1155 bus = pci_bus_range.lo; /* primary bus number of this bus node */ 1156 1157 ndi_devi_alloc_sleep(new_device, DEVI_PSEUDO_NEXNAME, 1158 (pnode_t)DEVI_SID_NODEID, &new_ntbridgechild); 1159 1160 if (pcicfg_add_config_reg(new_ntbridgechild, bus, devno, 0) 1161 != DDI_PROP_SUCCESS) { 1162 cmn_err(CE_WARN, 1163 "Unconfigure: Failed to add conf reg prop for ntbridge " 1164 "child.\n"); 1165 (void) ndi_devi_free(new_ntbridgechild); 1166 return (PCICFG_FAILURE); 1167 } 1168 1169 if (pci_config_setup(new_ntbridgechild, &config_handle) 1170 != DDI_SUCCESS) { 1171 cmn_err(CE_WARN, 1172 "pcicfg: Cannot map ntbridge child %x\n", devno); 1173 (void) ndi_devi_free(new_ntbridgechild); 1174 return (PCICFG_FAILURE); 1175 } 1176 1177 /* 1178 * See if there is any PCI HW at this location 1179 * by reading the Vendor ID. If it returns with 0xffff 1180 * then there is no hardware at this location. 1181 */ 1182 vid = pci_config_get16(config_handle, PCI_CONF_VENID); 1183 1184 pci_config_teardown(&config_handle); 1185 (void) ndi_devi_free(new_ntbridgechild); 1186 if (vid == 0xffff) 1187 return (PCICFG_NODEVICE); 1188 1189 return (pcicfg_unconfigure(new_device, devno)); 1190 } 1191 1192 static uint_t 1193 pcicfg_ntbridge_unconfigure(dev_info_t *dip) 1194 { 1195 pcicfg_phdl_t *entry = pcicfg_find_phdl(dip); 1196 uint_t *bus; 1197 int k, rc = DDI_FAILURE; 1198 1199 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1200 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 1201 &k) != DDI_PROP_SUCCESS) { 1202 DEBUG0("ntbridge: Failed to read bus-range property\n"); 1203 return (rc); 1204 } 1205 1206 DEBUG2("ntbridge: Need to free bus [%d] range [%d]\n", 1207 bus[0], bus[1] - bus[0] + 1); 1208 1209 if (ndi_ra_free(ddi_get_parent(dip), 1210 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), 1211 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 1212 DEBUG0("ntbridge: Failed to free a bus number\n"); 1213 kmem_free(bus, k); 1214 return (rc); 1215 } 1216 1217 /* 1218 * Since our resources will be freed at the parent level, 1219 * just reset these values. 1220 */ 1221 entry->memory_len = 0; 1222 entry->io_len = 0; 1223 entry->pf_memory_len = 0; 1224 1225 kmem_free(bus, k); 1226 1227 /* the following will also free hole data. */ 1228 return (pcicfg_destroy_phdl(dip)); 1229 1230 } 1231 1232 static int 1233 pcicfg_is_ntbridge(dev_info_t *dip) 1234 { 1235 ddi_acc_handle_t config_handle; 1236 uint8_t class, subclass; 1237 int rc = DDI_SUCCESS; 1238 1239 if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) { 1240 cmn_err(CE_WARN, 1241 "pcicfg: cannot map config space, to get map type\n"); 1242 return (DDI_FAILURE); 1243 } 1244 class = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 1245 subclass = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 1246 1247 /* check for class=6, subclass=9, for non transparent bridges. */ 1248 if ((class != PCI_CLASS_BRIDGE) || (subclass != PCI_BRIDGE_STBRIDGE)) 1249 rc = DDI_FAILURE; 1250 1251 DEBUG3("pcicfg: checking device %x,%x for indirect map. rc=%d\n", 1252 pci_config_get16(config_handle, PCI_CONF_VENID), 1253 pci_config_get16(config_handle, PCI_CONF_DEVID), 1254 rc); 1255 pci_config_teardown(&config_handle); 1256 return (rc); 1257 } 1258 1259 static uint_t 1260 pcicfg_ntbridge_child(dev_info_t *dip) 1261 { 1262 int len, val, rc = DDI_FAILURE; 1263 dev_info_t *anode = dip; 1264 1265 /* 1266 * Find the attachment point node 1267 */ 1268 while ((anode != NULL) && (strcmp(ddi_binding_name(anode), 1269 "hp_attachment") != 0)) { 1270 anode = ddi_get_parent(anode); 1271 } 1272 1273 if (anode == NULL) { 1274 DEBUG0("ntbridge child tree not in PROBE state\n"); 1275 return (rc); 1276 } 1277 len = sizeof (int); 1278 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(anode), 1279 DDI_PROP_DONTPASS, PCI_DEV_CONF_MAP_PROP, (caddr_t)&val, 1280 &len) != DDI_SUCCESS) { 1281 1282 DEBUG1("ntbridge child: no \"%s\" property\n", 1283 PCI_DEV_CONF_MAP_PROP); 1284 return (rc); 1285 } 1286 DEBUG0("ntbridge child: success\n"); 1287 return (DDI_SUCCESS); 1288 } 1289 1290 static uint_t 1291 pcicfg_get_ntbridge_child_range(dev_info_t *dip, uint64_t *boundbase, 1292 uint64_t *boundlen, uint_t space_type) 1293 { 1294 int length, found = DDI_FAILURE, acount, i, ibridge; 1295 pci_regspec_t *assigned; 1296 1297 if ((ibridge = pcicfg_is_ntbridge(dip)) == DDI_FAILURE) 1298 return (found); 1299 1300 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1301 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, 1302 &length) != DDI_PROP_SUCCESS) { 1303 DEBUG1("Failed to get assigned-addresses property %llx\n", dip); 1304 return (found); 1305 } 1306 DEBUG1("pcicfg: ntbridge child range: dip = %s\n", 1307 ddi_driver_name(dip)); 1308 1309 acount = length / sizeof (pci_regspec_t); 1310 1311 for (i = 0; i < acount; i++) { 1312 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) 1313 == pcicfg_indirect_map_devs[ibridge].mem_range_bar_offset) && 1314 (space_type == PCI_BASE_SPACE_MEM)) { 1315 found = DDI_SUCCESS; 1316 break; 1317 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) 1318 == pcicfg_indirect_map_devs[ibridge].io_range_bar_offset) && 1319 (space_type == PCI_BASE_SPACE_IO)) { 1320 found = DDI_SUCCESS; 1321 break; 1322 } else { 1323 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == 1324 pcicfg_indirect_map_devs[ibridge]. 1325 prefetch_mem_range_bar_offset) && 1326 (space_type == (PCI_BASE_SPACE_MEM | 1327 PCI_BASE_PREF_M))) { 1328 found = DDI_SUCCESS; 1329 break; 1330 } 1331 } 1332 } 1333 DEBUG3("pcicfg: ntbridge child range: space=%x, base=%lx, len=%lx\n", 1334 space_type, assigned[i].pci_phys_low, assigned[i].pci_size_low); 1335 1336 if (found == DDI_SUCCESS) { 1337 *boundbase = assigned[i].pci_phys_low; 1338 *boundlen = assigned[i].pci_size_low; 1339 } 1340 1341 kmem_free(assigned, length); 1342 return (found); 1343 } 1344 1345 /* 1346 * This will turn resources allocated by pcicfg_configure() 1347 * and remove the device tree from the attachment point 1348 * and below. The routine assumes the devices have their 1349 * drivers detached. 1350 */ 1351 int 1352 pcicfg_unconfigure(dev_info_t *devi, uint_t device) 1353 { 1354 dev_info_t *child_dip; 1355 int func; 1356 int i; 1357 1358 /* 1359 * Cycle through devices to make sure none are busy. 1360 * If a single device is busy fail the whole unconfigure. 1361 */ 1362 for (func = 0; func < PCI_MAX_FUNCTIONS; func++) { 1363 if ((child_dip = pcicfg_devi_find(devi, device, func)) == NULL) 1364 continue; 1365 1366 if (ndi_devi_offline(child_dip, NDI_UNCONFIG) == NDI_SUCCESS) 1367 continue; 1368 /* 1369 * Device function is busy. Before returning we have to 1370 * put all functions back online which were taken 1371 * offline during the process. 1372 */ 1373 DEBUG2("Device [0x%x] function [0x%x] is busy\n", device, func); 1374 for (i = 0; i < func; i++) { 1375 if ((child_dip = pcicfg_devi_find(devi, device, i)) 1376 == NULL) { 1377 DEBUG0("No more devices to put back on line!!\n"); 1378 /* 1379 * Made it through all functions 1380 */ 1381 continue; 1382 } 1383 if (ndi_devi_online(child_dip, NDI_CONFIG) != NDI_SUCCESS) { 1384 DEBUG0("Failed to put back devices state\n"); 1385 return (PCICFG_FAILURE); 1386 } 1387 } 1388 return (PCICFG_FAILURE); 1389 } 1390 1391 /* 1392 * Now, tear down all devinfo nodes for this AP. 1393 */ 1394 for (func = 0; func < PCI_MAX_FUNCTIONS; func++) { 1395 if ((child_dip = pcicfg_devi_find(devi, 1396 device, func)) == NULL) { 1397 DEBUG2("No device at %x,%x\n", device, func); 1398 continue; 1399 } 1400 1401 DEBUG2("Tearing down device [0x%x] function [0x%x]\n", 1402 device, func); 1403 1404 if (pcicfg_is_ntbridge(child_dip) != DDI_FAILURE) 1405 if (pcicfg_ntbridge_unconfigure(child_dip) != 1406 PCICFG_SUCCESS) { 1407 cmn_err(CE_WARN, 1408 "ntbridge: unconfigure failed\n"); 1409 return (PCICFG_FAILURE); 1410 } 1411 1412 if (pcicfg_teardown_device(child_dip) != PCICFG_SUCCESS) { 1413 DEBUG2("Failed to tear down device [0x%x]" 1414 "function [0x%x]\n", 1415 device, func); 1416 return (PCICFG_FAILURE); 1417 } 1418 } 1419 return (PCICFG_SUCCESS); 1420 } 1421 1422 static int 1423 pcicfg_teardown_device(dev_info_t *dip) 1424 { 1425 ddi_acc_handle_t handle; 1426 1427 /* 1428 * Free up resources associated with 'dip' 1429 */ 1430 1431 if (pcicfg_free_resources(dip) != PCICFG_SUCCESS) { 1432 DEBUG0("Failed to free resources\n"); 1433 return (PCICFG_FAILURE); 1434 } 1435 1436 /* 1437 * disable the device 1438 */ 1439 if (pcicfg_config_setup(dip, &handle) != PCICFG_SUCCESS) 1440 return (PCICFG_FAILURE); 1441 pcicfg_device_off(handle); 1442 pcicfg_config_teardown(&handle); 1443 1444 /* 1445 * The framework provides this routine which can 1446 * tear down a sub-tree. 1447 */ 1448 if (ndi_devi_offline(dip, NDI_DEVI_REMOVE) != NDI_SUCCESS) { 1449 DEBUG0("Failed to offline and remove node\n"); 1450 return (PCICFG_FAILURE); 1451 } 1452 1453 return (PCICFG_SUCCESS); 1454 } 1455 1456 /* 1457 * BEGIN GENERIC SUPPORT ROUTINES 1458 */ 1459 static pcicfg_phdl_t * 1460 pcicfg_find_phdl(dev_info_t *dip) 1461 { 1462 pcicfg_phdl_t *entry; 1463 mutex_enter(&pcicfg_list_mutex); 1464 for (entry = pcicfg_phdl_list; entry != NULL; entry = entry->next) { 1465 if (entry->dip == dip) { 1466 mutex_exit(&pcicfg_list_mutex); 1467 return (entry); 1468 } 1469 } 1470 mutex_exit(&pcicfg_list_mutex); 1471 1472 /* 1473 * Did'nt find entry - create one 1474 */ 1475 return (pcicfg_create_phdl(dip)); 1476 } 1477 1478 static pcicfg_phdl_t * 1479 pcicfg_create_phdl(dev_info_t *dip) 1480 { 1481 pcicfg_phdl_t *new; 1482 1483 new = (pcicfg_phdl_t *)kmem_zalloc(sizeof (pcicfg_phdl_t), 1484 KM_SLEEP); 1485 1486 new->dip = dip; 1487 mutex_enter(&pcicfg_list_mutex); 1488 new->next = pcicfg_phdl_list; 1489 pcicfg_phdl_list = new; 1490 mutex_exit(&pcicfg_list_mutex); 1491 1492 return (new); 1493 } 1494 1495 static int 1496 pcicfg_destroy_phdl(dev_info_t *dip) 1497 { 1498 pcicfg_phdl_t *entry; 1499 pcicfg_phdl_t *follow = NULL; 1500 1501 mutex_enter(&pcicfg_list_mutex); 1502 for (entry = pcicfg_phdl_list; entry != NULL; follow = entry, 1503 entry = entry->next) { 1504 if (entry->dip == dip) { 1505 if (entry == pcicfg_phdl_list) { 1506 pcicfg_phdl_list = entry->next; 1507 } else { 1508 follow->next = entry->next; 1509 } 1510 /* 1511 * If this entry has any allocated memory 1512 * or IO space associated with it, that 1513 * must be freed up. 1514 */ 1515 if (entry->memory_len > 0) { 1516 (void) ndi_ra_free(ddi_get_parent(dip), 1517 entry->memory_base, 1518 entry->memory_len, 1519 NDI_RA_TYPE_MEM, NDI_RA_PASS); 1520 } 1521 pcicfg_free_hole(&entry->mem_hole); 1522 1523 if (entry->io_len > 0) { 1524 (void) ndi_ra_free(ddi_get_parent(dip), 1525 entry->io_base, 1526 entry->io_len, 1527 NDI_RA_TYPE_IO, NDI_RA_PASS); 1528 } 1529 pcicfg_free_hole(&entry->io_hole); 1530 1531 if (entry->pf_memory_len > 0) { 1532 (void) ndi_ra_free(ddi_get_parent(dip), 1533 entry->pf_memory_base, 1534 entry->pf_memory_len, 1535 NDI_RA_TYPE_PCI_PREFETCH_MEM, 1536 NDI_RA_PASS); 1537 } 1538 pcicfg_free_hole(&entry->pf_mem_hole); 1539 1540 /* 1541 * Destroy this entry 1542 */ 1543 kmem_free((caddr_t)entry, sizeof (pcicfg_phdl_t)); 1544 mutex_exit(&pcicfg_list_mutex); 1545 return (PCICFG_SUCCESS); 1546 } 1547 } 1548 mutex_exit(&pcicfg_list_mutex); 1549 /* 1550 * Did'nt find the entry 1551 */ 1552 return (PCICFG_FAILURE); 1553 } 1554 1555 static int 1556 pcicfg_bridge_assign(dev_info_t *dip, void *hdl) 1557 { 1558 ddi_acc_handle_t handle; 1559 pci_regspec_t *reg; 1560 int length; 1561 int rcount; 1562 int i; 1563 int offset; 1564 uint64_t mem_answer; 1565 uint32_t io_answer; 1566 int count; 1567 uint8_t header_type; 1568 ppb_ranges_t range[PCICFG_RANGE_LEN]; 1569 int bus_range[2]; 1570 uint64_t mem_residual; 1571 uint64_t pf_mem_residual; 1572 uint64_t io_residual; 1573 1574 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 1575 1576 DEBUG1("bridge assign: assigning addresses to %s\n", 1577 ddi_get_name(dip)); 1578 1579 entry->error = PCICFG_SUCCESS; 1580 1581 if (entry == NULL) { 1582 DEBUG0("Failed to get entry\n"); 1583 entry->error = PCICFG_FAILURE; 1584 return (DDI_WALK_TERMINATE); 1585 } 1586 1587 if (pcicfg_config_setup(dip, &handle) 1588 != DDI_SUCCESS) { 1589 DEBUG0("Failed to map config space!\n"); 1590 entry->error = PCICFG_FAILURE; 1591 return (DDI_WALK_TERMINATE); 1592 } 1593 1594 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1595 1596 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 1597 1598 bzero((caddr_t)range, 1599 sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 1600 1601 (void) pcicfg_setup_bridge(entry, handle); 1602 1603 range[0].child_high = range[0].parent_high |= 1604 (PCI_REG_REL_M | PCI_ADDR_IO); 1605 range[0].child_low = range[0].parent_low = 1606 entry->io_last; 1607 range[1].child_high = range[1].parent_high |= 1608 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1609 range[1].child_low = range[1].parent_low = 1610 entry->memory_last; 1611 range[2].child_high = range[2].parent_high |= 1612 (PCI_REG_REL_M | PCI_ADDR_MEM32 | PCI_REG_PF_M); 1613 range[2].child_low = range[2].parent_low = 1614 entry->pf_memory_last; 1615 1616 ndi_devi_enter(dip, &count); 1617 ddi_walk_devs(ddi_get_child(dip), 1618 pcicfg_bridge_assign, (void *)entry); 1619 ndi_devi_exit(dip, count); 1620 1621 (void) pcicfg_update_bridge(entry, handle); 1622 1623 bus_range[0] = pci_config_get8(handle, PCI_BCNF_SECBUS); 1624 bus_range[1] = pci_config_get8(handle, PCI_BCNF_SUBBUS); 1625 1626 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1627 "bus-range", bus_range, 2) != DDI_SUCCESS) { 1628 DEBUG0("Failed to set bus-range property"); 1629 entry->error = PCICFG_FAILURE; 1630 return (DDI_WALK_TERMINATE); 1631 } 1632 1633 /* 1634 * Put back memory and I/O space not allocated 1635 * under the bridge. 1636 */ 1637 mem_residual = entry->memory_len - 1638 (entry->memory_last - entry->memory_base); 1639 if (mem_residual > 0) { 1640 (void) ndi_ra_free(ddi_get_parent(dip), 1641 entry->memory_last, 1642 mem_residual, 1643 NDI_RA_TYPE_MEM, NDI_RA_PASS); 1644 } 1645 1646 io_residual = entry->io_len - 1647 (entry->io_last - entry->io_base); 1648 if (io_residual > 0) { 1649 (void) ndi_ra_free(ddi_get_parent(dip), 1650 entry->io_last, 1651 io_residual, 1652 NDI_RA_TYPE_IO, NDI_RA_PASS); 1653 } 1654 1655 pf_mem_residual = entry->pf_memory_len - 1656 (entry->pf_memory_last - entry->pf_memory_base); 1657 if (pf_mem_residual > 0) { 1658 (void) ndi_ra_free(ddi_get_parent(dip), 1659 entry->pf_memory_last, 1660 pf_mem_residual, 1661 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 1662 } 1663 1664 if (entry->io_len > 0) { 1665 range[0].size_low = entry->io_last - entry->io_base; 1666 if (pcicfg_update_ranges_prop(dip, &range[0])) { 1667 DEBUG0("Failed to update ranges (i/o)\n"); 1668 entry->error = PCICFG_FAILURE; 1669 return (DDI_WALK_TERMINATE); 1670 } 1671 } 1672 if (entry->memory_len > 0) { 1673 range[1].size_low = 1674 entry->memory_last - entry->memory_base; 1675 if (pcicfg_update_ranges_prop(dip, &range[1])) { 1676 DEBUG0("Failed to update ranges (memory)\n"); 1677 entry->error = PCICFG_FAILURE; 1678 return (DDI_WALK_TERMINATE); 1679 } 1680 } 1681 if (entry->pf_memory_len > 0) { 1682 range[2].size_low = 1683 entry->pf_memory_last - entry->pf_memory_base; 1684 if (pcicfg_update_ranges_prop(dip, &range[2])) { 1685 DEBUG0("Failed to update ranges (PF memory)\n"); 1686 entry->error = PCICFG_FAILURE; 1687 return (DDI_WALK_TERMINATE); 1688 } 1689 } 1690 1691 (void) pcicfg_device_on(handle); 1692 1693 PCICFG_DUMP_BRIDGE_CONFIG(handle); 1694 1695 return (DDI_WALK_PRUNECHILD); 1696 } 1697 1698 /* 1699 * If there is an interrupt pin set program 1700 * interrupt line with default values. 1701 */ 1702 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1703 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1704 } 1705 1706 /* 1707 * A single device (under a bridge). 1708 * For each "reg" property with a length, allocate memory 1709 * and program the base registers. 1710 */ 1711 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1712 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1713 &length) != DDI_PROP_SUCCESS) { 1714 DEBUG0("Failed to read reg property\n"); 1715 entry->error = PCICFG_FAILURE; 1716 return (DDI_WALK_TERMINATE); 1717 } 1718 1719 rcount = length / sizeof (pci_regspec_t); 1720 offset = PCI_CONF_BASE0; 1721 for (i = 0; i < rcount; i++) { 1722 if ((reg[i].pci_size_low != 0)|| 1723 (reg[i].pci_size_hi != 0)) { 1724 1725 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 1726 1727 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 1728 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 1729 1730 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 1731 /* allocate prefetchable memory */ 1732 pcicfg_get_pf_mem(entry, 1733 reg[i].pci_size_low, &mem_answer); 1734 } else { /* get non prefetchable memory */ 1735 pcicfg_get_mem(entry, 1736 reg[i].pci_size_low, &mem_answer); 1737 } 1738 pci_config_put64(handle, offset, mem_answer); 1739 DEBUG2("REGISTER off %x (64)LO ----> [0x%x]\n", 1740 offset, 1741 pci_config_get32(handle, offset)); 1742 DEBUG2("REGISTER off %x (64)HI ----> [0x%x]\n", 1743 offset + 4, 1744 pci_config_get32(handle, offset + 4)); 1745 1746 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1747 reg[i].pci_phys_low = PCICFG_LOADDR(mem_answer); 1748 reg[i].pci_phys_mid = 1749 PCICFG_HIADDR(mem_answer); 1750 break; 1751 1752 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 1753 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 1754 /* allocate prefetchable memory */ 1755 pcicfg_get_pf_mem(entry, 1756 reg[i].pci_size_low, &mem_answer); 1757 } else { 1758 /* get non prefetchable memory */ 1759 pcicfg_get_mem(entry, 1760 reg[i].pci_size_low, &mem_answer); 1761 } 1762 1763 pci_config_put32(handle, 1764 offset, (uint32_t)mem_answer); 1765 1766 DEBUG2("REGISTER off %x(32)LO ----> [0x%x]\n", 1767 offset, 1768 pci_config_get32(handle, offset)); 1769 1770 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1771 reg[i].pci_phys_low = (uint32_t)mem_answer; 1772 1773 break; 1774 case PCI_REG_ADDR_G(PCI_ADDR_IO): 1775 /* allocate I/O space from the allocator */ 1776 1777 (void) pcicfg_get_io(entry, 1778 reg[i].pci_size_low, &io_answer); 1779 pci_config_put32(handle, offset, io_answer); 1780 1781 DEBUG2("REGISTER off %x (I/O)LO ----> [0x%x]\n", 1782 offset, 1783 pci_config_get32(handle, offset)); 1784 1785 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1786 reg[i].pci_phys_low = io_answer; 1787 1788 break; 1789 default: 1790 DEBUG0("Unknown register type\n"); 1791 kmem_free(reg, length); 1792 (void) pcicfg_config_teardown(&handle); 1793 entry->error = PCICFG_FAILURE; 1794 return (DDI_WALK_TERMINATE); 1795 } /* switch */ 1796 1797 /* 1798 * Now that memory locations are assigned, 1799 * update the assigned address property. 1800 */ 1801 if (pcicfg_update_assigned_prop(dip, 1802 ®[i]) != PCICFG_SUCCESS) { 1803 kmem_free(reg, length); 1804 (void) pcicfg_config_teardown(&handle); 1805 entry->error = PCICFG_FAILURE; 1806 return (DDI_WALK_TERMINATE); 1807 } 1808 } 1809 } 1810 (void) pcicfg_device_on(handle); 1811 1812 PCICFG_DUMP_DEVICE_CONFIG(handle); 1813 1814 (void) pcicfg_config_teardown(&handle); 1815 kmem_free((caddr_t)reg, length); 1816 return (DDI_WALK_CONTINUE); 1817 } 1818 1819 static int 1820 pcicfg_device_assign(dev_info_t *dip) 1821 { 1822 ddi_acc_handle_t handle; 1823 pci_regspec_t *reg; 1824 int length; 1825 int rcount; 1826 int i; 1827 int offset; 1828 ndi_ra_request_t request; 1829 uint64_t answer; 1830 uint64_t alen; 1831 1832 1833 DEBUG1("%llx now under configuration\n", dip); 1834 1835 /* request.ra_len = PCICFG_ROUND_UP(request.ra_len, PCICFG_IOGRAN); */ 1836 if (pcicfg_ntbridge_child(dip) == DDI_SUCCESS) { 1837 1838 return (pcicfg_ntbridge_program_child(dip)); 1839 } 1840 /* 1841 * XXX Failure here should be noted 1842 */ 1843 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1844 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1845 &length) != DDI_PROP_SUCCESS) { 1846 DEBUG0("Failed to read reg property\n"); 1847 return (PCICFG_FAILURE); 1848 } 1849 1850 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 1851 DEBUG0("Failed to map config space!\n"); 1852 return (PCICFG_FAILURE); 1853 } 1854 1855 /* 1856 * A single device 1857 * 1858 * For each "reg" property with a length, allocate memory 1859 * and program the base registers. 1860 */ 1861 1862 /* 1863 * If there is an interrupt pin set program 1864 * interrupt line with default values. 1865 */ 1866 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1867 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1868 } 1869 1870 bzero((caddr_t)&request, sizeof (ndi_ra_request_t)); 1871 1872 /* 1873 * Note: Both non-prefetchable and prefetchable memory space 1874 * allocations are made within 32bit space. Currently, BIOSs 1875 * allocate device memory for PCI devices within the 32bit space 1876 * so this will not be a problem. 1877 */ 1878 request.ra_flags |= NDI_RA_ALIGN_SIZE | NDI_RA_ALLOC_BOUNDED; 1879 request.ra_boundbase = 0; 1880 request.ra_boundlen = PCICFG_4GIG_LIMIT; 1881 1882 rcount = length / sizeof (pci_regspec_t); 1883 offset = PCI_CONF_BASE0; 1884 for (i = 0; i < rcount; i++) { 1885 char *mem_type; 1886 1887 if ((reg[i].pci_size_low != 0)|| 1888 (reg[i].pci_size_hi != 0)) { 1889 1890 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 1891 request.ra_len = reg[i].pci_size_low; 1892 1893 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 1894 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 1895 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 1896 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 1897 } else { 1898 mem_type = NDI_RA_TYPE_MEM; 1899 } 1900 /* allocate memory space from the allocator */ 1901 if (ndi_ra_alloc(ddi_get_parent(dip), 1902 &request, &answer, &alen, 1903 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 1904 DEBUG0("Failed to allocate 64b mem\n"); 1905 kmem_free(reg, length); 1906 (void) pcicfg_config_teardown(&handle); 1907 return (PCICFG_FAILURE); 1908 } 1909 DEBUG3("64 addr = [0x%x.0x%x] len [0x%x]\n", 1910 PCICFG_HIADDR(answer), 1911 PCICFG_LOADDR(answer), 1912 alen); 1913 /* program the low word */ 1914 pci_config_put32(handle, 1915 offset, PCICFG_LOADDR(answer)); 1916 /* program the high word */ 1917 pci_config_put32(handle, offset + 4, 1918 PCICFG_HIADDR(answer)); 1919 1920 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1921 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 1922 reg[i].pci_phys_mid = PCICFG_HIADDR(answer); 1923 /* 1924 * currently support 32b address space 1925 * assignments only. 1926 */ 1927 reg[i].pci_phys_hi ^= PCI_ADDR_MEM64 ^ 1928 PCI_ADDR_MEM32; 1929 1930 offset += 8; 1931 break; 1932 1933 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 1934 if (reg[i].pci_phys_hi & PCI_REG_PF_M) 1935 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 1936 else 1937 mem_type = NDI_RA_TYPE_MEM; 1938 /* allocate memory space from the allocator */ 1939 if (ndi_ra_alloc(ddi_get_parent(dip), 1940 &request, &answer, &alen, 1941 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 1942 DEBUG0("Failed to allocate 32b mem\n"); 1943 kmem_free(reg, length); 1944 (void) pcicfg_config_teardown(&handle); 1945 return (PCICFG_FAILURE); 1946 } 1947 DEBUG3("32 addr = [0x%x.0x%x] len [0x%x]\n", 1948 PCICFG_HIADDR(answer), 1949 PCICFG_LOADDR(answer), 1950 alen); 1951 /* program the low word */ 1952 pci_config_put32(handle, 1953 offset, PCICFG_LOADDR(answer)); 1954 1955 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1956 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 1957 reg[i].pci_phys_mid = 0; 1958 1959 offset += 4; 1960 break; 1961 case PCI_REG_ADDR_G(PCI_ADDR_IO): 1962 /* allocate I/O space from the allocator */ 1963 if (ndi_ra_alloc(ddi_get_parent(dip), 1964 &request, &answer, &alen, 1965 NDI_RA_TYPE_IO, NDI_RA_PASS) 1966 != NDI_SUCCESS) { 1967 DEBUG0("Failed to allocate I/O\n"); 1968 kmem_free(reg, length); 1969 (void) pcicfg_config_teardown(&handle); 1970 return (PCICFG_FAILURE); 1971 } 1972 DEBUG3("I/O addr = [0x%x.0x%x] len [0x%x]\n", 1973 PCICFG_HIADDR(answer), 1974 PCICFG_LOADDR(answer), 1975 alen); 1976 pci_config_put32(handle, 1977 offset, PCICFG_LOADDR(answer)); 1978 1979 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1980 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 1981 1982 offset += 4; 1983 break; 1984 default: 1985 DEBUG0("Unknown register type\n"); 1986 kmem_free(reg, length); 1987 (void) pcicfg_config_teardown(&handle); 1988 return (PCICFG_FAILURE); 1989 } /* switch */ 1990 1991 /* 1992 * Now that memory locations are assigned, 1993 * update the assigned address property. 1994 */ 1995 1996 if (pcicfg_update_assigned_prop(dip, 1997 ®[i]) != PCICFG_SUCCESS) { 1998 kmem_free(reg, length); 1999 (void) pcicfg_config_teardown(&handle); 2000 return (PCICFG_FAILURE); 2001 } 2002 } 2003 } 2004 2005 (void) pcicfg_device_on(handle); 2006 kmem_free(reg, length); 2007 2008 PCICFG_DUMP_DEVICE_CONFIG(handle); 2009 2010 (void) pcicfg_config_teardown(&handle); 2011 return (PCICFG_SUCCESS); 2012 } 2013 2014 #ifdef DEBUG 2015 /* 2016 * This function is useful in debug mode, where we can measure how 2017 * much memory was wasted/unallocated in bridge device's domain. 2018 */ 2019 static uint64_t 2020 pcicfg_unused_space(hole_t *hole, uint32_t *hole_count) 2021 { 2022 uint64_t len = 0; 2023 uint32_t count = 0; 2024 2025 do { 2026 len += hole->len; 2027 hole = hole->next; 2028 count++; 2029 } while (hole); 2030 *hole_count = count; 2031 return (len); 2032 } 2033 #endif 2034 2035 /* 2036 * This function frees data structures that hold the hole information 2037 * which are allocated in pcicfg_alloc_hole(). This is not freeing 2038 * any memory allocated through NDI calls. 2039 */ 2040 static void 2041 pcicfg_free_hole(hole_t *addr_hole) 2042 { 2043 hole_t *nhole, *hole = addr_hole->next; 2044 2045 while (hole) { 2046 nhole = hole->next; 2047 kmem_free(hole, sizeof (hole_t)); 2048 hole = nhole; 2049 } 2050 } 2051 2052 static uint64_t 2053 pcicfg_alloc_hole(hole_t *addr_hole, uint64_t *alast, uint32_t length) 2054 { 2055 uint64_t actual_hole_start, ostart, olen; 2056 hole_t *hole = addr_hole, *thole, *nhole; 2057 2058 do { 2059 actual_hole_start = PCICFG_ROUND_UP(hole->start, length); 2060 if (((actual_hole_start - hole->start) + length) <= hole->len) { 2061 DEBUG3("hole found. start %llx, len %llx, req=0x%x\n", 2062 hole->start, hole->len, length); 2063 ostart = hole->start; 2064 olen = hole->len; 2065 /* current hole parameters adjust */ 2066 if ((actual_hole_start - hole->start) == 0) { 2067 hole->start += length; 2068 hole->len -= length; 2069 if (hole->start > *alast) 2070 *alast = hole->start; 2071 } else { 2072 hole->len = actual_hole_start - hole->start; 2073 nhole = (hole_t *)kmem_zalloc(sizeof (hole_t), 2074 KM_SLEEP); 2075 nhole->start = actual_hole_start + length; 2076 nhole->len = (ostart + olen) - nhole->start; 2077 nhole->next = NULL; 2078 thole = hole->next; 2079 hole->next = nhole; 2080 nhole->next = thole; 2081 if (nhole->start > *alast) 2082 *alast = nhole->start; 2083 DEBUG2("put new hole to %llx, %llx\n", 2084 nhole->start, nhole->len); 2085 } 2086 DEBUG2("adjust current hole to %llx, %llx\n", 2087 hole->start, hole->len); 2088 break; 2089 } 2090 actual_hole_start = 0; 2091 hole = hole->next; 2092 } while (hole); 2093 2094 DEBUG1("return hole at %llx\n", actual_hole_start); 2095 return (actual_hole_start); 2096 } 2097 2098 static void 2099 pcicfg_get_mem(pcicfg_phdl_t *entry, 2100 uint32_t length, uint64_t *ans) 2101 { 2102 uint64_t new_mem; 2103 2104 /* See if there is a hole, that can hold this request. */ 2105 new_mem = pcicfg_alloc_hole(&entry->mem_hole, &entry->memory_last, 2106 length); 2107 if (new_mem) { /* if non-zero, found a hole. */ 2108 if (ans != NULL) 2109 *ans = new_mem; 2110 } else 2111 cmn_err(CE_WARN, "No %u bytes memory window for %s\n", 2112 length, ddi_get_name(entry->dip)); 2113 } 2114 2115 static void 2116 pcicfg_get_io(pcicfg_phdl_t *entry, 2117 uint32_t length, uint32_t *ans) 2118 { 2119 uint32_t new_io; 2120 uint64_t io_last; 2121 2122 /* 2123 * See if there is a hole, that can hold this request. 2124 * Pass 64 bit parameters and then truncate to 32 bit. 2125 */ 2126 io_last = entry->io_last; 2127 new_io = (uint32_t)pcicfg_alloc_hole(&entry->io_hole, &io_last, length); 2128 if (new_io) { /* if non-zero, found a hole. */ 2129 entry->io_last = (uint32_t)io_last; 2130 if (ans != NULL) 2131 *ans = new_io; 2132 } else 2133 cmn_err(CE_WARN, "No %u bytes IO space window for %s\n", 2134 length, ddi_get_name(entry->dip)); 2135 } 2136 2137 static void 2138 pcicfg_get_pf_mem(pcicfg_phdl_t *entry, 2139 uint32_t length, uint64_t *ans) 2140 { 2141 uint64_t new_mem; 2142 2143 /* See if there is a hole, that can hold this request. */ 2144 new_mem = pcicfg_alloc_hole(&entry->pf_mem_hole, &entry->pf_memory_last, 2145 length); 2146 if (new_mem) { /* if non-zero, found a hole. */ 2147 if (ans != NULL) 2148 *ans = new_mem; 2149 } else 2150 cmn_err(CE_WARN, "No %u bytes PF memory window for %s\n", 2151 length, ddi_get_name(entry->dip)); 2152 } 2153 2154 static int 2155 pcicfg_sum_resources(dev_info_t *dip, void *hdl) 2156 { 2157 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 2158 pci_regspec_t *pci_rp; 2159 int length; 2160 int rcount; 2161 int i; 2162 ndi_ra_request_t *pf_mem_request; 2163 ndi_ra_request_t *mem_request; 2164 ndi_ra_request_t *io_request; 2165 uint8_t header_type; 2166 ddi_acc_handle_t handle; 2167 2168 entry->error = PCICFG_SUCCESS; 2169 2170 pf_mem_request = &entry->pf_mem_req; 2171 mem_request = &entry->mem_req; 2172 io_request = &entry->io_req; 2173 2174 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 2175 DEBUG0("Failed to map config space!\n"); 2176 entry->error = PCICFG_FAILURE; 2177 return (DDI_WALK_TERMINATE); 2178 } 2179 2180 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 2181 2182 /* 2183 * If its a bridge - just record the highest bus seen 2184 */ 2185 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 2186 2187 if (entry->highest_bus < pci_config_get8(handle, 2188 PCI_BCNF_SECBUS)) { 2189 entry->highest_bus = 2190 pci_config_get8(handle, PCI_BCNF_SECBUS); 2191 } 2192 (void) pcicfg_config_teardown(&handle); 2193 entry->error = PCICFG_FAILURE; 2194 return (DDI_WALK_CONTINUE); 2195 } else { 2196 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2197 DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp, 2198 &length) != DDI_PROP_SUCCESS) { 2199 /* 2200 * If one node in (the subtree of nodes) 2201 * doesn't have a "reg" property fail the 2202 * allocation. 2203 */ 2204 entry->memory_len = 0; 2205 entry->io_len = 0; 2206 entry->pf_memory_len = 0; 2207 entry->error = PCICFG_FAILURE; 2208 return (DDI_WALK_TERMINATE); 2209 } 2210 /* 2211 * For each "reg" property with a length, add that to the 2212 * total memory (or I/O) to allocate. 2213 */ 2214 rcount = length / sizeof (pci_regspec_t); 2215 2216 for (i = 0; i < rcount; i++) { 2217 2218 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { 2219 2220 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2221 if (pci_rp[i].pci_phys_hi & PCI_REG_PF_M) { 2222 pf_mem_request->ra_len = 2223 pci_rp[i].pci_size_low + 2224 PCICFG_ROUND_UP(pf_mem_request->ra_len, 2225 pci_rp[i].pci_size_low); 2226 DEBUG1("ADDING 32 --->0x%x\n", 2227 pci_rp[i].pci_size_low); 2228 } else { 2229 mem_request->ra_len = 2230 pci_rp[i].pci_size_low + 2231 PCICFG_ROUND_UP(mem_request->ra_len, 2232 pci_rp[i].pci_size_low); 2233 DEBUG1("ADDING 32 --->0x%x\n", 2234 pci_rp[i].pci_size_low); 2235 } 2236 2237 break; 2238 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2239 if (pci_rp[i].pci_phys_hi & PCI_REG_PF_M) { 2240 pf_mem_request->ra_len = 2241 pci_rp[i].pci_size_low + 2242 PCICFG_ROUND_UP(pf_mem_request->ra_len, 2243 pci_rp[i].pci_size_low); 2244 DEBUG1("ADDING 64 --->0x%x\n", 2245 pci_rp[i].pci_size_low); 2246 } else { 2247 mem_request->ra_len = 2248 pci_rp[i].pci_size_low + 2249 PCICFG_ROUND_UP(mem_request->ra_len, 2250 pci_rp[i].pci_size_low); 2251 DEBUG1("ADDING 64 --->0x%x\n", 2252 pci_rp[i].pci_size_low); 2253 } 2254 2255 break; 2256 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2257 io_request->ra_len = 2258 pci_rp[i].pci_size_low + 2259 PCICFG_ROUND_UP(io_request->ra_len, 2260 pci_rp[i].pci_size_low); 2261 DEBUG1("ADDING I/O --->0x%x\n", 2262 pci_rp[i].pci_size_low); 2263 break; 2264 default: 2265 /* Config space register - not included */ 2266 break; 2267 } 2268 } 2269 2270 /* 2271 * free the memory allocated by ddi_getlongprop 2272 */ 2273 kmem_free(pci_rp, length); 2274 2275 /* 2276 * continue the walk to the next sibling to sum memory 2277 */ 2278 2279 (void) pcicfg_config_teardown(&handle); 2280 2281 return (DDI_WALK_CONTINUE); 2282 } 2283 } 2284 2285 static int 2286 pcicfg_free_bridge_resources(dev_info_t *dip) 2287 { 2288 ppb_ranges_t *ranges; 2289 uint_t *bus; 2290 int k; 2291 int length; 2292 int i; 2293 2294 2295 if ((i = ddi_getlongprop(DDI_DEV_T_ANY, dip, 2296 DDI_PROP_DONTPASS, "ranges", (caddr_t)&ranges, 2297 &length)) != DDI_PROP_SUCCESS) { 2298 DEBUG0("Failed to read ranges property\n"); 2299 if (ddi_get_child(dip)) { 2300 cmn_err(CE_WARN, "No ranges property found for %s", 2301 ddi_get_name(dip)); 2302 /* 2303 * strictly speaking, we can check for children with 2304 * assigned-addresses but for now it is better to 2305 * be conservative and assume that if there are child 2306 * nodes, then they do consume PCI memory or IO 2307 * resources, Hence return failure. 2308 */ 2309 return (PCICFG_FAILURE); 2310 } 2311 length = 0; 2312 } 2313 2314 for (i = 0; i < length / sizeof (ppb_ranges_t); i++) { 2315 char *mem_type; 2316 2317 if (ranges[i].size_low != 0 || 2318 ranges[i].size_high != 0) { 2319 switch (ranges[i].parent_high & PCI_REG_ADDR_M) { 2320 case PCI_ADDR_IO: 2321 DEBUG2("Free I/O " 2322 "base/length = [0x%x]/[0x%x]\n", 2323 ranges[i].child_low, 2324 ranges[i].size_low); 2325 if (ndi_ra_free(ddi_get_parent(dip), 2326 (uint64_t)ranges[i].child_low, 2327 (uint64_t)ranges[i].size_low, 2328 NDI_RA_TYPE_IO, NDI_RA_PASS) 2329 != NDI_SUCCESS) { 2330 DEBUG0("Trouble freeing " 2331 "PCI i/o space\n"); 2332 kmem_free(ranges, length); 2333 return (PCICFG_FAILURE); 2334 } 2335 break; 2336 case PCI_ADDR_MEM32: 2337 case PCI_ADDR_MEM64: 2338 if (ranges[i].parent_high & PCI_REG_PF_M) { 2339 DEBUG3("Free PF Memory base/length" 2340 " = [0x%x.0x%x]/[0x%x]\n", 2341 ranges[i].child_mid, 2342 ranges[i].child_low, 2343 ranges[i].size_low) 2344 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2345 } else { 2346 DEBUG3("Free Memory base/length" 2347 " = [0x%x.0x%x]/[0x%x]\n", 2348 ranges[i].child_mid, 2349 ranges[i].child_low, 2350 ranges[i].size_low) 2351 mem_type = NDI_RA_TYPE_MEM; 2352 } 2353 if (ndi_ra_free(ddi_get_parent(dip), 2354 PCICFG_LADDR( 2355 ranges[i].child_low, 2356 ranges[i].child_mid), 2357 (uint64_t)ranges[i].size_low, 2358 mem_type, 2359 NDI_RA_PASS) != NDI_SUCCESS) { 2360 DEBUG0("Trouble freeing " 2361 "PCI memory space\n"); 2362 kmem_free(ranges, length); 2363 return (PCICFG_FAILURE); 2364 } 2365 break; 2366 default: 2367 DEBUG0("Unknown memory space\n"); 2368 break; 2369 } 2370 } 2371 } 2372 2373 if (length) 2374 kmem_free(ranges, length); 2375 2376 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2377 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 2378 &k) != DDI_PROP_SUCCESS) { 2379 DEBUG0("Failed to read bus-range property\n"); 2380 return (PCICFG_FAILURE); 2381 } 2382 2383 DEBUG2("Need to free bus [%d] range [%d]\n", 2384 bus[0], bus[1] - bus[0] + 1); 2385 2386 if (ndi_ra_free(ddi_get_parent(dip), 2387 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), 2388 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 2389 DEBUG0("Failed to free a bus number\n"); 2390 return (PCICFG_FAILURE); 2391 } 2392 return (PCICFG_SUCCESS); 2393 } 2394 2395 static int 2396 pcicfg_free_device_resources(dev_info_t *dip) 2397 { 2398 pci_regspec_t *assigned; 2399 2400 int length; 2401 int acount; 2402 int i; 2403 2404 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2405 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, 2406 &length) != DDI_PROP_SUCCESS) { 2407 DEBUG0("Failed to read assigned-addresses property\n"); 2408 return (PCICFG_FAILURE); 2409 } 2410 2411 /* 2412 * For each "assigned-addresses" property entry with a length, 2413 * call the memory allocation routines to return the 2414 * resource. 2415 */ 2416 acount = length / sizeof (pci_regspec_t); 2417 for (i = 0; i < acount; i++) { 2418 char *mem_type; 2419 2420 /* 2421 * Free the resource if the size of it is not zero. 2422 */ 2423 if ((assigned[i].pci_size_low != 0)|| 2424 (assigned[i].pci_size_hi != 0)) { 2425 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2426 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2427 /* 2428 * Check the assigned address for zero. 2429 * (Workaround for Devconf (x86) bug to 2430 * skip bogus entry for ROM base address 2431 * register. If the assigned address is 2432 * zero then ignore the entry 2433 * (see bugid 4281306)). 2434 */ 2435 if (assigned[i].pci_phys_low == 0) 2436 break; /* ignore the entry */ 2437 2438 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) 2439 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2440 else 2441 mem_type = NDI_RA_TYPE_MEM; 2442 2443 if (ndi_ra_free(ddi_get_parent(dip), 2444 (uint64_t)assigned[i].pci_phys_low, 2445 (uint64_t)assigned[i].pci_size_low, 2446 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 2447 DEBUG0("Trouble freeing " 2448 "PCI memory space\n"); 2449 return (PCICFG_FAILURE); 2450 } 2451 2452 DEBUG4("Returned 0x%x of 32 bit %s space" 2453 " @ 0x%x from register 0x%x\n", 2454 assigned[i].pci_size_low, 2455 mem_type, 2456 assigned[i].pci_phys_low, 2457 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2458 2459 break; 2460 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2461 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) 2462 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2463 else 2464 mem_type = NDI_RA_TYPE_MEM; 2465 2466 if (ndi_ra_free(ddi_get_parent(dip), 2467 PCICFG_LADDR(assigned[i].pci_phys_low, 2468 assigned[i].pci_phys_mid), 2469 (uint64_t)assigned[i].pci_size_low, 2470 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 2471 DEBUG0("Trouble freeing " 2472 "PCI memory space\n"); 2473 return (PCICFG_FAILURE); 2474 } 2475 2476 DEBUG5("Returned 0x%x of 64 bit %s space" 2477 " @ 0x%x.0x%x from register 0x%x\n", 2478 assigned[i].pci_size_low, 2479 mem_type, 2480 assigned[i].pci_phys_mid, 2481 assigned[i].pci_phys_low, 2482 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2483 2484 break; 2485 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2486 if (ndi_ra_free(ddi_get_parent(dip), 2487 (uint64_t)assigned[i].pci_phys_low, 2488 (uint64_t)assigned[i].pci_size_low, 2489 NDI_RA_TYPE_IO, NDI_RA_PASS) != NDI_SUCCESS) { 2490 DEBUG0("Trouble freeing " 2491 "PCI IO space\n"); 2492 return (PCICFG_FAILURE); 2493 } 2494 DEBUG3("Returned 0x%x of IO space @ 0x%x" 2495 " from register 0x%x\n", 2496 assigned[i].pci_size_low, 2497 assigned[i].pci_phys_low, 2498 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2499 break; 2500 default: 2501 DEBUG0("Unknown register type\n"); 2502 kmem_free(assigned, length); 2503 return (PCICFG_FAILURE); 2504 } /* switch */ 2505 } 2506 } 2507 kmem_free(assigned, length); 2508 return (PCICFG_SUCCESS); 2509 } 2510 2511 static int 2512 pcicfg_free_resources(dev_info_t *dip) 2513 { 2514 ddi_acc_handle_t handle; 2515 uint8_t header_type; 2516 2517 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 2518 DEBUG0("Failed to map config space!\n"); 2519 return (PCICFG_FAILURE); 2520 } 2521 2522 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 2523 2524 (void) pci_config_teardown(&handle); 2525 2526 /* 2527 * A different algorithm is used for bridges and leaf devices. 2528 */ 2529 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 2530 if (pcicfg_free_bridge_resources(dip) != PCICFG_SUCCESS) { 2531 DEBUG0("Failed freeing up bridge resources\n"); 2532 return (PCICFG_FAILURE); 2533 } 2534 } else { 2535 if (pcicfg_free_device_resources(dip) != PCICFG_SUCCESS) { 2536 DEBUG0("Failed freeing up device resources\n"); 2537 return (PCICFG_FAILURE); 2538 } 2539 } 2540 2541 return (PCICFG_SUCCESS); 2542 } 2543 2544 #ifndef _DONT_USE_1275_GENERIC_NAMES 2545 static char * 2546 pcicfg_get_class_name(uint32_t classcode) 2547 { 2548 struct pcicfg_name_entry *ptr; 2549 2550 for (ptr = &pcicfg_class_lookup[0]; ptr->name != NULL; ptr++) { 2551 if (ptr->class_code == classcode) { 2552 return (ptr->name); 2553 } 2554 } 2555 return (NULL); 2556 } 2557 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 2558 2559 static dev_info_t * 2560 pcicfg_devi_find(dev_info_t *dip, uint_t device, uint_t function) 2561 { 2562 struct pcicfg_find_ctrl ctrl; 2563 int count; 2564 2565 ctrl.device = device; 2566 ctrl.function = function; 2567 ctrl.dip = NULL; 2568 2569 ndi_devi_enter(dip, &count); 2570 ddi_walk_devs(ddi_get_child(dip), pcicfg_match_dev, (void *)&ctrl); 2571 ndi_devi_exit(dip, count); 2572 2573 return (ctrl.dip); 2574 } 2575 2576 static int 2577 pcicfg_match_dev(dev_info_t *dip, void *hdl) 2578 { 2579 struct pcicfg_find_ctrl *ctrl = (struct pcicfg_find_ctrl *)hdl; 2580 pci_regspec_t *pci_rp; 2581 int length; 2582 int pci_dev; 2583 int pci_func; 2584 2585 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 2586 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, 2587 (uint_t *)&length) != DDI_PROP_SUCCESS) { 2588 ctrl->dip = NULL; 2589 return (DDI_WALK_TERMINATE); 2590 } 2591 2592 /* get the PCI device address info */ 2593 pci_dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi); 2594 pci_func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); 2595 2596 /* 2597 * free the memory allocated by ddi_prop_lookup_int_array 2598 */ 2599 ddi_prop_free(pci_rp); 2600 2601 2602 if ((pci_dev == ctrl->device) && (pci_func == ctrl->function)) { 2603 /* found the match for the specified device address */ 2604 ctrl->dip = dip; 2605 return (DDI_WALK_TERMINATE); 2606 } 2607 2608 /* 2609 * continue the walk to the next sibling to look for a match. 2610 */ 2611 return (DDI_WALK_PRUNECHILD); 2612 } 2613 2614 static int 2615 pcicfg_update_assigned_prop(dev_info_t *dip, pci_regspec_t *newone) 2616 { 2617 int alen; 2618 pci_regspec_t *assigned; 2619 caddr_t newreg; 2620 uint_t status; 2621 2622 status = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2623 "assigned-addresses", (caddr_t)&assigned, &alen); 2624 switch (status) { 2625 case DDI_PROP_SUCCESS: 2626 break; 2627 case DDI_PROP_NO_MEMORY: 2628 DEBUG0("no memory for assigned-addresses property\n"); 2629 return (PCICFG_FAILURE); 2630 default: 2631 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2632 "assigned-addresses", (int *)newone, 2633 sizeof (*newone)/sizeof (int)); 2634 return (PCICFG_SUCCESS); 2635 } 2636 2637 /* 2638 * Allocate memory for the existing 2639 * assigned-addresses(s) plus one and then 2640 * build it. 2641 */ 2642 2643 newreg = kmem_zalloc(alen+sizeof (*newone), KM_SLEEP); 2644 2645 bcopy(assigned, newreg, alen); 2646 bcopy(newone, newreg + alen, sizeof (*newone)); 2647 2648 /* 2649 * Write out the new "assigned-addresses" spec 2650 */ 2651 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2652 "assigned-addresses", (int *)newreg, 2653 (alen + sizeof (*newone))/sizeof (int)); 2654 2655 kmem_free((caddr_t)newreg, alen+sizeof (*newone)); 2656 kmem_free(assigned, alen); 2657 2658 return (PCICFG_SUCCESS); 2659 } 2660 2661 static int 2662 pcicfg_update_ranges_prop(dev_info_t *dip, ppb_ranges_t *addition) 2663 { 2664 int rlen; 2665 ppb_ranges_t *ranges; 2666 caddr_t newreg; 2667 uint_t status; 2668 2669 status = ddi_getlongprop(DDI_DEV_T_ANY, 2670 dip, DDI_PROP_DONTPASS, "ranges", (caddr_t)&ranges, &rlen); 2671 2672 2673 switch (status) { 2674 case DDI_PROP_SUCCESS: 2675 break; 2676 case DDI_PROP_NO_MEMORY: 2677 DEBUG0("ranges present, but unable to get memory\n"); 2678 return (PCICFG_FAILURE); 2679 default: 2680 DEBUG0("no ranges property - creating one\n"); 2681 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 2682 dip, "ranges", (int *)addition, 2683 sizeof (ppb_ranges_t)/sizeof (int)) 2684 != DDI_SUCCESS) { 2685 DEBUG0("Did'nt create ranges property\n"); 2686 return (PCICFG_FAILURE); 2687 } 2688 return (PCICFG_SUCCESS); 2689 } 2690 2691 /* 2692 * Allocate memory for the existing ranges plus one and then 2693 * build it. 2694 */ 2695 newreg = kmem_zalloc(rlen+sizeof (ppb_ranges_t), KM_SLEEP); 2696 2697 bcopy(ranges, newreg, rlen); 2698 bcopy(addition, newreg + rlen, sizeof (ppb_ranges_t)); 2699 2700 /* 2701 * Write out the new "ranges" property 2702 */ 2703 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2704 dip, "ranges", (int *)newreg, 2705 (rlen + sizeof (ppb_ranges_t))/sizeof (int)); 2706 2707 DEBUG1("Updating ranges property for %d entries", 2708 rlen / sizeof (ppb_ranges_t) + 1); 2709 2710 kmem_free((caddr_t)newreg, rlen+sizeof (ppb_ranges_t)); 2711 2712 kmem_free((caddr_t)ranges, rlen); 2713 2714 return (PCICFG_SUCCESS); 2715 } 2716 2717 static int 2718 pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) 2719 { 2720 int rlen; 2721 pci_regspec_t *reg; 2722 caddr_t newreg; 2723 uint32_t hiword; 2724 pci_regspec_t addition; 2725 uint32_t size; 2726 uint_t status; 2727 2728 status = ddi_getlongprop(DDI_DEV_T_ANY, 2729 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 2730 2731 switch (status) { 2732 case DDI_PROP_SUCCESS: 2733 break; 2734 case DDI_PROP_NO_MEMORY: 2735 DEBUG0("reg present, but unable to get memory\n"); 2736 return (PCICFG_FAILURE); 2737 default: 2738 DEBUG0("no reg property\n"); 2739 return (PCICFG_FAILURE); 2740 } 2741 2742 /* 2743 * Allocate memory for the existing reg(s) plus one and then 2744 * build it. 2745 */ 2746 newreg = kmem_zalloc(rlen+sizeof (pci_regspec_t), KM_SLEEP); 2747 2748 /* 2749 * Build the regspec, then add it to the existing one(s) 2750 */ 2751 2752 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 2753 PCI_REG_DEV_G(reg->pci_phys_hi), 2754 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); 2755 2756 if (reg_offset == PCI_CONF_ROM) { 2757 size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1; 2758 hiword |= PCI_ADDR_MEM32; 2759 } else { 2760 size = (~(PCI_BASE_M_ADDR_M & regvalue))+1; 2761 2762 if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) { 2763 if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) { 2764 hiword |= PCI_ADDR_MEM32; 2765 } else if ((PCI_BASE_TYPE_M & regvalue) 2766 == PCI_BASE_TYPE_ALL) { 2767 hiword |= PCI_ADDR_MEM64; 2768 } 2769 if (regvalue & PCI_BASE_PREF_M) 2770 hiword |= PCI_REG_PF_M; 2771 } else { 2772 hiword |= PCI_ADDR_IO; 2773 } 2774 } 2775 2776 addition.pci_phys_hi = hiword; 2777 addition.pci_phys_mid = 0; 2778 addition.pci_phys_low = 0; 2779 addition.pci_size_hi = 0; 2780 addition.pci_size_low = size; 2781 2782 bcopy(reg, newreg, rlen); 2783 bcopy(&addition, newreg + rlen, sizeof (pci_regspec_t)); 2784 2785 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size); 2786 /* 2787 * Write out the new "reg" property 2788 */ 2789 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2790 dip, "reg", (int *)newreg, 2791 (rlen + sizeof (pci_regspec_t))/sizeof (int)); 2792 2793 kmem_free((caddr_t)newreg, rlen+sizeof (pci_regspec_t)); 2794 kmem_free((caddr_t)reg, rlen); 2795 2796 return (PCICFG_SUCCESS); 2797 } 2798 2799 static void 2800 pcicfg_device_on(ddi_acc_handle_t config_handle) 2801 { 2802 /* 2803 * Enable memory, IO, and bus mastership 2804 * XXX should we enable parity, SERR#, 2805 * fast back-to-back, and addr. stepping? 2806 */ 2807 pci_config_put16(config_handle, PCI_CONF_COMM, 2808 pci_config_get16(config_handle, PCI_CONF_COMM) | 0x7); 2809 } 2810 2811 static void 2812 pcicfg_device_off(ddi_acc_handle_t config_handle) 2813 { 2814 /* 2815 * Disable I/O and memory traffic through the bridge 2816 */ 2817 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); 2818 } 2819 2820 /* 2821 * Setup the basic 1275 properties based on information found in the config 2822 * header of the PCI device 2823 */ 2824 static int 2825 pcicfg_set_standard_props(dev_info_t *dip, ddi_acc_handle_t config_handle, 2826 uint8_t pcie_dev) 2827 { 2828 int ret, cap_id_loc; 2829 uint16_t val; 2830 uint32_t wordval; 2831 uint8_t byteval; 2832 2833 /* These two exists only for non-bridges */ 2834 if (((pci_config_get8(config_handle, PCI_CONF_HEADER) 2835 & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) && !pcie_dev) { 2836 byteval = pci_config_get8(config_handle, PCI_CONF_MIN_G); 2837 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2838 "min-grant", byteval)) != DDI_SUCCESS) { 2839 return (ret); 2840 } 2841 2842 byteval = pci_config_get8(config_handle, PCI_CONF_MAX_L); 2843 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2844 "max-latency", byteval)) != DDI_SUCCESS) { 2845 return (ret); 2846 } 2847 } 2848 2849 /* 2850 * These should always exist and have the value of the 2851 * corresponding register value 2852 */ 2853 val = pci_config_get16(config_handle, PCI_CONF_VENID); 2854 2855 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2856 "vendor-id", val)) != DDI_SUCCESS) { 2857 return (ret); 2858 } 2859 val = pci_config_get16(config_handle, PCI_CONF_DEVID); 2860 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2861 "device-id", val)) != DDI_SUCCESS) { 2862 return (ret); 2863 } 2864 byteval = pci_config_get8(config_handle, PCI_CONF_REVID); 2865 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2866 "revision-id", byteval)) != DDI_SUCCESS) { 2867 return (ret); 2868 } 2869 2870 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 2871 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 2872 2873 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2874 "class-code", wordval)) != DDI_SUCCESS) { 2875 return (ret); 2876 } 2877 val = (pci_config_get16(config_handle, 2878 PCI_CONF_STAT) & PCI_STAT_DEVSELT); 2879 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2880 "devsel-speed", val)) != DDI_SUCCESS) { 2881 return (ret); 2882 } 2883 2884 /* 2885 * The next three are bits set in the status register. The property is 2886 * present (but with no value other than its own existence) if the bit 2887 * is set, non-existent otherwise 2888 */ 2889 if ((!pcie_dev) && 2890 (pci_config_get16(config_handle, PCI_CONF_STAT) & 2891 PCI_STAT_FBBC)) { 2892 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2893 "fast-back-to-back", 0)) != DDI_SUCCESS) { 2894 return (ret); 2895 } 2896 } 2897 if ((!pcie_dev) && 2898 (pci_config_get16(config_handle, PCI_CONF_STAT) & 2899 PCI_STAT_66MHZ)) { 2900 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2901 "66mhz-capable", 0)) != DDI_SUCCESS) { 2902 return (ret); 2903 } 2904 } 2905 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_UDF) { 2906 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2907 "udf-supported", 0)) != DDI_SUCCESS) { 2908 return (ret); 2909 } 2910 } 2911 2912 /* 2913 * These next three are optional and are not present 2914 * if the corresponding register is zero. If the value 2915 * is non-zero then the property exists with the value 2916 * of the register. 2917 */ 2918 if ((val = pci_config_get16(config_handle, 2919 PCI_CONF_SUBVENID)) != 0) { 2920 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2921 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 2922 return (ret); 2923 } 2924 } 2925 if ((val = pci_config_get16(config_handle, 2926 PCI_CONF_SUBSYSID)) != 0) { 2927 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2928 "subsystem-id", val)) != DDI_SUCCESS) { 2929 return (ret); 2930 } 2931 } 2932 if ((val = pci_config_get16(config_handle, 2933 PCI_CONF_CACHE_LINESZ)) != 0) { 2934 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2935 "cache-line-size", val)) != DDI_SUCCESS) { 2936 return (ret); 2937 } 2938 } 2939 2940 /* 2941 * If the Interrupt Pin register is non-zero then the 2942 * interrupts property exists 2943 */ 2944 if ((byteval = pci_config_get8(config_handle, PCI_CONF_IPIN)) != 0) { 2945 /* 2946 * If interrupt pin is non-zero, 2947 * record the interrupt line used 2948 */ 2949 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2950 "interrupts", byteval)) != DDI_SUCCESS) { 2951 return (ret); 2952 } 2953 } 2954 if ((cap_id_loc = pcicfg_get_cap(config_handle, PCI_CAP_ID_MSI)) > 0) { 2955 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2956 "pci-msi-capid-pointer", cap_id_loc)) != DDI_SUCCESS) 2957 return (ret); 2958 } 2959 if ((cap_id_loc = pcicfg_get_cap(config_handle, PCI_CAP_ID_MSI_X)) > 2960 0) { 2961 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2962 "pci-msix-capid-pointer", cap_id_loc)) != DDI_SUCCESS) 2963 return (ret); 2964 } 2965 if ((cap_id_loc = pcicfg_get_cap(config_handle, PCI_CAP_ID_PCIX)) > 0) { 2966 /* create the pcix-capid-pointer property */ 2967 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2968 "pcix-capid-pointer", cap_id_loc)) != DDI_SUCCESS) 2969 return (ret); 2970 } 2971 if (pcie_dev && (cap_id_loc = pcicfg_get_cap(config_handle, 2972 PCI_CAP_ID_PCI_E)) > 0) { 2973 /* create the pcie-capid-pointer property */ 2974 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2975 "pcie-capid-pointer", cap_id_loc)) != DDI_SUCCESS) 2976 return (ret); 2977 val = pci_config_get16(config_handle, cap_id_loc + 2978 PCIE_PCIECAP) & PCIE_PCIECAP_SLOT_IMPL; 2979 /* if slot implemented, get physical slot number */ 2980 if (val) { 2981 wordval = pci_config_get32(config_handle, cap_id_loc + 2982 PCIE_SLOTCAP); 2983 /* create the slotcap-reg property */ 2984 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, 2985 dip, "pcie-slotcap-reg", wordval)) != DDI_SUCCESS) 2986 return (ret); 2987 /* create the property only if slotnum set correctly? */ 2988 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2989 "physical-slot#", PCIE_SLOTCAP_PHY_SLOT_NUM( 2990 wordval))) != DDI_SUCCESS) { 2991 return (ret); 2992 } 2993 } 2994 } 2995 2996 return (PCICFG_SUCCESS); 2997 } 2998 2999 static int 3000 pcicfg_set_busnode_props(dev_info_t *dip, uint8_t pcie_device_type) 3001 { 3002 int ret; 3003 char device_type[8]; 3004 3005 if (pcie_device_type) 3006 (void) strcpy(device_type, "pciex"); 3007 else 3008 (void) strcpy(device_type, "pci"); 3009 3010 if ((ret = ndi_prop_update_string(DDI_DEV_T_NONE, dip, 3011 "device_type", device_type)) != DDI_SUCCESS) { 3012 return (ret); 3013 } 3014 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3015 "#address-cells", 3)) != DDI_SUCCESS) { 3016 return (ret); 3017 } 3018 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3019 "#size-cells", 2)) != DDI_SUCCESS) { 3020 return (ret); 3021 } 3022 return (PCICFG_SUCCESS); 3023 } 3024 3025 static int 3026 pcicfg_set_childnode_props(dev_info_t *dip, ddi_acc_handle_t config_handle, 3027 uint8_t pcie_dev) 3028 { 3029 3030 int ret; 3031 char *name; 3032 char buffer[64], pprefix[8], nprefix[8]; 3033 uint16_t classcode; 3034 uint8_t revid, pif, pclass, psubclass; 3035 char *compat[24]; 3036 int i; 3037 int n; 3038 uint16_t sub_vid, sub_sid, vid, did; 3039 /* set the property prefix based on the device type */ 3040 if (pcie_dev) { 3041 (void) sprintf(pprefix, "pciex"); 3042 } else 3043 (void) sprintf(pprefix, "pci"); 3044 3045 /* set the prefix right for name property */ 3046 /* x86 platforms need to go with pci for upgrade purposes */ 3047 (void) sprintf(nprefix, "pci"); 3048 3049 /* 3050 * NOTE: These are for both a child and PCI-PCI bridge node 3051 */ 3052 sub_vid = pci_config_get16(config_handle, PCI_CONF_SUBVENID), 3053 sub_sid = pci_config_get16(config_handle, PCI_CONF_SUBSYSID); 3054 vid = pci_config_get16(config_handle, PCI_CONF_VENID), 3055 did = pci_config_get16(config_handle, PCI_CONF_DEVID); 3056 revid = pci_config_get8(config_handle, PCI_CONF_REVID); 3057 pif = pci_config_get8(config_handle, PCI_CONF_PROGCLASS); 3058 classcode = pci_config_get16(config_handle, PCI_CONF_SUBCLASS); 3059 pclass = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 3060 psubclass = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 3061 3062 if (!sub_sid) /* XXX - different from pcicfg.e */ 3063 (void) sprintf(buffer, "%s%x,%x", nprefix, vid, did); 3064 else 3065 (void) sprintf(buffer, "%s%x,%x", nprefix, sub_vid, sub_sid); 3066 3067 /* 3068 * In some environments, trying to use "generic" 1275 names is 3069 * not the convention. In those cases use the name as created 3070 * above. In all the rest of the cases, check to see if there 3071 * is a generic name first. 3072 */ 3073 #ifdef _DONT_USE_1275_GENERIC_NAMES 3074 name = buffer; 3075 #else 3076 if ((name = pcicfg_get_class_name(classcode)) == NULL) { 3077 /* 3078 * Set name to the above fabricated name 3079 */ 3080 name = buffer; 3081 } 3082 #endif 3083 3084 /* 3085 * The node name field needs to be filled in with the name 3086 */ 3087 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3088 DEBUG0("Failed to set nodename for node\n"); 3089 return (PCICFG_FAILURE); 3090 } 3091 3092 /* 3093 * Create the compatible property as an array of pointers 3094 * to strings. Start with the buffer created above. 3095 */ 3096 n = 0; 3097 3098 /* 3099 * Setup 'compatible' as per the PCI2.1 bindings document. 3100 * pci[ex]VVVV,DDDD.SSSS.ssss.RR 3101 * pci[ex]VVVV,DDDD.SSSS.ssss 3102 * pciSSSS.ssss -> not created for PCIe as per PCIe bindings 3103 * pci[ex]VVVV,DDDD.RR 3104 * pci[ex]VVVV,DDDD 3105 * pci[ex]class,CCSSPP 3106 * pci[ex]class,CCSS 3107 * Add legacy entries for compatibility with legacy devices and OS 3108 * for x86. 3109 * pciVVVV,DDDD.SSSS.ssss.RR 3110 * pciVVVV,DDDD.SSSS.ssss 3111 * pciSSSS.ssss 3112 * pciVVVV,DDDD.RR 3113 * pciVVVV,DDDD 3114 * pciclass,CCSSPP 3115 * pciclass,CCSS 3116 */ 3117 3118 do { 3119 /* pci[ex]VVVV,DDDD.SSSS.ssss.RR */ 3120 (void) sprintf(buffer, "%s%x,%x.%x.%x.%x", pprefix, vid, did, 3121 sub_vid, sub_sid, revid); 3122 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3123 (void) strcpy(compat[n++], buffer); 3124 3125 /* pci[ex]VVVV,DDDD.SSSS.ssss */ 3126 (void) sprintf(buffer, "%s%x,%x.%x.%x", pprefix, vid, did, 3127 sub_vid, sub_sid); 3128 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3129 (void) strcpy(compat[n++], buffer); 3130 3131 /* pciSSSS.ssss -> not created for PCIe as per PCIe bindings */ 3132 if (!pcie_dev && pcicfg_do_legacy_props) { 3133 (void) sprintf(buffer, "pci%x,%x", sub_vid, sub_sid); 3134 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3135 (void) strcpy(compat[n++], buffer); 3136 } 3137 3138 /* pci[ex]VVVV,DDDD.RR */ 3139 (void) sprintf(buffer, "%s%x,%x.%x", pprefix, vid, did, revid); 3140 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3141 (void) strcpy(compat[n++], buffer); 3142 3143 /* pci[ex]VVVV,DDDD */ 3144 (void) sprintf(buffer, "%s%x,%x", pprefix, vid, did); 3145 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3146 (void) strcpy(compat[n++], buffer); 3147 3148 /* pci[ex]class,CCSSPP */ 3149 (void) sprintf(buffer, "%sclass,%02x%02x%02x", pprefix, 3150 pclass, psubclass, pif); 3151 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3152 (void) strcpy(compat[n++], buffer); 3153 3154 /* pci[ex]class,CCSS */ 3155 (void) sprintf(buffer, "%sclass,%04x", pprefix, classcode); 3156 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3157 (void) strcpy(compat[n++], buffer); 3158 3159 if (!pcie_dev) 3160 break; 3161 3162 /* also add compatible names using "pci" prefix */ 3163 (void) sprintf(pprefix, "pci"); 3164 pcie_dev = 0; 3165 3166 } while (pcicfg_do_legacy_props); 3167 3168 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3169 "compatible", (char **)compat, n)) != DDI_SUCCESS) { 3170 return (ret); 3171 } 3172 3173 for (i = 0; i < n; i++) { 3174 kmem_free(compat[i], strlen(compat[i]) + 1); 3175 } 3176 3177 return (PCICFG_SUCCESS); 3178 } 3179 3180 /* 3181 * Program the bus numbers into the bridge 3182 */ 3183 static void 3184 pcicfg_set_bus_numbers(ddi_acc_handle_t config_handle, 3185 uint_t primary, uint_t secondary, uint_t subordinate) 3186 { 3187 DEBUG3("Setting bridge bus-range %d,%d,%d\n", primary, secondary, 3188 subordinate); 3189 /* 3190 * Primary bus# 3191 */ 3192 pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary); 3193 3194 /* 3195 * Secondary bus# 3196 */ 3197 pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary); 3198 3199 /* 3200 * Set the subordinate bus number to ff in order to pass through any 3201 * type 1 cycle with a bus number higher than the secondary bus# 3202 */ 3203 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, subordinate); 3204 } 3205 3206 /* 3207 * Put bridge registers into initial state 3208 */ 3209 static void 3210 pcicfg_setup_bridge(pcicfg_phdl_t *entry, 3211 ddi_acc_handle_t handle) 3212 { 3213 /* 3214 * The highest bus seen during probing is the max-subordinate bus 3215 */ 3216 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus); 3217 3218 /* 3219 * Reset the secondary bus 3220 */ 3221 pci_config_put16(handle, PCI_BCNF_BCNTRL, 3222 pci_config_get16(handle, PCI_BCNF_BCNTRL) | 0x40); 3223 drv_usecwait(1000); 3224 pci_config_put16(handle, PCI_BCNF_BCNTRL, 3225 pci_config_get16(handle, PCI_BCNF_BCNTRL) & ~0x40); 3226 drv_usecwait(1000); 3227 3228 /* 3229 * Program the memory base register with the 3230 * start of the memory range 3231 */ 3232 pci_config_put16(handle, PCI_BCNF_MEM_BASE, 3233 PCICFG_HIWORD(PCICFG_LOADDR(entry->memory_last))); 3234 3235 /* 3236 * Program the I/O base register with the start of the I/O range 3237 */ 3238 pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW, 3239 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(entry->io_last)))); 3240 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, 3241 PCICFG_HIWORD(PCICFG_LOADDR(entry->io_last))); 3242 3243 /* 3244 * Program the PF memory base register with the start of 3245 * PF memory range 3246 */ 3247 pci_config_put16(handle, PCI_BCNF_PF_BASE_LOW, 3248 PCICFG_HIWORD(PCICFG_LOADDR(entry->pf_memory_last))); 3249 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 3250 PCICFG_HIADDR(entry->pf_memory_last)); 3251 3252 /* 3253 * Clear status bits 3254 */ 3255 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); 3256 3257 /* 3258 * Needs to be set to this value 3259 */ 3260 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 3261 3262 /* 3263 * XXX - may be delay should be used since noone configures 3264 * devices in the interrupt context 3265 */ 3266 drv_usecwait(pcicfg_sec_reset_delay); /* 1 sec wait */ 3267 } 3268 3269 static void 3270 pcicfg_update_bridge(pcicfg_phdl_t *entry, 3271 ddi_acc_handle_t handle) 3272 { 3273 uint_t length; 3274 3275 /* 3276 * Program the memory limit register with the end of the memory range 3277 */ 3278 3279 DEBUG1("DOWN ROUNDED ===>[0x%x]\n", 3280 PCICFG_ROUND_DOWN(entry->memory_last, 3281 PCICFG_MEMGRAN)); 3282 3283 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, 3284 PCICFG_HIWORD(PCICFG_LOADDR( 3285 PCICFG_ROUND_DOWN(entry->memory_last, 3286 PCICFG_MEMGRAN)))); 3287 /* 3288 * Since this is a bridge, the rest of this range will 3289 * be responded to by the bridge. We have to round up 3290 * so no other device claims it. 3291 */ 3292 if ((length = (PCICFG_ROUND_UP(entry->memory_last, 3293 PCICFG_MEMGRAN) - entry->memory_last)) > 0) { 3294 (void) pcicfg_get_mem(entry, length, NULL); 3295 DEBUG1("Added [0x%x]at the top of " 3296 "the bridge (mem)\n", length); 3297 } 3298 3299 /* 3300 * Program the PF memory limit register with the end of the memory range 3301 */ 3302 3303 DEBUG1("DOWN ROUNDED ===>[0x%x]\n", 3304 PCICFG_ROUND_DOWN(entry->pf_memory_last, 3305 PCICFG_MEMGRAN)); 3306 3307 pci_config_put16(handle, PCI_BCNF_PF_LIMIT_LOW, 3308 PCICFG_HIWORD(PCICFG_LOADDR( 3309 PCICFG_ROUND_DOWN(entry->pf_memory_last, 3310 PCICFG_MEMGRAN)))); 3311 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, 3312 PCICFG_HIADDR( 3313 PCICFG_ROUND_DOWN(entry->pf_memory_last, 3314 PCICFG_MEMGRAN))); 3315 if ((length = (PCICFG_ROUND_UP(entry->pf_memory_last, 3316 PCICFG_MEMGRAN) - entry->pf_memory_last)) > 0) { 3317 (void) pcicfg_get_pf_mem(entry, length, NULL); 3318 DEBUG1("Added [0x%x]at the top of " 3319 "the bridge (PF mem)\n", length); 3320 } 3321 3322 /* 3323 * Program the I/O limit register with the end of the I/O range 3324 */ 3325 pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW, 3326 PCICFG_HIBYTE(PCICFG_LOWORD( 3327 PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last, 3328 PCICFG_IOGRAN))))); 3329 3330 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, 3331 PCICFG_HIWORD(PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last, 3332 PCICFG_IOGRAN)))); 3333 3334 /* 3335 * Same as above for I/O space. Since this is a 3336 * bridge, the rest of this range will be responded 3337 * to by the bridge. We have to round up so no 3338 * other device claims it. 3339 */ 3340 if ((length = (PCICFG_ROUND_UP(entry->io_last, 3341 PCICFG_IOGRAN) - entry->io_last)) > 0) { 3342 (void) pcicfg_get_io(entry, length, NULL); 3343 DEBUG1("Added [0x%x]at the top of " 3344 "the bridge (I/O)\n", length); 3345 } 3346 } 3347 3348 static int 3349 pcicfg_probe_children(dev_info_t *parent, uint_t bus, 3350 uint_t device, uint_t func, uint_t *highest_bus) 3351 { 3352 dev_info_t *new_child; 3353 ddi_acc_handle_t config_handle; 3354 uint8_t header_type, pcie_dev = 0; 3355 int i; 3356 uint32_t request; 3357 int ret; 3358 3359 /* 3360 * This node will be put immediately below 3361 * "parent". Allocate a blank device node. It will either 3362 * be filled in or freed up based on further probing. 3363 */ 3364 3365 ndi_devi_alloc_sleep(parent, DEVI_PSEUDO_NEXNAME, 3366 (pnode_t)DEVI_SID_NODEID, &new_child); 3367 3368 if (pcicfg_add_config_reg(new_child, bus, 3369 device, func) != DDI_SUCCESS) { 3370 DEBUG0("pcicfg_probe_children():" 3371 "Failed to add candidate REG\n"); 3372 goto failedconfig; 3373 } 3374 3375 if ((ret = pcicfg_config_setup(new_child, &config_handle)) 3376 != PCICFG_SUCCESS) { 3377 if (ret == PCICFG_NODEVICE) { 3378 (void) ndi_devi_free(new_child); 3379 return (ret); 3380 } 3381 DEBUG0("pcicfg_probe_children():" 3382 "Failed to setup config space\n"); 3383 goto failedconfig; 3384 } 3385 3386 /* 3387 * As soon as we have access to config space, 3388 * turn off device. It will get turned on 3389 * later (after memory is assigned). 3390 */ 3391 (void) pcicfg_device_off(config_handle); 3392 3393 /* check if we are PCIe device */ 3394 if (pcicfg_pcie_dev(new_child, config_handle) == DDI_SUCCESS) { 3395 DEBUG0("PCIe device detected\n"); 3396 pcie_dev = 1; 3397 } 3398 3399 /* 3400 * Set 1275 properties common to all devices 3401 */ 3402 if (pcicfg_set_standard_props(new_child, config_handle, 3403 pcie_dev) != PCICFG_SUCCESS) { 3404 DEBUG0("Failed to set standard properties\n"); 3405 goto failedchild; 3406 } 3407 3408 /* 3409 * Child node properties NOTE: Both for PCI-PCI bridge and child node 3410 */ 3411 if (pcicfg_set_childnode_props(new_child, config_handle, 3412 pcie_dev) != PCICFG_SUCCESS) { 3413 goto failedchild; 3414 } 3415 3416 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 3417 3418 /* 3419 * If this is not a multi-function card only probe function zero. 3420 */ 3421 if ((!(header_type & PCI_HEADER_MULTI)) && (func != 0)) { 3422 3423 (void) pcicfg_config_teardown(&config_handle); 3424 (void) ndi_devi_free(new_child); 3425 return (PCICFG_NODEVICE); 3426 } 3427 3428 /* 3429 * Attach the child to its parent 3430 */ 3431 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3432 3433 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 3434 3435 DEBUG3("--Bridge found bus [0x%x] device" 3436 "[0x%x] func [0x%x]\n", bus, device, func); 3437 3438 if (pcicfg_probe_bridge(new_child, config_handle, 3439 bus, highest_bus) != PCICFG_SUCCESS) { 3440 (void) pcicfg_free_bridge_resources(new_child); 3441 goto failedchild; 3442 } 3443 3444 } else { 3445 3446 DEBUG3("--Leaf device found bus [0x%x] device" 3447 "[0x%x] func [0x%x]\n", 3448 bus, device, func); 3449 3450 i = PCI_CONF_BASE0; 3451 3452 while (i <= PCI_CONF_BASE5) { 3453 3454 pci_config_put32(config_handle, i, 0xffffffff); 3455 3456 request = pci_config_get32(config_handle, i); 3457 /* 3458 * If its a zero length, don't do 3459 * any programming. 3460 */ 3461 if (request != 0) { 3462 /* 3463 * Add to the "reg" property 3464 */ 3465 if (pcicfg_update_reg_prop(new_child, 3466 request, i) != PCICFG_SUCCESS) { 3467 goto failedchild; 3468 } 3469 } else { 3470 DEBUG1("BASE register [0x%x] asks for " 3471 "[0x0]=[0x0](32)\n", i); 3472 i += 4; 3473 continue; 3474 } 3475 3476 /* 3477 * Increment by eight if it is 64 bit address space 3478 */ 3479 if ((PCI_BASE_TYPE_M & request) == PCI_BASE_TYPE_ALL) { 3480 DEBUG3("BASE register [0x%x] asks for " 3481 "[0x%x]=[0x%x] (64)\n", 3482 i, request, 3483 (~(PCI_BASE_M_ADDR_M & request))+1) 3484 i += 8; 3485 } else { 3486 DEBUG3("BASE register [0x%x] asks for " 3487 "[0x%x]=[0x%x](32)\n", 3488 i, request, 3489 (~(PCI_BASE_M_ADDR_M & request))+1) 3490 i += 4; 3491 } 3492 } 3493 3494 /* 3495 * Get the ROM size and create register for it 3496 */ 3497 pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe); 3498 3499 request = pci_config_get32(config_handle, PCI_CONF_ROM); 3500 /* 3501 * If its a zero length, don't do 3502 * any programming. 3503 */ 3504 3505 if (request != 0) { 3506 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]\n", 3507 PCI_CONF_ROM, request, 3508 (~(PCI_BASE_ROM_ADDR_M & request))+1); 3509 /* 3510 * Add to the "reg" property 3511 */ 3512 if (pcicfg_update_reg_prop(new_child, 3513 request, PCI_CONF_ROM) != PCICFG_SUCCESS) { 3514 goto failedchild; 3515 } 3516 } 3517 3518 /* now allocate & program the resources */ 3519 if (pcicfg_device_assign(new_child) != PCICFG_SUCCESS) { 3520 (void) pcicfg_free_device_resources(new_child); 3521 goto failedchild; 3522 } 3523 (void) ndi_devi_bind_driver(new_child, 0); 3524 } 3525 3526 (void) pcicfg_config_teardown(&config_handle); 3527 3528 return (PCICFG_SUCCESS); 3529 3530 failedchild: 3531 /* 3532 * XXX check if it should be taken offline (if online) 3533 */ 3534 (void) pcicfg_config_teardown(&config_handle); 3535 3536 failedconfig: 3537 3538 (void) ndi_devi_free(new_child); 3539 return (PCICFG_FAILURE); 3540 } 3541 3542 static int 3543 pcicfg_probe_bridge(dev_info_t *new_child, ddi_acc_handle_t h, uint_t bus, 3544 uint_t *highest_bus) 3545 { 3546 uint64_t next_bus; 3547 uint_t new_bus, num_slots; 3548 ndi_ra_request_t req; 3549 int rval, i, j; 3550 uint64_t mem_answer, io_answer, mem_base, io_base, mem_alen, io_alen; 3551 uint64_t pf_mem_answer, pf_mem_base, pf_mem_alen; 3552 uint64_t mem_size, io_size, pf_mem_size; 3553 uint64_t mem_end, pf_mem_end, io_end; 3554 uint64_t round_answer, round_len; 3555 ppb_ranges_t range[PCICFG_RANGE_LEN]; 3556 int bus_range[2]; 3557 pcicfg_phdl_t phdl; 3558 int count; 3559 uint64_t pcibus_base, pcibus_alen; 3560 uint64_t max_bus; 3561 uint8_t pcie_device_type = 0; 3562 uint_t pf_mem_supported = 0; 3563 3564 io_answer = io_base = io_alen = io_size = 0; 3565 pf_mem_answer = pf_mem_base = pf_mem_size = pf_mem_alen = 0; 3566 3567 /* 3568 * setup resource maps for the bridge node 3569 */ 3570 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_PCI_BUSNUM) 3571 == NDI_FAILURE) { 3572 DEBUG0("Can not setup resource map - NDI_RA_TYPE_PCI_BUSNUM\n"); 3573 rval = PCICFG_FAILURE; 3574 goto cleanup; 3575 } 3576 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_MEM) == NDI_FAILURE) { 3577 DEBUG0("Can not setup resource map - NDI_RA_TYPE_MEM\n"); 3578 rval = PCICFG_FAILURE; 3579 goto cleanup; 3580 } 3581 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_IO) == NDI_FAILURE) { 3582 DEBUG0("Can not setup resource map - NDI_RA_TYPE_IO\n"); 3583 rval = PCICFG_FAILURE; 3584 goto cleanup; 3585 } 3586 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_PCI_PREFETCH_MEM) == 3587 NDI_FAILURE) { 3588 DEBUG0("Can not setup resource map -" 3589 " NDI_RA_TYPE_PCI_PREFETCH_MEM\n"); 3590 rval = PCICFG_FAILURE; 3591 goto cleanup; 3592 } 3593 3594 /* 3595 * Allocate bus range pool for the bridge. 3596 */ 3597 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 3598 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 3599 req.ra_boundbase = 0; 3600 req.ra_boundlen = req.ra_len = (PCI_MAX_BUS_NUM -1); 3601 req.ra_align_mask = 0; /* no alignment needed */ 3602 3603 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 3604 &pcibus_base, &pcibus_alen, NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 3605 3606 if (rval != NDI_SUCCESS) { 3607 if (rval == NDI_RA_PARTIAL_REQ) { 3608 /*EMPTY*/ 3609 DEBUG0("NDI_RA_PARTIAL_REQ returned for bus range\n"); 3610 } else { 3611 DEBUG0( 3612 "Failed to allocate bus range for bridge\n"); 3613 rval = PCICFG_FAILURE; 3614 goto cleanup; 3615 } 3616 } 3617 3618 DEBUG2("Bus Range Allocated [base=%d] [len=%d]\n", 3619 pcibus_base, pcibus_alen); 3620 3621 /* 3622 * Put available bus range into the pool. 3623 * Take the first one for this bridge to use and don't give 3624 * to child. 3625 */ 3626 (void) ndi_ra_free(new_child, pcibus_base+1, pcibus_alen-1, 3627 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 3628 3629 next_bus = pcibus_base; 3630 max_bus = pcibus_base + pcibus_alen - 1; 3631 3632 new_bus = next_bus; 3633 3634 DEBUG1("NEW bus found ->[%d]\n", new_bus); 3635 3636 /* Keep track of highest bus for subordinate bus programming */ 3637 *highest_bus = new_bus; 3638 3639 /* 3640 * Allocate (non-prefetchable) Memory Space for Bridge 3641 */ 3642 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 3643 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 3644 req.ra_boundbase = 0; 3645 /* 3646 * limit the boundlen,len to a 32b quantity. It should be Ok to 3647 * lose alignment-based-size of resource due to this. 3648 */ 3649 req.ra_boundlen = PCICFG_4GIG_LIMIT; 3650 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 3651 req.ra_align_mask = 3652 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 3653 3654 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 3655 &mem_answer, &mem_alen, NDI_RA_TYPE_MEM, NDI_RA_PASS); 3656 3657 if (rval != NDI_SUCCESS) { 3658 if (rval == NDI_RA_PARTIAL_REQ) { 3659 /*EMPTY*/ 3660 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 3661 } else { 3662 DEBUG0( 3663 "Failed to allocate memory for bridge\n"); 3664 rval = PCICFG_FAILURE; 3665 goto cleanup; 3666 } 3667 } 3668 3669 DEBUG3("Bridge Memory Allocated [0x%x.%x] len [0x%x]\n", 3670 PCICFG_HIADDR(mem_answer), 3671 PCICFG_LOADDR(mem_answer), 3672 mem_alen); 3673 3674 /* 3675 * Put available memory into the pool. 3676 */ 3677 (void) ndi_ra_free(new_child, mem_answer, mem_alen, NDI_RA_TYPE_MEM, 3678 NDI_RA_PASS); 3679 3680 mem_base = mem_answer; 3681 3682 /* 3683 * Allocate I/O Space for Bridge 3684 */ 3685 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 3686 req.ra_align_mask = PCICFG_IOGRAN - 1; /* 4k alignment */ 3687 req.ra_boundbase = 0; 3688 req.ra_boundlen = PCICFG_4GIG_LIMIT; 3689 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 3690 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 3691 3692 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, &io_answer, 3693 &io_alen, NDI_RA_TYPE_IO, NDI_RA_PASS); 3694 3695 if (rval != NDI_SUCCESS) { 3696 if (rval == NDI_RA_PARTIAL_REQ) { 3697 /*EMPTY*/ 3698 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 3699 } else { 3700 DEBUG0("Failed to allocate io space for bridge\n"); 3701 /* i/o space is an optional requirement so continue */ 3702 } 3703 } 3704 3705 DEBUG3("Bridge IO Space Allocated [0x%x.%x] len [0x%x]\n", 3706 PCICFG_HIADDR(io_answer), PCICFG_LOADDR(io_answer), io_alen); 3707 3708 /* 3709 * Put available I/O into the pool. 3710 */ 3711 (void) ndi_ra_free(new_child, io_answer, io_alen, NDI_RA_TYPE_IO, 3712 NDI_RA_PASS); 3713 3714 io_base = io_answer; 3715 3716 /* 3717 * Check if the bridge supports Prefetchable memory range. 3718 * If it does, then we setup PF memory range for the bridge. 3719 * Otherwise, we skip the step of setting up PF memory 3720 * range for it. This could cause config operation to 3721 * fail if any devices under the bridge need PF memory. 3722 */ 3723 /* write a non zero value to the PF BASE register */ 3724 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0xfff0); 3725 /* if the read returns zero then PF range is not supported */ 3726 if (pci_config_get16(h, PCI_BCNF_PF_BASE_LOW) == 0) { 3727 /* bridge doesn't support PF memory range */ 3728 goto pf_setup_end; 3729 } else { 3730 pf_mem_supported = 1; 3731 /* reset the PF BASE register */ 3732 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0); 3733 } 3734 3735 /* 3736 * Bridge supports PF mem range; Allocate PF Memory Space for it. 3737 * 3738 * Note: Both non-prefetchable and prefetchable memory space 3739 * allocations are made within 32bit space. Currently, BIOSs 3740 * allocate device memory for PCI devices within the 32bit space 3741 * so this will not be a problem. 3742 */ 3743 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 3744 req.ra_flags = NDI_RA_ALLOC_PARTIAL_OK | NDI_RA_ALLOC_BOUNDED; 3745 req.ra_boundbase = 0; 3746 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 3747 req.ra_align_mask = 3748 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 3749 3750 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 3751 &pf_mem_answer, &pf_mem_alen, NDI_RA_TYPE_PCI_PREFETCH_MEM, 3752 NDI_RA_PASS); 3753 3754 if (rval != NDI_SUCCESS) { 3755 if (rval == NDI_RA_PARTIAL_REQ) { 3756 /*EMPTY*/ 3757 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 3758 } else { 3759 DEBUG0( 3760 "Failed to allocate PF memory for bridge\n"); 3761 /* PF mem is an optional requirement so continue */ 3762 } 3763 } 3764 3765 DEBUG3("Bridge PF Memory Allocated [0x%x.%x] len [0x%x]\n", 3766 PCICFG_HIADDR(pf_mem_answer), 3767 PCICFG_LOADDR(pf_mem_answer), 3768 pf_mem_alen); 3769 3770 /* 3771 * Put available PF memory into the pool. 3772 */ 3773 (void) ndi_ra_free(new_child, pf_mem_answer, pf_mem_alen, 3774 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 3775 3776 pf_mem_base = pf_mem_answer; 3777 3778 /* 3779 * Program the PF memory base register with the 3780 * start of the memory range 3781 */ 3782 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 3783 PCICFG_HIWORD(PCICFG_LOADDR(pf_mem_answer))); 3784 pci_config_put32(h, PCI_BCNF_PF_BASE_HIGH, 3785 PCICFG_HIADDR(pf_mem_answer)); 3786 3787 /* 3788 * Program the PF memory limit register with the 3789 * end of the memory range. 3790 */ 3791 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 3792 PCICFG_HIWORD(PCICFG_LOADDR( 3793 PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 3794 PCICFG_MEMGRAN) - 1))); 3795 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 3796 PCICFG_HIADDR(PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 3797 PCICFG_MEMGRAN) - 1)); 3798 3799 /* 3800 * Allocate the chunk of PF memory (if any) not programmed into the 3801 * bridge because of the round down. 3802 */ 3803 if (PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), PCICFG_MEMGRAN) 3804 != (pf_mem_answer + pf_mem_alen)) { 3805 DEBUG0("Need to allocate Memory round off chunk\n"); 3806 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 3807 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 3808 req.ra_addr = PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 3809 PCICFG_MEMGRAN); 3810 req.ra_len = (pf_mem_answer + pf_mem_alen) - 3811 (PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 3812 PCICFG_MEMGRAN)); 3813 3814 (void) ndi_ra_alloc(new_child, &req, 3815 &round_answer, &round_len, NDI_RA_TYPE_PCI_PREFETCH_MEM, 3816 NDI_RA_PASS); 3817 } 3818 3819 pf_setup_end: 3820 3821 /* 3822 * Program the memory base register with the 3823 * start of the memory range 3824 */ 3825 pci_config_put16(h, PCI_BCNF_MEM_BASE, 3826 PCICFG_HIWORD(PCICFG_LOADDR(mem_answer))); 3827 3828 /* 3829 * Program the memory limit register with the 3830 * end of the memory range. 3831 */ 3832 3833 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 3834 PCICFG_HIWORD(PCICFG_LOADDR( 3835 PCICFG_ROUND_DOWN((mem_answer + mem_alen), PCICFG_MEMGRAN) - 1))); 3836 3837 /* 3838 * Allocate the chunk of memory (if any) not programmed into the 3839 * bridge because of the round down. 3840 */ 3841 if (PCICFG_ROUND_DOWN((mem_answer + mem_alen), PCICFG_MEMGRAN) 3842 != (mem_answer + mem_alen)) { 3843 DEBUG0("Need to allocate Memory round off chunk\n"); 3844 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 3845 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 3846 req.ra_addr = PCICFG_ROUND_DOWN((mem_answer + mem_alen), 3847 PCICFG_MEMGRAN); 3848 req.ra_len = (mem_answer + mem_alen) - 3849 (PCICFG_ROUND_DOWN((mem_answer + mem_alen), 3850 PCICFG_MEMGRAN)); 3851 3852 (void) ndi_ra_alloc(new_child, &req, 3853 &round_answer, &round_len, NDI_RA_TYPE_MEM, NDI_RA_PASS); 3854 } 3855 3856 /* 3857 * Program the I/O Space Base 3858 */ 3859 pci_config_put8(h, PCI_BCNF_IO_BASE_LOW, 3860 PCICFG_HIBYTE(PCICFG_LOWORD( 3861 PCICFG_LOADDR(io_answer)))); 3862 3863 pci_config_put16(h, PCI_BCNF_IO_BASE_HI, 3864 PCICFG_HIWORD(PCICFG_LOADDR(io_answer))); 3865 3866 /* 3867 * Program the I/O Space Limit 3868 */ 3869 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 3870 PCICFG_HIBYTE(PCICFG_LOWORD( 3871 PCICFG_LOADDR(PCICFG_ROUND_DOWN(io_answer + io_alen, 3872 PCICFG_IOGRAN)))) - 1); 3873 3874 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 3875 PCICFG_HIWORD(PCICFG_LOADDR( 3876 PCICFG_ROUND_DOWN(io_answer + io_alen, PCICFG_IOGRAN))) 3877 - 1); 3878 3879 /* 3880 * Allocate the chunk of I/O (if any) not programmed into the 3881 * bridge because of the round down. 3882 */ 3883 if (PCICFG_ROUND_DOWN((io_answer + io_alen), PCICFG_IOGRAN) 3884 != (io_answer + io_alen)) { 3885 DEBUG0("Need to allocate I/O round off chunk\n"); 3886 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 3887 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 3888 req.ra_addr = PCICFG_ROUND_DOWN((io_answer + io_alen), 3889 PCICFG_IOGRAN); 3890 req.ra_len = (io_answer + io_alen) - 3891 (PCICFG_ROUND_DOWN((io_answer + io_alen), 3892 PCICFG_IOGRAN)); 3893 3894 (void) ndi_ra_alloc(new_child, &req, 3895 &round_answer, &round_len, NDI_RA_TYPE_IO, NDI_RA_PASS); 3896 } 3897 3898 (void) pcicfg_set_bus_numbers(h, bus, new_bus, max_bus); 3899 3900 /* 3901 * Reset the secondary bus 3902 */ 3903 pci_config_put16(h, PCI_BCNF_BCNTRL, 3904 pci_config_get16(h, PCI_BCNF_BCNTRL) | 0x40); 3905 3906 drv_usecwait(100); 3907 3908 pci_config_put16(h, PCI_BCNF_BCNTRL, 3909 pci_config_get16(h, PCI_BCNF_BCNTRL) & ~0x40); 3910 3911 /* 3912 * Clear status bits 3913 */ 3914 pci_config_put16(h, PCI_BCNF_SEC_STATUS, 0xffff); 3915 3916 /* 3917 * Needs to be set to this value 3918 */ 3919 pci_config_put8(h, PCI_CONF_ILINE, 0xf); 3920 3921 /* check our device_type as defined by Open Firmware */ 3922 if (pcicfg_pcie_device_type(new_child, h) == DDI_SUCCESS) 3923 pcie_device_type = 1; 3924 3925 /* 3926 * Set bus properties 3927 */ 3928 if (pcicfg_set_busnode_props(new_child, pcie_device_type) 3929 != PCICFG_SUCCESS) { 3930 DEBUG0("Failed to set busnode props\n"); 3931 rval = PCICFG_FAILURE; 3932 goto cleanup; 3933 } 3934 3935 (void) pcicfg_device_on(h); 3936 3937 if (ndi_devi_online(new_child, NDI_NO_EVENT|NDI_CONFIG) 3938 != NDI_SUCCESS) { 3939 DEBUG0("Unable to online bridge\n"); 3940 rval = PCICFG_FAILURE; 3941 goto cleanup; 3942 } 3943 3944 DEBUG0("Bridge is ONLINE\n"); 3945 3946 /* 3947 * After a Reset, we need to wait 2^25 clock cycles before the 3948 * first Configuration access. The worst case is 33MHz, which 3949 * is a 1 second wait. 3950 */ 3951 drv_usecwait(pcicfg_sec_reset_delay); 3952 3953 /* 3954 * Probe all children devices 3955 */ 3956 DEBUG0("Bridge Programming Complete - probe children\n"); 3957 ndi_devi_enter(new_child, &count); 3958 for (i = 0; i < PCI_MAX_DEVICES; i++) { 3959 for (j = 0; j < PCI_MAX_FUNCTIONS; j++) { 3960 if ((rval = pcicfg_probe_children(new_child, 3961 new_bus, i, j, highest_bus)) 3962 != PCICFG_SUCCESS) { 3963 if (rval == PCICFG_NODEVICE) { 3964 DEBUG3("No Device at bus [0x%x]" 3965 "device [0x%x] " 3966 "func [0x%x]\n", new_bus, i, j); 3967 if (j) 3968 continue; 3969 } else 3970 /*EMPTY*/ 3971 DEBUG3("Failed to configure bus " 3972 "[0x%x] device [0x%x] " 3973 "func [0x%x]\n", new_bus, i, j); 3974 break; 3975 } 3976 } 3977 /* if any function fails to be configured, no need to proceed */ 3978 if (rval != PCICFG_NODEVICE) 3979 break; 3980 } 3981 ndi_devi_exit(new_child, count); 3982 3983 /* 3984 * Offline the bridge to allow reprogramming of resources. 3985 */ 3986 (void) ndi_devi_offline(new_child, NDI_NO_EVENT|NDI_UNCONFIG); 3987 3988 phdl.dip = new_child; 3989 phdl.memory_base = mem_answer; 3990 phdl.io_base = io_answer; 3991 phdl.pf_memory_base = pf_mem_answer; 3992 phdl.error = PCICFG_SUCCESS; /* in case of empty child tree */ 3993 3994 ndi_devi_enter(ddi_get_parent(new_child), &count); 3995 ddi_walk_devs(new_child, pcicfg_find_resource_end, (void *)&phdl); 3996 ndi_devi_exit(ddi_get_parent(new_child), count); 3997 3998 num_slots = pcicfg_get_nslots(new_child, h); 3999 mem_end = PCICFG_ROUND_UP(phdl.memory_base, PCICFG_MEMGRAN); 4000 io_end = PCICFG_ROUND_UP(phdl.io_base, PCICFG_IOGRAN); 4001 pf_mem_end = PCICFG_ROUND_UP(phdl.pf_memory_base, PCICFG_MEMGRAN); 4002 4003 DEBUG4("Start of Unallocated Bridge(%d slots) Resources " 4004 "Mem=0x%lx I/O=0x%lx PF_mem=%x%lx\n", num_slots, mem_end, 4005 io_end, pf_mem_end); 4006 4007 /* 4008 * if the bridge a slots, then preallocate. If not, assume static 4009 * configuration. Also check for preallocation limits and spit 4010 * warning messages appropriately (perhaps some can be in debug mode). 4011 */ 4012 if (num_slots) { 4013 uint64_t mem_reqd = mem_answer + (num_slots * 4014 pcicfg_slot_memsize); 4015 uint64_t io_reqd = io_answer + (num_slots * 4016 pcicfg_slot_iosize); 4017 uint64_t pf_mem_reqd = pf_mem_answer + (num_slots * 4018 pcicfg_slot_pf_memsize); 4019 uint8_t highest_bus_reqd = new_bus + (num_slots * 4020 pcicfg_slot_busnums); 4021 4022 if (mem_end > mem_reqd) 4023 cmn_err(CE_WARN, "Memory space consumed by bridge more " 4024 "than planned for %d slot(s)(%" PRIx64 ",%" 4025 PRIx64 ")", num_slots, mem_answer, mem_end); 4026 if (io_end > io_reqd) 4027 cmn_err(CE_WARN, "IO space consumed by bridge more than" 4028 " planned for %d slot(s)(%" PRIx64 ",%" PRIx64 ")", 4029 num_slots, io_answer, io_end); 4030 if (pf_mem_end > pf_mem_reqd) 4031 cmn_err(CE_WARN, "PF Memory space consumed by bridge" 4032 " more than planned for %d slot(s)(%" PRIx64 ",%" 4033 PRIx64 ")", num_slots, pf_mem_answer, pf_mem_end); 4034 if (*highest_bus > highest_bus_reqd) 4035 cmn_err(CE_WARN, "Buses consumed by bridge more " 4036 "than planned for %d slot(s)(%x, %x)", 4037 num_slots, new_bus, *highest_bus); 4038 4039 if (mem_reqd > (mem_answer + mem_alen)) 4040 cmn_err(CE_WARN, "Memory space required by bridge more " 4041 "than available for %d slot(s)(%" PRIx64 ",%" 4042 PRIx64 ")", num_slots, mem_answer, mem_end); 4043 if (io_reqd > (io_answer + io_alen)) 4044 cmn_err(CE_WARN, "IO space required by bridge more than" 4045 "available for %d slot(s)(%" PRIx64 ",%" PRIx64 ")", 4046 num_slots, io_answer, io_end); 4047 if (pf_mem_reqd > (pf_mem_answer + pf_mem_alen)) 4048 cmn_err(CE_WARN, "PF Memory space required by bridge" 4049 " more than available for %d slot(s)(%" PRIx64 ",%" 4050 PRIx64 ")", num_slots, pf_mem_answer, pf_mem_end); 4051 if (highest_bus_reqd > max_bus) 4052 cmn_err(CE_WARN, "Bus numbers required by bridge more " 4053 "than available for %d slot(s)(%x, %x)", 4054 num_slots, new_bus, *highest_bus); 4055 4056 mem_end = MAX((MIN(mem_reqd, (mem_answer + mem_alen))), 4057 mem_end); 4058 io_end = MAX((MIN(io_reqd, (io_answer + io_alen))), io_end); 4059 pf_mem_end = MAX((MIN(pf_mem_reqd, (pf_mem_answer + 4060 pf_mem_alen))), pf_mem_end); 4061 *highest_bus = MAX((MIN(highest_bus_reqd, max_bus)), 4062 *highest_bus); 4063 DEBUG4("mem_end %lx, io_end %lx, pf_mem_end %lx" 4064 " highest_bus %x\n", mem_end, io_end, 4065 pf_mem_end, *highest_bus); 4066 } 4067 4068 /* 4069 * Give back unused memory space to parent. 4070 */ 4071 (void) ndi_ra_free(ddi_get_parent(new_child), 4072 mem_end, (mem_answer + mem_alen) - mem_end, NDI_RA_TYPE_MEM, 4073 NDI_RA_PASS); 4074 4075 if (mem_end == mem_answer) { 4076 DEBUG0("No memory resources used\n"); 4077 /* 4078 * To prevent the bridge from forwarding any Memory 4079 * transactions, the Memory Limit will be programmed 4080 * with a smaller value than the Memory Base. 4081 */ 4082 pci_config_put16(h, PCI_BCNF_MEM_BASE, 0xffff); 4083 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 0); 4084 4085 mem_size = 0; 4086 } else { 4087 /* 4088 * Reprogram the end of the memory. 4089 */ 4090 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 4091 PCICFG_HIWORD(mem_end) - 1); 4092 mem_size = mem_end - mem_base; 4093 } 4094 4095 /* 4096 * Give back unused io space to parent. 4097 */ 4098 (void) ndi_ra_free(ddi_get_parent(new_child), 4099 io_end, (io_answer + io_alen) - io_end, 4100 NDI_RA_TYPE_IO, NDI_RA_PASS); 4101 4102 if (io_end == io_answer) { 4103 DEBUG0("No IO Space resources used\n"); 4104 4105 /* 4106 * To prevent the bridge from forwarding any I/O 4107 * transactions, the I/O Limit will be programmed 4108 * with a smaller value than the I/O Base. 4109 */ 4110 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 0); 4111 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 0); 4112 pci_config_put8(h, PCI_BCNF_IO_BASE_LOW, 0xff); 4113 pci_config_put16(h, PCI_BCNF_IO_BASE_HI, 0); 4114 4115 io_size = 0; 4116 } else { 4117 /* 4118 * Reprogram the end of the io space. 4119 */ 4120 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 4121 PCICFG_HIBYTE(PCICFG_LOWORD( 4122 PCICFG_LOADDR(io_end) - 1))); 4123 4124 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 4125 PCICFG_HIWORD(PCICFG_LOADDR(io_end - 1))); 4126 4127 io_size = io_end - io_base; 4128 } 4129 4130 /* 4131 * Give back unused PF memory space to parent. 4132 */ 4133 if (pf_mem_supported) { 4134 (void) ndi_ra_free(ddi_get_parent(new_child), 4135 pf_mem_end, (pf_mem_answer + pf_mem_alen) - pf_mem_end, 4136 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 4137 4138 if (pf_mem_end == pf_mem_answer) { 4139 DEBUG0("No PF memory resources used\n"); 4140 /* 4141 * To prevent the bridge from forwarding any PF Memory 4142 * transactions, the PF Memory Limit will be programmed 4143 * with a smaller value than the Memory Base. 4144 */ 4145 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0xfff0); 4146 pci_config_put32(h, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); 4147 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 0); 4148 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 0); 4149 4150 pf_mem_size = 0; 4151 } else { 4152 /* 4153 * Reprogram the end of the PF memory range. 4154 */ 4155 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 4156 PCICFG_HIWORD(PCICFG_LOADDR(pf_mem_end - 1))); 4157 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 4158 PCICFG_HIADDR(pf_mem_end - 1)); 4159 pf_mem_size = pf_mem_end - pf_mem_base; 4160 } 4161 } 4162 4163 if ((max_bus - *highest_bus) > 0) { 4164 /* 4165 * Give back unused bus numbers 4166 */ 4167 (void) ndi_ra_free(ddi_get_parent(new_child), 4168 *highest_bus+1, max_bus - *highest_bus, 4169 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 4170 } 4171 4172 /* 4173 * Set bus numbers to ranges encountered during scan 4174 */ 4175 (void) pcicfg_set_bus_numbers(h, bus, new_bus, *highest_bus); 4176 4177 /* 4178 * Remove the ranges property if it exists since we will create 4179 * a new one. 4180 */ 4181 (void) ndi_prop_remove(DDI_DEV_T_NONE, new_child, "ranges"); 4182 4183 DEBUG2("Creating Ranges property - Mem Address %lx Mem Size %x\n", 4184 mem_base, mem_size); 4185 DEBUG2(" - I/O Address %lx I/O Size %x\n", 4186 io_base, io_size); 4187 DEBUG2(" - PF Mem address %lx PF Mem Size %x\n", 4188 pf_mem_base, pf_mem_size); 4189 4190 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 4191 4192 range[0].child_high = range[0].parent_high |= (PCI_REG_REL_M | 4193 PCI_ADDR_IO); 4194 range[0].child_low = range[0].parent_low = io_base; 4195 range[1].child_high = range[1].parent_high |= 4196 (PCI_REG_REL_M | PCI_ADDR_MEM32); 4197 range[1].child_low = range[1].parent_low = mem_base; 4198 range[2].child_high = range[2].parent_high |= 4199 (PCI_REG_REL_M | PCI_ADDR_MEM64 | PCI_REG_PF_M); 4200 range[2].child_low = range[2].parent_low = pf_mem_base; 4201 4202 if (io_size > 0) { 4203 range[0].size_low = io_size; 4204 (void) pcicfg_update_ranges_prop(new_child, &range[0]); 4205 } 4206 if (mem_size > 0) { 4207 range[1].size_low = mem_size; 4208 (void) pcicfg_update_ranges_prop(new_child, &range[1]); 4209 } 4210 if (pf_mem_size > 0) { 4211 range[2].size_low = pf_mem_size; 4212 (void) pcicfg_update_ranges_prop(new_child, &range[2]); 4213 } 4214 4215 bus_range[0] = pci_config_get8(h, PCI_BCNF_SECBUS); 4216 bus_range[1] = pci_config_get8(h, PCI_BCNF_SUBBUS); 4217 DEBUG1("End of bridge probe: bus_range[0] = %d\n", bus_range[0]); 4218 DEBUG1("End of bridge probe: bus_range[1] = %d\n", bus_range[1]); 4219 4220 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 4221 "bus-range", bus_range, 2); 4222 4223 rval = PCICFG_SUCCESS; 4224 4225 PCICFG_DUMP_BRIDGE_CONFIG(h); 4226 4227 cleanup: 4228 /* free up resources (for error return case only) */ 4229 if (rval != PCICFG_SUCCESS) { 4230 if (mem_alen) 4231 (void) ndi_ra_free(ddi_get_parent(new_child), mem_base, 4232 mem_alen, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4233 if (io_alen) 4234 (void) ndi_ra_free(ddi_get_parent(new_child), io_base, 4235 io_alen, NDI_RA_TYPE_IO, NDI_RA_PASS); 4236 if (pf_mem_alen) 4237 (void) ndi_ra_free(ddi_get_parent(new_child), pf_mem_base, 4238 pf_mem_alen, NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 4239 if (pcibus_alen) 4240 (void) ndi_ra_free(ddi_get_parent(new_child), pcibus_base, 4241 pcibus_alen, NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 4242 } 4243 4244 /* free up any resource maps setup for the bridge node */ 4245 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_PCI_BUSNUM); 4246 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_IO); 4247 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_MEM); 4248 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_PCI_PREFETCH_MEM); 4249 4250 return (rval); 4251 } 4252 4253 static int 4254 pcicfg_find_resource_end(dev_info_t *dip, void *hdl) 4255 { 4256 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 4257 pci_regspec_t *pci_ap; 4258 int length; 4259 int rcount; 4260 int i; 4261 4262 entry->error = PCICFG_SUCCESS; 4263 4264 if (dip == entry->dip) { 4265 DEBUG0("Don't include parent bridge node\n"); 4266 return (DDI_WALK_CONTINUE); 4267 } else { 4268 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 4269 DDI_PROP_DONTPASS, "assigned-addresses", 4270 (caddr_t)&pci_ap, &length) != DDI_PROP_SUCCESS) { 4271 DEBUG0("Node doesn't have assigned-addresses\n"); 4272 return (DDI_WALK_CONTINUE); 4273 } 4274 4275 rcount = length / sizeof (pci_regspec_t); 4276 4277 for (i = 0; i < rcount; i++) { 4278 4279 switch (PCI_REG_ADDR_G(pci_ap[i].pci_phys_hi)) { 4280 4281 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 4282 if (pci_ap[i].pci_phys_hi & PCI_REG_PF_M) { 4283 if ((pci_ap[i].pci_phys_low + 4284 pci_ap[i].pci_size_low) > 4285 entry->pf_memory_base) { 4286 entry->pf_memory_base = 4287 pci_ap[i].pci_phys_low + 4288 pci_ap[i].pci_size_low; 4289 } 4290 } else { 4291 if ((pci_ap[i].pci_phys_low + 4292 pci_ap[i].pci_size_low) > 4293 entry->memory_base) { 4294 entry->memory_base = 4295 pci_ap[i].pci_phys_low + 4296 pci_ap[i].pci_size_low; 4297 } 4298 } 4299 break; 4300 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 4301 if (pci_ap[i].pci_phys_hi & PCI_REG_PF_M) { 4302 if ((PCICFG_LADDR(pci_ap[i].pci_phys_low, 4303 pci_ap[i].pci_phys_mid) + 4304 pci_ap[i].pci_size_low) > 4305 entry->pf_memory_base) { 4306 entry->pf_memory_base = PCICFG_LADDR( 4307 pci_ap[i].pci_phys_low, 4308 pci_ap[i].pci_phys_mid) + 4309 pci_ap[i].pci_size_low; 4310 } 4311 } else { 4312 if ((PCICFG_LADDR(pci_ap[i].pci_phys_low, 4313 pci_ap[i].pci_phys_mid) + 4314 pci_ap[i].pci_size_low) > 4315 entry->memory_base) { 4316 entry->memory_base = PCICFG_LADDR( 4317 pci_ap[i].pci_phys_low, 4318 pci_ap[i].pci_phys_mid) + 4319 pci_ap[i].pci_size_low; 4320 } 4321 } 4322 break; 4323 case PCI_REG_ADDR_G(PCI_ADDR_IO): 4324 if ((pci_ap[i].pci_phys_low + 4325 pci_ap[i].pci_size_low) > 4326 entry->io_base) { 4327 entry->io_base = 4328 pci_ap[i].pci_phys_low + 4329 pci_ap[i].pci_size_low; 4330 } 4331 break; 4332 } 4333 } 4334 4335 /* 4336 * free the memory allocated by ddi_getlongprop 4337 */ 4338 kmem_free(pci_ap, length); 4339 4340 /* 4341 * continue the walk to the next sibling to sum memory 4342 */ 4343 return (DDI_WALK_CONTINUE); 4344 } 4345 } 4346 4347 /* 4348 * Make "parent" be the parent of the "child" dip 4349 */ 4350 static void 4351 pcicfg_reparent_node(dev_info_t *child, dev_info_t *parent) 4352 { 4353 int circ; 4354 dev_info_t *opdip; 4355 4356 ASSERT(i_ddi_node_state(child) <= DS_LINKED); 4357 /* 4358 * Unlink node from tree before reparenting 4359 */ 4360 opdip = ddi_get_parent(child); 4361 ndi_devi_enter(opdip, &circ); 4362 (void) i_ndi_unconfig_node(child, DS_PROTO, 0); 4363 ndi_devi_exit(opdip, circ); 4364 4365 DEVI(child)->devi_parent = DEVI(parent); 4366 DEVI(child)->devi_bus_ctl = DEVI(parent); 4367 (void) ndi_devi_bind_driver(child, 0); 4368 } 4369 4370 /* 4371 * Return PCICFG_SUCCESS if device exists at the specified address. 4372 * Return PCICFG_NODEVICE is no device exists at the specified address. 4373 */ 4374 int 4375 pcicfg_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 4376 { 4377 caddr_t cfgaddr; 4378 ddi_device_acc_attr_t attr; 4379 dev_info_t *anode; 4380 int status; 4381 int rlen; 4382 pci_regspec_t *reg; 4383 int ret = DDI_SUCCESS; 4384 int16_t tmp; 4385 4386 /* 4387 * Get the pci register spec from the node 4388 */ 4389 status = ddi_getlongprop(DDI_DEV_T_ANY, 4390 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 4391 4392 switch (status) { 4393 case DDI_PROP_SUCCESS: 4394 break; 4395 case DDI_PROP_NO_MEMORY: 4396 DEBUG0("reg present, but unable to get memory\n"); 4397 return (PCICFG_FAILURE); 4398 default: 4399 DEBUG0("no reg property\n"); 4400 return (PCICFG_FAILURE); 4401 } 4402 4403 anode = dip; 4404 DEBUG2("conf_map: dip=%p, anode=%p\n", dip, anode); 4405 4406 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 4407 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 4408 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 4409 4410 if (ddi_regs_map_setup(anode, 0, &cfgaddr, 4411 0, 0, &attr, handle) != DDI_SUCCESS) { 4412 DEBUG0("Failed to setup registers\n"); 4413 kmem_free((caddr_t)reg, rlen); 4414 return (PCICFG_FAILURE); 4415 } 4416 4417 /* 4418 * need to use DDI interfaces as the conf space is 4419 * cannot be directly accessed by the host. 4420 */ 4421 tmp = (int16_t)ddi_get16(*handle, (uint16_t *)cfgaddr); 4422 if ((tmp == (int16_t)0xffff) || (tmp == -1)) { 4423 DEBUG1("NO DEVICEFOUND, read %x\n", tmp); 4424 ret = PCICFG_NODEVICE; 4425 } else { 4426 if (tmp == 0) { 4427 DEBUG0("Device Not Ready yet ?"); 4428 ret = PCICFG_NODEVICE; 4429 } else { 4430 DEBUG1("DEVICEFOUND, read %x\n", tmp); 4431 ret = PCICFG_SUCCESS; 4432 } 4433 } 4434 4435 if (ret == PCICFG_NODEVICE) 4436 ddi_regs_map_free(handle); 4437 kmem_free((caddr_t)reg, rlen); 4438 4439 return (ret); 4440 4441 } 4442 4443 static void 4444 pcicfg_config_teardown(ddi_acc_handle_t *handle) 4445 { 4446 (void) ddi_regs_map_free(handle); 4447 } 4448 4449 static int 4450 pcicfg_add_config_reg(dev_info_t *dip, 4451 uint_t bus, uint_t device, uint_t func) 4452 { 4453 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0}; 4454 4455 reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0); 4456 4457 return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 4458 "reg", reg, 5)); 4459 } 4460 4461 #ifdef DEBUG 4462 static void 4463 debug(char *fmt, uintptr_t a1, uintptr_t a2, uintptr_t a3, 4464 uintptr_t a4, uintptr_t a5) 4465 { 4466 if (pcicfg_debug > 1) { 4467 prom_printf("pcicfg: "); 4468 prom_printf(fmt, a1, a2, a3, a4, a5); 4469 } 4470 } 4471 #endif 4472 4473 /* 4474 * given a cap_id, return its cap_id location in config space 4475 */ 4476 static int 4477 pcicfg_get_cap(ddi_acc_handle_t config_handle, uint8_t cap_id) 4478 { 4479 uint8_t curcap; 4480 uint_t cap_id_loc; 4481 uint16_t status; 4482 int location = -1; 4483 4484 /* 4485 * Need to check the Status register for ECP support first. 4486 * Also please note that for type 1 devices, the 4487 * offset could change. Should support type 1 next. 4488 */ 4489 status = pci_config_get16(config_handle, PCI_CONF_STAT); 4490 if (!(status & PCI_STAT_CAP)) { 4491 return (-1); 4492 } 4493 cap_id_loc = pci_config_get8(config_handle, PCI_CONF_CAP_PTR); 4494 4495 /* Walk the list of capabilities */ 4496 while (cap_id_loc) { 4497 4498 curcap = pci_config_get8(config_handle, cap_id_loc); 4499 4500 if (curcap == cap_id) { 4501 location = cap_id_loc; 4502 break; 4503 } 4504 cap_id_loc = pci_config_get8(config_handle, 4505 cap_id_loc + 1); 4506 } 4507 return (location); 4508 } 4509 4510 /*ARGSUSED*/ 4511 static uint8_t 4512 pcicfg_get_nslots(dev_info_t *dip, ddi_acc_handle_t handle) 4513 { 4514 int cap_id_loc; 4515 uint8_t num_slots = 0; 4516 4517 /* just depend on the pcie_cap for now. */ 4518 if ((cap_id_loc = pcicfg_get_cap(handle, PCI_CAP_ID_PCI_E)) 4519 > 0) { 4520 if (pci_config_get8(handle, cap_id_loc + 4521 PCI_CAP_ID_REGS_OFF) & 4522 PCIE_PCIECAP_SLOT_IMPL) 4523 num_slots = 1; 4524 } else /* not a PCIe switch/bridge. Must be a PCI-PCI[-X] bridge */ 4525 if ((cap_id_loc = pcicfg_get_cap(handle, PCI_CAP_ID_SLOT_ID)) 4526 > 0) { 4527 uint8_t esr_reg = pci_config_get8(handle, cap_id_loc + 2); 4528 num_slots = PCI_CAPSLOT_NSLOTS(esr_reg); 4529 } 4530 /* XXX - need to cover PCI-PCIe bridge with n slots */ 4531 return (num_slots); 4532 } 4533 4534 /*ARGSUSED*/ 4535 static int 4536 pcicfg_pcie_dev(dev_info_t *dip, ddi_acc_handle_t handle) 4537 { 4538 /* get parent device's device_type property */ 4539 char *device_type; 4540 int val; 4541 dev_info_t *pdip = ddi_get_parent(dip); 4542 4543 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, 4544 DDI_PROP_DONTPASS, "device_type", &device_type) 4545 != DDI_PROP_SUCCESS) { 4546 DEBUG2("device_type property missing for %s#%d", 4547 ddi_get_name(pdip), ddi_get_instance(pdip)); 4548 return (DDI_FAILURE); 4549 } 4550 DEBUG1("device_type=<%s>\n", device_type); 4551 4552 val = DDI_FAILURE; 4553 if (strcmp(device_type, "pciex") == 0) 4554 val = DDI_SUCCESS; 4555 ddi_prop_free(device_type); 4556 return (val); 4557 } 4558 4559 static int 4560 pcicfg_pcie_device_type(dev_info_t *dip, ddi_acc_handle_t handle) 4561 { 4562 int port_type = pcicfg_pcie_port_type(dip, handle); 4563 4564 DEBUG1("device port_type = %x\n", port_type); 4565 /* No PCIe CAP regs, we are not PCIe device_type */ 4566 if (port_type < 0) 4567 return (DDI_FAILURE); 4568 4569 /* check for all PCIe device_types */ 4570 if ((port_type == PCIE_PCIECAP_DEV_TYPE_UP) || 4571 (port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) || 4572 (port_type == PCIE_PCIECAP_DEV_TYPE_ROOT) || 4573 (port_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) 4574 return (DDI_SUCCESS); 4575 4576 return (DDI_FAILURE); 4577 4578 } 4579 4580 /*ARGSUSED*/ 4581 static int 4582 pcicfg_pcie_port_type(dev_info_t *dip, ddi_acc_handle_t handle) 4583 { 4584 int port_type = -1; 4585 int cap_loc; 4586 4587 /* Note: need to look at the port type information here */ 4588 if ((cap_loc = pcicfg_get_cap(handle, PCI_CAP_ID_PCI_E)) > 0) 4589 port_type = pci_config_get16(handle, 4590 cap_loc + PCIE_PCIECAP) & PCIE_PCIECAP_DEV_TYPE_MASK; 4591 4592 return (port_type); 4593 } 4594