1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. 29 * Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T 30 * All Rights Reserved 31 */ 32 33#pragma ident "%Z%%M% %I% %E% SMI" 34 35/* 36 * General assembly language routines. 37 * It is the intent of this file to contain routines that are 38 * independent of the specific kernel architecture, and those that are 39 * common across kernel architectures. 40 * As architectures diverge, and implementations of specific 41 * architecture-dependent routines change, the routines should be moved 42 * from this file into the respective ../`arch -k`/subr.s file. 43 */ 44 45#include <sys/asm_linkage.h> 46#include <sys/asm_misc.h> 47#include <sys/panic.h> 48#include <sys/ontrap.h> 49#include <sys/regset.h> 50#include <sys/privregs.h> 51#include <sys/reboot.h> 52#include <sys/psw.h> 53#include <sys/x86_archext.h> 54 55#if defined(__lint) 56#include <sys/types.h> 57#include <sys/systm.h> 58#include <sys/thread.h> 59#include <sys/archsystm.h> 60#include <sys/byteorder.h> 61#include <sys/dtrace.h> 62#else /* __lint */ 63#include "assym.h" 64#endif /* __lint */ 65#include <sys/dditypes.h> 66 67/* 68 * on_fault() 69 * Catch lofault faults. Like setjmp except it returns one 70 * if code following causes uncorrectable fault. Turned off 71 * by calling no_fault(). 72 */ 73 74#if defined(__lint) 75 76/* ARGSUSED */ 77int 78on_fault(label_t *ljb) 79{ return (0); } 80 81void 82no_fault(void) 83{} 84 85#else /* __lint */ 86 87#if defined(__amd64) 88 89 ENTRY(on_fault) 90 movq %gs:CPU_THREAD, %rsi 91 leaq catch_fault(%rip), %rdx 92 movq %rdi, T_ONFAULT(%rsi) /* jumpbuf in t_onfault */ 93 movq %rdx, T_LOFAULT(%rsi) /* catch_fault in t_lofault */ 94 jmp setjmp /* let setjmp do the rest */ 95 96catch_fault: 97 movq %gs:CPU_THREAD, %rsi 98 movq T_ONFAULT(%rsi), %rdi /* address of save area */ 99 xorl %eax, %eax 100 movq %rax, T_ONFAULT(%rsi) /* turn off onfault */ 101 movq %rax, T_LOFAULT(%rsi) /* turn off lofault */ 102 jmp longjmp /* let longjmp do the rest */ 103 SET_SIZE(on_fault) 104 105 ENTRY(no_fault) 106 movq %gs:CPU_THREAD, %rsi 107 xorl %eax, %eax 108 movq %rax, T_ONFAULT(%rsi) /* turn off onfault */ 109 movq %rax, T_LOFAULT(%rsi) /* turn off lofault */ 110 ret 111 SET_SIZE(no_fault) 112 113#elif defined(__i386) 114 115 ENTRY(on_fault) 116 movl %gs:CPU_THREAD, %edx 117 movl 4(%esp), %eax /* jumpbuf address */ 118 leal catch_fault, %ecx 119 movl %eax, T_ONFAULT(%edx) /* jumpbuf in t_onfault */ 120 movl %ecx, T_LOFAULT(%edx) /* catch_fault in t_lofault */ 121 jmp setjmp /* let setjmp do the rest */ 122 123catch_fault: 124 movl %gs:CPU_THREAD, %edx 125 xorl %eax, %eax 126 movl T_ONFAULT(%edx), %ecx /* address of save area */ 127 movl %eax, T_ONFAULT(%edx) /* turn off onfault */ 128 movl %eax, T_LOFAULT(%edx) /* turn off lofault */ 129 pushl %ecx 130 call longjmp /* let longjmp do the rest */ 131 SET_SIZE(on_fault) 132 133 ENTRY(no_fault) 134 movl %gs:CPU_THREAD, %edx 135 xorl %eax, %eax 136 movl %eax, T_ONFAULT(%edx) /* turn off onfault */ 137 movl %eax, T_LOFAULT(%edx) /* turn off lofault */ 138 ret 139 SET_SIZE(no_fault) 140 141#endif /* __i386 */ 142#endif /* __lint */ 143 144/* 145 * Default trampoline code for on_trap() (see <sys/ontrap.h>). We just 146 * do a longjmp(&curthread->t_ontrap->ot_jmpbuf) if this is ever called. 147 */ 148 149#if defined(lint) 150 151void 152on_trap_trampoline(void) 153{} 154 155#else /* __lint */ 156 157#if defined(__amd64) 158 159 ENTRY(on_trap_trampoline) 160 movq %gs:CPU_THREAD, %rsi 161 movq T_ONTRAP(%rsi), %rdi 162 addq $OT_JMPBUF, %rdi 163 jmp longjmp 164 SET_SIZE(on_trap_trampoline) 165 166#elif defined(__i386) 167 168 ENTRY(on_trap_trampoline) 169 movl %gs:CPU_THREAD, %eax 170 movl T_ONTRAP(%eax), %eax 171 addl $OT_JMPBUF, %eax 172 pushl %eax 173 call longjmp 174 SET_SIZE(on_trap_trampoline) 175 176#endif /* __i386 */ 177#endif /* __lint */ 178 179/* 180 * Push a new element on to the t_ontrap stack. Refer to <sys/ontrap.h> for 181 * more information about the on_trap() mechanism. If the on_trap_data is the 182 * same as the topmost stack element, we just modify that element. 183 */ 184#if defined(lint) 185 186/*ARGSUSED*/ 187int 188on_trap(on_trap_data_t *otp, uint_t prot) 189{ return (0); } 190 191#else /* __lint */ 192 193#if defined(__amd64) 194 195 ENTRY(on_trap) 196 movw %si, OT_PROT(%rdi) /* ot_prot = prot */ 197 movw $0, OT_TRAP(%rdi) /* ot_trap = 0 */ 198 leaq on_trap_trampoline(%rip), %rdx /* rdx = &on_trap_trampoline */ 199 movq %rdx, OT_TRAMPOLINE(%rdi) /* ot_trampoline = rdx */ 200 xorl %ecx, %ecx 201 movq %rcx, OT_HANDLE(%rdi) /* ot_handle = NULL */ 202 movq %rcx, OT_PAD1(%rdi) /* ot_pad1 = NULL */ 203 movq %gs:CPU_THREAD, %rdx /* rdx = curthread */ 204 movq T_ONTRAP(%rdx), %rcx /* rcx = curthread->t_ontrap */ 205 cmpq %rdi, %rcx /* if (otp == %rcx) */ 206 je 0f /* don't modify t_ontrap */ 207 208 movq %rcx, OT_PREV(%rdi) /* ot_prev = t_ontrap */ 209 movq %rdi, T_ONTRAP(%rdx) /* curthread->t_ontrap = otp */ 210 2110: addq $OT_JMPBUF, %rdi /* &ot_jmpbuf */ 212 jmp setjmp 213 SET_SIZE(on_trap) 214 215#elif defined(__i386) 216 217 ENTRY(on_trap) 218 movl 4(%esp), %eax /* %eax = otp */ 219 movl 8(%esp), %edx /* %edx = prot */ 220 221 movw %dx, OT_PROT(%eax) /* ot_prot = prot */ 222 movw $0, OT_TRAP(%eax) /* ot_trap = 0 */ 223 leal on_trap_trampoline, %edx /* %edx = &on_trap_trampoline */ 224 movl %edx, OT_TRAMPOLINE(%eax) /* ot_trampoline = %edx */ 225 movl $0, OT_HANDLE(%eax) /* ot_handle = NULL */ 226 movl $0, OT_PAD1(%eax) /* ot_pad1 = NULL */ 227 movl %gs:CPU_THREAD, %edx /* %edx = curthread */ 228 movl T_ONTRAP(%edx), %ecx /* %ecx = curthread->t_ontrap */ 229 cmpl %eax, %ecx /* if (otp == %ecx) */ 230 je 0f /* don't modify t_ontrap */ 231 232 movl %ecx, OT_PREV(%eax) /* ot_prev = t_ontrap */ 233 movl %eax, T_ONTRAP(%edx) /* curthread->t_ontrap = otp */ 234 2350: addl $OT_JMPBUF, %eax /* %eax = &ot_jmpbuf */ 236 movl %eax, 4(%esp) /* put %eax back on the stack */ 237 jmp setjmp /* let setjmp do the rest */ 238 SET_SIZE(on_trap) 239 240#endif /* __i386 */ 241#endif /* __lint */ 242 243/* 244 * Setjmp and longjmp implement non-local gotos using state vectors 245 * type label_t. 246 */ 247 248#if defined(__lint) 249 250/* ARGSUSED */ 251int 252setjmp(label_t *lp) 253{ return (0); } 254 255/* ARGSUSED */ 256void 257longjmp(label_t *lp) 258{} 259 260#else /* __lint */ 261 262#if LABEL_PC != 0 263#error LABEL_PC MUST be defined as 0 for setjmp/longjmp to work as coded 264#endif /* LABEL_PC != 0 */ 265 266#if defined(__amd64) 267 268 ENTRY(setjmp) 269 movq %rsp, LABEL_SP(%rdi) 270 movq %rbp, LABEL_RBP(%rdi) 271 movq %rbx, LABEL_RBX(%rdi) 272 movq %r12, LABEL_R12(%rdi) 273 movq %r13, LABEL_R13(%rdi) 274 movq %r14, LABEL_R14(%rdi) 275 movq %r15, LABEL_R15(%rdi) 276 movq (%rsp), %rdx /* return address */ 277 movq %rdx, (%rdi) /* LABEL_PC is 0 */ 278 xorl %eax, %eax /* return 0 */ 279 ret 280 SET_SIZE(setjmp) 281 282 ENTRY(longjmp) 283 movq LABEL_SP(%rdi), %rsp 284 movq LABEL_RBP(%rdi), %rbp 285 movq LABEL_RBX(%rdi), %rbx 286 movq LABEL_R12(%rdi), %r12 287 movq LABEL_R13(%rdi), %r13 288 movq LABEL_R14(%rdi), %r14 289 movq LABEL_R15(%rdi), %r15 290 movq (%rdi), %rdx /* return address; LABEL_PC is 0 */ 291 movq %rdx, (%rsp) 292 xorl %eax, %eax 293 incl %eax /* return 1 */ 294 ret 295 SET_SIZE(longjmp) 296 297#elif defined(__i386) 298 299 ENTRY(setjmp) 300 movl 4(%esp), %edx /* address of save area */ 301 movl %ebp, LABEL_EBP(%edx) 302 movl %ebx, LABEL_EBX(%edx) 303 movl %esi, LABEL_ESI(%edx) 304 movl %edi, LABEL_EDI(%edx) 305 movl %esp, 4(%edx) 306 movl (%esp), %ecx /* %eip (return address) */ 307 movl %ecx, (%edx) /* LABEL_PC is 0 */ 308 subl %eax, %eax /* return 0 */ 309 ret 310 SET_SIZE(setjmp) 311 312 ENTRY(longjmp) 313 movl 4(%esp), %edx /* address of save area */ 314 movl LABEL_EBP(%edx), %ebp 315 movl LABEL_EBX(%edx), %ebx 316 movl LABEL_ESI(%edx), %esi 317 movl LABEL_EDI(%edx), %edi 318 movl 4(%edx), %esp 319 movl (%edx), %ecx /* %eip (return addr); LABEL_PC is 0 */ 320 movl $1, %eax 321 addl $4, %esp /* pop ret adr */ 322 jmp *%ecx /* indirect */ 323 SET_SIZE(longjmp) 324 325#endif /* __i386 */ 326#endif /* __lint */ 327 328/* 329 * if a() calls b() calls caller(), 330 * caller() returns return address in a(). 331 * (Note: We assume a() and b() are C routines which do the normal entry/exit 332 * sequence.) 333 */ 334 335#if defined(__lint) 336 337caddr_t 338caller(void) 339{ return (0); } 340 341#else /* __lint */ 342 343#if defined(__amd64) 344 345 ENTRY(caller) 346 movq 8(%rbp), %rax /* b()'s return pc, in a() */ 347 ret 348 SET_SIZE(caller) 349 350#elif defined(__i386) 351 352 ENTRY(caller) 353 movl 4(%ebp), %eax /* b()'s return pc, in a() */ 354 ret 355 SET_SIZE(caller) 356 357#endif /* __i386 */ 358#endif /* __lint */ 359 360/* 361 * if a() calls callee(), callee() returns the 362 * return address in a(); 363 */ 364 365#if defined(__lint) 366 367caddr_t 368callee(void) 369{ return (0); } 370 371#else /* __lint */ 372 373#if defined(__amd64) 374 375 ENTRY(callee) 376 movq (%rsp), %rax /* callee()'s return pc, in a() */ 377 ret 378 SET_SIZE(callee) 379 380#elif defined(__i386) 381 382 ENTRY(callee) 383 movl (%esp), %eax /* callee()'s return pc, in a() */ 384 ret 385 SET_SIZE(callee) 386 387#endif /* __i386 */ 388#endif /* __lint */ 389 390/* 391 * return the current frame pointer 392 */ 393 394#if defined(__lint) 395 396greg_t 397getfp(void) 398{ return (0); } 399 400#else /* __lint */ 401 402#if defined(__amd64) 403 404 ENTRY(getfp) 405 movq %rbp, %rax 406 ret 407 SET_SIZE(getfp) 408 409#elif defined(__i386) 410 411 ENTRY(getfp) 412 movl %ebp, %eax 413 ret 414 SET_SIZE(getfp) 415 416#endif /* __i386 */ 417#endif /* __lint */ 418 419/* 420 * Invalidate a single page table entry in the TLB 421 */ 422 423#if defined(__lint) 424 425/* ARGSUSED */ 426void 427mmu_tlbflush_entry(caddr_t m) 428{} 429 430#else /* __lint */ 431 432#if defined(__amd64) 433 434 ENTRY(mmu_tlbflush_entry) 435 invlpg (%rdi) 436 ret 437 SET_SIZE(mmu_tlbflush_entry) 438 439#elif defined(__i386) 440 441 ENTRY(mmu_tlbflush_entry) 442 movl 4(%esp), %eax 443 invlpg (%eax) 444 ret 445 SET_SIZE(mmu_tlbflush_entry) 446 447#endif /* __i386 */ 448#endif /* __lint */ 449 450 451/* 452 * Get/Set the value of various control registers 453 */ 454 455#if defined(__lint) 456 457ulong_t 458getcr0(void) 459{ return (0); } 460 461/* ARGSUSED */ 462void 463setcr0(ulong_t value) 464{} 465 466ulong_t 467getcr2(void) 468{ return (0); } 469 470ulong_t 471getcr3(void) 472{ return (0); } 473 474/* ARGSUSED */ 475void 476setcr3(ulong_t val) 477{} 478 479void 480reload_cr3(void) 481{} 482 483ulong_t 484getcr4(void) 485{ return (0); } 486 487/* ARGSUSED */ 488void 489setcr4(ulong_t val) 490{} 491 492#if defined(__amd64) 493 494ulong_t 495getcr8(void) 496{ return (0); } 497 498/* ARGSUSED */ 499void 500setcr8(ulong_t val) 501{} 502 503#endif /* __amd64 */ 504 505#else /* __lint */ 506 507#if defined(__amd64) 508 509 ENTRY(getcr0) 510 movq %cr0, %rax 511 ret 512 SET_SIZE(getcr0) 513 514 ENTRY(setcr0) 515 movq %rdi, %cr0 516 ret 517 SET_SIZE(setcr0) 518 519 ENTRY(getcr2) 520 movq %cr2, %rax 521 ret 522 SET_SIZE(getcr2) 523 524 ENTRY(getcr3) 525 movq %cr3, %rax 526 ret 527 SET_SIZE(getcr3) 528 529 ENTRY(setcr3) 530 movq %rdi, %cr3 531 ret 532 SET_SIZE(setcr3) 533 534 ENTRY(reload_cr3) 535 movq %cr3, %rdi 536 movq %rdi, %cr3 537 ret 538 SET_SIZE(reload_cr3) 539 540 ENTRY(getcr4) 541 movq %cr4, %rax 542 ret 543 SET_SIZE(getcr4) 544 545 ENTRY(setcr4) 546 movq %rdi, %cr4 547 ret 548 SET_SIZE(setcr4) 549 550 ENTRY(getcr8) 551 movq %cr8, %rax 552 ret 553 SET_SIZE(getcr8) 554 555 ENTRY(setcr8) 556 movq %rdi, %cr8 557 ret 558 SET_SIZE(setcr8) 559 560#elif defined(__i386) 561 562 ENTRY(getcr0) 563 movl %cr0, %eax 564 ret 565 SET_SIZE(getcr0) 566 567 ENTRY(setcr0) 568 movl 4(%esp), %eax 569 movl %eax, %cr0 570 ret 571 SET_SIZE(setcr0) 572 573 ENTRY(getcr2) 574 movl %cr2, %eax 575 ret 576 SET_SIZE(getcr2) 577 578 ENTRY(getcr3) 579 movl %cr3, %eax 580 ret 581 SET_SIZE(getcr3) 582 583 ENTRY(setcr3) 584 movl 4(%esp), %eax 585 movl %eax, %cr3 586 ret 587 SET_SIZE(setcr3) 588 589 ENTRY(reload_cr3) 590 movl %cr3, %eax 591 movl %eax, %cr3 592 ret 593 SET_SIZE(reload_cr3) 594 595 ENTRY(getcr4) 596 movl %cr4, %eax 597 ret 598 SET_SIZE(getcr4) 599 600 ENTRY(setcr4) 601 movl 4(%esp), %eax 602 movl %eax, %cr4 603 ret 604 SET_SIZE(setcr4) 605 606#endif /* __i386 */ 607#endif /* __lint */ 608 609#if defined(__lint) 610 611/*ARGSUSED*/ 612uint32_t 613__cpuid_insn(uint32_t eax, uint32_t *ebxp, uint32_t *ecxp, uint32_t *edxp) 614{ return (0); } 615 616#else /* __lint */ 617 618#if defined(__amd64) 619 620 ENTRY(__cpuid_insn) 621 movq %rbx, %r11 622 movq %rdx, %r8 /* r8 = ecxp */ 623 movq %rcx, %r9 /* r9 = edxp */ 624 movl %edi, %eax 625 cpuid 626 movl %ebx, (%rsi) 627 movl %ecx, (%r8) 628 movl %edx, (%r9) 629 movq %r11, %rbx 630 ret 631 SET_SIZE(__cpuid_insn) 632 633#elif defined(__i386) 634 635 ENTRY(__cpuid_insn) 636 pushl %ebp 637 movl %esp, %ebp 638 pushl %ebx 639 movl 8(%ebp), %eax 640 cpuid 641 pushl %eax 642 movl 0x0c(%ebp), %eax 643 movl %ebx, (%eax) 644 movl 0x10(%ebp), %eax 645 movl %ecx, (%eax) 646 movl 0x14(%ebp), %eax 647 movl %edx, (%eax) 648 popl %eax 649 popl %ebx 650 popl %ebp 651 ret 652 SET_SIZE(__cpuid_insn) 653 654#endif /* __i386 */ 655#endif /* __lint */ 656 657/* 658 * Insert entryp after predp in a doubly linked list. 659 */ 660 661#if defined(__lint) 662 663/*ARGSUSED*/ 664void 665_insque(caddr_t entryp, caddr_t predp) 666{} 667 668#else /* __lint */ 669 670#if defined(__amd64) 671 672 ENTRY(_insque) 673 movq (%rsi), %rax /* predp->forw */ 674 movq %rsi, CPTRSIZE(%rdi) /* entryp->back = predp */ 675 movq %rax, (%rdi) /* entryp->forw = predp->forw */ 676 movq %rdi, (%rsi) /* predp->forw = entryp */ 677 movq %rdi, CPTRSIZE(%rax) /* predp->forw->back = entryp */ 678 ret 679 SET_SIZE(_insque) 680 681#elif defined(__i386) 682 683 ENTRY(_insque) 684 movl 8(%esp), %edx 685 movl 4(%esp), %ecx 686 movl (%edx), %eax /* predp->forw */ 687 movl %edx, CPTRSIZE(%ecx) /* entryp->back = predp */ 688 movl %eax, (%ecx) /* entryp->forw = predp->forw */ 689 movl %ecx, (%edx) /* predp->forw = entryp */ 690 movl %ecx, CPTRSIZE(%eax) /* predp->forw->back = entryp */ 691 ret 692 SET_SIZE(_insque) 693 694#endif /* __i386 */ 695#endif /* __lint */ 696 697/* 698 * Remove entryp from a doubly linked list 699 */ 700 701#if defined(__lint) 702 703/*ARGSUSED*/ 704void 705_remque(caddr_t entryp) 706{} 707 708#else /* __lint */ 709 710#if defined(__amd64) 711 712 ENTRY(_remque) 713 movq (%rdi), %rax /* entry->forw */ 714 movq CPTRSIZE(%rdi), %rdx /* entry->back */ 715 movq %rax, (%rdx) /* entry->back->forw = entry->forw */ 716 movq %rdx, CPTRSIZE(%rax) /* entry->forw->back = entry->back */ 717 ret 718 SET_SIZE(_remque) 719 720#elif defined(__i386) 721 722 ENTRY(_remque) 723 movl 4(%esp), %ecx 724 movl (%ecx), %eax /* entry->forw */ 725 movl CPTRSIZE(%ecx), %edx /* entry->back */ 726 movl %eax, (%edx) /* entry->back->forw = entry->forw */ 727 movl %edx, CPTRSIZE(%eax) /* entry->forw->back = entry->back */ 728 ret 729 SET_SIZE(_remque) 730 731#endif /* __i386 */ 732#endif /* __lint */ 733 734/* 735 * Returns the number of 736 * non-NULL bytes in string argument. 737 */ 738 739#if defined(__lint) 740 741/* ARGSUSED */ 742size_t 743strlen(const char *str) 744{ return (0); } 745 746#else /* __lint */ 747 748#if defined(__amd64) 749 750/* 751 * This is close to a simple transliteration of a C version of this 752 * routine. We should either just -make- this be a C version, or 753 * justify having it in assembler by making it significantly faster. 754 * 755 * size_t 756 * strlen(const char *s) 757 * { 758 * const char *s0; 759 * #if defined(DEBUG) 760 * if ((uintptr_t)s < KERNELBASE) 761 * panic(.str_panic_msg); 762 * #endif 763 * for (s0 = s; *s; s++) 764 * ; 765 * return (s - s0); 766 * } 767 */ 768 769 ENTRY(strlen) 770#ifdef DEBUG 771 movq kernelbase(%rip), %rax 772 cmpq %rax, %rdi 773 jae str_valid 774 pushq %rbp 775 movq %rsp, %rbp 776 leaq .str_panic_msg(%rip), %rdi 777 xorl %eax, %eax 778 call panic 779#endif /* DEBUG */ 780str_valid: 781 cmpb $0, (%rdi) 782 movq %rdi, %rax 783 je .null_found 784 .align 4 785.strlen_loop: 786 incq %rdi 787 cmpb $0, (%rdi) 788 jne .strlen_loop 789.null_found: 790 subq %rax, %rdi 791 movq %rdi, %rax 792 ret 793 SET_SIZE(strlen) 794 795#elif defined(__i386) 796 797 ENTRY(strlen) 798#ifdef DEBUG 799 movl kernelbase, %eax 800 cmpl %eax, 4(%esp) 801 jae str_valid 802 pushl %ebp 803 movl %esp, %ebp 804 pushl $.str_panic_msg 805 call panic 806#endif /* DEBUG */ 807 808str_valid: 809 movl 4(%esp), %eax /* %eax = string address */ 810 testl $3, %eax /* if %eax not word aligned */ 811 jnz .not_word_aligned /* goto .not_word_aligned */ 812 .align 4 813.word_aligned: 814 movl (%eax), %edx /* move 1 word from (%eax) to %edx */ 815 movl $0x7f7f7f7f, %ecx 816 andl %edx, %ecx /* %ecx = %edx & 0x7f7f7f7f */ 817 addl $4, %eax /* next word */ 818 addl $0x7f7f7f7f, %ecx /* %ecx += 0x7f7f7f7f */ 819 orl %edx, %ecx /* %ecx |= %edx */ 820 andl $0x80808080, %ecx /* %ecx &= 0x80808080 */ 821 cmpl $0x80808080, %ecx /* if no null byte in this word */ 822 je .word_aligned /* goto .word_aligned */ 823 subl $4, %eax /* post-incremented */ 824.not_word_aligned: 825 cmpb $0, (%eax) /* if a byte in (%eax) is null */ 826 je .null_found /* goto .null_found */ 827 incl %eax /* next byte */ 828 testl $3, %eax /* if %eax not word aligned */ 829 jnz .not_word_aligned /* goto .not_word_aligned */ 830 jmp .word_aligned /* goto .word_aligned */ 831 .align 4 832.null_found: 833 subl 4(%esp), %eax /* %eax -= string address */ 834 ret 835 SET_SIZE(strlen) 836 837#endif /* __i386 */ 838 839#ifdef DEBUG 840 .text 841.str_panic_msg: 842 .string "strlen: argument below kernelbase" 843#endif /* DEBUG */ 844 845#endif /* __lint */ 846 847 /* 848 * Berkley 4.3 introduced symbolically named interrupt levels 849 * as a way deal with priority in a machine independent fashion. 850 * Numbered priorities are machine specific, and should be 851 * discouraged where possible. 852 * 853 * Note, for the machine specific priorities there are 854 * examples listed for devices that use a particular priority. 855 * It should not be construed that all devices of that 856 * type should be at that priority. It is currently were 857 * the current devices fit into the priority scheme based 858 * upon time criticalness. 859 * 860 * The underlying assumption of these assignments is that 861 * IPL 10 is the highest level from which a device 862 * routine can call wakeup. Devices that interrupt from higher 863 * levels are restricted in what they can do. If they need 864 * kernels services they should schedule a routine at a lower 865 * level (via software interrupt) to do the required 866 * processing. 867 * 868 * Examples of this higher usage: 869 * Level Usage 870 * 14 Profiling clock (and PROM uart polling clock) 871 * 12 Serial ports 872 * 873 * The serial ports request lower level processing on level 6. 874 * 875 * Also, almost all splN routines (where N is a number or a 876 * mnemonic) will do a RAISE(), on the assumption that they are 877 * never used to lower our priority. 878 * The exceptions are: 879 * spl8() Because you can't be above 15 to begin with! 880 * splzs() Because this is used at boot time to lower our 881 * priority, to allow the PROM to poll the uart. 882 * spl0() Used to lower priority to 0. 883 */ 884 885#if defined(__lint) 886 887int spl0(void) { return (0); } 888int spl6(void) { return (0); } 889int spl7(void) { return (0); } 890int spl8(void) { return (0); } 891int splhigh(void) { return (0); } 892int splhi(void) { return (0); } 893int splzs(void) { return (0); } 894 895#else /* __lint */ 896 897/* reg = cpu->cpu_m.cpu_pri; */ 898#define GETIPL_NOGS(reg, cpup) \ 899 movl CPU_PRI(cpup), reg; 900 901/* cpu->cpu_m.cpu_pri; */ 902#define SETIPL_NOGS(val, cpup) \ 903 movl val, CPU_PRI(cpup); 904 905/* reg = cpu->cpu_m.cpu_pri; */ 906#define GETIPL(reg) \ 907 movl %gs:CPU_PRI, reg; 908 909/* cpu->cpu_m.cpu_pri; */ 910#define SETIPL(val) \ 911 movl val, %gs:CPU_PRI; 912 913/* 914 * Macro to raise processor priority level. 915 * Avoid dropping processor priority if already at high level. 916 * Also avoid going below CPU->cpu_base_spl, which could've just been set by 917 * a higher-level interrupt thread that just blocked. 918 */ 919#if defined(__amd64) 920 921#define RAISE(level) \ 922 cli; \ 923 LOADCPU(%rcx); \ 924 movl $/**/level, %edi;\ 925 GETIPL_NOGS(%eax, %rcx);\ 926 cmpl %eax, %edi; \ 927 jg spl; \ 928 jmp setsplhisti 929 930#elif defined(__i386) 931 932#define RAISE(level) \ 933 cli; \ 934 LOADCPU(%ecx); \ 935 movl $/**/level, %edx;\ 936 GETIPL_NOGS(%eax, %ecx);\ 937 cmpl %eax, %edx; \ 938 jg spl; \ 939 jmp setsplhisti 940 941#endif /* __i386 */ 942 943/* 944 * Macro to set the priority to a specified level. 945 * Avoid dropping the priority below CPU->cpu_base_spl. 946 */ 947#if defined(__amd64) 948 949#define SETPRI(level) \ 950 cli; \ 951 LOADCPU(%rcx); \ 952 movl $/**/level, %edi; \ 953 jmp spl 954 955#elif defined(__i386) 956 957#define SETPRI(level) \ 958 cli; \ 959 LOADCPU(%ecx); \ 960 movl $/**/level, %edx; \ 961 jmp spl 962 963#endif /* __i386 */ 964 965 /* locks out all interrupts, including memory errors */ 966 ENTRY(spl8) 967 SETPRI(15) 968 SET_SIZE(spl8) 969 970 /* just below the level that profiling runs */ 971 ENTRY(spl7) 972 RAISE(13) 973 SET_SIZE(spl7) 974 975 /* sun specific - highest priority onboard serial i/o asy ports */ 976 ENTRY(splzs) 977 SETPRI(12) /* Can't be a RAISE, as it's used to lower us */ 978 SET_SIZE(splzs) 979 980 /* 981 * should lock out clocks and all interrupts, 982 * as you can see, there are exceptions 983 */ 984 985#if defined(__amd64) 986 987 .align 16 988 ENTRY(splhi) 989 ALTENTRY(splhigh) 990 ALTENTRY(spl6) 991 ALTENTRY(i_ddi_splhigh) 992 cli 993 LOADCPU(%rcx) 994 movl $DISP_LEVEL, %edi 995 movl CPU_PRI(%rcx), %eax 996 cmpl %eax, %edi 997 jle setsplhisti 998 SETIPL_NOGS(%edi, %rcx) 999 /* 1000 * If we aren't using cr8 to control ipl then we patch this 1001 * with a jump to slow_setsplhi 1002 */ 1003 ALTENTRY(setsplhi_patch) 1004 movq CPU_PRI_DATA(%rcx), %r11 /* get pri data ptr */ 1005 movzb (%r11, %rdi, 1), %rdx /* get apic mask for this ipl */ 1006 movq %rdx, %cr8 /* set new apic priority */ 1007 /* 1008 * enable interrupts 1009 */ 1010setsplhisti: 1011 nop /* patch this to a sti when a proper setspl routine appears */ 1012 ret 1013 1014 ALTENTRY(slow_setsplhi) 1015 pushq %rbp 1016 movq %rsp, %rbp 1017 subq $16, %rsp 1018 movl %eax, -4(%rbp) /* save old ipl */ 1019 call *setspl(%rip) 1020 movl -4(%rbp), %eax /* return old ipl */ 1021 leave 1022 jmp setsplhisti 1023 1024 SET_SIZE(i_ddi_splhigh) 1025 SET_SIZE(spl6) 1026 SET_SIZE(splhigh) 1027 SET_SIZE(splhi) 1028 1029#elif defined(__i386) 1030 1031 .align 16 1032 ENTRY(splhi) 1033 ALTENTRY(splhigh) 1034 ALTENTRY(spl6) 1035 ALTENTRY(i_ddi_splhigh) 1036 cli 1037 LOADCPU(%ecx) 1038 movl $DISP_LEVEL, %edx 1039 movl CPU_PRI(%ecx), %eax 1040 cmpl %eax, %edx 1041 jle setsplhisti 1042 SETIPL_NOGS(%edx, %ecx) /* set new ipl */ 1043 1044 pushl %eax /* save old ipl */ 1045 pushl %edx /* pass new ipl */ 1046 call *setspl 1047 popl %ecx /* dummy pop */ 1048 popl %eax /* return old ipl */ 1049 /* 1050 * enable interrupts 1051 * 1052 * (we patch this to an sti once a proper setspl routine 1053 * is installed) 1054 */ 1055setsplhisti: 1056 nop /* patch this to a sti when a proper setspl routine appears */ 1057 ret 1058 SET_SIZE(i_ddi_splhigh) 1059 SET_SIZE(spl6) 1060 SET_SIZE(splhigh) 1061 SET_SIZE(splhi) 1062 1063#endif /* __i386 */ 1064 1065 /* allow all interrupts */ 1066 ENTRY(spl0) 1067 SETPRI(0) 1068 SET_SIZE(spl0) 1069 1070#endif /* __lint */ 1071 1072/* 1073 * splr is like splx but will only raise the priority and never drop it 1074 */ 1075#if defined(__lint) 1076 1077/* ARGSUSED */ 1078int 1079splr(int level) 1080{ return (0); } 1081 1082#else /* __lint */ 1083 1084#if defined(__amd64) 1085 1086 ENTRY(splr) 1087 cli 1088 LOADCPU(%rcx) 1089 GETIPL_NOGS(%eax, %rcx) 1090 cmpl %eax, %edi /* if new level > current level */ 1091 jg spl /* then set ipl to new level */ 1092splr_setsti: 1093 nop /* patch this to a sti when a proper setspl routine appears */ 1094 ret /* else return the current level */ 1095 SET_SIZE(splr) 1096 1097#elif defined(__i386) 1098 1099 ENTRY(splr) 1100 cli 1101 LOADCPU(%ecx) 1102 movl 4(%esp), %edx /* get new spl level */ 1103 GETIPL_NOGS(%eax, %ecx) 1104 cmpl %eax, %edx /* if new level > current level */ 1105 jg spl /* then set ipl to new level */ 1106splr_setsti: 1107 nop /* patch this to a sti when a proper setspl routine appears */ 1108 ret /* else return the current level */ 1109 SET_SIZE(splr) 1110 1111#endif /* __i386 */ 1112#endif /* __lint */ 1113 1114 1115 1116/* 1117 * splx - set PIL back to that indicated by the level passed as an argument, 1118 * or to the CPU's base priority, whichever is higher. 1119 * Needs to be fall through to spl to save cycles. 1120 * Algorithm for spl: 1121 * 1122 * turn off interrupts 1123 * 1124 * if (CPU->cpu_base_spl > newipl) 1125 * newipl = CPU->cpu_base_spl; 1126 * oldipl = CPU->cpu_pridata->c_ipl; 1127 * CPU->cpu_pridata->c_ipl = newipl; 1128 * 1129 * /indirectly call function to set spl values (usually setpicmasks) 1130 * setspl(); // load new masks into pics 1131 * 1132 * Be careful not to set priority lower than CPU->cpu_base_pri, 1133 * even though it seems we're raising the priority, it could be set 1134 * higher at any time by an interrupt routine, so we must block interrupts 1135 * and look at CPU->cpu_base_pri 1136 */ 1137#if defined(__lint) 1138 1139/* ARGSUSED */ 1140void 1141splx(int level) 1142{} 1143 1144#else /* __lint */ 1145 1146#if defined(__amd64) 1147 1148 ENTRY(splx) 1149 ALTENTRY(i_ddi_splx) 1150 cli /* disable interrupts */ 1151 LOADCPU(%rcx) 1152 /*FALLTHRU*/ 1153 .align 4 1154spl: 1155 /* 1156 * New priority level is in %edi, cpu struct pointer is in %rcx 1157 */ 1158 GETIPL_NOGS(%eax, %rcx) /* get current ipl */ 1159 cmpl %edi, CPU_BASE_SPL(%rcx) /* if (base spl > new ipl) */ 1160 ja set_to_base_spl /* then use base_spl */ 1161 1162setprilev: 1163 SETIPL_NOGS(%edi, %rcx) /* set new ipl */ 1164 /* 1165 * If we aren't using cr8 to control ipl then we patch this 1166 * with a jump to slow_spl 1167 */ 1168 ALTENTRY(spl_patch) 1169 movq CPU_PRI_DATA(%rcx), %r11 /* get pri data ptr */ 1170 movzb (%r11, %rdi, 1), %rdx /* get apic mask for this ipl */ 1171 movq %rdx, %cr8 /* set new apic priority */ 1172 xorl %edx, %edx 1173 bsrl CPU_SOFTINFO(%rcx), %edx /* fls(cpu->cpu_softinfo.st_pending) */ 1174 cmpl %edi, %edx /* new ipl vs. st_pending */ 1175 jle setsplsti 1176 1177 pushq %rbp 1178 movq %rsp, %rbp 1179 /* stack now 16-byte aligned */ 1180 pushq %rax /* save old spl */ 1181 pushq %rdi /* save new ipl too */ 1182 jmp fakesoftint 1183 1184setsplsti: 1185 nop /* patch this to a sti when a proper setspl routine appears */ 1186 ret 1187 1188 ALTENTRY(slow_spl) 1189 pushq %rbp 1190 movq %rsp, %rbp 1191 /* stack now 16-byte aligned */ 1192 1193 pushq %rax /* save old spl */ 1194 pushq %rdi /* save new ipl too */ 1195 1196 call *setspl(%rip) 1197 1198 LOADCPU(%rcx) 1199 movl CPU_SOFTINFO(%rcx), %eax 1200 orl %eax, %eax 1201 jz slow_setsplsti 1202 1203 bsrl %eax, %edx /* fls(cpu->cpu_softinfo.st_pending) */ 1204 cmpl 0(%rsp), %edx /* new ipl vs. st_pending */ 1205 jg fakesoftint 1206 1207 ALTENTRY(fakesoftint_return) 1208 /* 1209 * enable interrupts 1210 */ 1211slow_setsplsti: 1212 nop /* patch this to a sti when a proper setspl routine appears */ 1213 popq %rdi 1214 popq %rax /* return old ipl */ 1215 leave 1216 ret 1217 SET_SIZE(fakesoftint_return) 1218 1219set_to_base_spl: 1220 movl CPU_BASE_SPL(%rcx), %edi 1221 jmp setprilev 1222 SET_SIZE(spl) 1223 SET_SIZE(i_ddi_splx) 1224 SET_SIZE(splx) 1225 1226#elif defined(__i386) 1227 1228 ENTRY(splx) 1229 ALTENTRY(i_ddi_splx) 1230 cli /* disable interrupts */ 1231 LOADCPU(%ecx) 1232 movl 4(%esp), %edx /* get new spl level */ 1233 /*FALLTHRU*/ 1234 1235 .align 4 1236 ALTENTRY(spl) 1237 /* 1238 * New priority level is in %edx 1239 * (doing this early to avoid an AGI in the next instruction) 1240 */ 1241 GETIPL_NOGS(%eax, %ecx) /* get current ipl */ 1242 cmpl %edx, CPU_BASE_SPL(%ecx) /* if ( base spl > new ipl) */ 1243 ja set_to_base_spl /* then use base_spl */ 1244 1245setprilev: 1246 SETIPL_NOGS(%edx, %ecx) /* set new ipl */ 1247 1248 pushl %eax /* save old ipl */ 1249 pushl %edx /* pass new ipl */ 1250 call *setspl 1251 1252 LOADCPU(%ecx) 1253 movl CPU_SOFTINFO(%ecx), %eax 1254 orl %eax, %eax 1255 jz setsplsti 1256 1257 /* 1258 * Before dashing off, check that setsplsti has been patched. 1259 */ 1260 cmpl $NOP_INSTR, setsplsti 1261 je setsplsti 1262 1263 bsrl %eax, %edx 1264 cmpl 0(%esp), %edx 1265 jg fakesoftint 1266 1267 ALTENTRY(fakesoftint_return) 1268 /* 1269 * enable interrupts 1270 */ 1271setsplsti: 1272 nop /* patch this to a sti when a proper setspl routine appears */ 1273 popl %eax 1274 popl %eax / return old ipl 1275 ret 1276 SET_SIZE(fakesoftint_return) 1277 1278set_to_base_spl: 1279 movl CPU_BASE_SPL(%ecx), %edx 1280 jmp setprilev 1281 SET_SIZE(spl) 1282 SET_SIZE(i_ddi_splx) 1283 SET_SIZE(splx) 1284 1285#endif /* __i386 */ 1286#endif /* __lint */ 1287 1288#if defined(__lint) 1289 1290void 1291install_spl(void) 1292{} 1293 1294#else /* __lint */ 1295 1296#if defined(__amd64) 1297 1298 ENTRY_NP(install_spl) 1299 movq %cr0, %rax 1300 movq %rax, %rdx 1301 movl $_BITNOT(CR0_WP), %ecx 1302 movslq %ecx, %rcx 1303 andq %rcx, %rax /* we don't want to take a fault */ 1304 movq %rax, %cr0 1305 jmp 1f 13061: movb $STI_INSTR, setsplsti(%rip) 1307 movb $STI_INSTR, slow_setsplsti(%rip) 1308 movb $STI_INSTR, setsplhisti(%rip) 1309 movb $STI_INSTR, splr_setsti(%rip) 1310 testl $1, intpri_use_cr8(%rip) /* are using %cr8 ? */ 1311 jz 2f /* no, go patch more */ 1312 movq %rdx, %cr0 1313 ret 13142: 1315 /* 1316 * Patch spl functions to use slow spl method 1317 */ 1318 leaq setsplhi_patch(%rip), %rdi /* get patch point addr */ 1319 leaq slow_setsplhi(%rip), %rax /* jmp target */ 1320 subq %rdi, %rax /* calculate jmp distance */ 1321 subq $2, %rax /* minus size of jmp instr */ 1322 shlq $8, %rax /* construct jmp instr */ 1323 addq $JMP_INSTR, %rax 1324 movw %ax, setsplhi_patch(%rip) /* patch in the jmp */ 1325 leaq spl_patch(%rip), %rdi /* get patch point addr */ 1326 leaq slow_spl(%rip), %rax /* jmp target */ 1327 subq %rdi, %rax /* calculate jmp distance */ 1328 subq $2, %rax /* minus size of jmp instr */ 1329 shlq $8, %rax /* construct jmp instr */ 1330 addq $JMP_INSTR, %rax 1331 movw %ax, spl_patch(%rip) /* patch in the jmp */ 1332 /* 1333 * Ensure %cr8 is zero since we aren't using it 1334 */ 1335 xorl %eax, %eax 1336 movq %rax, %cr8 1337 movq %rdx, %cr0 1338 ret 1339 SET_SIZE(install_spl) 1340 1341#elif defined(__i386) 1342 1343 ENTRY_NP(install_spl) 1344 movl %cr0, %eax 1345 movl %eax, %edx 1346 andl $_BITNOT(CR0_WP), %eax /* we don't want to take a fault */ 1347 movl %eax, %cr0 1348 jmp 1f 13491: movb $STI_INSTR, setsplsti 1350 movb $STI_INSTR, setsplhisti 1351 movb $STI_INSTR, splr_setsti 1352 movl %edx, %cr0 1353 ret 1354 SET_SIZE(install_spl) 1355 1356#endif /* __i386 */ 1357#endif /* __lint */ 1358 1359 1360/* 1361 * Get current processor interrupt level 1362 */ 1363 1364#if defined(__lint) 1365 1366int 1367getpil(void) 1368{ return (0); } 1369 1370#else /* __lint */ 1371 1372#if defined(__amd64) 1373 1374 ENTRY(getpil) 1375 GETIPL(%eax) /* priority level into %eax */ 1376 ret 1377 SET_SIZE(getpil) 1378 1379#elif defined(__i386) 1380 1381 ENTRY(getpil) 1382 GETIPL(%eax) /* priority level into %eax */ 1383 ret 1384 SET_SIZE(getpil) 1385 1386#endif /* __i386 */ 1387#endif /* __lint */ 1388 1389#if defined(__i386) 1390 1391/* 1392 * Read and write the %gs register 1393 */ 1394 1395#if defined(__lint) 1396 1397/*ARGSUSED*/ 1398uint16_t 1399getgs(void) 1400{ return (0); } 1401 1402/*ARGSUSED*/ 1403void 1404setgs(uint16_t sel) 1405{} 1406 1407#else /* __lint */ 1408 1409 ENTRY(getgs) 1410 clr %eax 1411 movw %gs, %ax 1412 ret 1413 SET_SIZE(getgs) 1414 1415 ENTRY(setgs) 1416 movw 4(%esp), %gs 1417 ret 1418 SET_SIZE(setgs) 1419 1420#endif /* __lint */ 1421#endif /* __i386 */ 1422 1423#if defined(__lint) 1424 1425void 1426pc_reset(void) 1427{} 1428 1429#else /* __lint */ 1430 1431 ENTRY(wait_500ms) 1432 movl $50000, %ecx 14331: 1434 call tenmicrosec 1435 loop 1b 1436 ret 1437 SET_SIZE(wait_500ms) 1438 1439#define RESET_METHOD_KBC 1 1440#define RESET_METHOD_PORT92 2 1441#define RESET_METHOD_PCI 4 1442 1443 DGDEF3(pc_reset_methods, 4, 8) 1444 .long RESET_METHOD_KBC|RESET_METHOD_PORT92|RESET_METHOD_PCI; 1445 1446 ENTRY(pc_reset) 1447 1448 testl $RESET_METHOD_KBC, pc_reset_methods 1449 jz 1f 1450 1451 / 1452 / Try the classic keyboard controller-triggered reset. 1453 / 1454 movw $0x64, %dx 1455 movb $0xfe, %al 1456 outb (%dx) 1457 1458 / Wait up to 500 milliseconds here for the keyboard controller 1459 / to pull the reset line. On some systems where the keyboard 1460 / controller is slow to pull the reset line, the next reset method 1461 / may be executed (which may be bad if those systems hang when the 1462 / next reset method is used, e.g. Ferrari 3400 (doesn't like port 92), 1463 / and Ferrari 4000 (doesn't like the cf9 reset method)) 1464 1465 call wait_500ms 1466 14671: 1468 testl $RESET_METHOD_PORT92, pc_reset_methods 1469 jz 3f 1470 1471 / 1472 / Try port 0x92 fast reset 1473 / 1474 movw $0x92, %dx 1475 inb (%dx) 1476 cmpb $0xff, %al / If port's not there, we should get back 0xFF 1477 je 1f 1478 testb $1, %al / If bit 0 1479 jz 2f / is clear, jump to perform the reset 1480 andb $0xfe, %al / otherwise, 1481 outb (%dx) / clear bit 0 first, then 14822: 1483 orb $1, %al / Set bit 0 1484 outb (%dx) / and reset the system 14851: 1486 1487 call wait_500ms 1488 14893: 1490 testl $RESET_METHOD_PCI, pc_reset_methods 1491 jz 4f 1492 1493 / Try the PCI (soft) reset vector (should work on all modern systems, 1494 / but has been shown to cause problems on 450NX systems, and some newer 1495 / systems (e.g. ATI IXP400-equipped systems)) 1496 / When resetting via this method, 2 writes are required. The first 1497 / targets bit 1 (0=hard reset without power cycle, 1=hard reset with 1498 / power cycle). 1499 / The reset occurs on the second write, during bit 2's transition from 1500 / 0->1. 1501 movw $0xcf9, %dx 1502 movb $0x2, %al / Reset mode = hard, no power cycle 1503 outb (%dx) 1504 movb $0x6, %al 1505 outb (%dx) 1506 1507 call wait_500ms 1508 15094: 1510 / 1511 / port 0xcf9 failed also. Last-ditch effort is to 1512 / triple-fault the CPU. 1513 / 1514#if defined(__amd64) 1515 pushq $0x0 1516 pushq $0x0 / IDT base of 0, limit of 0 + 2 unused bytes 1517 lidt (%rsp) 1518#elif defined(__i386) 1519 pushl $0x0 1520 pushl $0x0 / IDT base of 0, limit of 0 + 2 unused bytes 1521 lidt (%esp) 1522#endif 1523 int $0x0 / Trigger interrupt, generate triple-fault 1524 1525 cli 1526 hlt / Wait forever 1527 /*NOTREACHED*/ 1528 SET_SIZE(pc_reset) 1529 1530#endif /* __lint */ 1531 1532/* 1533 * C callable in and out routines 1534 */ 1535 1536#if defined(__lint) 1537 1538/* ARGSUSED */ 1539void 1540outl(int port_address, uint32_t val) 1541{} 1542 1543#else /* __lint */ 1544 1545#if defined(__amd64) 1546 1547 ENTRY(outl) 1548 movw %di, %dx 1549 movl %esi, %eax 1550 outl (%dx) 1551 ret 1552 SET_SIZE(outl) 1553 1554#elif defined(__i386) 1555 1556 .set PORT, 4 1557 .set VAL, 8 1558 1559 ENTRY(outl) 1560 movw PORT(%esp), %dx 1561 movl VAL(%esp), %eax 1562 outl (%dx) 1563 ret 1564 SET_SIZE(outl) 1565 1566#endif /* __i386 */ 1567#endif /* __lint */ 1568 1569#if defined(__lint) 1570 1571/* ARGSUSED */ 1572void 1573outw(int port_address, uint16_t val) 1574{} 1575 1576#else /* __lint */ 1577 1578#if defined(__amd64) 1579 1580 ENTRY(outw) 1581 movw %di, %dx 1582 movw %si, %ax 1583 D16 outl (%dx) /* XX64 why not outw? */ 1584 ret 1585 SET_SIZE(outw) 1586 1587#elif defined(__i386) 1588 1589 ENTRY(outw) 1590 movw PORT(%esp), %dx 1591 movw VAL(%esp), %ax 1592 D16 outl (%dx) 1593 ret 1594 SET_SIZE(outw) 1595 1596#endif /* __i386 */ 1597#endif /* __lint */ 1598 1599#if defined(__lint) 1600 1601/* ARGSUSED */ 1602void 1603outb(int port_address, uint8_t val) 1604{} 1605 1606#else /* __lint */ 1607 1608#if defined(__amd64) 1609 1610 ENTRY(outb) 1611 movw %di, %dx 1612 movb %sil, %al 1613 outb (%dx) 1614 ret 1615 SET_SIZE(outb) 1616 1617#elif defined(__i386) 1618 1619 ENTRY(outb) 1620 movw PORT(%esp), %dx 1621 movb VAL(%esp), %al 1622 outb (%dx) 1623 ret 1624 SET_SIZE(outb) 1625 1626#endif /* __i386 */ 1627#endif /* __lint */ 1628 1629#if defined(__lint) 1630 1631/* ARGSUSED */ 1632uint32_t 1633inl(int port_address) 1634{ return (0); } 1635 1636#else /* __lint */ 1637 1638#if defined(__amd64) 1639 1640 ENTRY(inl) 1641 xorl %eax, %eax 1642 movw %di, %dx 1643 inl (%dx) 1644 ret 1645 SET_SIZE(inl) 1646 1647#elif defined(__i386) 1648 1649 ENTRY(inl) 1650 movw PORT(%esp), %dx 1651 inl (%dx) 1652 ret 1653 SET_SIZE(inl) 1654 1655#endif /* __i386 */ 1656#endif /* __lint */ 1657 1658#if defined(__lint) 1659 1660/* ARGSUSED */ 1661uint16_t 1662inw(int port_address) 1663{ return (0); } 1664 1665#else /* __lint */ 1666 1667#if defined(__amd64) 1668 1669 ENTRY(inw) 1670 xorl %eax, %eax 1671 movw %di, %dx 1672 D16 inl (%dx) 1673 ret 1674 SET_SIZE(inw) 1675 1676#elif defined(__i386) 1677 1678 ENTRY(inw) 1679 subl %eax, %eax 1680 movw PORT(%esp), %dx 1681 D16 inl (%dx) 1682 ret 1683 SET_SIZE(inw) 1684 1685#endif /* __i386 */ 1686#endif /* __lint */ 1687 1688 1689#if defined(__lint) 1690 1691/* ARGSUSED */ 1692uint8_t 1693inb(int port_address) 1694{ return (0); } 1695 1696#else /* __lint */ 1697 1698#if defined(__amd64) 1699 1700 ENTRY(inb) 1701 xorl %eax, %eax 1702 movw %di, %dx 1703 inb (%dx) 1704 ret 1705 SET_SIZE(inb) 1706 1707#elif defined(__i386) 1708 1709 ENTRY(inb) 1710 subl %eax, %eax 1711 movw PORT(%esp), %dx 1712 inb (%dx) 1713 ret 1714 SET_SIZE(inb) 1715 1716#endif /* __i386 */ 1717#endif /* __lint */ 1718 1719 1720#if defined(__lint) 1721 1722/* ARGSUSED */ 1723void 1724repoutsw(int port, uint16_t *addr, int cnt) 1725{} 1726 1727#else /* __lint */ 1728 1729#if defined(__amd64) 1730 1731 ENTRY(repoutsw) 1732 movl %edx, %ecx 1733 movw %di, %dx 1734 rep 1735 D16 outsl 1736 ret 1737 SET_SIZE(repoutsw) 1738 1739#elif defined(__i386) 1740 1741 /* 1742 * The arguments and saved registers are on the stack in the 1743 * following order: 1744 * | cnt | +16 1745 * | *addr | +12 1746 * | port | +8 1747 * | eip | +4 1748 * | esi | <-- %esp 1749 * If additional values are pushed onto the stack, make sure 1750 * to adjust the following constants accordingly. 1751 */ 1752 .set PORT, 8 1753 .set ADDR, 12 1754 .set COUNT, 16 1755 1756 ENTRY(repoutsw) 1757 pushl %esi 1758 movl PORT(%esp), %edx 1759 movl ADDR(%esp), %esi 1760 movl COUNT(%esp), %ecx 1761 rep 1762 D16 outsl 1763 popl %esi 1764 ret 1765 SET_SIZE(repoutsw) 1766 1767#endif /* __i386 */ 1768#endif /* __lint */ 1769 1770 1771#if defined(__lint) 1772 1773/* ARGSUSED */ 1774void 1775repinsw(int port_addr, uint16_t *addr, int cnt) 1776{} 1777 1778#else /* __lint */ 1779 1780#if defined(__amd64) 1781 1782 ENTRY(repinsw) 1783 movl %edx, %ecx 1784 movw %di, %dx 1785 rep 1786 D16 insl 1787 ret 1788 SET_SIZE(repinsw) 1789 1790#elif defined(__i386) 1791 1792 ENTRY(repinsw) 1793 pushl %edi 1794 movl PORT(%esp), %edx 1795 movl ADDR(%esp), %edi 1796 movl COUNT(%esp), %ecx 1797 rep 1798 D16 insl 1799 popl %edi 1800 ret 1801 SET_SIZE(repinsw) 1802 1803#endif /* __i386 */ 1804#endif /* __lint */ 1805 1806 1807#if defined(__lint) 1808 1809/* ARGSUSED */ 1810void 1811repinsb(int port, uint8_t *addr, int count) 1812{} 1813 1814#else /* __lint */ 1815 1816#if defined(__amd64) 1817 1818 ENTRY(repinsb) 1819 movl %edx, %ecx 1820 movw %di, %dx 1821 movq %rsi, %rdi 1822 rep 1823 insb 1824 ret 1825 SET_SIZE(repinsb) 1826 1827#elif defined(__i386) 1828 1829 /* 1830 * The arguments and saved registers are on the stack in the 1831 * following order: 1832 * | cnt | +16 1833 * | *addr | +12 1834 * | port | +8 1835 * | eip | +4 1836 * | esi | <-- %esp 1837 * If additional values are pushed onto the stack, make sure 1838 * to adjust the following constants accordingly. 1839 */ 1840 .set IO_PORT, 8 1841 .set IO_ADDR, 12 1842 .set IO_COUNT, 16 1843 1844 ENTRY(repinsb) 1845 pushl %edi 1846 movl IO_ADDR(%esp), %edi 1847 movl IO_COUNT(%esp), %ecx 1848 movl IO_PORT(%esp), %edx 1849 rep 1850 insb 1851 popl %edi 1852 ret 1853 SET_SIZE(repinsb) 1854 1855#endif /* __i386 */ 1856#endif /* __lint */ 1857 1858 1859/* 1860 * Input a stream of 32-bit words. 1861 * NOTE: count is a DWORD count. 1862 */ 1863#if defined(__lint) 1864 1865/* ARGSUSED */ 1866void 1867repinsd(int port, uint32_t *addr, int count) 1868{} 1869 1870#else /* __lint */ 1871 1872#if defined(__amd64) 1873 1874 ENTRY(repinsd) 1875 movl %edx, %ecx 1876 movw %di, %dx 1877 movq %rsi, %rdi 1878 rep 1879 insl 1880 ret 1881 SET_SIZE(repinsd) 1882 1883#elif defined(__i386) 1884 1885 ENTRY(repinsd) 1886 pushl %edi 1887 movl IO_ADDR(%esp), %edi 1888 movl IO_COUNT(%esp), %ecx 1889 movl IO_PORT(%esp), %edx 1890 rep 1891 insl 1892 popl %edi 1893 ret 1894 SET_SIZE(repinsd) 1895 1896#endif /* __i386 */ 1897#endif /* __lint */ 1898 1899/* 1900 * Output a stream of bytes 1901 * NOTE: count is a byte count 1902 */ 1903#if defined(__lint) 1904 1905/* ARGSUSED */ 1906void 1907repoutsb(int port, uint8_t *addr, int count) 1908{} 1909 1910#else /* __lint */ 1911 1912#if defined(__amd64) 1913 1914 ENTRY(repoutsb) 1915 movl %edx, %ecx 1916 movw %di, %dx 1917 rep 1918 outsb 1919 ret 1920 SET_SIZE(repoutsb) 1921 1922#elif defined(__i386) 1923 1924 ENTRY(repoutsb) 1925 pushl %esi 1926 movl IO_ADDR(%esp), %esi 1927 movl IO_COUNT(%esp), %ecx 1928 movl IO_PORT(%esp), %edx 1929 rep 1930 outsb 1931 popl %esi 1932 ret 1933 SET_SIZE(repoutsb) 1934 1935#endif /* __i386 */ 1936#endif /* __lint */ 1937 1938/* 1939 * Output a stream of 32-bit words 1940 * NOTE: count is a DWORD count 1941 */ 1942#if defined(__lint) 1943 1944/* ARGSUSED */ 1945void 1946repoutsd(int port, uint32_t *addr, int count) 1947{} 1948 1949#else /* __lint */ 1950 1951#if defined(__amd64) 1952 1953 ENTRY(repoutsd) 1954 movl %edx, %ecx 1955 movw %di, %dx 1956 rep 1957 outsl 1958 ret 1959 SET_SIZE(repoutsd) 1960 1961#elif defined(__i386) 1962 1963 ENTRY(repoutsd) 1964 pushl %esi 1965 movl IO_ADDR(%esp), %esi 1966 movl IO_COUNT(%esp), %ecx 1967 movl IO_PORT(%esp), %edx 1968 rep 1969 outsl 1970 popl %esi 1971 ret 1972 SET_SIZE(repoutsd) 1973 1974#endif /* __i386 */ 1975#endif /* __lint */ 1976 1977/* 1978 * void int20(void) 1979 */ 1980 1981#if defined(__lint) 1982 1983void 1984int20(void) 1985{} 1986 1987#else /* __lint */ 1988 1989 ENTRY(int20) 1990 movl boothowto, %eax 1991 andl $RB_DEBUG, %eax 1992 jz 1f 1993 1994 int $20 19951: 1996 rep; ret /* use 2 byte return instruction when branch target */ 1997 /* AMD Software Optimization Guide - Section 6.2 */ 1998 SET_SIZE(int20) 1999 2000#endif /* __lint */ 2001 2002#if defined(__lint) 2003 2004/* ARGSUSED */ 2005int 2006scanc(size_t size, uchar_t *cp, uchar_t *table, uchar_t mask) 2007{ return (0); } 2008 2009#else /* __lint */ 2010 2011#if defined(__amd64) 2012 2013 ENTRY(scanc) 2014 /* rdi == size */ 2015 /* rsi == cp */ 2016 /* rdx == table */ 2017 /* rcx == mask */ 2018 addq %rsi, %rdi /* end = &cp[size] */ 2019.scanloop: 2020 cmpq %rdi, %rsi /* while (cp < end */ 2021 jnb .scandone 2022 movzbq (%rsi), %r8 /* %r8 = *cp */ 2023 incq %rsi /* cp++ */ 2024 testb %cl, (%r8, %rdx) 2025 jz .scanloop /* && (table[*cp] & mask) == 0) */ 2026 decq %rsi /* (fix post-increment) */ 2027.scandone: 2028 movl %edi, %eax 2029 subl %esi, %eax /* return (end - cp) */ 2030 ret 2031 SET_SIZE(scanc) 2032 2033#elif defined(__i386) 2034 2035 ENTRY(scanc) 2036 pushl %edi 2037 pushl %esi 2038 movb 24(%esp), %cl /* mask = %cl */ 2039 movl 16(%esp), %esi /* cp = %esi */ 2040 movl 20(%esp), %edx /* table = %edx */ 2041 movl %esi, %edi 2042 addl 12(%esp), %edi /* end = &cp[size]; */ 2043.scanloop: 2044 cmpl %edi, %esi /* while (cp < end */ 2045 jnb .scandone 2046 movzbl (%esi), %eax /* %al = *cp */ 2047 incl %esi /* cp++ */ 2048 movb (%edx, %eax), %al /* %al = table[*cp] */ 2049 testb %al, %cl 2050 jz .scanloop /* && (table[*cp] & mask) == 0) */ 2051 dec %esi /* post-incremented */ 2052.scandone: 2053 movl %edi, %eax 2054 subl %esi, %eax /* return (end - cp) */ 2055 popl %esi 2056 popl %edi 2057 ret 2058 SET_SIZE(scanc) 2059 2060#endif /* __i386 */ 2061#endif /* __lint */ 2062 2063/* 2064 * Replacement functions for ones that are normally inlined. 2065 * In addition to the copy in i86.il, they are defined here just in case. 2066 */ 2067 2068#if defined(__lint) 2069 2070int 2071intr_clear(void) 2072{ return 0; } 2073 2074int 2075clear_int_flag(void) 2076{ return 0; } 2077 2078#else /* __lint */ 2079 2080#if defined(__amd64) 2081 2082 ENTRY(intr_clear) 2083 ENTRY(clear_int_flag) 2084 pushfq 2085 cli 2086 popq %rax 2087 ret 2088 SET_SIZE(clear_int_flag) 2089 SET_SIZE(intr_clear) 2090 2091#elif defined(__i386) 2092 2093 ENTRY(intr_clear) 2094 ENTRY(clear_int_flag) 2095 pushfl 2096 cli 2097 popl %eax 2098 ret 2099 SET_SIZE(clear_int_flag) 2100 SET_SIZE(intr_clear) 2101 2102#endif /* __i386 */ 2103#endif /* __lint */ 2104 2105#if defined(__lint) 2106 2107struct cpu * 2108curcpup(void) 2109{ return 0; } 2110 2111#else /* __lint */ 2112 2113#if defined(__amd64) 2114 2115 ENTRY(curcpup) 2116 movq %gs:CPU_SELF, %rax 2117 ret 2118 SET_SIZE(curcpup) 2119 2120#elif defined(__i386) 2121 2122 ENTRY(curcpup) 2123 movl %gs:CPU_SELF, %eax 2124 ret 2125 SET_SIZE(curcpup) 2126 2127#endif /* __i386 */ 2128#endif /* __lint */ 2129 2130#if defined(__lint) 2131 2132/* ARGSUSED */ 2133uint32_t 2134htonl(uint32_t i) 2135{ return (0); } 2136 2137/* ARGSUSED */ 2138uint32_t 2139ntohl(uint32_t i) 2140{ return (0); } 2141 2142#else /* __lint */ 2143 2144#if defined(__amd64) 2145 2146 /* XX64 there must be shorter sequences for this */ 2147 ENTRY(htonl) 2148 ALTENTRY(ntohl) 2149 movl %edi, %eax 2150 bswap %eax 2151 ret 2152 SET_SIZE(ntohl) 2153 SET_SIZE(htonl) 2154 2155#elif defined(__i386) 2156 2157 ENTRY(htonl) 2158 ALTENTRY(ntohl) 2159 movl 4(%esp), %eax 2160 bswap %eax 2161 ret 2162 SET_SIZE(ntohl) 2163 SET_SIZE(htonl) 2164 2165#endif /* __i386 */ 2166#endif /* __lint */ 2167 2168#if defined(__lint) 2169 2170/* ARGSUSED */ 2171uint16_t 2172htons(uint16_t i) 2173{ return (0); } 2174 2175/* ARGSUSED */ 2176uint16_t 2177ntohs(uint16_t i) 2178{ return (0); } 2179 2180 2181#else /* __lint */ 2182 2183#if defined(__amd64) 2184 2185 /* XX64 there must be better sequences for this */ 2186 ENTRY(htons) 2187 ALTENTRY(ntohs) 2188 movl %edi, %eax 2189 bswap %eax 2190 shrl $16, %eax 2191 ret 2192 SET_SIZE(ntohs) 2193 SET_SIZE(htons) 2194 2195#elif defined(__i386) 2196 2197 ENTRY(htons) 2198 ALTENTRY(ntohs) 2199 movl 4(%esp), %eax 2200 bswap %eax 2201 shrl $16, %eax 2202 ret 2203 SET_SIZE(ntohs) 2204 SET_SIZE(htons) 2205 2206#endif /* __i386 */ 2207#endif /* __lint */ 2208 2209 2210#if defined(__lint) 2211 2212/* ARGSUSED */ 2213void 2214intr_restore(uint_t i) 2215{ return; } 2216 2217/* ARGSUSED */ 2218void 2219restore_int_flag(int i) 2220{ return; } 2221 2222#else /* __lint */ 2223 2224#if defined(__amd64) 2225 2226 ENTRY(intr_restore) 2227 ENTRY(restore_int_flag) 2228 pushq %rdi 2229 popfq 2230 ret 2231 SET_SIZE(restore_int_flag) 2232 SET_SIZE(intr_restore) 2233 2234#elif defined(__i386) 2235 2236 ENTRY(intr_restore) 2237 ENTRY(restore_int_flag) 2238 pushl 4(%esp) 2239 popfl 2240 ret 2241 SET_SIZE(restore_int_flag) 2242 SET_SIZE(intr_restore) 2243 2244#endif /* __i386 */ 2245#endif /* __lint */ 2246 2247#if defined(__lint) 2248 2249void 2250sti(void) 2251{} 2252 2253#else /* __lint */ 2254 2255 ENTRY(sti) 2256 sti 2257 ret 2258 SET_SIZE(sti) 2259 2260#endif /* __lint */ 2261 2262#if defined(__lint) 2263 2264dtrace_icookie_t 2265dtrace_interrupt_disable(void) 2266{ return (0); } 2267 2268#else /* __lint */ 2269 2270#if defined(__amd64) 2271 2272 ENTRY(dtrace_interrupt_disable) 2273 pushfq 2274 popq %rax 2275 cli 2276 ret 2277 SET_SIZE(dtrace_interrupt_disable) 2278 2279#elif defined(__i386) 2280 2281 ENTRY(dtrace_interrupt_disable) 2282 pushfl 2283 popl %eax 2284 cli 2285 ret 2286 SET_SIZE(dtrace_interrupt_disable) 2287 2288#endif /* __i386 */ 2289#endif /* __lint */ 2290 2291#if defined(__lint) 2292 2293/*ARGSUSED*/ 2294void 2295dtrace_interrupt_enable(dtrace_icookie_t cookie) 2296{} 2297 2298#else /* __lint */ 2299 2300#if defined(__amd64) 2301 2302 ENTRY(dtrace_interrupt_enable) 2303 pushq %rdi 2304 popfq 2305 ret 2306 SET_SIZE(dtrace_interrupt_enable) 2307 2308#elif defined(__i386) 2309 2310 ENTRY(dtrace_interrupt_enable) 2311 movl 4(%esp), %eax 2312 pushl %eax 2313 popfl 2314 ret 2315 SET_SIZE(dtrace_interrupt_enable) 2316 2317#endif /* __i386 */ 2318#endif /* __lint */ 2319 2320 2321#if defined(lint) 2322 2323void 2324dtrace_membar_producer(void) 2325{} 2326 2327void 2328dtrace_membar_consumer(void) 2329{} 2330 2331#else /* __lint */ 2332 2333 ENTRY(dtrace_membar_producer) 2334 rep; ret /* use 2 byte return instruction when branch target */ 2335 /* AMD Software Optimization Guide - Section 6.2 */ 2336 SET_SIZE(dtrace_membar_producer) 2337 2338 ENTRY(dtrace_membar_consumer) 2339 rep; ret /* use 2 byte return instruction when branch target */ 2340 /* AMD Software Optimization Guide - Section 6.2 */ 2341 SET_SIZE(dtrace_membar_consumer) 2342 2343#endif /* __lint */ 2344 2345#if defined(__lint) 2346 2347kthread_id_t 2348threadp(void) 2349{ return ((kthread_id_t)0); } 2350 2351#else /* __lint */ 2352 2353#if defined(__amd64) 2354 2355 ENTRY(threadp) 2356 movq %gs:CPU_THREAD, %rax 2357 ret 2358 SET_SIZE(threadp) 2359 2360#elif defined(__i386) 2361 2362 ENTRY(threadp) 2363 movl %gs:CPU_THREAD, %eax 2364 ret 2365 SET_SIZE(threadp) 2366 2367#endif /* __i386 */ 2368#endif /* __lint */ 2369 2370/* 2371 * Checksum routine for Internet Protocol Headers 2372 */ 2373 2374#if defined(__lint) 2375 2376/* ARGSUSED */ 2377unsigned int 2378ip_ocsum( 2379 ushort_t *address, /* ptr to 1st message buffer */ 2380 int halfword_count, /* length of data */ 2381 unsigned int sum) /* partial checksum */ 2382{ 2383 int i; 2384 unsigned int psum = 0; /* partial sum */ 2385 2386 for (i = 0; i < halfword_count; i++, address++) { 2387 psum += *address; 2388 } 2389 2390 while ((psum >> 16) != 0) { 2391 psum = (psum & 0xffff) + (psum >> 16); 2392 } 2393 2394 psum += sum; 2395 2396 while ((psum >> 16) != 0) { 2397 psum = (psum & 0xffff) + (psum >> 16); 2398 } 2399 2400 return (psum); 2401} 2402 2403#else /* __lint */ 2404 2405#if defined(__amd64) 2406 2407 ENTRY(ip_ocsum) 2408 pushq %rbp 2409 movq %rsp, %rbp 2410#ifdef DEBUG 2411 movq kernelbase(%rip), %rax 2412 cmpq %rax, %rdi 2413 jnb 1f 2414 xorl %eax, %eax 2415 movq %rdi, %rsi 2416 leaq .ip_ocsum_panic_msg(%rip), %rdi 2417 call panic 2418 /*NOTREACHED*/ 2419.ip_ocsum_panic_msg: 2420 .string "ip_ocsum: address 0x%p below kernelbase\n" 24211: 2422#endif 2423 movl %esi, %ecx /* halfword_count */ 2424 movq %rdi, %rsi /* address */ 2425 /* partial sum in %edx */ 2426 xorl %eax, %eax 2427 testl %ecx, %ecx 2428 jz .ip_ocsum_done 2429 testq $3, %rsi 2430 jnz .ip_csum_notaligned 2431.ip_csum_aligned: /* XX64 opportunities for 8-byte operations? */ 2432.next_iter: 2433 /* XX64 opportunities for prefetch? */ 2434 /* XX64 compute csum with 64 bit quantities? */ 2435 subl $32, %ecx 2436 jl .less_than_32 2437 2438 addl 0(%rsi), %edx 2439.only60: 2440 adcl 4(%rsi), %eax 2441.only56: 2442 adcl 8(%rsi), %edx 2443.only52: 2444 adcl 12(%rsi), %eax 2445.only48: 2446 adcl 16(%rsi), %edx 2447.only44: 2448 adcl 20(%rsi), %eax 2449.only40: 2450 adcl 24(%rsi), %edx 2451.only36: 2452 adcl 28(%rsi), %eax 2453.only32: 2454 adcl 32(%rsi), %edx 2455.only28: 2456 adcl 36(%rsi), %eax 2457.only24: 2458 adcl 40(%rsi), %edx 2459.only20: 2460 adcl 44(%rsi), %eax 2461.only16: 2462 adcl 48(%rsi), %edx 2463.only12: 2464 adcl 52(%rsi), %eax 2465.only8: 2466 adcl 56(%rsi), %edx 2467.only4: 2468 adcl 60(%rsi), %eax /* could be adding -1 and -1 with a carry */ 2469.only0: 2470 adcl $0, %eax /* could be adding -1 in eax with a carry */ 2471 adcl $0, %eax 2472 2473 addq $64, %rsi 2474 testl %ecx, %ecx 2475 jnz .next_iter 2476 2477.ip_ocsum_done: 2478 addl %eax, %edx 2479 adcl $0, %edx 2480 movl %edx, %eax /* form a 16 bit checksum by */ 2481 shrl $16, %eax /* adding two halves of 32 bit checksum */ 2482 addw %dx, %ax 2483 adcw $0, %ax 2484 andl $0xffff, %eax 2485 leave 2486 ret 2487 2488.ip_csum_notaligned: 2489 xorl %edi, %edi 2490 movw (%rsi), %di 2491 addl %edi, %edx 2492 adcl $0, %edx 2493 addq $2, %rsi 2494 decl %ecx 2495 jmp .ip_csum_aligned 2496 2497.less_than_32: 2498 addl $32, %ecx 2499 testl $1, %ecx 2500 jz .size_aligned 2501 andl $0xfe, %ecx 2502 movzwl (%rsi, %rcx, 2), %edi 2503 addl %edi, %edx 2504 adcl $0, %edx 2505.size_aligned: 2506 movl %ecx, %edi 2507 shrl $1, %ecx 2508 shl $1, %edi 2509 subq $64, %rdi 2510 addq %rdi, %rsi 2511 leaq .ip_ocsum_jmptbl(%rip), %rdi 2512 leaq (%rdi, %rcx, 8), %rdi 2513 xorl %ecx, %ecx 2514 clc 2515 jmp *(%rdi) 2516 2517 .align 8 2518.ip_ocsum_jmptbl: 2519 .quad .only0, .only4, .only8, .only12, .only16, .only20 2520 .quad .only24, .only28, .only32, .only36, .only40, .only44 2521 .quad .only48, .only52, .only56, .only60 2522 SET_SIZE(ip_ocsum) 2523 2524#elif defined(__i386) 2525 2526 ENTRY(ip_ocsum) 2527 pushl %ebp 2528 movl %esp, %ebp 2529 pushl %ebx 2530 pushl %esi 2531 pushl %edi 2532 movl 12(%ebp), %ecx /* count of half words */ 2533 movl 16(%ebp), %edx /* partial checksum */ 2534 movl 8(%ebp), %esi 2535 xorl %eax, %eax 2536 testl %ecx, %ecx 2537 jz .ip_ocsum_done 2538 2539 testl $3, %esi 2540 jnz .ip_csum_notaligned 2541.ip_csum_aligned: 2542.next_iter: 2543 subl $32, %ecx 2544 jl .less_than_32 2545 2546 addl 0(%esi), %edx 2547.only60: 2548 adcl 4(%esi), %eax 2549.only56: 2550 adcl 8(%esi), %edx 2551.only52: 2552 adcl 12(%esi), %eax 2553.only48: 2554 adcl 16(%esi), %edx 2555.only44: 2556 adcl 20(%esi), %eax 2557.only40: 2558 adcl 24(%esi), %edx 2559.only36: 2560 adcl 28(%esi), %eax 2561.only32: 2562 adcl 32(%esi), %edx 2563.only28: 2564 adcl 36(%esi), %eax 2565.only24: 2566 adcl 40(%esi), %edx 2567.only20: 2568 adcl 44(%esi), %eax 2569.only16: 2570 adcl 48(%esi), %edx 2571.only12: 2572 adcl 52(%esi), %eax 2573.only8: 2574 adcl 56(%esi), %edx 2575.only4: 2576 adcl 60(%esi), %eax /* We could be adding -1 and -1 with a carry */ 2577.only0: 2578 adcl $0, %eax /* we could be adding -1 in eax with a carry */ 2579 adcl $0, %eax 2580 2581 addl $64, %esi 2582 andl %ecx, %ecx 2583 jnz .next_iter 2584 2585.ip_ocsum_done: 2586 addl %eax, %edx 2587 adcl $0, %edx 2588 movl %edx, %eax /* form a 16 bit checksum by */ 2589 shrl $16, %eax /* adding two halves of 32 bit checksum */ 2590 addw %dx, %ax 2591 adcw $0, %ax 2592 andl $0xffff, %eax 2593 popl %edi /* restore registers */ 2594 popl %esi 2595 popl %ebx 2596 leave 2597 ret 2598 2599.ip_csum_notaligned: 2600 xorl %edi, %edi 2601 movw (%esi), %di 2602 addl %edi, %edx 2603 adcl $0, %edx 2604 addl $2, %esi 2605 decl %ecx 2606 jmp .ip_csum_aligned 2607 2608.less_than_32: 2609 addl $32, %ecx 2610 testl $1, %ecx 2611 jz .size_aligned 2612 andl $0xfe, %ecx 2613 movzwl (%esi, %ecx, 2), %edi 2614 addl %edi, %edx 2615 adcl $0, %edx 2616.size_aligned: 2617 movl %ecx, %edi 2618 shrl $1, %ecx 2619 shl $1, %edi 2620 subl $64, %edi 2621 addl %edi, %esi 2622 movl $.ip_ocsum_jmptbl, %edi 2623 lea (%edi, %ecx, 4), %edi 2624 xorl %ecx, %ecx 2625 clc 2626 jmp *(%edi) 2627 SET_SIZE(ip_ocsum) 2628 2629 .data 2630 .align 4 2631 2632.ip_ocsum_jmptbl: 2633 .long .only0, .only4, .only8, .only12, .only16, .only20 2634 .long .only24, .only28, .only32, .only36, .only40, .only44 2635 .long .only48, .only52, .only56, .only60 2636 2637 2638#endif /* __i386 */ 2639#endif /* __lint */ 2640 2641/* 2642 * multiply two long numbers and yield a u_longlong_t result, callable from C. 2643 * Provided to manipulate hrtime_t values. 2644 */ 2645#if defined(__lint) 2646 2647/* result = a * b; */ 2648 2649/* ARGSUSED */ 2650unsigned long long 2651mul32(uint_t a, uint_t b) 2652{ return (0); } 2653 2654#else /* __lint */ 2655 2656#if defined(__amd64) 2657 2658 ENTRY(mul32) 2659 xorl %edx, %edx /* XX64 joe, paranoia? */ 2660 movl %edi, %eax 2661 mull %esi 2662 shlq $32, %rdx 2663 orq %rdx, %rax 2664 ret 2665 SET_SIZE(mul32) 2666 2667#elif defined(__i386) 2668 2669 ENTRY(mul32) 2670 movl 8(%esp), %eax 2671 movl 4(%esp), %ecx 2672 mull %ecx 2673 ret 2674 SET_SIZE(mul32) 2675 2676#endif /* __i386 */ 2677#endif /* __lint */ 2678 2679#if defined(notused) 2680#if defined(__lint) 2681/* ARGSUSED */ 2682void 2683load_pte64(uint64_t *pte, uint64_t pte_value) 2684{} 2685#else /* __lint */ 2686 .globl load_pte64 2687load_pte64: 2688 movl 4(%esp), %eax 2689 movl 8(%esp), %ecx 2690 movl 12(%esp), %edx 2691 movl %edx, 4(%eax) 2692 movl %ecx, (%eax) 2693 ret 2694#endif /* __lint */ 2695#endif /* notused */ 2696 2697#if defined(__lint) 2698 2699/*ARGSUSED*/ 2700void 2701scan_memory(caddr_t addr, size_t size) 2702{} 2703 2704#else /* __lint */ 2705 2706#if defined(__amd64) 2707 2708 ENTRY(scan_memory) 2709 shrq $3, %rsi /* convert %rsi from byte to quadword count */ 2710 jz .scanm_done 2711 movq %rsi, %rcx /* move count into rep control register */ 2712 movq %rdi, %rsi /* move addr into lodsq control reg. */ 2713 rep lodsq /* scan the memory range */ 2714.scanm_done: 2715 rep; ret /* use 2 byte return instruction when branch target */ 2716 /* AMD Software Optimization Guide - Section 6.2 */ 2717 SET_SIZE(scan_memory) 2718 2719#elif defined(__i386) 2720 2721 ENTRY(scan_memory) 2722 pushl %ecx 2723 pushl %esi 2724 movl 16(%esp), %ecx /* move 2nd arg into rep control register */ 2725 shrl $2, %ecx /* convert from byte count to word count */ 2726 jz .scanm_done 2727 movl 12(%esp), %esi /* move 1st arg into lodsw control register */ 2728 .byte 0xf3 /* rep prefix. lame assembler. sigh. */ 2729 lodsl 2730.scanm_done: 2731 popl %esi 2732 popl %ecx 2733 ret 2734 SET_SIZE(scan_memory) 2735 2736#endif /* __i386 */ 2737#endif /* __lint */ 2738 2739 2740#if defined(__lint) 2741 2742/*ARGSUSED */ 2743int 2744lowbit(ulong_t i) 2745{ return (0); } 2746 2747#else /* __lint */ 2748 2749#if defined(__amd64) 2750 2751 ENTRY(lowbit) 2752 movl $-1, %eax 2753 bsfq %rdi, %rax 2754 incl %eax 2755 ret 2756 SET_SIZE(lowbit) 2757 2758#elif defined(__i386) 2759 2760 ENTRY(lowbit) 2761 movl $-1, %eax 2762 bsfl 4(%esp), %eax 2763 incl %eax 2764 ret 2765 SET_SIZE(lowbit) 2766 2767#endif /* __i386 */ 2768#endif /* __lint */ 2769 2770#if defined(__lint) 2771 2772/*ARGSUSED*/ 2773int 2774highbit(ulong_t i) 2775{ return (0); } 2776 2777#else /* __lint */ 2778 2779#if defined(__amd64) 2780 2781 ENTRY(highbit) 2782 movl $-1, %eax 2783 bsrq %rdi, %rax 2784 incl %eax 2785 ret 2786 SET_SIZE(highbit) 2787 2788#elif defined(__i386) 2789 2790 ENTRY(highbit) 2791 movl $-1, %eax 2792 bsrl 4(%esp), %eax 2793 incl %eax 2794 ret 2795 SET_SIZE(highbit) 2796 2797#endif /* __i386 */ 2798#endif /* __lint */ 2799 2800#if defined(__lint) 2801 2802/*ARGSUSED*/ 2803uint64_t 2804rdmsr(uint_t r) 2805{ return (0); } 2806 2807/*ARGSUSED*/ 2808void 2809wrmsr(uint_t r, const uint64_t val) 2810{} 2811 2812void 2813invalidate_cache(void) 2814{} 2815 2816#else /* __lint */ 2817 2818#if defined(__amd64) 2819 2820 ENTRY(rdmsr) 2821 movl %edi, %ecx 2822 rdmsr 2823 shlq $32, %rdx 2824 orq %rdx, %rax 2825 ret 2826 SET_SIZE(rdmsr) 2827 2828 ENTRY(wrmsr) 2829 movq %rsi, %rdx 2830 shrq $32, %rdx 2831 movl %esi, %eax 2832 movl %edi, %ecx 2833 wrmsr 2834 ret 2835 SET_SIZE(wrmsr) 2836 2837#elif defined(__i386) 2838 2839 ENTRY(rdmsr) 2840 movl 4(%esp), %ecx 2841 rdmsr 2842 ret 2843 SET_SIZE(rdmsr) 2844 2845 ENTRY(wrmsr) 2846 movl 4(%esp), %ecx 2847 movl 8(%esp), %eax 2848 movl 12(%esp), %edx 2849 wrmsr 2850 ret 2851 SET_SIZE(wrmsr) 2852 2853#endif /* __i386 */ 2854 2855 ENTRY(invalidate_cache) 2856 wbinvd 2857 ret 2858 SET_SIZE(invalidate_cache) 2859 2860#endif /* __lint */ 2861 2862#if defined(__lint) 2863 2864/*ARGSUSED*/ 2865void getcregs(struct cregs *crp) 2866{} 2867 2868#else /* __lint */ 2869 2870#if defined(__amd64) 2871 2872#define GETMSR(r, off, d) \ 2873 movl $r, %ecx; \ 2874 rdmsr; \ 2875 movl %eax, off(d); \ 2876 movl %edx, off+4(d) 2877 2878 ENTRY_NP(getcregs) 2879 xorl %eax, %eax 2880 movq %rax, CREG_GDT+8(%rdi) 2881 sgdt CREG_GDT(%rdi) /* 10 bytes */ 2882 movq %rax, CREG_IDT+8(%rdi) 2883 sidt CREG_IDT(%rdi) /* 10 bytes */ 2884 movq %rax, CREG_LDT(%rdi) 2885 sldt CREG_LDT(%rdi) /* 2 bytes */ 2886 movq %rax, CREG_TASKR(%rdi) 2887 str CREG_TASKR(%rdi) /* 2 bytes */ 2888 movq %cr0, %rax 2889 movq %rax, CREG_CR0(%rdi) /* cr0 */ 2890 movq %cr2, %rax 2891 movq %rax, CREG_CR2(%rdi) /* cr2 */ 2892 movq %cr3, %rax 2893 movq %rax, CREG_CR3(%rdi) /* cr3 */ 2894 movq %cr4, %rax 2895 movq %rax, CREG_CR8(%rdi) /* cr4 */ 2896 movq %cr8, %rax 2897 movq %rax, CREG_CR8(%rdi) /* cr8 */ 2898 GETMSR(MSR_AMD_KGSBASE, CREG_KGSBASE, %rdi) 2899 GETMSR(MSR_AMD_EFER, CREG_EFER, %rdi) 2900 SET_SIZE(getcregs) 2901 2902#undef GETMSR 2903 2904#elif defined(__i386) 2905 2906 ENTRY_NP(getcregs) 2907 movl 4(%esp), %edx 2908 movw $0, CREG_GDT+6(%edx) 2909 movw $0, CREG_IDT+6(%edx) 2910 sgdt CREG_GDT(%edx) /* gdt */ 2911 sidt CREG_IDT(%edx) /* idt */ 2912 sldt CREG_LDT(%edx) /* ldt */ 2913 str CREG_TASKR(%edx) /* task */ 2914 movl %cr0, %eax 2915 movl %eax, CREG_CR0(%edx) /* cr0 */ 2916 movl %cr2, %eax 2917 movl %eax, CREG_CR2(%edx) /* cr2 */ 2918 movl %cr3, %eax 2919 movl %eax, CREG_CR3(%edx) /* cr3 */ 2920 testl $X86_LARGEPAGE, x86_feature 2921 jz .nocr4 2922 movl %cr4, %eax 2923 movl %eax, CREG_CR4(%edx) /* cr4 */ 2924 jmp .skip 2925.nocr4: 2926 movl $0, CREG_CR4(%edx) 2927.skip: 2928 rep; ret /* use 2 byte return instruction when branch target */ 2929 /* AMD Software Optimization Guide - Section 6.2 */ 2930 SET_SIZE(getcregs) 2931 2932#endif /* __i386 */ 2933#endif /* __lint */ 2934 2935 2936/* 2937 * A panic trigger is a word which is updated atomically and can only be set 2938 * once. We atomically store 0xDEFACEDD and load the old value. If the 2939 * previous value was 0, we succeed and return 1; otherwise return 0. 2940 * This allows a partially corrupt trigger to still trigger correctly. DTrace 2941 * has its own version of this function to allow it to panic correctly from 2942 * probe context. 2943 */ 2944#if defined(__lint) 2945 2946/*ARGSUSED*/ 2947int 2948panic_trigger(int *tp) 2949{ return (0); } 2950 2951/*ARGSUSED*/ 2952int 2953dtrace_panic_trigger(int *tp) 2954{ return (0); } 2955 2956#else /* __lint */ 2957 2958#if defined(__amd64) 2959 2960 ENTRY_NP(panic_trigger) 2961 xorl %eax, %eax 2962 movl $0xdefacedd, %edx 2963 lock 2964 xchgl %edx, (%rdi) 2965 cmpl $0, %edx 2966 je 0f 2967 movl $0, %eax 2968 ret 29690: movl $1, %eax 2970 ret 2971 SET_SIZE(panic_trigger) 2972 2973 ENTRY_NP(dtrace_panic_trigger) 2974 xorl %eax, %eax 2975 movl $0xdefacedd, %edx 2976 lock 2977 xchgl %edx, (%rdi) 2978 cmpl $0, %edx 2979 je 0f 2980 movl $0, %eax 2981 ret 29820: movl $1, %eax 2983 ret 2984 SET_SIZE(dtrace_panic_trigger) 2985 2986#elif defined(__i386) 2987 2988 ENTRY_NP(panic_trigger) 2989 movl 4(%esp), %edx / %edx = address of trigger 2990 movl $0xdefacedd, %eax / %eax = 0xdefacedd 2991 lock / assert lock 2992 xchgl %eax, (%edx) / exchange %eax and the trigger 2993 cmpl $0, %eax / if (%eax == 0x0) 2994 je 0f / return (1); 2995 movl $0, %eax / else 2996 ret / return (0); 29970: movl $1, %eax 2998 ret 2999 SET_SIZE(panic_trigger) 3000 3001 ENTRY_NP(dtrace_panic_trigger) 3002 movl 4(%esp), %edx / %edx = address of trigger 3003 movl $0xdefacedd, %eax / %eax = 0xdefacedd 3004 lock / assert lock 3005 xchgl %eax, (%edx) / exchange %eax and the trigger 3006 cmpl $0, %eax / if (%eax == 0x0) 3007 je 0f / return (1); 3008 movl $0, %eax / else 3009 ret / return (0); 30100: movl $1, %eax 3011 ret 3012 SET_SIZE(dtrace_panic_trigger) 3013 3014#endif /* __i386 */ 3015#endif /* __lint */ 3016 3017/* 3018 * The panic() and cmn_err() functions invoke vpanic() as a common entry point 3019 * into the panic code implemented in panicsys(). vpanic() is responsible 3020 * for passing through the format string and arguments, and constructing a 3021 * regs structure on the stack into which it saves the current register 3022 * values. If we are not dying due to a fatal trap, these registers will 3023 * then be preserved in panicbuf as the current processor state. Before 3024 * invoking panicsys(), vpanic() activates the first panic trigger (see 3025 * common/os/panic.c) and switches to the panic_stack if successful. Note that 3026 * DTrace takes a slightly different panic path if it must panic from probe 3027 * context. Instead of calling panic, it calls into dtrace_vpanic(), which 3028 * sets up the initial stack as vpanic does, calls dtrace_panic_trigger(), and 3029 * branches back into vpanic(). 3030 */ 3031#if defined(__lint) 3032 3033/*ARGSUSED*/ 3034void 3035vpanic(const char *format, va_list alist) 3036{} 3037 3038/*ARGSUSED*/ 3039void 3040dtrace_vpanic(const char *format, va_list alist) 3041{} 3042 3043#else /* __lint */ 3044 3045#if defined(__amd64) 3046 3047 ENTRY_NP(vpanic) /* Initial stack layout: */ 3048 3049 pushq %rbp /* | %rip | 0x60 */ 3050 movq %rsp, %rbp /* | %rbp | 0x58 */ 3051 pushfq /* | rfl | 0x50 */ 3052 pushq %r11 /* | %r11 | 0x48 */ 3053 pushq %r10 /* | %r10 | 0x40 */ 3054 pushq %rbx /* | %rbx | 0x38 */ 3055 pushq %rax /* | %rax | 0x30 */ 3056 pushq %r9 /* | %r9 | 0x28 */ 3057 pushq %r8 /* | %r8 | 0x20 */ 3058 pushq %rcx /* | %rcx | 0x18 */ 3059 pushq %rdx /* | %rdx | 0x10 */ 3060 pushq %rsi /* | %rsi | 0x8 alist */ 3061 pushq %rdi /* | %rdi | 0x0 format */ 3062 3063 movq %rsp, %rbx /* %rbx = current %rsp */ 3064 3065 leaq panic_quiesce(%rip), %rdi /* %rdi = &panic_quiesce */ 3066 call panic_trigger /* %eax = panic_trigger() */ 3067 3068vpanic_common: 3069 cmpl $0, %eax 3070 je 0f 3071 3072 /* 3073 * If panic_trigger() was successful, we are the first to initiate a 3074 * panic: we now switch to the reserved panic_stack before continuing. 3075 */ 3076 leaq panic_stack(%rip), %rsp 3077 addq $PANICSTKSIZE, %rsp 30780: subq $REGSIZE, %rsp 3079 /* 3080 * Now that we've got everything set up, store the register values as 3081 * they were when we entered vpanic() to the designated location in 3082 * the regs structure we allocated on the stack. 3083 */ 3084 movq 0x0(%rbx), %rcx 3085 movq %rcx, REGOFF_RDI(%rsp) 3086 movq 0x8(%rbx), %rcx 3087 movq %rcx, REGOFF_RSI(%rsp) 3088 movq 0x10(%rbx), %rcx 3089 movq %rcx, REGOFF_RDX(%rsp) 3090 movq 0x18(%rbx), %rcx 3091 movq %rcx, REGOFF_RCX(%rsp) 3092 movq 0x20(%rbx), %rcx 3093 3094 movq %rcx, REGOFF_R8(%rsp) 3095 movq 0x28(%rbx), %rcx 3096 movq %rcx, REGOFF_R9(%rsp) 3097 movq 0x30(%rbx), %rcx 3098 movq %rcx, REGOFF_RAX(%rsp) 3099 movq 0x38(%rbx), %rcx 3100 movq %rbx, REGOFF_RBX(%rsp) 3101 movq 0x58(%rbx), %rcx 3102 3103 movq %rcx, REGOFF_RBP(%rsp) 3104 movq 0x40(%rbx), %rcx 3105 movq %rcx, REGOFF_R10(%rsp) 3106 movq 0x48(%rbx), %rcx 3107 movq %rcx, REGOFF_R11(%rsp) 3108 movq %r12, REGOFF_R12(%rsp) 3109 3110 movq %r13, REGOFF_R13(%rsp) 3111 movq %r14, REGOFF_R14(%rsp) 3112 movq %r15, REGOFF_R15(%rsp) 3113 3114 movl $MSR_AMD_FSBASE, %ecx 3115 rdmsr 3116 movl %eax, REGOFF_FSBASE(%rsp) 3117 movl %edx, REGOFF_FSBASE+4(%rsp) 3118 3119 movl $MSR_AMD_GSBASE, %ecx 3120 rdmsr 3121 movl %eax, REGOFF_GSBASE(%rsp) 3122 movl %edx, REGOFF_GSBASE+4(%rsp) 3123 3124 xorl %ecx, %ecx 3125 movw %ds, %cx 3126 movq %rcx, REGOFF_DS(%rsp) 3127 movw %es, %cx 3128 movq %rcx, REGOFF_ES(%rsp) 3129 movw %fs, %cx 3130 movq %rcx, REGOFF_FS(%rsp) 3131 movw %gs, %cx 3132 movq %rcx, REGOFF_GS(%rsp) 3133 3134 movq $0, REGOFF_TRAPNO(%rsp) 3135 3136 movq $0, REGOFF_ERR(%rsp) 3137 leaq vpanic(%rip), %rcx 3138 movq %rcx, REGOFF_RIP(%rsp) 3139 movw %cs, %cx 3140 movzwq %cx, %rcx 3141 movq %rcx, REGOFF_CS(%rsp) 3142 movq 0x50(%rbx), %rcx 3143 movq %rcx, REGOFF_RFL(%rsp) 3144 movq %rbx, %rcx 3145 addq $0x60, %rcx 3146 movq %rcx, REGOFF_RSP(%rsp) 3147 movw %ss, %cx 3148 movzwq %cx, %rcx 3149 movq %rcx, REGOFF_SS(%rsp) 3150 3151 /* 3152 * panicsys(format, alist, rp, on_panic_stack) 3153 */ 3154 movq REGOFF_RDI(%rsp), %rdi /* format */ 3155 movq REGOFF_RSI(%rsp), %rsi /* alist */ 3156 movq %rsp, %rdx /* struct regs */ 3157 movl %eax, %ecx /* on_panic_stack */ 3158 call panicsys 3159 addq $REGSIZE, %rsp 3160 popq %rdi 3161 popq %rsi 3162 popq %rdx 3163 popq %rcx 3164 popq %r8 3165 popq %r9 3166 popq %rax 3167 popq %rbx 3168 popq %r10 3169 popq %r11 3170 popfq 3171 leave 3172 ret 3173 SET_SIZE(vpanic) 3174 3175 ENTRY_NP(dtrace_vpanic) /* Initial stack layout: */ 3176 3177 pushq %rbp /* | %rip | 0x60 */ 3178 movq %rsp, %rbp /* | %rbp | 0x58 */ 3179 pushfq /* | rfl | 0x50 */ 3180 pushq %r11 /* | %r11 | 0x48 */ 3181 pushq %r10 /* | %r10 | 0x40 */ 3182 pushq %rbx /* | %rbx | 0x38 */ 3183 pushq %rax /* | %rax | 0x30 */ 3184 pushq %r9 /* | %r9 | 0x28 */ 3185 pushq %r8 /* | %r8 | 0x20 */ 3186 pushq %rcx /* | %rcx | 0x18 */ 3187 pushq %rdx /* | %rdx | 0x10 */ 3188 pushq %rsi /* | %rsi | 0x8 alist */ 3189 pushq %rdi /* | %rdi | 0x0 format */ 3190 3191 movq %rsp, %rbx /* %rbx = current %rsp */ 3192 3193 leaq panic_quiesce(%rip), %rdi /* %rdi = &panic_quiesce */ 3194 call dtrace_panic_trigger /* %eax = dtrace_panic_trigger() */ 3195 jmp vpanic_common 3196 3197 SET_SIZE(dtrace_vpanic) 3198 3199#elif defined(__i386) 3200 3201 ENTRY_NP(vpanic) / Initial stack layout: 3202 3203 pushl %ebp / | %eip | 20 3204 movl %esp, %ebp / | %ebp | 16 3205 pushl %eax / | %eax | 12 3206 pushl %ebx / | %ebx | 8 3207 pushl %ecx / | %ecx | 4 3208 pushl %edx / | %edx | 0 3209 3210 movl %esp, %ebx / %ebx = current stack pointer 3211 3212 lea panic_quiesce, %eax / %eax = &panic_quiesce 3213 pushl %eax / push &panic_quiesce 3214 call panic_trigger / %eax = panic_trigger() 3215 addl $4, %esp / reset stack pointer 3216 3217vpanic_common: 3218 cmpl $0, %eax / if (%eax == 0) 3219 je 0f / goto 0f; 3220 3221 /* 3222 * If panic_trigger() was successful, we are the first to initiate a 3223 * panic: we now switch to the reserved panic_stack before continuing. 3224 */ 3225 lea panic_stack, %esp / %esp = panic_stack 3226 addl $PANICSTKSIZE, %esp / %esp += PANICSTKSIZE 3227 32280: subl $REGSIZE, %esp / allocate struct regs 3229 3230 /* 3231 * Now that we've got everything set up, store the register values as 3232 * they were when we entered vpanic() to the designated location in 3233 * the regs structure we allocated on the stack. 3234 */ 3235#if !defined(__GNUC_AS__) 3236 movw %gs, %edx 3237 movl %edx, REGOFF_GS(%esp) 3238 movw %fs, %edx 3239 movl %edx, REGOFF_FS(%esp) 3240 movw %es, %edx 3241 movl %edx, REGOFF_ES(%esp) 3242 movw %ds, %edx 3243 movl %edx, REGOFF_DS(%esp) 3244#else /* __GNUC_AS__ */ 3245 mov %gs, %edx 3246 mov %edx, REGOFF_GS(%esp) 3247 mov %fs, %edx 3248 mov %edx, REGOFF_FS(%esp) 3249 mov %es, %edx 3250 mov %edx, REGOFF_ES(%esp) 3251 mov %ds, %edx 3252 mov %edx, REGOFF_DS(%esp) 3253#endif /* __GNUC_AS__ */ 3254 movl %edi, REGOFF_EDI(%esp) 3255 movl %esi, REGOFF_ESI(%esp) 3256 movl 16(%ebx), %ecx 3257 movl %ecx, REGOFF_EBP(%esp) 3258 movl %ebx, %ecx 3259 addl $20, %ecx 3260 movl %ecx, REGOFF_ESP(%esp) 3261 movl 8(%ebx), %ecx 3262 movl %ecx, REGOFF_EBX(%esp) 3263 movl 0(%ebx), %ecx 3264 movl %ecx, REGOFF_EDX(%esp) 3265 movl 4(%ebx), %ecx 3266 movl %ecx, REGOFF_ECX(%esp) 3267 movl 12(%ebx), %ecx 3268 movl %ecx, REGOFF_EAX(%esp) 3269 movl $0, REGOFF_TRAPNO(%esp) 3270 movl $0, REGOFF_ERR(%esp) 3271 lea vpanic, %ecx 3272 movl %ecx, REGOFF_EIP(%esp) 3273#if !defined(__GNUC_AS__) 3274 movw %cs, %edx 3275#else /* __GNUC_AS__ */ 3276 mov %cs, %edx 3277#endif /* __GNUC_AS__ */ 3278 movl %edx, REGOFF_CS(%esp) 3279 pushfl 3280 popl %ecx 3281 movl %ecx, REGOFF_EFL(%esp) 3282 movl $0, REGOFF_UESP(%esp) 3283#if !defined(__GNUC_AS__) 3284 movw %ss, %edx 3285#else /* __GNUC_AS__ */ 3286 mov %ss, %edx 3287#endif /* __GNUC_AS__ */ 3288 movl %edx, REGOFF_SS(%esp) 3289 3290 movl %esp, %ecx / %ecx = ®s 3291 pushl %eax / push on_panic_stack 3292 pushl %ecx / push ®s 3293 movl 12(%ebp), %ecx / %ecx = alist 3294 pushl %ecx / push alist 3295 movl 8(%ebp), %ecx / %ecx = format 3296 pushl %ecx / push format 3297 call panicsys / panicsys(); 3298 addl $16, %esp / pop arguments 3299 3300 addl $REGSIZE, %esp 3301 popl %edx 3302 popl %ecx 3303 popl %ebx 3304 popl %eax 3305 leave 3306 ret 3307 SET_SIZE(vpanic) 3308 3309 ENTRY_NP(dtrace_vpanic) / Initial stack layout: 3310 3311 pushl %ebp / | %eip | 20 3312 movl %esp, %ebp / | %ebp | 16 3313 pushl %eax / | %eax | 12 3314 pushl %ebx / | %ebx | 8 3315 pushl %ecx / | %ecx | 4 3316 pushl %edx / | %edx | 0 3317 3318 movl %esp, %ebx / %ebx = current stack pointer 3319 3320 lea panic_quiesce, %eax / %eax = &panic_quiesce 3321 pushl %eax / push &panic_quiesce 3322 call dtrace_panic_trigger / %eax = dtrace_panic_trigger() 3323 addl $4, %esp / reset stack pointer 3324 jmp vpanic_common / jump back to common code 3325 3326 SET_SIZE(dtrace_vpanic) 3327 3328#endif /* __i386 */ 3329#endif /* __lint */ 3330 3331#if defined(__lint) 3332 3333void 3334hres_tick(void) 3335{} 3336 3337int64_t timedelta; 3338hrtime_t hres_last_tick; 3339timestruc_t hrestime; 3340int64_t hrestime_adj; 3341volatile int hres_lock; 3342uint_t nsec_scale; 3343hrtime_t hrtime_base; 3344 3345#else /* __lint */ 3346 3347 DGDEF3(hrestime, _MUL(2, CLONGSIZE), 8) 3348 .NWORD 0, 0 3349 3350 DGDEF3(hrestime_adj, 8, 8) 3351 .long 0, 0 3352 3353 DGDEF3(hres_last_tick, 8, 8) 3354 .long 0, 0 3355 3356 DGDEF3(timedelta, 8, 8) 3357 .long 0, 0 3358 3359 DGDEF3(hres_lock, 4, 8) 3360 .long 0 3361 3362 /* 3363 * initialized to a non zero value to make pc_gethrtime() 3364 * work correctly even before clock is initialized 3365 */ 3366 DGDEF3(hrtime_base, 8, 8) 3367 .long _MUL(NSEC_PER_CLOCK_TICK, 6), 0 3368 3369 DGDEF3(adj_shift, 4, 4) 3370 .long ADJ_SHIFT 3371 3372#if defined(__amd64) 3373 3374 ENTRY_NP(hres_tick) 3375 pushq %rbp 3376 movq %rsp, %rbp 3377 3378 /* 3379 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously, 3380 * hres_last_tick can only be modified while holding CLOCK_LOCK). 3381 * At worst, performing this now instead of under CLOCK_LOCK may 3382 * introduce some jitter in pc_gethrestime(). 3383 */ 3384 call *gethrtimef(%rip) 3385 movq %rax, %r8 3386 3387 leaq hres_lock(%rip), %rax 3388 movb $-1, %dl 3389.CL1: 3390 xchgb %dl, (%rax) 3391 testb %dl, %dl 3392 jz .CL3 /* got it */ 3393.CL2: 3394 cmpb $0, (%rax) /* possible to get lock? */ 3395 pause 3396 jne .CL2 3397 jmp .CL1 /* yes, try again */ 3398.CL3: 3399 /* 3400 * compute the interval since last time hres_tick was called 3401 * and adjust hrtime_base and hrestime accordingly 3402 * hrtime_base is an 8 byte value (in nsec), hrestime is 3403 * a timestruc_t (sec, nsec) 3404 */ 3405 leaq hres_last_tick(%rip), %rax 3406 movq %r8, %r11 3407 subq (%rax), %r8 3408 addq %r8, hrtime_base(%rip) /* add interval to hrtime_base */ 3409 addq %r8, hrestime+8(%rip) /* add interval to hrestime.tv_nsec */ 3410 /* 3411 * Now that we have CLOCK_LOCK, we can update hres_last_tick 3412 */ 3413 movq %r11, (%rax) 3414 3415 call __adj_hrestime 3416 3417 /* 3418 * release the hres_lock 3419 */ 3420 incl hres_lock(%rip) 3421 leave 3422 ret 3423 SET_SIZE(hres_tick) 3424 3425#elif defined(__i386) 3426 3427 ENTRY_NP(hres_tick) 3428 pushl %ebp 3429 movl %esp, %ebp 3430 pushl %esi 3431 pushl %ebx 3432 3433 /* 3434 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously, 3435 * hres_last_tick can only be modified while holding CLOCK_LOCK). 3436 * At worst, performing this now instead of under CLOCK_LOCK may 3437 * introduce some jitter in pc_gethrestime(). 3438 */ 3439 call *gethrtimef 3440 movl %eax, %ebx 3441 movl %edx, %esi 3442 3443 movl $hres_lock, %eax 3444 movl $-1, %edx 3445.CL1: 3446 xchgb %dl, (%eax) 3447 testb %dl, %dl 3448 jz .CL3 / got it 3449.CL2: 3450 cmpb $0, (%eax) / possible to get lock? 3451 pause 3452 jne .CL2 3453 jmp .CL1 / yes, try again 3454.CL3: 3455 /* 3456 * compute the interval since last time hres_tick was called 3457 * and adjust hrtime_base and hrestime accordingly 3458 * hrtime_base is an 8 byte value (in nsec), hrestime is 3459 * timestruc_t (sec, nsec) 3460 */ 3461 3462 lea hres_last_tick, %eax 3463 3464 movl %ebx, %edx 3465 movl %esi, %ecx 3466 3467 subl (%eax), %edx 3468 sbbl 4(%eax), %ecx 3469 3470 addl %edx, hrtime_base / add interval to hrtime_base 3471 adcl %ecx, hrtime_base+4 3472 3473 addl %edx, hrestime+4 / add interval to hrestime.tv_nsec 3474 3475 / 3476 / Now that we have CLOCK_LOCK, we can update hres_last_tick. 3477 / 3478 movl %ebx, (%eax) 3479 movl %esi, 4(%eax) 3480 3481 / get hrestime at this moment. used as base for pc_gethrestime 3482 / 3483 / Apply adjustment, if any 3484 / 3485 / #define HRES_ADJ (NSEC_PER_CLOCK_TICK >> ADJ_SHIFT) 3486 / (max_hres_adj) 3487 / 3488 / void 3489 / adj_hrestime() 3490 / { 3491 / long long adj; 3492 / 3493 / if (hrestime_adj == 0) 3494 / adj = 0; 3495 / else if (hrestime_adj > 0) { 3496 / if (hrestime_adj < HRES_ADJ) 3497 / adj = hrestime_adj; 3498 / else 3499 / adj = HRES_ADJ; 3500 / } 3501 / else { 3502 / if (hrestime_adj < -(HRES_ADJ)) 3503 / adj = -(HRES_ADJ); 3504 / else 3505 / adj = hrestime_adj; 3506 / } 3507 / 3508 / timedelta -= adj; 3509 / hrestime_adj = timedelta; 3510 / hrestime.tv_nsec += adj; 3511 / 3512 / while (hrestime.tv_nsec >= NANOSEC) { 3513 / one_sec++; 3514 / hrestime.tv_sec++; 3515 / hrestime.tv_nsec -= NANOSEC; 3516 / } 3517 / } 3518__adj_hrestime: 3519 movl hrestime_adj, %esi / if (hrestime_adj == 0) 3520 movl hrestime_adj+4, %edx 3521 andl %esi, %esi 3522 jne .CL4 / no 3523 andl %edx, %edx 3524 jne .CL4 / no 3525 subl %ecx, %ecx / yes, adj = 0; 3526 subl %edx, %edx 3527 jmp .CL5 3528.CL4: 3529 subl %ecx, %ecx 3530 subl %eax, %eax 3531 subl %esi, %ecx 3532 sbbl %edx, %eax 3533 andl %eax, %eax / if (hrestime_adj > 0) 3534 jge .CL6 3535 3536 / In the following comments, HRES_ADJ is used, while in the code 3537 / max_hres_adj is used. 3538 / 3539 / The test for "hrestime_adj < HRES_ADJ" is complicated because 3540 / hrestime_adj is 64-bits, while HRES_ADJ is 32-bits. We rely 3541 / on the logical equivalence of: 3542 / 3543 / !(hrestime_adj < HRES_ADJ) 3544 / 3545 / and the two step sequence: 3546 / 3547 / (HRES_ADJ - lsw(hrestime_adj)) generates a Borrow/Carry 3548 / 3549 / which computes whether or not the least significant 32-bits 3550 / of hrestime_adj is greater than HRES_ADJ, followed by: 3551 / 3552 / Previous Borrow/Carry + -1 + msw(hrestime_adj) generates a Carry 3553 / 3554 / which generates a carry whenever step 1 is true or the most 3555 / significant long of the longlong hrestime_adj is non-zero. 3556 3557 movl max_hres_adj, %ecx / hrestime_adj is positive 3558 subl %esi, %ecx 3559 movl %edx, %eax 3560 adcl $-1, %eax 3561 jnc .CL7 3562 movl max_hres_adj, %ecx / adj = HRES_ADJ; 3563 subl %edx, %edx 3564 jmp .CL5 3565 3566 / The following computation is similar to the one above. 3567 / 3568 / The test for "hrestime_adj < -(HRES_ADJ)" is complicated because 3569 / hrestime_adj is 64-bits, while HRES_ADJ is 32-bits. We rely 3570 / on the logical equivalence of: 3571 / 3572 / (hrestime_adj > -HRES_ADJ) 3573 / 3574 / and the two step sequence: 3575 / 3576 / (HRES_ADJ + lsw(hrestime_adj)) generates a Carry 3577 / 3578 / which means the least significant 32-bits of hrestime_adj is 3579 / greater than -HRES_ADJ, followed by: 3580 / 3581 / Previous Carry + 0 + msw(hrestime_adj) generates a Carry 3582 / 3583 / which generates a carry only when step 1 is true and the most 3584 / significant long of the longlong hrestime_adj is -1. 3585 3586.CL6: / hrestime_adj is negative 3587 movl %esi, %ecx 3588 addl max_hres_adj, %ecx 3589 movl %edx, %eax 3590 adcl $0, %eax 3591 jc .CL7 3592 xor %ecx, %ecx 3593 subl max_hres_adj, %ecx / adj = -(HRES_ADJ); 3594 movl $-1, %edx 3595 jmp .CL5 3596.CL7: 3597 movl %esi, %ecx / adj = hrestime_adj; 3598.CL5: 3599 movl timedelta, %esi 3600 subl %ecx, %esi 3601 movl timedelta+4, %eax 3602 sbbl %edx, %eax 3603 movl %esi, timedelta 3604 movl %eax, timedelta+4 / timedelta -= adj; 3605 movl %esi, hrestime_adj 3606 movl %eax, hrestime_adj+4 / hrestime_adj = timedelta; 3607 addl hrestime+4, %ecx 3608 3609 movl %ecx, %eax / eax = tv_nsec 36101: 3611 cmpl $NANOSEC, %eax / if ((unsigned long)tv_nsec >= NANOSEC) 3612 jb .CL8 / no 3613 incl one_sec / yes, one_sec++; 3614 incl hrestime / hrestime.tv_sec++; 3615 addl $-NANOSEC, %eax / tv_nsec -= NANOSEC 3616 jmp 1b / check for more seconds 3617 3618.CL8: 3619 movl %eax, hrestime+4 / store final into hrestime.tv_nsec 3620 incl hres_lock / release the hres_lock 3621 3622 popl %ebx 3623 popl %esi 3624 leave 3625 ret 3626 SET_SIZE(hres_tick) 3627 3628#endif /* __i386 */ 3629#endif /* __lint */ 3630 3631/* 3632 * void prefetch_smap_w(void *) 3633 * 3634 * Prefetch ahead within a linear list of smap structures. 3635 * Not implemented for ia32. Stub for compatibility. 3636 */ 3637 3638#if defined(__lint) 3639 3640/*ARGSUSED*/ 3641void prefetch_smap_w(void *smp) 3642{} 3643 3644#else /* __lint */ 3645 3646 ENTRY(prefetch_smap_w) 3647 rep; ret /* use 2 byte return instruction when branch target */ 3648 /* AMD Software Optimization Guide - Section 6.2 */ 3649 SET_SIZE(prefetch_smap_w) 3650 3651#endif /* __lint */ 3652 3653/* 3654 * prefetch_page_r(page_t *) 3655 * issue prefetch instructions for a page_t 3656 */ 3657#if defined(__lint) 3658 3659/*ARGSUSED*/ 3660void 3661prefetch_page_r(void *pp) 3662{} 3663 3664#else /* __lint */ 3665 3666 ENTRY(prefetch_page_r) 3667 rep; ret /* use 2 byte return instruction when branch target */ 3668 /* AMD Software Optimization Guide - Section 6.2 */ 3669 SET_SIZE(prefetch_page_r) 3670 3671#endif /* __lint */ 3672 3673#if defined(__lint) 3674 3675/*ARGSUSED*/ 3676int 3677bcmp(const void *s1, const void *s2, size_t count) 3678{ return (0); } 3679 3680#else /* __lint */ 3681 3682#if defined(__amd64) 3683 3684 ENTRY(bcmp) 3685 pushq %rbp 3686 movq %rsp, %rbp 3687#ifdef DEBUG 3688 movq kernelbase(%rip), %r11 3689 cmpq %r11, %rdi 3690 jb 0f 3691 cmpq %r11, %rsi 3692 jnb 1f 36930: leaq .bcmp_panic_msg(%rip), %rdi 3694 xorl %eax, %eax 3695 call panic 36961: 3697#endif /* DEBUG */ 3698 call memcmp 3699 testl %eax, %eax 3700 setne %dl 3701 leave 3702 movzbl %dl, %eax 3703 ret 3704 SET_SIZE(bcmp) 3705 3706#elif defined(__i386) 3707 3708#define ARG_S1 8 3709#define ARG_S2 12 3710#define ARG_LENGTH 16 3711 3712 ENTRY(bcmp) 3713#ifdef DEBUG 3714 pushl %ebp 3715 movl %esp, %ebp 3716 movl kernelbase, %eax 3717 cmpl %eax, ARG_S1(%ebp) 3718 jb 0f 3719 cmpl %eax, ARG_S2(%ebp) 3720 jnb 1f 37210: pushl $.bcmp_panic_msg 3722 call panic 37231: popl %ebp 3724#endif /* DEBUG */ 3725 3726 pushl %edi / save register variable 3727 movl ARG_S1(%esp), %eax / %eax = address of string 1 3728 movl ARG_S2(%esp), %ecx / %ecx = address of string 2 3729 cmpl %eax, %ecx / if the same string 3730 je .equal / goto .equal 3731 movl ARG_LENGTH(%esp), %edi / %edi = length in bytes 3732 cmpl $4, %edi / if %edi < 4 3733 jb .byte_check / goto .byte_check 3734 .align 4 3735.word_loop: 3736 movl (%ecx), %edx / move 1 word from (%ecx) to %edx 3737 leal -4(%edi), %edi / %edi -= 4 3738 cmpl (%eax), %edx / compare 1 word from (%eax) with %edx 3739 jne .word_not_equal / if not equal, goto .word_not_equal 3740 leal 4(%ecx), %ecx / %ecx += 4 (next word) 3741 leal 4(%eax), %eax / %eax += 4 (next word) 3742 cmpl $4, %edi / if %edi >= 4 3743 jae .word_loop / goto .word_loop 3744.byte_check: 3745 cmpl $0, %edi / if %edi == 0 3746 je .equal / goto .equal 3747 jmp .byte_loop / goto .byte_loop (checks in bytes) 3748.word_not_equal: 3749 leal 4(%edi), %edi / %edi += 4 (post-decremented) 3750 .align 4 3751.byte_loop: 3752 movb (%ecx), %dl / move 1 byte from (%ecx) to %dl 3753 cmpb %dl, (%eax) / compare %dl with 1 byte from (%eax) 3754 jne .not_equal / if not equal, goto .not_equal 3755 incl %ecx / %ecx++ (next byte) 3756 incl %eax / %eax++ (next byte) 3757 decl %edi / %edi-- 3758 jnz .byte_loop / if not zero, goto .byte_loop 3759.equal: 3760 xorl %eax, %eax / %eax = 0 3761 popl %edi / restore register variable 3762 ret / return (NULL) 3763 .align 4 3764.not_equal: 3765 movl $1, %eax / return 1 3766 popl %edi / restore register variable 3767 ret / return (NULL) 3768 SET_SIZE(bcmp) 3769 3770#endif /* __i386 */ 3771 3772#ifdef DEBUG 3773 .text 3774.bcmp_panic_msg: 3775 .string "bcmp: arguments below kernelbase" 3776#endif /* DEBUG */ 3777 3778#endif /* __lint */ 3779