1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 /* 27 * evtchn.h (renamed to evtchn_impl.h) 28 * 29 * Communication via Xen event channels. 30 * Also definitions for the device that demuxes notifications to userspace. 31 * 32 * Copyright (c) 2004-2005, K A Fraser 33 * 34 * This file may be distributed separately from the Linux kernel, or 35 * incorporated into other software packages, subject to the following license: 36 * 37 * Permission is hereby granted, free of charge, to any person obtaining a copy 38 * of this source file (the "Software"), to deal in the Software without 39 * restriction, including without limitation the rights to use, copy, modify, 40 * merge, publish, distribute, sublicense, and/or sell copies of the Software, 41 * and to permit persons to whom the Software is furnished to do so, subject to 42 * the following conditions: 43 * 44 * The above copyright notice and this permission notice shall be included in 45 * all copies or substantial portions of the Software. 46 * 47 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 48 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 49 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 50 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 51 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 52 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 53 * IN THE SOFTWARE. 54 */ 55 56 #ifndef _SYS_EVTCHN_H 57 #define _SYS_EVTCHN_H 58 59 #pragma ident "%Z%%M% %I% %E% SMI" 60 61 #ifdef __cplusplus 62 extern "C" { 63 #endif 64 65 #include <sys/types.h> 66 #include <sys/privregs.h> 67 #include <sys/systm.h> 68 #include <sys/traptrace.h> 69 #include <sys/ddi_intr.h> 70 #include <sys/ddi_intr_impl.h> 71 #include <sys/avintr.h> 72 #include <sys/cpuvar.h> 73 #include <sys/hypervisor.h> 74 75 /* evtchn binding types */ 76 #define IRQT_UNBOUND 0 /* unassigned irq */ 77 #define IRQT_PIRQ 1 /* IRQ from phys hdw device */ 78 #define IRQT_VIRQ 2 /* Virtual IRQ from Xen */ 79 #define IRQT_IPI 3 /* Inter VCPU interrupt IRQ */ 80 #define IRQT_EVTCHN 4 /* Virtual device IRQ */ 81 #define IRQT_DEV_EVTCHN 5 /* Special evtchn device IRQ */ 82 83 #define SET_EVTCHN_BIT(bit, arrayp) \ 84 ((arrayp)[bit >> EVTCHN_SHIFT] |= \ 85 (1ul << ((bit) & ((1ul << EVTCHN_SHIFT) - 1)))) 86 #define CLEAR_EVTCHN_BIT(bit, arrayp) \ 87 ((arrayp)[bit >> EVTCHN_SHIFT] &= \ 88 ~((1ul << ((bit) & ((1ul << EVTCHN_SHIFT) - 1))))) 89 #define TEST_EVTCHN_BIT(bit, arrayp) \ 90 ((arrayp)[bit >> EVTCHN_SHIFT] & \ 91 (1ul << ((bit) & ((1ul << EVTCHN_SHIFT) - 1)))) 92 93 /* Xen will never allocate port zero for any purpose. */ 94 #define INVALID_EVTCHN 0 95 96 /* XXPV - should these defines be somewhere else? xenos.h perhaps? */ 97 98 #define IPL_DEBUG 15 /* domain debug interrupt */ 99 #define IPL_CONS 9 100 #define IPL_VIF 6 101 #define IPL_VBD 5 102 #define IPL_EVTCHN 1 103 104 #define PIRQ_BASE 0 /* base of pirq range */ 105 #define NR_PIRQS 256 /* Number of supported physical irqs */ 106 #define DYNIRQ_BASE (PIRQ_BASE + NR_PIRQS) /* base of dynamic irq range */ 107 #define NR_DYNIRQS 256 /* Number of dynamic irqs */ 108 #define NR_IRQS (NR_PIRQS + NR_DYNIRQS) /* total irq count */ 109 110 #define PIRQ_TO_IRQ(pirq) ((pirq) + PIRQ_BASE) 111 #define IRQ_TO_PIRQ(irq) ((irq) - PIRQ_BASE) 112 113 #define DYNIRQ_TO_IRQ(dirq) ((dirq) + DYNIRQ_BASE) 114 #define IRQ_TO_DYNIRQ(irq) ((irq) - DYNIRQ_BASE) 115 116 #if defined(_LP64) 117 #define EVTCHN_SHIFT 6 /* log2(NBBY * sizeof (ulong_t)) */ 118 #else 119 #define EVTCHN_SHIFT 5 /* log2(NBBY * sizeof (ulong_t)) */ 120 #endif 121 122 #define INVALID_IRQ -1 123 124 extern int ec_dev_irq; 125 extern volatile int ec_dev_mbox; 126 extern kmutex_t ec_lock; 127 128 typedef struct mec_info { 129 ushort_t mi_evtchns[NCPU]; /* event channels for this IRQ */ 130 short mi_irq; /* the IRQ, or INVALID_IRQ */ 131 char mi_shared; /* one evtchn for all CPUs? */ 132 } mec_info_t; 133 134 /* 135 * Careful: ii_ipl is /only/ set if there's a handler for this IRQ. 136 */ 137 typedef struct irq_info { 138 union { 139 ushort_t evtchn; /* event channel */ 140 ushort_t index; /* index to next table if mec */ 141 } ii_u; 142 uchar_t ii_type; /* IRQ type as above */ 143 union { 144 uchar_t ipl; /* IPL of IRQ, != 0 => has handler */ 145 uchar_t has_handler; /* alternate name for ipl */ 146 } ii_u2; 147 } irq_info_t; 148 149 extern void ec_init(void); 150 extern void ec_init_debug_irq(void); 151 extern void ec_suspend(void); 152 extern void ec_resume(void); 153 extern void ec_wait_on_evtchn(int, int (*)(void *), void *); 154 extern void ec_wait_on_ipi(int, int (*)(void *), void *); 155 156 extern void ec_setup_pirq(int, int, cpuset_t *); 157 extern int ec_probe_pirq(int); 158 extern void ec_set_irq_affinity(int, cpuset_t); 159 extern int ec_set_irq_priority(int, int); 160 161 extern int ec_bind_ipi_to_irq(int, int); 162 extern void ec_bind_cpu_ipis(int); 163 extern int ec_bind_evtchn_to_irq(int); 164 extern int ec_bind_virq_to_irq(int, int); 165 extern void ec_unbind_irq(int irq); 166 167 extern void ec_send_ipi(int, int); 168 extern void ec_try_ipi(int, int); 169 extern void ec_clear_irq(int); 170 extern void ec_unmask_irq(int); 171 extern void ec_try_unmask_irq(int); 172 extern int ec_block_irq(int); 173 extern void ec_unpend_irq(int); 174 extern int ec_irq_needs_rebind(int, int); 175 extern int ec_irq_rebindable(int); 176 extern int ec_pending_irq(unsigned int); 177 extern void ec_enable_irq(unsigned int); 178 extern void ec_disable_irq(unsigned int); 179 180 extern int xen_bind_interdomain(int, int, int *); 181 extern int xen_bind_virq(unsigned int, processorid_t, int *); 182 extern int xen_alloc_unbound_evtchn(int, int *); 183 extern void ec_bind_vcpu(int, int); 184 185 extern int ec_mask_evtchn(unsigned int); 186 extern void ec_unmask_evtchn(unsigned int); 187 extern void ec_clear_evtchn(unsigned int); 188 189 extern void ec_notify_via_evtchn(unsigned int); 190 191 /* 192 * /dev/xen/evtchn handling. 193 */ 194 extern void ec_irq_add_evtchn(int, int); 195 extern void ec_irq_rm_evtchn(int, int); 196 extern int ec_dev_alloc_irq(void); 197 198 #ifdef __cplusplus 199 } 200 #endif 201 202 #endif /* _SYS_EVTCHN_H */ 203