xref: /titanic_51/usr/src/uts/i86pc/sys/pci_cfgspace_impl.h (revision c0da627439dfb642fb41ab7d78406fc69d2c64b2)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_PCI_CFGSPACE_IMPL_H
28 #define	_SYS_PCI_CFGSPACE_IMPL_H
29 
30 /*
31  * Routines to support particular PCI chipsets
32  */
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 /*
39  * Generic Mechanism 1 routines
40  * XX64 putb -> put8, putw -> put16 etc.
41  */
42 extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg);
43 extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg);
44 extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg);
45 extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val);
46 extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val);
47 extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val);
48 
49 /*
50  * Generic Mechanism 2 routines
51  */
52 extern uint8_t pci_mech2_getb(int bus, int dev, int func, int reg);
53 extern uint16_t pci_mech2_getw(int bus, int dev, int func, int reg);
54 extern uint32_t pci_mech2_getl(int bus, int dev, int func, int reg);
55 extern void pci_mech2_putb(int bus, int dev, int func, int reg, uint8_t val);
56 extern void pci_mech2_putw(int bus, int dev, int func, int reg, uint16_t val);
57 extern void pci_mech2_putl(int bus, int dev, int func, int reg, uint32_t val);
58 
59 /*
60  * Intel Neptune routines.  Neptune is Mech 1, except that BIOSes
61  * often initialize it into Mech 2 so we dynamically switch it to
62  * Mech 1.  The chipset's buggy, so we have to do it carefully.
63  */
64 extern boolean_t pci_check_neptune(void);
65 extern uint8_t pci_neptune_getb(int bus, int dev, int func, int reg);
66 extern uint16_t pci_neptune_getw(int bus, int dev, int func, int reg);
67 extern uint32_t pci_neptune_getl(int bus, int dev, int func, int reg);
68 extern void pci_neptune_putb(int bus, int dev, int func, int reg, uint8_t val);
69 extern void pci_neptune_putw(int bus, int dev, int func, int reg, uint16_t val);
70 extern void pci_neptune_putl(int bus, int dev, int func, int reg, uint32_t val);
71 
72 /*
73  * Intel Orion routines.  Orion is Mech 1, except that there's a bug
74  * in the peer bridge that requires that it be tweaked specially
75  * around accesses to config space.
76  */
77 extern boolean_t pci_is_broken_orion(void);
78 extern uint8_t pci_orion_getb(int bus, int dev, int func, int reg);
79 extern uint16_t pci_orion_getw(int bus, int dev, int func, int reg);
80 extern uint32_t pci_orion_getl(int bus, int dev, int func, int reg);
81 extern void pci_orion_putb(int bus, int dev, int func, int reg, uint8_t val);
82 extern void pci_orion_putw(int bus, int dev, int func, int reg, uint16_t val);
83 extern void pci_orion_putl(int bus, int dev, int func, int reg, uint32_t val);
84 
85 /*
86  * Generic PCI constants.  Probably these should be in pci.h.
87  */
88 #define	PCI_MAX_BUSSES		256
89 #define	PCI_MAX_DEVS		32
90 #define	PCI_MAX_FUNCS		8
91 /*
92  * PCI access mechanism constants.  Probably these should be in pci_impl.h.
93  */
94 #define	PCI_MECH2_CONFIG_ENABLE	0x10	/* any nonzero high nibble works */
95 
96 #define	PCI_MECH1_SPEC_CYCLE_DEV	0x1f	/* dev to request spec cyc */
97 #define	PCI_MECH1_SPEC_CYCLE_FUNC	0x07	/* func to request spec cyc */
98 
99 extern uint64_t mcfg_mem_base;
100 extern uint8_t mcfg_bus_start;
101 extern uint8_t mcfg_bus_end;
102 
103 /*
104  * Mutex for all pci config space routines to share
105  */
106 extern kmutex_t pcicfg_mutex;
107 
108 /*
109  * Orion/Neptune cfg access wraps mech1 cfg access, so needs a separate mutex
110  */
111 
112 extern kmutex_t pcicfg_chipset_mutex;
113 
114 /*
115  * pci get irq routing information support
116  */
117 #define	PCI_GET_IRQ_ROUTING	0x0e
118 
119 #define	PCI_FUNCTION_ID		(0xb1)
120 #define	PCI_BIOS_PRESENT	(0x1)
121 
122 /*
123  * low-mem addresses for irq routing bios operations
124  * We set up the initial request for up to 32 table entries, and will
125  * re-issue for up to 255 entries if the bios indicates it requires
126  * a larger table.  255 entries plus the header would consume the
127  * memory between 0x7000-0x7fff.
128  */
129 #define	BIOS_IRQ_ROUTING_HDR	0x7000
130 #define	BIOS_IRQ_ROUTING_DATA	0x7010
131 
132 #define	N_PCI_IRQ_ROUTES	32
133 #define	N_PCI_IRQ_ROUTES_MAX	255
134 
135 #define	MCFG_PROPNAME		"ecfg"
136 
137 #define	FP_OFF(fp)	(((uintptr_t)(fp)) & 0xFFFF)
138 #define	FP_SEG(fp)	((((uintptr_t)(fp)) >> 16) & 0xFFFF)
139 
140 #pragma pack(1)
141 typedef struct pci_irq_route {
142 	uchar_t		pir_bus;
143 	uchar_t		pir_dev;
144 	uchar_t		pir_inta_link;
145 	uint16_t	pir_inta_irq_map;
146 	uchar_t		pir_intb_link;
147 	uint16_t	pir_intb_irq_map;
148 	uchar_t		pir_intc_link;
149 	uint16_t	pir_intc_irq_map;
150 	uchar_t		pir_intd_link;
151 	uint16_t	pir_intd_irq_map;
152 	uchar_t		pir_slot;
153 	uchar_t		pir_reserved;
154 } pci_irq_route_t;
155 #pragma pack()
156 
157 #pragma pack(1)
158 typedef struct pci_irq_route_hdr {
159 	uint16_t	pir_size;
160 	uint32_t	pir_addr;
161 } pci_irq_route_hdr_t;
162 #pragma pack()
163 
164 #ifdef __cplusplus
165 }
166 #endif
167 
168 #endif /* _SYS_PCI_CFGSPACE_IMPL_H */
169