1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_APIC_APIC_H 27 #define _SYS_APIC_APIC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/psm_types.h> 32 #include <sys/avintr.h> 33 #include <sys/pci.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include <sys/psm_common.h> 40 41 #define APIC_PCPLUSMP_NAME "pcplusmp" 42 43 #define APIC_IO_ADDR 0xfec00000 44 #define APIC_LOCAL_ADDR 0xfee00000 45 #define APIC_IO_MEMLEN 0xf 46 #define APIC_LOCAL_MEMLEN 0xfffff 47 48 /* Local Unit ID register */ 49 #define APIC_LID_REG 0x8 50 51 /* I/o Unit Version Register */ 52 #define APIC_VERS_REG 0xc 53 54 /* Task Priority register */ 55 #define APIC_TASK_REG 0x20 56 57 /* EOI register */ 58 #define APIC_EOI_REG 0x2c 59 60 /* Remote Read register */ 61 #define APIC_REMOTE_READ 0x30 62 63 /* Logical Destination register */ 64 #define APIC_DEST_REG 0x34 65 66 /* Destination Format rgister */ 67 #define APIC_FORMAT_REG 0x38 68 69 /* Spurious Interrupt Vector register */ 70 #define APIC_SPUR_INT_REG 0x3c 71 72 /* Error Status Register */ 73 #define APIC_ERROR_STATUS 0xa0 74 75 /* Interrupt Command registers */ 76 #define APIC_INT_CMD1 0xc0 77 #define APIC_INT_CMD2 0xc4 78 79 /* Timer Vector Table register */ 80 #define APIC_LOCAL_TIMER 0xc8 81 82 /* Local Interrupt Vector registers */ 83 #define APIC_THERM_VECT 0xcc 84 #define APIC_PCINT_VECT 0xd0 85 #define APIC_INT_VECT0 0xd4 86 #define APIC_INT_VECT1 0xd8 87 #define APIC_ERR_VECT 0xdc 88 89 /* IPL for performance counter interrupts */ 90 #define APIC_PCINT_IPL 0xe 91 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 92 93 /* Initial Count register */ 94 #define APIC_INIT_COUNT 0xe0 95 96 /* Current Count Register */ 97 #define APIC_CURR_COUNT 0xe4 98 #define APIC_CURR_ADD 0x39 /* used for remote read command */ 99 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 100 101 /* Divider Configuration Register */ 102 #define APIC_DIVIDE_REG 0xf8 103 104 /* Various mode for local APIC. Modes are mutually exclusive */ 105 #define APIC_IS_DISABLED 0x0 106 #define APIC_MODE_NOTSET 0x1 107 #define LOCAL_APIC 0x2 108 #define LOCAL_X2APIC 0x3 109 110 /* x2APIC SELF IPI Reguster */ 111 #define X2APIC_SELF_IPI 0x100 112 113 /* General x2APIC constants used at various places */ 114 #define APIC_SVR 12 115 #define APIC_DIRECTED_EOI 24 116 117 /* IRR register */ 118 #define APIC_IRR_REG 0x80 119 120 /* ISR register */ 121 #define APIC_ISR_REG 0x40 122 123 #define APIC_IO_REG 0x0 124 #define APIC_IO_DATA 0x4 125 #define APIC_IO_EOI 0x10 126 127 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 128 #define APIC_ID_BIT_OFFSET 24 129 #define APIC_ICR_ID_BIT_OFFSET 24 130 #define APIC_LDR_ID_BIT_OFFSET 24 131 132 /* 133 * Choose between flat and clustered models by writing the following to the 134 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 135 * disable logical destination mode. 136 * Does not seem to be in the docs for local APICs on the processors. 137 */ 138 #define APIC_FLAT_MODEL 0xFFFFFFFFUL 139 #define APIC_CLUSTER_MODEL 0x0FFFFFFF 140 141 /* 142 * The commands which follow are window selectors written to APIC_IO_REG 143 * before data can be read/written from/to APIC_IO_DATA 144 */ 145 146 #define APIC_ID_CMD 0x0 147 #define APIC_VERS_CMD 0x1 148 #define APIC_RDT_CMD 0x10 149 #define APIC_RDT_CMD2 0x11 150 151 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 152 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 153 154 #define APIC_INT_SPURIOUS -1 155 156 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 157 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 158 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 159 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 160 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 161 162 #define APIC_CT_VECT 0x4ac /* conf table vector */ 163 #define APIC_CT_SIZE 1024 /* conf table size */ 164 165 #define APIC_ID 'MPAT' /* conf table signature */ 166 167 #define VENID_AMD 0x1022 168 #define DEVID_8131_IOAPIC 0x7451 169 #define DEVID_8132_IOAPIC 0x7459 170 171 #define IOAPICS_NODE_NAME "ioapics" 172 #define IOAPICS_CHILD_NAME "ioapic" 173 #define IOAPICS_DEV_TYPE "ioapic" 174 #define IOAPICS_PROP_VENID "vendor-id" 175 #define IOAPICS_PROP_DEVID "device-id" 176 177 #define IS_CLASS_IOAPIC(b, s, p) \ 178 ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \ 179 ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \ 180 (p) == PCI_PERIPH_PIC_IF_IOX_APIC)) 181 182 /* 183 * These macros are used in frequently called routines like 184 * apic_intr_enter(). 185 */ 186 #define X2APIC_WRITE(reg, v) \ 187 wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v) 188 189 #define LOCAL_APIC_WRITE_REG(reg, v) \ 190 apicadr[reg] = v 191 192 /* 193 * MP floating pointer structure defined in Intel MP Spec 1.1 194 */ 195 struct apic_mpfps_hdr { 196 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 197 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 198 uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 199 uchar_t mpfps_spec_rev; /* version number of MP spec */ 200 uchar_t mpfps_checksum; /* checksum of complete structure */ 201 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 202 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 203 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 204 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 205 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 206 }; 207 208 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 209 210 #define APIC_MPS_OEM_ID_LEN 8 211 #define APIC_MPS_PROD_ID_LEN 12 212 213 struct apic_mp_cnf_hdr { 214 uint_t mpcnf_sig; 215 216 uint_t mpcnf_tbl_length: 16, 217 mpcnf_spec: 8, 218 mpcnf_cksum: 8; 219 220 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 221 222 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 223 224 uint_t mpcnf_oem_ptr; 225 226 uint_t mpcnf_oem_tbl_size: 16, 227 mpcnf_entry_cnt: 16; 228 229 uint_t mpcnf_local_apic; 230 231 uint_t mpcnf_resv; 232 }; 233 234 struct apic_procent { 235 uint_t proc_entry: 8, 236 proc_apicid: 8, 237 proc_version: 8, 238 proc_cpuflags: 8; 239 240 uint_t proc_stepping: 4, 241 proc_model: 4, 242 proc_family: 4, 243 proc_type: 2, /* undocumented feature */ 244 proc_resv1: 18; 245 246 uint_t proc_feature; 247 248 uint_t proc_resv2; 249 250 uint_t proc_resv3; 251 }; 252 253 /* 254 * proc_cpuflags definitions 255 */ 256 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 257 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 258 259 260 struct apic_bus { 261 uchar_t bus_entry; 262 uchar_t bus_id; 263 ushort_t bus_str1; 264 uint_t bus_str2; 265 }; 266 267 struct apic_io_entry { 268 uint_t io_entry: 8, 269 io_apicid: 8, 270 io_version: 8, 271 io_flags: 8; 272 273 uint_t io_apic_addr; 274 }; 275 276 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 277 278 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 279 280 struct apic_io_intr { 281 uint_t intr_entry: 8, 282 intr_type: 8, 283 intr_po: 2, 284 intr_el: 2, 285 intr_resv: 12; 286 287 uint_t intr_busid: 8, 288 intr_irq: 8, 289 intr_destid: 8, 290 intr_destintin: 8; 291 }; 292 293 /* 294 * intr_type definitions 295 */ 296 #define IO_INTR_INT 0x00 297 #define IO_INTR_NMI 0x01 298 #define IO_INTR_SMI 0x02 299 #define IO_INTR_EXTINT 0x03 300 301 /* 302 * destination APIC ID 303 */ 304 #define INTR_ALL_APIC 0xff 305 306 307 /* local vector table */ 308 #define AV_MASK 0x10000 309 310 /* interrupt command register 32-63 */ 311 #define AV_TOALL 0x7fffffff 312 #define AV_HIGH_ORDER 0x40000000 313 #define AV_IM_OFF 0x40000000 314 315 /* interrupt command register 0-31 */ 316 #define AV_DELIV_MODE 0x700 317 318 #define AV_FIXED 0x000 319 #define AV_LOPRI 0x100 320 #define AV_SMI 0x200 321 #define AV_REMOTE 0x300 322 #define AV_NMI 0x400 323 #define AV_RESET 0x500 324 #define AV_STARTUP 0x600 325 #define AV_EXTINT 0x700 326 327 #define AV_PDEST 0x000 328 #define AV_LDEST 0x800 329 330 /* IO & Local APIC Bit Definitions */ 331 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 332 #define AV_PENDING 0x1000 333 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 334 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 335 #define AV_LEVEL 0x8000 336 #define AV_DEASSERT AV_LEVEL 337 #define AV_ASSERT 0xc000 338 339 #define AV_READ_PENDING 0x10000 340 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 341 342 #define AV_SH_SELF 0x40000 /* Short hand for self */ 343 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 344 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 345 /* spurious interrupt vector register */ 346 #define AV_UNIT_ENABLE 0x100 347 348 /* timer vector table */ 349 #define AV_TIME 0x20000 /* Set timer mode to periodic */ 350 351 #define APIC_MAXVAL 0xffffffffUL 352 #define APIC_TIME_MIN 0x5000 353 #define APIC_TIME_COUNT 0x4000 354 355 /* 356 * Range of the low byte value in apic_tick before starting calibration 357 */ 358 #define APIC_LB_MIN 0x60 359 #define APIC_LB_MAX 0xe0 360 361 #define APIC_MAX_VECTOR 255 362 #define APIC_RESV_VECT 0x00 363 #define APIC_RESV_IRQ 0xfe 364 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 365 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 366 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 367 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 368 #define APIC_VECTOR_MASK 0x0f 369 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 370 #define APIC_IPL_MASK 0xf0 371 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 372 #define APIC_FIRST_FREE_IRQ 0x10 373 #define APIC_MAX_ISA_IRQ 15 374 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 375 #define APIC_IDLE_IPL 0x00 376 377 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 378 379 /* spurious interrupt vector */ 380 #define APIC_SPUR_INTR 0xFF 381 382 /* special or reserve vectors */ 383 #define APIC_CHECK_RESERVE_VECTORS(v) \ 384 (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \ 385 ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET) || ((v) == T_INT80)) 386 387 /* cmos shutdown code for BIOS */ 388 #define BIOS_SHUTDOWN 0x0a 389 390 /* define the entry types for BIOS information tables as defined in PC+MP */ 391 #define APIC_CPU_ENTRY 0 392 #define APIC_BUS_ENTRY 1 393 #define APIC_IO_ENTRY 2 394 #define APIC_IO_INTR_ENTRY 3 395 #define APIC_LOCAL_INTR_ENTRY 4 396 #define APIC_MPTBL_ADDR (639 * 1024) 397 /* 398 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 399 * of system base memory or in ROM between 0xF0000 and 0xFFFFF 400 */ 401 #define MPFPS_RAM_WIN_LEN 1024 402 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 403 #define MPFPS_ROM_WIN_LEN 0x10000 404 405 #define EISA_LEVEL_CNTL 0x4D0 406 407 /* definitions for apic_irq_table */ 408 #define FREE_INDEX (short)-1 /* empty slot */ 409 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 410 #define ACPI_INDEX (short)-3 /* ACPI */ 411 #define MSI_INDEX (short)-4 /* MSI */ 412 #define MSIX_INDEX (short)-5 /* MSI-X */ 413 #define DEFAULT_INDEX (short)0x7FFF 414 /* biggest positive no. to avoid conflict with actual index */ 415 416 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 417 ((index) == MSI_INDEX || (index) == MSIX_INDEX) 418 419 /* 420 * definitions for MSI Address 421 */ 422 #define MSI_ADDR_HDR APIC_LOCAL_ADDR 423 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 424 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 425 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 426 #define MSI_ADDR_RH_SHIFT 3 427 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 428 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 429 #define MSI_ADDR_DM_SHIFT 2 430 431 /* 432 * definitions for MSI Data 433 */ 434 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 435 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 436 #define MSI_DATA_DELIVERY_SMI 0x2 437 #define MSI_DATA_DELIVERY_NMI 0x4 438 #define MSI_DATA_DELIVERY_INIT 0x5 439 #define MSI_DATA_DELIVERY_EXTINT 0x7 440 #define MSI_DATA_DELIVERY_SHIFT 8 441 #define MSI_DATA_TM_EDGE 0x0 /* MSI is edge sensitive */ 442 #define MSI_DATA_TM_LEVEL 0x1 /* level sensitive */ 443 #define MSI_DATA_TM_SHIFT 15 444 #define MSI_DATA_LEVEL_DEASSERT 0x0 445 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 446 #define MSI_DATA_LEVEL_SHIFT 14 447 448 /* 449 * use to define each irq setup by the apic 450 */ 451 typedef struct apic_irq { 452 short airq_mps_intr_index; /* index into mps interrupt entries */ 453 /* table */ 454 uchar_t airq_intin_no; 455 uchar_t airq_ioapicindex; 456 dev_info_t *airq_dip; /* device corresponding to this interrupt */ 457 /* 458 * IRQ could be shared (in H/W) in which case dip & major will be 459 * for the one that was last added at this level. We cannot keep a 460 * linked list as delspl does not tell us which device has just 461 * been unloaded. For most servers where we are worried about 462 * performance, interrupt should not be shared & should not be 463 * a problem. This does not cause any correctness issue - dip is 464 * used only as an optimisation to avoid going thru all the tables 465 * in translate IRQ (which is always called twice due to brokenness 466 * in the way IPLs are determined for devices). major is used only 467 * to bind interrupts corresponding to the same device on the same 468 * CPU. Not finding major will just cause it to be potentially bound 469 * to another CPU. 470 */ 471 major_t airq_major; /* major number corresponding to the device */ 472 ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 473 uint32_t airq_cpu; /* Which CPU are we bound to ? */ 474 uint32_t airq_temp_cpu; /* Could be diff from cpu due to disable_intr */ 475 uchar_t airq_vector; /* Vector chosen for this irq */ 476 uchar_t airq_share; /* number of interrupts at this irq */ 477 uchar_t airq_share_id; /* id to identify source from irqno */ 478 uchar_t airq_ipl; /* The ipl at which this is handled */ 479 iflag_t airq_iflag; /* interrupt flag */ 480 uchar_t airq_origirq; /* original irq passed in */ 481 uint_t airq_busy; /* How frequently did clock find */ 482 /* us in this */ 483 struct apic_irq *airq_next; /* chain of shared intpts */ 484 } apic_irq_t; 485 486 #define IRQ_USER_BOUND 0x80000000 /* user requested bind if set in airq_cpu */ 487 #define IRQ_UNBOUND (uint32_t)-1 /* set in airq_cpu and airq_temp_cpu */ 488 #define IRQ_UNINIT (uint32_t)-2 /* in airq_temp_cpu till addspl called */ 489 490 /* Macros to help deal with shared interrupts */ 491 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 492 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 493 494 typedef struct apic_cpus_info { 495 uint32_t aci_local_id; 496 uchar_t aci_local_ver; 497 uchar_t aci_status; 498 uchar_t aci_redistribute; /* Selected for redistribution */ 499 uint_t aci_busy; /* Number of ticks we were in ISR */ 500 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 501 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 502 uchar_t aci_curipl; /* IPL of current ISR */ 503 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 504 uint32_t aci_bound; /* # of user requested binds ? */ 505 uint32_t aci_temp_bound; /* # of non user IRQ binds */ 506 uchar_t aci_idle; /* The CPU is idle */ 507 /* 508 * fill to make sure each struct is in seperate cache line. 509 * Or atleast that ISR_in_progress/curipl is not shared with something 510 * that is read/written heavily by another CPU. 511 * Given kmem_alloc guarantees alignment to 8 bytes, having 8 512 * bytes on each side will isolate us in a 16 byte cache line. 513 */ 514 } apic_cpus_info_t; 515 516 #define APIC_CPU_ONLINE 1 517 #define APIC_CPU_INTR_ENABLE 2 518 519 /* 520 * APIC ops to support various flavors of APIC like APIC and x2APIC. 521 */ 522 typedef struct apic_regs_ops { 523 uint64_t (*apic_read)(uint32_t); 524 void (*apic_write)(uint32_t, uint64_t); 525 int (*apic_get_pri)(void); 526 void (*apic_write_task_reg)(uint64_t); 527 void (*apic_write_int_cmd)(uint32_t, uint32_t); 528 void (*apic_send_eoi)(uint32_t); 529 } apic_reg_ops_t; 530 531 /* 532 * Various poweroff methods and ports & bits for them 533 */ 534 #define APIC_POWEROFF_NONE 0 535 #define APIC_POWEROFF_VIA_RTC 1 536 #define APIC_POWEROFF_VIA_ASPEN_BMC 2 537 #define APIC_POWEROFF_VIA_SITKA_BMC 3 538 539 /* For RTC */ 540 #define RTC_REGA 0x0a 541 #define PFR_REG 0x4a /* extended control register */ 542 #define PAB_CBIT 0x08 543 #define WF_FLAG 0x02 544 #define KS_FLAG 0x01 545 #define EXT_BANK 0x10 546 547 /* For Aspen/Drake BMC */ 548 549 #define CC_SMS_GET_STATUS 0x40 550 #define CC_SMS_WR_START 0x41 551 #define CC_SMS_WR_NEXT 0x42 552 #define CC_SMS_WR_END 0x43 553 554 #define MISMIC_DATA_REGISTER 0x0ca9 555 #define MISMIC_CNTL_REGISTER 0x0caa 556 #define MISMIC_FLAG_REGISTER 0x0cab 557 558 #define MISMIC_BUSY_MASK 0x01 559 560 /* For Sitka/Cabrillo BMC */ 561 562 #define SMS_GET_STATUS 0x60 563 #define SMS_WRITE_START 0x61 564 #define SMS_WRITE_END 0x62 565 566 #define SMS_DATA_REGISTER 0x0ca2 567 #define SMS_STATUS_REGISTER 0x0ca3 568 #define SMS_COMMAND_REGISTER 0x0ca3 569 570 #define SMS_IBF_MASK 0x02 571 #define SMS_STATE_MASK 0xc0 572 573 #define SMS_IDLE_STATE 0x00 574 #define SMS_READ_STATE 0x40 575 #define SMS_WRITE_STATE 0x80 576 #define SMS_ERROR_STATE 0xc0 577 578 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 579 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 580 extern void ioapic_write_eoi(int ioapic_ix, uint32_t value); 581 582 /* Macros for reading/writing the IOAPIC RDT entries */ 583 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 584 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 585 586 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 587 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 588 589 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 590 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 591 592 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 593 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 594 595 /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 596 typedef struct { 597 uint16_t avgi_req_flags; /* request flags - to kernel */ 598 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 599 uint8_t avgi_vector; /* vector */ 600 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 601 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 602 /* Contains num_devs elements. */ 603 } apic_get_intr_t; 604 605 /* Masks for avgi_req_flags. */ 606 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 607 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 608 #define PSMGI_REQ_VECTOR 0x4 609 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 610 #define PSMGI_REQ_ALL 0xf /* Request everything */ 611 612 /* Other flags */ 613 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 614 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 615 #define PSMGI_INTRBY_FLAGS 0x8000 /* Mask for this flag */ 616 617 /* 618 * Use scaled-fixed-point arithmetic to calculate apic ticks. 619 * Round when dividing (by adding half of divisor to dividend) 620 * for one extra bit of precision. 621 */ 622 623 #define SF (1ULL<<20) /* Scaling Factor: scale by 2^20 */ 624 #define APIC_TICKS_TO_NSECS(ticks) ((((int64_t)(ticks) * SF) + \ 625 apic_ticks_per_SFnsecs / 2) / \ 626 apic_ticks_per_SFnsecs); 627 #define APIC_NSECS_TO_TICKS(nsecs) (((int64_t)(nsecs) * \ 628 apic_ticks_per_SFnsecs + (SF/2)) / SF) 629 630 extern int apic_verbose; 631 632 /* Flag definitions for apic_verbose */ 633 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 634 #define APIC_VERBOSE_IRQ_FLAG 0x00000002 635 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 636 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 637 638 639 #define APIC_VERBOSE_IOAPIC(fmt) \ 640 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 641 cmn_err fmt; 642 643 #define APIC_VERBOSE_IRQ(fmt) \ 644 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 645 cmn_err fmt; 646 647 #define APIC_VERBOSE_POWEROFF(fmt) \ 648 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 649 prom_printf fmt; 650 651 #ifdef DEBUG 652 #define DENT 0x0001 653 extern int apic_debug; 654 /* 655 * set apic_restrict_vector to the # of vectors we want to allow per range 656 * useful in testing shared interrupt logic by setting it to 2 or 3 657 */ 658 extern int apic_restrict_vector; 659 660 #define APIC_DEBUG_MSGBUFSIZE 2048 661 extern int apic_debug_msgbuf[]; 662 extern int apic_debug_msgbufindex; 663 664 /* 665 * Put "int" info into debug buffer. No MP consistency, but light weight. 666 * Good enough for most debugging. 667 */ 668 #define APIC_DEBUG_BUF_PUT(x) \ 669 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 670 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 671 apic_debug_msgbufindex = 0; 672 673 #endif /* DEBUG */ 674 675 extern int apic_error; 676 /* values which apic_error can take. Not catastrophic, but may help debug */ 677 #define APIC_ERR_BOOT_EOI 0x1 678 #define APIC_ERR_GET_IPIVECT_FAIL 0x2 679 #define APIC_ERR_INVALID_INDEX 0x4 680 #define APIC_ERR_MARK_VECTOR_FAIL 0x8 681 #define APIC_ERR_APIC_ERROR 0x40000000 682 #define APIC_ERR_NMI 0x80000000 683 684 /* 685 * ACPI definitions 686 */ 687 /* _PIC method arguments */ 688 #define ACPI_PIC_MODE 0 689 #define ACPI_APIC_MODE 1 690 691 /* APIC error flags we care about */ 692 #define APIC_SEND_CS_ERROR 0x01 693 #define APIC_RECV_CS_ERROR 0x02 694 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 695 696 /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 697 #define APIC_REPROGRAM_MAX_TRIES 10000 698 699 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 700 #define IOAPIC_MASK 1 701 #define IOAPIC_NOMASK 0 702 703 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 704 #define INTR_ROUND_ROBIN 1 705 #define INTR_LOWEST_PRIORITY 2 706 707 708 709 struct ioapic_reprogram_data { 710 boolean_t done; 711 apic_irq_t *irqp; 712 /* The CPU to which the int will be bound */ 713 int bindcpu; 714 /* # times the reprogram timeout was called */ 715 unsigned tries; 716 }; 717 718 /* The irq # is implicit in the array index: */ 719 extern struct ioapic_reprogram_data apic_reprogram_info[]; 720 721 extern void apic_intr_exit(int ipl, int irq); 722 extern void x2apic_intr_exit(int ipl, int irq); 723 extern int apic_probe_common(); 724 extern void apic_init_common(); 725 extern void ioapic_init_intr(); 726 extern void ioapic_disable_redirection(); 727 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 728 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 729 extern void apic_cleanup_busy(); 730 extern void apic_intr_redistribute(); 731 extern uchar_t apic_xlate_vector(uchar_t vector); 732 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 733 extern void apic_free_vector(uchar_t vector); 734 extern int apic_allocate_irq(int irq); 735 extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 736 uchar_t intin); 737 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 738 struct ioapic_reprogram_data *drep); 739 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 740 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 741 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 742 psm_intr_op_t intr_op, int *result); 743 extern int apic_state(psm_state_request_t *); 744 extern boolean_t apic_cpu_in_range(int cpu); 745 extern int apic_check_msi_support(); 746 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 747 int type); 748 extern int apic_navail_vector(dev_info_t *dip, int pri); 749 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, 750 int pri, int behavior); 751 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, 752 int pri, int behavior); 753 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 754 int type); 755 extern int apic_get_vector_intr_info(int vecirq, 756 apic_get_intr_t *intr_params_p); 757 extern uchar_t apic_find_multi_vectors(int pri, int count); 758 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 759 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 760 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 761 extern void mapout_apic(caddr_t addr, size_t len); 762 extern void mapout_ioapic(caddr_t addr, size_t len); 763 extern uchar_t apic_modify_vector(uchar_t vector, int irq); 764 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 765 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type); 766 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 767 extern void apic_pci_msi_enable_vector(dev_info_t *dip, int type, int inum, 768 int vector, int count, int target_apic_id); 769 extern char *apic_get_apic_type(); 770 extern uint16_t apic_get_apic_version(); 771 extern void x2apic_send_ipi(); 772 extern void apic_ret(); 773 extern int apic_detect_x2apic(); 774 extern void apic_enable_x2apic(); 775 extern void apic_change_eoi(); 776 extern void apic_send_EOI(uint32_t); 777 extern void apic_send_directed_EOI(uint32_t); 778 779 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 780 extern int apic_forceload; 781 extern apic_cpus_info_t *apic_cpus; 782 #ifdef _MACHDEP 783 extern cpuset_t apic_cpumask; 784 #endif 785 extern uint_t apic_picinit_called; 786 extern uchar_t apic_ipltopri[MAXIPL+1]; 787 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 788 extern int apic_max_device_irq; 789 extern int apic_min_device_irq; 790 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 791 extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 792 extern uchar_t apic_io_id[MAX_IO_APIC]; 793 extern lock_t apic_ioapic_lock; 794 extern uint32_t apic_physaddr[MAX_IO_APIC]; 795 extern kmutex_t airq_mutex; 796 extern int apic_first_avail_irq; 797 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 798 extern int apic_imcrp; 799 extern int apic_revector_pending; 800 extern char apic_level_intr[APIC_MAX_VECTOR+1]; 801 extern uchar_t apic_resv_vector[MAXIPL+1]; 802 extern int apic_sample_factor_redistribution; 803 extern int apic_int_busy_mark; 804 extern int apic_int_free_mark; 805 extern int apic_diff_for_redistribution; 806 extern int apic_poweroff_method; 807 extern int apic_enable_acpi; 808 extern int apic_nproc; 809 extern int apic_next_bind_cpu; 810 extern int apic_redistribute_sample_interval; 811 extern int apic_multi_msi_enable; 812 extern int apic_multi_msi_max; 813 extern int apic_msix_max; 814 extern int apic_sci_vect; 815 extern uchar_t apic_ipls[]; 816 extern apic_reg_ops_t *apic_reg_ops; 817 extern int apic_mode; 818 extern int apic_direct_EOI; 819 extern void x2apic_update_psm(); 820 821 822 #ifdef __cplusplus 823 } 824 #endif 825 826 #endif /* _SYS_APIC_APIC_H */ 827