xref: /titanic_51/usr/src/uts/i86pc/os/mp_startup.c (revision c586600796766c83eb9485c446886fd9ed2359a9)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 /*
27  * Copyright (c) 2010, Intel Corporation.
28  * All rights reserved.
29  */
30 
31 #include <sys/types.h>
32 #include <sys/thread.h>
33 #include <sys/cpuvar.h>
34 #include <sys/cpu.h>
35 #include <sys/t_lock.h>
36 #include <sys/param.h>
37 #include <sys/proc.h>
38 #include <sys/disp.h>
39 #include <sys/class.h>
40 #include <sys/cmn_err.h>
41 #include <sys/debug.h>
42 #include <sys/note.h>
43 #include <sys/asm_linkage.h>
44 #include <sys/x_call.h>
45 #include <sys/systm.h>
46 #include <sys/var.h>
47 #include <sys/vtrace.h>
48 #include <vm/hat.h>
49 #include <vm/as.h>
50 #include <vm/seg_kmem.h>
51 #include <vm/seg_kp.h>
52 #include <sys/segments.h>
53 #include <sys/kmem.h>
54 #include <sys/stack.h>
55 #include <sys/smp_impldefs.h>
56 #include <sys/x86_archext.h>
57 #include <sys/machsystm.h>
58 #include <sys/traptrace.h>
59 #include <sys/clock.h>
60 #include <sys/cpc_impl.h>
61 #include <sys/pg.h>
62 #include <sys/cmt.h>
63 #include <sys/dtrace.h>
64 #include <sys/archsystm.h>
65 #include <sys/fp.h>
66 #include <sys/reboot.h>
67 #include <sys/kdi_machimpl.h>
68 #include <vm/hat_i86.h>
69 #include <vm/vm_dep.h>
70 #include <sys/memnode.h>
71 #include <sys/pci_cfgspace.h>
72 #include <sys/mach_mmu.h>
73 #include <sys/sysmacros.h>
74 #if defined(__xpv)
75 #include <sys/hypervisor.h>
76 #endif
77 #include <sys/cpu_module.h>
78 
79 struct cpu	cpus[1];			/* CPU data */
80 struct cpu	*cpu[NCPU] = {&cpus[0]};	/* pointers to all CPUs */
81 struct cpu	*cpu_free_list;			/* list for released CPUs */
82 cpu_core_t	cpu_core[NCPU];			/* cpu_core structures */
83 
84 #define	cpu_next_free	cpu_prev
85 
86 /*
87  * Useful for disabling MP bring-up on a MP capable system.
88  */
89 int use_mp = 1;
90 
91 /*
92  * to be set by a PSM to indicate what cpus
93  * are sitting around on the system.
94  */
95 cpuset_t mp_cpus;
96 
97 /*
98  * This variable is used by the hat layer to decide whether or not
99  * critical sections are needed to prevent race conditions.  For sun4m,
100  * this variable is set once enough MP initialization has been done in
101  * order to allow cross calls.
102  */
103 int flushes_require_xcalls;
104 
105 cpuset_t cpu_ready_set;		/* initialized in startup() */
106 
107 static void mp_startup_boot(void);
108 static void mp_startup_hotplug(void);
109 
110 static void cpu_sep_enable(void);
111 static void cpu_sep_disable(void);
112 static void cpu_asysc_enable(void);
113 static void cpu_asysc_disable(void);
114 
115 /*
116  * Init CPU info - get CPU type info for processor_info system call.
117  */
118 void
119 init_cpu_info(struct cpu *cp)
120 {
121 	processor_info_t *pi = &cp->cpu_type_info;
122 
123 	/*
124 	 * Get clock-frequency property for the CPU.
125 	 */
126 	pi->pi_clock = cpu_freq;
127 
128 	/*
129 	 * Current frequency in Hz.
130 	 */
131 	cp->cpu_curr_clock = cpu_freq_hz;
132 
133 	/*
134 	 * Supported frequencies.
135 	 */
136 	if (cp->cpu_supp_freqs == NULL) {
137 		cpu_set_supp_freqs(cp, NULL);
138 	}
139 
140 	(void) strcpy(pi->pi_processor_type, "i386");
141 	if (fpu_exists)
142 		(void) strcpy(pi->pi_fputypes, "i387 compatible");
143 
144 	cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
145 	cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
146 
147 	/*
148 	 * If called for the BSP, cp is equal to current CPU.
149 	 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
150 	 * of current CPU as default values for cpu_idstr and cpu_brandstr.
151 	 * They will be corrected in mp_startup_common() after cpuid_pass1()
152 	 * has been invoked on target CPU.
153 	 */
154 	(void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
155 	(void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
156 }
157 
158 /*
159  * Configure syscall support on this CPU.
160  */
161 /*ARGSUSED*/
162 void
163 init_cpu_syscall(struct cpu *cp)
164 {
165 	kpreempt_disable();
166 
167 #if defined(__amd64)
168 	if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) {
169 
170 #if !defined(__lint)
171 		/*
172 		 * The syscall instruction imposes a certain ordering on
173 		 * segment selectors, so we double-check that ordering
174 		 * here.
175 		 */
176 		ASSERT(KDS_SEL == KCS_SEL + 8);
177 		ASSERT(UDS_SEL == U32CS_SEL + 8);
178 		ASSERT(UCS_SEL == U32CS_SEL + 16);
179 #endif
180 		/*
181 		 * Turn syscall/sysret extensions on.
182 		 */
183 		cpu_asysc_enable();
184 
185 		/*
186 		 * Program the magic registers ..
187 		 */
188 		wrmsr(MSR_AMD_STAR,
189 		    ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
190 		wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall);
191 		wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32);
192 
193 		/*
194 		 * This list of flags is masked off the incoming
195 		 * %rfl when we enter the kernel.
196 		 */
197 		wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T));
198 	}
199 #endif
200 
201 	/*
202 	 * On 32-bit kernels, we use sysenter/sysexit because it's too
203 	 * hard to use syscall/sysret, and it is more portable anyway.
204 	 *
205 	 * On 64-bit kernels on Nocona machines, the 32-bit syscall
206 	 * variant isn't available to 32-bit applications, but sysenter is.
207 	 */
208 	if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) {
209 
210 #if !defined(__lint)
211 		/*
212 		 * The sysenter instruction imposes a certain ordering on
213 		 * segment selectors, so we double-check that ordering
214 		 * here. See "sysenter" in Intel document 245471-012, "IA-32
215 		 * Intel Architecture Software Developer's Manual Volume 2:
216 		 * Instruction Set Reference"
217 		 */
218 		ASSERT(KDS_SEL == KCS_SEL + 8);
219 
220 		ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3));
221 		ASSERT32(UDS_SEL == UCS_SEL + 8);
222 
223 		ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3));
224 		ASSERT64(UDS_SEL == U32CS_SEL + 8);
225 #endif
226 
227 		cpu_sep_enable();
228 
229 		/*
230 		 * resume() sets this value to the base of the threads stack
231 		 * via a context handler.
232 		 */
233 		wrmsr(MSR_INTC_SEP_ESP, 0);
234 		wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter);
235 	}
236 
237 	kpreempt_enable();
238 }
239 
240 /*
241  * Multiprocessor initialization.
242  *
243  * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
244  * startup and idle threads for the specified CPU.
245  * Parameter boot is true for boot time operations and is false for CPU
246  * DR operations.
247  */
248 static struct cpu *
249 mp_cpu_configure_common(int cpun, boolean_t boot)
250 {
251 	struct cpu *cp;
252 	kthread_id_t tp;
253 	caddr_t	sp;
254 	proc_t *procp;
255 #if !defined(__xpv)
256 	extern int idle_cpu_prefer_mwait;
257 	extern void cpu_idle_mwait();
258 #endif
259 	extern void idle();
260 	extern void cpu_idle();
261 
262 #ifdef TRAPTRACE
263 	trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
264 #endif
265 
266 	ASSERT(MUTEX_HELD(&cpu_lock));
267 	ASSERT(cpun < NCPU && cpu[cpun] == NULL);
268 
269 	if (cpu_free_list == NULL) {
270 		cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
271 	} else {
272 		cp = cpu_free_list;
273 		cpu_free_list = cp->cpu_next_free;
274 	}
275 
276 	cp->cpu_m.mcpu_istamp = cpun << 16;
277 
278 	/* Create per CPU specific threads in the process p0. */
279 	procp = &p0;
280 
281 	/*
282 	 * Initialize the dispatcher first.
283 	 */
284 	disp_cpu_init(cp);
285 
286 	cpu_vm_data_init(cp);
287 
288 	/*
289 	 * Allocate and initialize the startup thread for this CPU.
290 	 * Interrupt and process switch stacks get allocated later
291 	 * when the CPU starts running.
292 	 */
293 	tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
294 	    TS_STOPPED, maxclsyspri);
295 
296 	/*
297 	 * Set state to TS_ONPROC since this thread will start running
298 	 * as soon as the CPU comes online.
299 	 *
300 	 * All the other fields of the thread structure are setup by
301 	 * thread_create().
302 	 */
303 	THREAD_ONPROC(tp, cp);
304 	tp->t_preempt = 1;
305 	tp->t_bound_cpu = cp;
306 	tp->t_affinitycnt = 1;
307 	tp->t_cpu = cp;
308 	tp->t_disp_queue = cp->cpu_disp;
309 
310 	/*
311 	 * Setup thread to start in mp_startup_common.
312 	 */
313 	sp = tp->t_stk;
314 	tp->t_sp = (uintptr_t)(sp - MINFRAME);
315 #if defined(__amd64)
316 	tp->t_sp -= STACK_ENTRY_ALIGN;		/* fake a call */
317 #endif
318 	/*
319 	 * Setup thread start entry point for boot or hotplug.
320 	 */
321 	if (boot) {
322 		tp->t_pc = (uintptr_t)mp_startup_boot;
323 	} else {
324 		tp->t_pc = (uintptr_t)mp_startup_hotplug;
325 	}
326 
327 	cp->cpu_id = cpun;
328 	cp->cpu_self = cp;
329 	cp->cpu_thread = tp;
330 	cp->cpu_lwp = NULL;
331 	cp->cpu_dispthread = tp;
332 	cp->cpu_dispatch_pri = DISP_PRIO(tp);
333 
334 	/*
335 	 * cpu_base_spl must be set explicitly here to prevent any blocking
336 	 * operations in mp_startup_common from causing the spl of the cpu
337 	 * to drop to 0 (allowing device interrupts before we're ready) in
338 	 * resume().
339 	 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
340 	 * As an extra bit of security on DEBUG kernels, this is enforced with
341 	 * an assertion in mp_startup_common() -- before cpu_base_spl is set
342 	 * to its proper value.
343 	 */
344 	cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
345 
346 	/*
347 	 * Now, initialize per-CPU idle thread for this CPU.
348 	 */
349 	tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
350 
351 	cp->cpu_idle_thread = tp;
352 
353 	tp->t_preempt = 1;
354 	tp->t_bound_cpu = cp;
355 	tp->t_affinitycnt = 1;
356 	tp->t_cpu = cp;
357 	tp->t_disp_queue = cp->cpu_disp;
358 
359 	/*
360 	 * Bootstrap the CPU's PG data
361 	 */
362 	pg_cpu_bootstrap(cp);
363 
364 	/*
365 	 * Perform CPC initialization on the new CPU.
366 	 */
367 	kcpc_hw_init(cp);
368 
369 	/*
370 	 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
371 	 * for each CPU.
372 	 */
373 	setup_vaddr_for_ppcopy(cp);
374 
375 	/*
376 	 * Allocate page for new GDT and initialize from current GDT.
377 	 */
378 #if !defined(__lint)
379 	ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
380 #endif
381 	cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
382 	bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
383 
384 #if defined(__i386)
385 	/*
386 	 * setup kernel %gs.
387 	 */
388 	set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
389 	    SEL_KPL, 0, 1);
390 #endif
391 
392 	/*
393 	 * If we have more than one node, each cpu gets a copy of IDT
394 	 * local to its node. If this is a Pentium box, we use cpu 0's
395 	 * IDT. cpu 0's IDT has been made read-only to workaround the
396 	 * cmpxchgl register bug
397 	 */
398 	if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) {
399 #if !defined(__lint)
400 		ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
401 #endif
402 		cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP);
403 		bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
404 	} else {
405 		cp->cpu_idt = CPU->cpu_idt;
406 	}
407 
408 	/*
409 	 * Get interrupt priority data from cpu 0.
410 	 */
411 	cp->cpu_pri_data = CPU->cpu_pri_data;
412 
413 	/*
414 	 * alloc space for cpuid info
415 	 */
416 	cpuid_alloc_space(cp);
417 #if !defined(__xpv)
418 	if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) {
419 		cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
420 		cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
421 	} else
422 #endif
423 		cp->cpu_m.mcpu_idle_cpu = cpu_idle;
424 
425 	init_cpu_info(cp);
426 
427 	/*
428 	 * alloc space for ucode_info
429 	 */
430 	ucode_alloc_space(cp);
431 	xc_init_cpu(cp);
432 	hat_cpu_online(cp);
433 
434 #ifdef TRAPTRACE
435 	/*
436 	 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
437 	 */
438 	ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
439 	ttc->ttc_next = ttc->ttc_first;
440 	ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
441 #endif
442 
443 	/*
444 	 * Record that we have another CPU.
445 	 */
446 	/*
447 	 * Initialize the interrupt threads for this CPU
448 	 */
449 	cpu_intr_alloc(cp, NINTR_THREADS);
450 
451 	cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
452 	cpu_set_state(cp);
453 
454 	/*
455 	 * Add CPU to list of available CPUs.  It'll be on the active list
456 	 * after mp_startup_common().
457 	 */
458 	cpu_add_unit(cp);
459 
460 	return (cp);
461 }
462 
463 /*
464  * Undo what was done in mp_cpu_configure_common
465  */
466 static void
467 mp_cpu_unconfigure_common(struct cpu *cp, int error)
468 {
469 	ASSERT(MUTEX_HELD(&cpu_lock));
470 
471 	/*
472 	 * Remove the CPU from the list of available CPUs.
473 	 */
474 	cpu_del_unit(cp->cpu_id);
475 
476 	if (error == ETIMEDOUT) {
477 		/*
478 		 * The cpu was started, but never *seemed* to run any
479 		 * code in the kernel; it's probably off spinning in its
480 		 * own private world, though with potential references to
481 		 * our kmem-allocated IDTs and GDTs (for example).
482 		 *
483 		 * Worse still, it may actually wake up some time later,
484 		 * so rather than guess what it might or might not do, we
485 		 * leave the fundamental data structures intact.
486 		 */
487 		cp->cpu_flags = 0;
488 		return;
489 	}
490 
491 	/*
492 	 * At this point, the only threads bound to this CPU should
493 	 * special per-cpu threads: it's idle thread, it's pause threads,
494 	 * and it's interrupt threads.  Clean these up.
495 	 */
496 	cpu_destroy_bound_threads(cp);
497 	cp->cpu_idle_thread = NULL;
498 
499 	/*
500 	 * Free the interrupt stack.
501 	 */
502 	segkp_release(segkp,
503 	    cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
504 	cp->cpu_intr_stack = NULL;
505 
506 #ifdef TRAPTRACE
507 	/*
508 	 * Discard the trap trace buffer
509 	 */
510 	{
511 		trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
512 
513 		kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
514 		ttc->ttc_first = NULL;
515 	}
516 #endif
517 
518 	hat_cpu_offline(cp);
519 
520 	ucode_free_space(cp);
521 
522 	/* Free CPU ID string and brand string. */
523 	if (cp->cpu_idstr) {
524 		kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
525 		cp->cpu_idstr = NULL;
526 	}
527 	if (cp->cpu_brandstr) {
528 		kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
529 		cp->cpu_brandstr = NULL;
530 	}
531 
532 #if !defined(__xpv)
533 	if (cp->cpu_m.mcpu_mwait != NULL) {
534 		cpuid_mwait_free(cp);
535 		cp->cpu_m.mcpu_mwait = NULL;
536 	}
537 #endif
538 	cpuid_free_space(cp);
539 
540 	if (cp->cpu_idt != CPU->cpu_idt)
541 		kmem_free(cp->cpu_idt, PAGESIZE);
542 	cp->cpu_idt = NULL;
543 
544 	kmem_free(cp->cpu_gdt, PAGESIZE);
545 	cp->cpu_gdt = NULL;
546 
547 	if (cp->cpu_supp_freqs != NULL) {
548 		size_t len = strlen(cp->cpu_supp_freqs) + 1;
549 		kmem_free(cp->cpu_supp_freqs, len);
550 		cp->cpu_supp_freqs = NULL;
551 	}
552 
553 	teardown_vaddr_for_ppcopy(cp);
554 
555 	kcpc_hw_fini(cp);
556 
557 	cp->cpu_dispthread = NULL;
558 	cp->cpu_thread = NULL;	/* discarded by cpu_destroy_bound_threads() */
559 
560 	cpu_vm_data_destroy(cp);
561 
562 	xc_fini_cpu(cp);
563 	disp_cpu_fini(cp);
564 
565 	ASSERT(cp != CPU0);
566 	bzero(cp, sizeof (*cp));
567 	cp->cpu_next_free = cpu_free_list;
568 	cpu_free_list = cp;
569 }
570 
571 /*
572  * Apply workarounds for known errata, and warn about those that are absent.
573  *
574  * System vendors occasionally create configurations which contain different
575  * revisions of the CPUs that are almost but not exactly the same.  At the
576  * time of writing, this meant that their clock rates were the same, their
577  * feature sets were the same, but the required workaround were -not-
578  * necessarily the same.  So, this routine is invoked on -every- CPU soon
579  * after starting to make sure that the resulting system contains the most
580  * pessimal set of workarounds needed to cope with *any* of the CPUs in the
581  * system.
582  *
583  * workaround_errata is invoked early in mlsetup() for CPU 0, and in
584  * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
585  * prior to acknowledging their readiness to the master, so this routine will
586  * never be executed by multiple CPUs in parallel, thus making updates to
587  * global data safe.
588  *
589  * These workarounds are based on Rev 3.57 of the Revision Guide for
590  * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
591  */
592 
593 #if defined(OPTERON_ERRATUM_88)
594 int opteron_erratum_88;		/* if non-zero -> at least one cpu has it */
595 #endif
596 
597 #if defined(OPTERON_ERRATUM_91)
598 int opteron_erratum_91;		/* if non-zero -> at least one cpu has it */
599 #endif
600 
601 #if defined(OPTERON_ERRATUM_93)
602 int opteron_erratum_93;		/* if non-zero -> at least one cpu has it */
603 #endif
604 
605 #if defined(OPTERON_ERRATUM_95)
606 int opteron_erratum_95;		/* if non-zero -> at least one cpu has it */
607 #endif
608 
609 #if defined(OPTERON_ERRATUM_100)
610 int opteron_erratum_100;	/* if non-zero -> at least one cpu has it */
611 #endif
612 
613 #if defined(OPTERON_ERRATUM_108)
614 int opteron_erratum_108;	/* if non-zero -> at least one cpu has it */
615 #endif
616 
617 #if defined(OPTERON_ERRATUM_109)
618 int opteron_erratum_109;	/* if non-zero -> at least one cpu has it */
619 #endif
620 
621 #if defined(OPTERON_ERRATUM_121)
622 int opteron_erratum_121;	/* if non-zero -> at least one cpu has it */
623 #endif
624 
625 #if defined(OPTERON_ERRATUM_122)
626 int opteron_erratum_122;	/* if non-zero -> at least one cpu has it */
627 #endif
628 
629 #if defined(OPTERON_ERRATUM_123)
630 int opteron_erratum_123;	/* if non-zero -> at least one cpu has it */
631 #endif
632 
633 #if defined(OPTERON_ERRATUM_131)
634 int opteron_erratum_131;	/* if non-zero -> at least one cpu has it */
635 #endif
636 
637 #if defined(OPTERON_WORKAROUND_6336786)
638 int opteron_workaround_6336786;	/* non-zero -> WA relevant and applied */
639 int opteron_workaround_6336786_UP = 0;	/* Not needed for UP */
640 #endif
641 
642 #if defined(OPTERON_WORKAROUND_6323525)
643 int opteron_workaround_6323525;	/* if non-zero -> at least one cpu has it */
644 #endif
645 
646 #if defined(OPTERON_ERRATUM_298)
647 int opteron_erratum_298;
648 #endif
649 
650 static void
651 workaround_warning(cpu_t *cp, uint_t erratum)
652 {
653 	cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
654 	    cp->cpu_id, erratum);
655 }
656 
657 static void
658 workaround_applied(uint_t erratum)
659 {
660 	if (erratum > 1000000)
661 		cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
662 		    erratum);
663 	else
664 		cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
665 		    erratum);
666 }
667 
668 static void
669 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
670 {
671 	cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
672 	    cp->cpu_id, rw, msr, error);
673 }
674 
675 /*
676  * Determine the number of nodes in a Hammer / Greyhound / Griffin family
677  * system.
678  */
679 static uint_t
680 opteron_get_nnodes(void)
681 {
682 	static uint_t nnodes = 0;
683 
684 	if (nnodes == 0) {
685 #ifdef	DEBUG
686 		uint_t family;
687 
688 		/*
689 		 * This routine uses a PCI config space based mechanism
690 		 * for retrieving the number of nodes in the system.
691 		 * Device 24, function 0, offset 0x60 as used here is not
692 		 * AMD processor architectural, and may not work on processor
693 		 * families other than those listed below.
694 		 *
695 		 * Callers of this routine must ensure that we're running on
696 		 * a processor which supports this mechanism.
697 		 * The assertion below is meant to catch calls on unsupported
698 		 * processors.
699 		 */
700 		family = cpuid_getfamily(CPU);
701 		ASSERT(family == 0xf || family == 0x10 || family == 0x11);
702 #endif	/* DEBUG */
703 
704 		/*
705 		 * Obtain the number of nodes in the system from
706 		 * bits [6:4] of the Node ID register on node 0.
707 		 *
708 		 * The actual node count is NodeID[6:4] + 1
709 		 *
710 		 * The Node ID register is accessed via function 0,
711 		 * offset 0x60. Node 0 is device 24.
712 		 */
713 		nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
714 	}
715 	return (nnodes);
716 }
717 
718 uint_t
719 do_erratum_298(struct cpu *cpu)
720 {
721 	static int	osvwrc = -3;
722 	extern int	osvw_opteron_erratum(cpu_t *, uint_t);
723 
724 	/*
725 	 * L2 Eviction May Occur During Processor Operation To Set
726 	 * Accessed or Dirty Bit.
727 	 */
728 	if (osvwrc == -3) {
729 		osvwrc = osvw_opteron_erratum(cpu, 298);
730 	} else {
731 		/* osvw return codes should be consistent for all cpus */
732 		ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
733 	}
734 
735 	switch (osvwrc) {
736 	case 0:		/* erratum is not present: do nothing */
737 		break;
738 	case 1:		/* erratum is present: BIOS workaround applied */
739 		/*
740 		 * check if workaround is actually in place and issue warning
741 		 * if not.
742 		 */
743 		if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
744 		    ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
745 #if defined(OPTERON_ERRATUM_298)
746 			opteron_erratum_298++;
747 #else
748 			workaround_warning(cpu, 298);
749 			return (1);
750 #endif
751 		}
752 		break;
753 	case -1:	/* cannot determine via osvw: check cpuid */
754 		if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
755 		    (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
756 		    ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
757 #if defined(OPTERON_ERRATUM_298)
758 			opteron_erratum_298++;
759 #else
760 			workaround_warning(cpu, 298);
761 			return (1);
762 #endif
763 		}
764 		break;
765 	}
766 	return (0);
767 }
768 
769 uint_t
770 workaround_errata(struct cpu *cpu)
771 {
772 	uint_t missing = 0;
773 
774 	ASSERT(cpu == CPU);
775 
776 	/*LINTED*/
777 	if (cpuid_opteron_erratum(cpu, 88) > 0) {
778 		/*
779 		 * SWAPGS May Fail To Read Correct GS Base
780 		 */
781 #if defined(OPTERON_ERRATUM_88)
782 		/*
783 		 * The workaround is an mfence in the relevant assembler code
784 		 */
785 		opteron_erratum_88++;
786 #else
787 		workaround_warning(cpu, 88);
788 		missing++;
789 #endif
790 	}
791 
792 	if (cpuid_opteron_erratum(cpu, 91) > 0) {
793 		/*
794 		 * Software Prefetches May Report A Page Fault
795 		 */
796 #if defined(OPTERON_ERRATUM_91)
797 		/*
798 		 * fix is in trap.c
799 		 */
800 		opteron_erratum_91++;
801 #else
802 		workaround_warning(cpu, 91);
803 		missing++;
804 #endif
805 	}
806 
807 	if (cpuid_opteron_erratum(cpu, 93) > 0) {
808 		/*
809 		 * RSM Auto-Halt Restart Returns to Incorrect RIP
810 		 */
811 #if defined(OPTERON_ERRATUM_93)
812 		/*
813 		 * fix is in trap.c
814 		 */
815 		opteron_erratum_93++;
816 #else
817 		workaround_warning(cpu, 93);
818 		missing++;
819 #endif
820 	}
821 
822 	/*LINTED*/
823 	if (cpuid_opteron_erratum(cpu, 95) > 0) {
824 		/*
825 		 * RET Instruction May Return to Incorrect EIP
826 		 */
827 #if defined(OPTERON_ERRATUM_95)
828 #if defined(_LP64)
829 		/*
830 		 * Workaround this by ensuring that 32-bit user code and
831 		 * 64-bit kernel code never occupy the same address
832 		 * range mod 4G.
833 		 */
834 		if (_userlimit32 > 0xc0000000ul)
835 			*(uintptr_t *)&_userlimit32 = 0xc0000000ul;
836 
837 		/*LINTED*/
838 		ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
839 		opteron_erratum_95++;
840 #endif	/* _LP64 */
841 #else
842 		workaround_warning(cpu, 95);
843 		missing++;
844 #endif
845 	}
846 
847 	if (cpuid_opteron_erratum(cpu, 100) > 0) {
848 		/*
849 		 * Compatibility Mode Branches Transfer to Illegal Address
850 		 */
851 #if defined(OPTERON_ERRATUM_100)
852 		/*
853 		 * fix is in trap.c
854 		 */
855 		opteron_erratum_100++;
856 #else
857 		workaround_warning(cpu, 100);
858 		missing++;
859 #endif
860 	}
861 
862 	/*LINTED*/
863 	if (cpuid_opteron_erratum(cpu, 108) > 0) {
864 		/*
865 		 * CPUID Instruction May Return Incorrect Model Number In
866 		 * Some Processors
867 		 */
868 #if defined(OPTERON_ERRATUM_108)
869 		/*
870 		 * (Our cpuid-handling code corrects the model number on
871 		 * those processors)
872 		 */
873 #else
874 		workaround_warning(cpu, 108);
875 		missing++;
876 #endif
877 	}
878 
879 	/*LINTED*/
880 	if (cpuid_opteron_erratum(cpu, 109) > 0) do {
881 		/*
882 		 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
883 		 */
884 #if defined(OPTERON_ERRATUM_109)
885 		/*
886 		 * The "workaround" is to print a warning to upgrade the BIOS
887 		 */
888 		uint64_t value;
889 		const uint_t msr = MSR_AMD_PATCHLEVEL;
890 		int err;
891 
892 		if ((err = checked_rdmsr(msr, &value)) != 0) {
893 			msr_warning(cpu, "rd", msr, err);
894 			workaround_warning(cpu, 109);
895 			missing++;
896 		}
897 		if (value == 0)
898 			opteron_erratum_109++;
899 #else
900 		workaround_warning(cpu, 109);
901 		missing++;
902 #endif
903 	/*CONSTANTCONDITION*/
904 	} while (0);
905 
906 	/*LINTED*/
907 	if (cpuid_opteron_erratum(cpu, 121) > 0) {
908 		/*
909 		 * Sequential Execution Across Non_Canonical Boundary Caused
910 		 * Processor Hang
911 		 */
912 #if defined(OPTERON_ERRATUM_121)
913 #if defined(_LP64)
914 		/*
915 		 * Erratum 121 is only present in long (64 bit) mode.
916 		 * Workaround is to include the page immediately before the
917 		 * va hole to eliminate the possibility of system hangs due to
918 		 * sequential execution across the va hole boundary.
919 		 */
920 		if (opteron_erratum_121)
921 			opteron_erratum_121++;
922 		else {
923 			if (hole_start) {
924 				hole_start -= PAGESIZE;
925 			} else {
926 				/*
927 				 * hole_start not yet initialized by
928 				 * mmu_init. Initialize hole_start
929 				 * with value to be subtracted.
930 				 */
931 				hole_start = PAGESIZE;
932 			}
933 			opteron_erratum_121++;
934 		}
935 #endif	/* _LP64 */
936 #else
937 		workaround_warning(cpu, 121);
938 		missing++;
939 #endif
940 	}
941 
942 	/*LINTED*/
943 	if (cpuid_opteron_erratum(cpu, 122) > 0) do {
944 		/*
945 		 * TLB Flush Filter May Cause Coherency Problem in
946 		 * Multiprocessor Systems
947 		 */
948 #if defined(OPTERON_ERRATUM_122)
949 		uint64_t value;
950 		const uint_t msr = MSR_AMD_HWCR;
951 		int error;
952 
953 		/*
954 		 * Erratum 122 is only present in MP configurations (multi-core
955 		 * or multi-processor).
956 		 */
957 #if defined(__xpv)
958 		if (!DOMAIN_IS_INITDOMAIN(xen_info))
959 			break;
960 		if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
961 			break;
962 #else
963 		if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
964 		    cpuid_get_ncpu_per_chip(cpu) == 1)
965 			break;
966 #endif
967 		/* disable TLB Flush Filter */
968 
969 		if ((error = checked_rdmsr(msr, &value)) != 0) {
970 			msr_warning(cpu, "rd", msr, error);
971 			workaround_warning(cpu, 122);
972 			missing++;
973 		} else {
974 			value |= (uint64_t)AMD_HWCR_FFDIS;
975 			if ((error = checked_wrmsr(msr, value)) != 0) {
976 				msr_warning(cpu, "wr", msr, error);
977 				workaround_warning(cpu, 122);
978 				missing++;
979 			}
980 		}
981 		opteron_erratum_122++;
982 #else
983 		workaround_warning(cpu, 122);
984 		missing++;
985 #endif
986 	/*CONSTANTCONDITION*/
987 	} while (0);
988 
989 	/*LINTED*/
990 	if (cpuid_opteron_erratum(cpu, 123) > 0) do {
991 		/*
992 		 * Bypassed Reads May Cause Data Corruption of System Hang in
993 		 * Dual Core Processors
994 		 */
995 #if defined(OPTERON_ERRATUM_123)
996 		uint64_t value;
997 		const uint_t msr = MSR_AMD_PATCHLEVEL;
998 		int err;
999 
1000 		/*
1001 		 * Erratum 123 applies only to multi-core cpus.
1002 		 */
1003 		if (cpuid_get_ncpu_per_chip(cpu) < 2)
1004 			break;
1005 #if defined(__xpv)
1006 		if (!DOMAIN_IS_INITDOMAIN(xen_info))
1007 			break;
1008 #endif
1009 		/*
1010 		 * The "workaround" is to print a warning to upgrade the BIOS
1011 		 */
1012 		if ((err = checked_rdmsr(msr, &value)) != 0) {
1013 			msr_warning(cpu, "rd", msr, err);
1014 			workaround_warning(cpu, 123);
1015 			missing++;
1016 		}
1017 		if (value == 0)
1018 			opteron_erratum_123++;
1019 #else
1020 		workaround_warning(cpu, 123);
1021 		missing++;
1022 
1023 #endif
1024 	/*CONSTANTCONDITION*/
1025 	} while (0);
1026 
1027 	/*LINTED*/
1028 	if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1029 		/*
1030 		 * Multiprocessor Systems with Four or More Cores May Deadlock
1031 		 * Waiting for a Probe Response
1032 		 */
1033 #if defined(OPTERON_ERRATUM_131)
1034 		uint64_t nbcfg;
1035 		const uint_t msr = MSR_AMD_NB_CFG;
1036 		const uint64_t wabits =
1037 		    AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1038 		int error;
1039 
1040 		/*
1041 		 * Erratum 131 applies to any system with four or more cores.
1042 		 */
1043 		if (opteron_erratum_131)
1044 			break;
1045 #if defined(__xpv)
1046 		if (!DOMAIN_IS_INITDOMAIN(xen_info))
1047 			break;
1048 		if (xpv_nr_phys_cpus() < 4)
1049 			break;
1050 #else
1051 		if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1052 			break;
1053 #endif
1054 		/*
1055 		 * Print a warning if neither of the workarounds for
1056 		 * erratum 131 is present.
1057 		 */
1058 		if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1059 			msr_warning(cpu, "rd", msr, error);
1060 			workaround_warning(cpu, 131);
1061 			missing++;
1062 		} else if ((nbcfg & wabits) == 0) {
1063 			opteron_erratum_131++;
1064 		} else {
1065 			/* cannot have both workarounds set */
1066 			ASSERT((nbcfg & wabits) != wabits);
1067 		}
1068 #else
1069 		workaround_warning(cpu, 131);
1070 		missing++;
1071 #endif
1072 	/*CONSTANTCONDITION*/
1073 	} while (0);
1074 
1075 	/*
1076 	 * This isn't really an erratum, but for convenience the
1077 	 * detection/workaround code lives here and in cpuid_opteron_erratum.
1078 	 */
1079 	if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1080 #if defined(OPTERON_WORKAROUND_6336786)
1081 		/*
1082 		 * Disable C1-Clock ramping on multi-core/multi-processor
1083 		 * K8 platforms to guard against TSC drift.
1084 		 */
1085 		if (opteron_workaround_6336786) {
1086 			opteron_workaround_6336786++;
1087 #if defined(__xpv)
1088 		} else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1089 		    xpv_nr_phys_cpus() > 1) ||
1090 		    opteron_workaround_6336786_UP) {
1091 			/*
1092 			 * XXPV	Hmm.  We can't walk the Northbridges on
1093 			 *	the hypervisor; so just complain and drive
1094 			 *	on.  This probably needs to be fixed in
1095 			 *	the hypervisor itself.
1096 			 */
1097 			opteron_workaround_6336786++;
1098 			workaround_warning(cpu, 6336786);
1099 #else	/* __xpv */
1100 		} else if ((opteron_get_nnodes() *
1101 		    cpuid_get_ncpu_per_chip(cpu) > 1) ||
1102 		    opteron_workaround_6336786_UP) {
1103 
1104 			uint_t	node, nnodes;
1105 			uint8_t data;
1106 
1107 			nnodes = opteron_get_nnodes();
1108 			for (node = 0; node < nnodes; node++) {
1109 				/*
1110 				 * Clear PMM7[1:0] (function 3, offset 0x87)
1111 				 * Northbridge device is the node id + 24.
1112 				 */
1113 				data = pci_getb_func(0, node + 24, 3, 0x87);
1114 				data &= 0xFC;
1115 				pci_putb_func(0, node + 24, 3, 0x87, data);
1116 			}
1117 			opteron_workaround_6336786++;
1118 #endif	/* __xpv */
1119 		}
1120 #else
1121 		workaround_warning(cpu, 6336786);
1122 		missing++;
1123 #endif
1124 	}
1125 
1126 	/*LINTED*/
1127 	/*
1128 	 * Mutex primitives don't work as expected.
1129 	 */
1130 	if (cpuid_opteron_erratum(cpu, 6323525) > 0) {
1131 #if defined(OPTERON_WORKAROUND_6323525)
1132 		/*
1133 		 * This problem only occurs with 2 or more cores. If bit in
1134 		 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1135 		 * is to patch the semaphone routines with the lfence
1136 		 * instruction to provide necessary load memory barrier with
1137 		 * possible subsequent read-modify-write ops.
1138 		 *
1139 		 * It is too early in boot to call the patch routine so
1140 		 * set erratum variable to be done in startup_end().
1141 		 */
1142 		if (opteron_workaround_6323525) {
1143 			opteron_workaround_6323525++;
1144 #if defined(__xpv)
1145 		} else if (x86_feature & X86_SSE2) {
1146 			if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1147 				/*
1148 				 * XXPV	Use dom0_msr here when extended
1149 				 *	operations are supported?
1150 				 */
1151 				if (xpv_nr_phys_cpus() > 1)
1152 					opteron_workaround_6323525++;
1153 			} else {
1154 				/*
1155 				 * We have no way to tell how many physical
1156 				 * cpus there are, or even if this processor
1157 				 * has the problem, so enable the workaround
1158 				 * unconditionally (at some performance cost).
1159 				 */
1160 				opteron_workaround_6323525++;
1161 			}
1162 #else	/* __xpv */
1163 		} else if ((x86_feature & X86_SSE2) && ((opteron_get_nnodes() *
1164 		    cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1165 			if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1166 				opteron_workaround_6323525++;
1167 #endif	/* __xpv */
1168 		}
1169 #else
1170 		workaround_warning(cpu, 6323525);
1171 		missing++;
1172 #endif
1173 	}
1174 
1175 	missing += do_erratum_298(cpu);
1176 
1177 #ifdef __xpv
1178 	return (0);
1179 #else
1180 	return (missing);
1181 #endif
1182 }
1183 
1184 void
1185 workaround_errata_end()
1186 {
1187 #if defined(OPTERON_ERRATUM_88)
1188 	if (opteron_erratum_88)
1189 		workaround_applied(88);
1190 #endif
1191 #if defined(OPTERON_ERRATUM_91)
1192 	if (opteron_erratum_91)
1193 		workaround_applied(91);
1194 #endif
1195 #if defined(OPTERON_ERRATUM_93)
1196 	if (opteron_erratum_93)
1197 		workaround_applied(93);
1198 #endif
1199 #if defined(OPTERON_ERRATUM_95)
1200 	if (opteron_erratum_95)
1201 		workaround_applied(95);
1202 #endif
1203 #if defined(OPTERON_ERRATUM_100)
1204 	if (opteron_erratum_100)
1205 		workaround_applied(100);
1206 #endif
1207 #if defined(OPTERON_ERRATUM_108)
1208 	if (opteron_erratum_108)
1209 		workaround_applied(108);
1210 #endif
1211 #if defined(OPTERON_ERRATUM_109)
1212 	if (opteron_erratum_109) {
1213 		cmn_err(CE_WARN,
1214 		    "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1215 		    " processor\nerratum 109 was not detected; updating your"
1216 		    " system's BIOS to a version\ncontaining this"
1217 		    " microcode patch is HIGHLY recommended or erroneous"
1218 		    " system\noperation may occur.\n");
1219 	}
1220 #endif
1221 #if defined(OPTERON_ERRATUM_121)
1222 	if (opteron_erratum_121)
1223 		workaround_applied(121);
1224 #endif
1225 #if defined(OPTERON_ERRATUM_122)
1226 	if (opteron_erratum_122)
1227 		workaround_applied(122);
1228 #endif
1229 #if defined(OPTERON_ERRATUM_123)
1230 	if (opteron_erratum_123) {
1231 		cmn_err(CE_WARN,
1232 		    "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1233 		    " processor\nerratum 123 was not detected; updating your"
1234 		    " system's BIOS to a version\ncontaining this"
1235 		    " microcode patch is HIGHLY recommended or erroneous"
1236 		    " system\noperation may occur.\n");
1237 	}
1238 #endif
1239 #if defined(OPTERON_ERRATUM_131)
1240 	if (opteron_erratum_131) {
1241 		cmn_err(CE_WARN,
1242 		    "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1243 		    " processor\nerratum 131 was not detected; updating your"
1244 		    " system's BIOS to a version\ncontaining this"
1245 		    " microcode patch is HIGHLY recommended or erroneous"
1246 		    " system\noperation may occur.\n");
1247 	}
1248 #endif
1249 #if defined(OPTERON_WORKAROUND_6336786)
1250 	if (opteron_workaround_6336786)
1251 		workaround_applied(6336786);
1252 #endif
1253 #if defined(OPTERON_WORKAROUND_6323525)
1254 	if (opteron_workaround_6323525)
1255 		workaround_applied(6323525);
1256 #endif
1257 #if defined(OPTERON_ERRATUM_298)
1258 	if (opteron_erratum_298) {
1259 		cmn_err(CE_WARN,
1260 		    "BIOS microcode patch for AMD 64/Opteron(tm)"
1261 		    " processor\nerratum 298 was not detected; updating your"
1262 		    " system's BIOS to a version\ncontaining this"
1263 		    " microcode patch is HIGHLY recommended or erroneous"
1264 		    " system\noperation may occur.\n");
1265 	}
1266 #endif
1267 }
1268 
1269 /*
1270  * The procset_slave and procset_master are used to synchronize
1271  * between the control CPU and the target CPU when starting CPUs.
1272  */
1273 static cpuset_t procset_slave, procset_master;
1274 
1275 static void
1276 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1277 {
1278 	cpuset_t tempset;
1279 
1280 	for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1281 	    tempset = *(volatile cpuset_t *)sp) {
1282 		SMT_PAUSE();
1283 	}
1284 	CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1285 }
1286 
1287 static void
1288 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1289 {
1290 	cpuset_t tempset;
1291 
1292 	CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1293 	for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1294 	    tempset = *(volatile cpuset_t *)sp) {
1295 		SMT_PAUSE();
1296 	}
1297 }
1298 
1299 int
1300 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1301 {
1302 	_NOTE(ARGUNUSED(boot));
1303 
1304 	void *ctx;
1305 	int delays;
1306 	int error = 0;
1307 	cpuset_t tempset;
1308 	processorid_t cpuid;
1309 #ifndef __xpv
1310 	extern void cpupm_init(cpu_t *);
1311 #endif
1312 
1313 	ASSERT(cp != NULL);
1314 	cpuid = cp->cpu_id;
1315 	ctx = mach_cpucontext_alloc(cp);
1316 	if (ctx == NULL) {
1317 		cmn_err(CE_WARN,
1318 		    "cpu%d: failed to allocate context", cp->cpu_id);
1319 		return (EAGAIN);
1320 	}
1321 	error = mach_cpu_start(cp, ctx);
1322 	if (error != 0) {
1323 		cmn_err(CE_WARN,
1324 		    "cpu%d: failed to start, error %d", cp->cpu_id, error);
1325 		mach_cpucontext_free(cp, ctx, error);
1326 		return (error);
1327 	}
1328 
1329 	for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1330 	    delays++) {
1331 		if (delays == 500) {
1332 			/*
1333 			 * After five seconds, things are probably looking
1334 			 * a bit bleak - explain the hang.
1335 			 */
1336 			cmn_err(CE_NOTE, "cpu%d: started, "
1337 			    "but not running in the kernel yet", cpuid);
1338 		} else if (delays > 2000) {
1339 			/*
1340 			 * We waited at least 20 seconds, bail ..
1341 			 */
1342 			error = ETIMEDOUT;
1343 			cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1344 			mach_cpucontext_free(cp, ctx, error);
1345 			return (error);
1346 		}
1347 
1348 		/*
1349 		 * wait at least 10ms, then check again..
1350 		 */
1351 		delay(USEC_TO_TICK_ROUNDUP(10000));
1352 		tempset = *((volatile cpuset_t *)&procset_slave);
1353 	}
1354 	CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1355 
1356 	mach_cpucontext_free(cp, ctx, 0);
1357 
1358 #ifndef __xpv
1359 	if (tsc_gethrtime_enable)
1360 		tsc_sync_master(cpuid);
1361 #endif
1362 
1363 	if (dtrace_cpu_init != NULL) {
1364 		(*dtrace_cpu_init)(cpuid);
1365 	}
1366 
1367 	/*
1368 	 * During CPU DR operations, the cpu_lock is held by current
1369 	 * (the control) thread. We can't release the cpu_lock here
1370 	 * because that will break the CPU DR logic.
1371 	 * On the other hand, CPUPM and processor group initialization
1372 	 * routines need to access the cpu_lock. So we invoke those
1373 	 * routines here on behalf of mp_startup_common().
1374 	 *
1375 	 * CPUPM and processor group initialization routines depend
1376 	 * on the cpuid probing results. Wait for mp_startup_common()
1377 	 * to signal that cpuid probing is done.
1378 	 */
1379 	mp_startup_wait(&procset_slave, cpuid);
1380 #ifndef __xpv
1381 	cpupm_init(cp);
1382 #endif
1383 	(void) pg_cpu_init(cp, B_FALSE);
1384 	cpu_set_state(cp);
1385 	mp_startup_signal(&procset_master, cpuid);
1386 
1387 	return (0);
1388 }
1389 
1390 /*
1391  * Start a single cpu, assuming that the kernel context is available
1392  * to successfully start another cpu.
1393  *
1394  * (For example, real mode code is mapped into the right place
1395  * in memory and is ready to be run.)
1396  */
1397 int
1398 start_cpu(processorid_t who)
1399 {
1400 	cpu_t *cp;
1401 	int error = 0;
1402 	cpuset_t tempset;
1403 
1404 	ASSERT(who != 0);
1405 
1406 	/*
1407 	 * Check if there's at least a Mbyte of kmem available
1408 	 * before attempting to start the cpu.
1409 	 */
1410 	if (kmem_avail() < 1024 * 1024) {
1411 		/*
1412 		 * Kick off a reap in case that helps us with
1413 		 * later attempts ..
1414 		 */
1415 		kmem_reap();
1416 		return (ENOMEM);
1417 	}
1418 
1419 	/*
1420 	 * First configure cpu.
1421 	 */
1422 	cp = mp_cpu_configure_common(who, B_TRUE);
1423 	ASSERT(cp != NULL);
1424 
1425 	/*
1426 	 * Then start cpu.
1427 	 */
1428 	error = mp_start_cpu_common(cp, B_TRUE);
1429 	if (error != 0) {
1430 		mp_cpu_unconfigure_common(cp, error);
1431 		return (error);
1432 	}
1433 
1434 	mutex_exit(&cpu_lock);
1435 	tempset = cpu_ready_set;
1436 	while (!CPU_IN_SET(tempset, who)) {
1437 		drv_usecwait(1);
1438 		tempset = *((volatile cpuset_t *)&cpu_ready_set);
1439 	}
1440 	mutex_enter(&cpu_lock);
1441 
1442 	return (0);
1443 }
1444 
1445 void
1446 start_other_cpus(int cprboot)
1447 {
1448 	_NOTE(ARGUNUSED(cprboot));
1449 
1450 	uint_t who;
1451 	uint_t bootcpuid = 0;
1452 
1453 	/*
1454 	 * Initialize our own cpu_info.
1455 	 */
1456 	init_cpu_info(CPU);
1457 
1458 	cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1459 	cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1460 
1461 	/*
1462 	 * Initialize our syscall handlers
1463 	 */
1464 	init_cpu_syscall(CPU);
1465 
1466 	/*
1467 	 * Take the boot cpu out of the mp_cpus set because we know
1468 	 * it's already running.  Add it to the cpu_ready_set for
1469 	 * precisely the same reason.
1470 	 */
1471 	CPUSET_DEL(mp_cpus, bootcpuid);
1472 	CPUSET_ADD(cpu_ready_set, bootcpuid);
1473 
1474 	/*
1475 	 * skip the rest of this if
1476 	 * . only 1 cpu dectected and system isn't hotplug-capable
1477 	 * . not using MP
1478 	 */
1479 	if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1480 	    use_mp == 0) {
1481 		if (use_mp == 0)
1482 			cmn_err(CE_CONT, "?***** Not in MP mode\n");
1483 		goto done;
1484 	}
1485 
1486 	/*
1487 	 * perform such initialization as is needed
1488 	 * to be able to take CPUs on- and off-line.
1489 	 */
1490 	cpu_pause_init();
1491 
1492 	xc_init_cpu(CPU);		/* initialize processor crosscalls */
1493 
1494 	if (mach_cpucontext_init() != 0)
1495 		goto done;
1496 
1497 	flushes_require_xcalls = 1;
1498 
1499 	/*
1500 	 * We lock our affinity to the master CPU to ensure that all slave CPUs
1501 	 * do their TSC syncs with the same CPU.
1502 	 */
1503 	affinity_set(CPU_CURRENT);
1504 
1505 	for (who = 0; who < NCPU; who++) {
1506 		if (!CPU_IN_SET(mp_cpus, who))
1507 			continue;
1508 		ASSERT(who != bootcpuid);
1509 
1510 		mutex_enter(&cpu_lock);
1511 		if (start_cpu(who) != 0)
1512 			CPUSET_DEL(mp_cpus, who);
1513 		cpu_state_change_notify(who, CPU_SETUP);
1514 		mutex_exit(&cpu_lock);
1515 	}
1516 
1517 	/* Free the space allocated to hold the microcode file */
1518 	ucode_cleanup();
1519 
1520 	affinity_clear();
1521 
1522 	mach_cpucontext_fini();
1523 
1524 done:
1525 	if (get_hwenv() == HW_NATIVE)
1526 		workaround_errata_end();
1527 	cmi_post_mpstartup();
1528 
1529 	if (use_mp && ncpus != boot_max_ncpus) {
1530 		cmn_err(CE_NOTE,
1531 		    "System detected %d cpus, but "
1532 		    "only %d cpu(s) were enabled during boot.",
1533 		    boot_max_ncpus, ncpus);
1534 		cmn_err(CE_NOTE,
1535 		    "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1536 		    "See eeprom(1M).");
1537 	}
1538 }
1539 
1540 int
1541 mp_cpu_configure(int cpuid)
1542 {
1543 	cpu_t *cp;
1544 
1545 	if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1546 		return (ENOTSUP);
1547 	}
1548 
1549 	cp = cpu_get(cpuid);
1550 	if (cp != NULL) {
1551 		return (EALREADY);
1552 	}
1553 
1554 	/*
1555 	 * Check if there's at least a Mbyte of kmem available
1556 	 * before attempting to start the cpu.
1557 	 */
1558 	if (kmem_avail() < 1024 * 1024) {
1559 		/*
1560 		 * Kick off a reap in case that helps us with
1561 		 * later attempts ..
1562 		 */
1563 		kmem_reap();
1564 		return (ENOMEM);
1565 	}
1566 
1567 	cp = mp_cpu_configure_common(cpuid, B_FALSE);
1568 	ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1569 
1570 	return (cp != NULL ? 0 : EAGAIN);
1571 }
1572 
1573 int
1574 mp_cpu_unconfigure(int cpuid)
1575 {
1576 	cpu_t *cp;
1577 
1578 	if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1579 		return (ENOTSUP);
1580 	} else if (cpuid < 0 || cpuid >= max_ncpus) {
1581 		return (EINVAL);
1582 	}
1583 
1584 	cp = cpu_get(cpuid);
1585 	if (cp == NULL) {
1586 		return (ENODEV);
1587 	}
1588 	mp_cpu_unconfigure_common(cp, 0);
1589 
1590 	return (0);
1591 }
1592 
1593 /*
1594  * Startup function for 'other' CPUs (besides boot cpu).
1595  * Called from real_mode_start.
1596  *
1597  * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1598  * mp_startup_common should not call routines (e.g. kmem_free) that could call
1599  * hat_unload which requires CPU_READY to be set.
1600  */
1601 static void
1602 mp_startup_common(boolean_t boot)
1603 {
1604 	cpu_t *cp = CPU;
1605 	uint_t new_x86_feature;
1606 	const char *fmt = "?cpu%d: %b\n";
1607 	extern void cpu_event_init_cpu(cpu_t *);
1608 
1609 	/*
1610 	 * We need to get TSC on this proc synced (i.e., any delta
1611 	 * from cpu0 accounted for) as soon as we can, because many
1612 	 * many things use gethrtime/pc_gethrestime, including
1613 	 * interrupts, cmn_err, etc.
1614 	 */
1615 
1616 	/* Let the control CPU continue into tsc_sync_master() */
1617 	mp_startup_signal(&procset_slave, cp->cpu_id);
1618 
1619 #ifndef __xpv
1620 	if (tsc_gethrtime_enable)
1621 		tsc_sync_slave();
1622 #endif
1623 
1624 	/*
1625 	 * Once this was done from assembly, but it's safer here; if
1626 	 * it blocks, we need to be able to swtch() to and from, and
1627 	 * since we get here by calling t_pc, we need to do that call
1628 	 * before swtch() overwrites it.
1629 	 */
1630 	(void) (*ap_mlsetup)();
1631 
1632 	new_x86_feature = cpuid_pass1(cp);
1633 
1634 #ifndef __xpv
1635 	/*
1636 	 * Program this cpu's PAT
1637 	 */
1638 	if (x86_feature & X86_PAT)
1639 		pat_sync();
1640 #endif
1641 
1642 	/*
1643 	 * Set up TSC_AUX to contain the cpuid for this processor
1644 	 * for the rdtscp instruction.
1645 	 */
1646 	if (x86_feature & X86_TSCP)
1647 		(void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1648 
1649 	/*
1650 	 * Initialize this CPU's syscall handlers
1651 	 */
1652 	init_cpu_syscall(cp);
1653 
1654 	/*
1655 	 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1656 	 * highest level at which a routine is permitted to block on
1657 	 * an adaptive mutex (allows for cpu poke interrupt in case
1658 	 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1659 	 * device interrupts that may end up in the hat layer issuing cross
1660 	 * calls before CPU_READY is set.
1661 	 */
1662 	splx(ipltospl(LOCK_LEVEL));
1663 	sti();
1664 
1665 	/*
1666 	 * Do a sanity check to make sure this new CPU is a sane thing
1667 	 * to add to the collection of processors running this system.
1668 	 *
1669 	 * XXX	Clearly this needs to get more sophisticated, if x86
1670 	 * systems start to get built out of heterogenous CPUs; as is
1671 	 * likely to happen once the number of processors in a configuration
1672 	 * gets large enough.
1673 	 */
1674 	if ((x86_feature & new_x86_feature) != x86_feature) {
1675 		cmn_err(CE_CONT, fmt, cp->cpu_id, new_x86_feature,
1676 		    FMT_X86_FEATURE);
1677 		cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1678 	}
1679 
1680 	/*
1681 	 * We do not support cpus with mixed monitor/mwait support if the
1682 	 * boot cpu supports monitor/mwait.
1683 	 */
1684 	if ((x86_feature & ~new_x86_feature) & X86_MWAIT)
1685 		panic("unsupported mixed cpu monitor/mwait support detected");
1686 
1687 	/*
1688 	 * We could be more sophisticated here, and just mark the CPU
1689 	 * as "faulted" but at this point we'll opt for the easier
1690 	 * answer of dying horribly.  Provided the boot cpu is ok,
1691 	 * the system can be recovered by booting with use_mp set to zero.
1692 	 */
1693 	if (workaround_errata(cp) != 0)
1694 		panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1695 
1696 	/*
1697 	 * We can touch cpu_flags here without acquiring the cpu_lock here
1698 	 * because the cpu_lock is held by the control CPU which is running
1699 	 * mp_start_cpu_common().
1700 	 * Need to clear CPU_QUIESCED flag before calling any function which
1701 	 * may cause thread context switching, such as kmem_alloc() etc.
1702 	 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1703 	 * it's set. So the startup thread may have no chance to switch back
1704 	 * again if it's switched away with CPU_QUIESCED set.
1705 	 */
1706 	cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1707 
1708 	cpuid_pass2(cp);
1709 	cpuid_pass3(cp);
1710 	(void) cpuid_pass4(cp);
1711 
1712 	/*
1713 	 * Correct cpu_idstr and cpu_brandstr on target CPU after
1714 	 * cpuid_pass1() is done.
1715 	 */
1716 	(void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1717 	(void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1718 
1719 	cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1720 
1721 	post_startup_cpu_fixups();
1722 
1723 	cpu_event_init_cpu(cp);
1724 
1725 	/*
1726 	 * Enable preemption here so that contention for any locks acquired
1727 	 * later in mp_startup_common may be preempted if the thread owning
1728 	 * those locks is continuously executing on other CPUs (for example,
1729 	 * this CPU must be preemptible to allow other CPUs to pause it during
1730 	 * their startup phases).  It's safe to enable preemption here because
1731 	 * the CPU state is pretty-much fully constructed.
1732 	 */
1733 	curthread->t_preempt = 0;
1734 
1735 	/* The base spl should still be at LOCK LEVEL here */
1736 	ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1737 	set_base_spl();		/* Restore the spl to its proper value */
1738 
1739 	pghw_physid_create(cp);
1740 	/*
1741 	 * Delegate initialization tasks, which need to access the cpu_lock,
1742 	 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1743 	 * during CPU DR operations.
1744 	 */
1745 	mp_startup_signal(&procset_slave, cp->cpu_id);
1746 	mp_startup_wait(&procset_master, cp->cpu_id);
1747 	pg_cmt_cpu_startup(cp);
1748 
1749 	if (boot) {
1750 		mutex_enter(&cpu_lock);
1751 		cp->cpu_flags &= ~CPU_OFFLINE;
1752 		cpu_enable_intr(cp);
1753 		cpu_add_active(cp);
1754 		mutex_exit(&cpu_lock);
1755 	}
1756 
1757 	/* Enable interrupts */
1758 	(void) spl0();
1759 
1760 	/*
1761 	 * Fill out cpu_ucode_info.  Update microcode if necessary.
1762 	 */
1763 	ucode_check(cp);
1764 
1765 #ifndef __xpv
1766 	{
1767 		/*
1768 		 * Set up the CPU module for this CPU.  This can't be done
1769 		 * before this CPU is made CPU_READY, because we may (in
1770 		 * heterogeneous systems) need to go load another CPU module.
1771 		 * The act of attempting to load a module may trigger a
1772 		 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1773 		 */
1774 		cmi_hdl_t hdl;
1775 
1776 		if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1777 		    cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1778 			if (x86_feature & X86_MCA)
1779 				cmi_mca_init(hdl);
1780 			cp->cpu_m.mcpu_cmi_hdl = hdl;
1781 		}
1782 	}
1783 #endif /* __xpv */
1784 
1785 	if (boothowto & RB_DEBUG)
1786 		kdi_cpu_init();
1787 
1788 	/*
1789 	 * Setting the bit in cpu_ready_set must be the last operation in
1790 	 * processor initialization; the boot CPU will continue to boot once
1791 	 * it sees this bit set for all active CPUs.
1792 	 */
1793 	CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1794 
1795 	(void) mach_cpu_create_device_node(cp, NULL);
1796 
1797 	cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1798 	cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1799 	cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1800 	    cp->cpu_id);
1801 
1802 	/*
1803 	 * Now we are done with the startup thread, so free it up.
1804 	 */
1805 	thread_exit();
1806 	panic("mp_startup: cannot return");
1807 	/*NOTREACHED*/
1808 }
1809 
1810 /*
1811  * Startup function for 'other' CPUs at boot time (besides boot cpu).
1812  */
1813 static void
1814 mp_startup_boot(void)
1815 {
1816 	mp_startup_common(B_TRUE);
1817 }
1818 
1819 /*
1820  * Startup function for hotplug CPUs at runtime.
1821  */
1822 void
1823 mp_startup_hotplug(void)
1824 {
1825 	mp_startup_common(B_FALSE);
1826 }
1827 
1828 /*
1829  * Start CPU on user request.
1830  */
1831 /* ARGSUSED */
1832 int
1833 mp_cpu_start(struct cpu *cp)
1834 {
1835 	ASSERT(MUTEX_HELD(&cpu_lock));
1836 	return (0);
1837 }
1838 
1839 /*
1840  * Stop CPU on user request.
1841  */
1842 int
1843 mp_cpu_stop(struct cpu *cp)
1844 {
1845 	extern int cbe_psm_timer_mode;
1846 	ASSERT(MUTEX_HELD(&cpu_lock));
1847 
1848 #ifdef __xpv
1849 	/*
1850 	 * We can't offline vcpu0.
1851 	 */
1852 	if (cp->cpu_id == 0)
1853 		return (EBUSY);
1854 #endif
1855 
1856 	/*
1857 	 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1858 	 * can't stop it.  (This is true only for machines with no TSC.)
1859 	 */
1860 
1861 	if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
1862 		return (EBUSY);
1863 
1864 	return (0);
1865 }
1866 
1867 /*
1868  * Take the specified CPU out of participation in interrupts.
1869  */
1870 int
1871 cpu_disable_intr(struct cpu *cp)
1872 {
1873 	if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
1874 		return (EBUSY);
1875 
1876 	cp->cpu_flags &= ~CPU_ENABLE;
1877 	return (0);
1878 }
1879 
1880 /*
1881  * Allow the specified CPU to participate in interrupts.
1882  */
1883 void
1884 cpu_enable_intr(struct cpu *cp)
1885 {
1886 	ASSERT(MUTEX_HELD(&cpu_lock));
1887 	cp->cpu_flags |= CPU_ENABLE;
1888 	psm_enable_intr(cp->cpu_id);
1889 }
1890 
1891 void
1892 mp_cpu_faulted_enter(struct cpu *cp)
1893 {
1894 #ifdef __xpv
1895 	_NOTE(ARGUNUSED(cp));
1896 #else
1897 	cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1898 
1899 	if (hdl != NULL) {
1900 		cmi_hdl_hold(hdl);
1901 	} else {
1902 		hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1903 		    cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1904 	}
1905 	if (hdl != NULL) {
1906 		cmi_faulted_enter(hdl);
1907 		cmi_hdl_rele(hdl);
1908 	}
1909 #endif
1910 }
1911 
1912 void
1913 mp_cpu_faulted_exit(struct cpu *cp)
1914 {
1915 #ifdef __xpv
1916 	_NOTE(ARGUNUSED(cp));
1917 #else
1918 	cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1919 
1920 	if (hdl != NULL) {
1921 		cmi_hdl_hold(hdl);
1922 	} else {
1923 		hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1924 		    cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1925 	}
1926 	if (hdl != NULL) {
1927 		cmi_faulted_exit(hdl);
1928 		cmi_hdl_rele(hdl);
1929 	}
1930 #endif
1931 }
1932 
1933 /*
1934  * The following two routines are used as context operators on threads belonging
1935  * to processes with a private LDT (see sysi86).  Due to the rarity of such
1936  * processes, these routines are currently written for best code readability and
1937  * organization rather than speed.  We could avoid checking x86_feature at every
1938  * context switch by installing different context ops, depending on the
1939  * x86_feature flags, at LDT creation time -- one for each combination of fast
1940  * syscall feature flags.
1941  */
1942 
1943 /*ARGSUSED*/
1944 void
1945 cpu_fast_syscall_disable(void *arg)
1946 {
1947 	if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP))
1948 		cpu_sep_disable();
1949 	if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC))
1950 		cpu_asysc_disable();
1951 }
1952 
1953 /*ARGSUSED*/
1954 void
1955 cpu_fast_syscall_enable(void *arg)
1956 {
1957 	if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP))
1958 		cpu_sep_enable();
1959 	if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC))
1960 		cpu_asysc_enable();
1961 }
1962 
1963 static void
1964 cpu_sep_enable(void)
1965 {
1966 	ASSERT(x86_feature & X86_SEP);
1967 	ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
1968 
1969 	wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
1970 }
1971 
1972 static void
1973 cpu_sep_disable(void)
1974 {
1975 	ASSERT(x86_feature & X86_SEP);
1976 	ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
1977 
1978 	/*
1979 	 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
1980 	 * the sysenter or sysexit instruction to trigger a #gp fault.
1981 	 */
1982 	wrmsr(MSR_INTC_SEP_CS, 0);
1983 }
1984 
1985 static void
1986 cpu_asysc_enable(void)
1987 {
1988 	ASSERT(x86_feature & X86_ASYSC);
1989 	ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
1990 
1991 	wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
1992 	    (uint64_t)(uintptr_t)AMD_EFER_SCE);
1993 }
1994 
1995 static void
1996 cpu_asysc_disable(void)
1997 {
1998 	ASSERT(x86_feature & X86_ASYSC);
1999 	ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2000 
2001 	/*
2002 	 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2003 	 * executing syscall or sysret with this bit off will incur a #ud trap.
2004 	 */
2005 	wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2006 	    ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2007 }
2008