1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/thread.h> 31 #include <sys/cpuvar.h> 32 #include <sys/t_lock.h> 33 #include <sys/param.h> 34 #include <sys/proc.h> 35 #include <sys/disp.h> 36 #include <sys/class.h> 37 #include <sys/cmn_err.h> 38 #include <sys/debug.h> 39 #include <sys/asm_linkage.h> 40 #include <sys/x_call.h> 41 #include <sys/systm.h> 42 #include <sys/var.h> 43 #include <sys/vtrace.h> 44 #include <vm/hat.h> 45 #include <vm/as.h> 46 #include <vm/seg_kmem.h> 47 #include <vm/seg_kp.h> 48 #include <sys/segments.h> 49 #include <sys/kmem.h> 50 #include <sys/stack.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/x86_archext.h> 53 #include <sys/machsystm.h> 54 #include <sys/traptrace.h> 55 #include <sys/clock.h> 56 #include <sys/cpc_impl.h> 57 #include <sys/pg.h> 58 #include <sys/cmt.h> 59 #include <sys/dtrace.h> 60 #include <sys/archsystm.h> 61 #include <sys/fp.h> 62 #include <sys/reboot.h> 63 #include <sys/kdi_machimpl.h> 64 #include <vm/hat_i86.h> 65 #include <sys/memnode.h> 66 #include <sys/pci_cfgspace.h> 67 #include <sys/mach_mmu.h> 68 #include <sys/sysmacros.h> 69 #if defined(__xpv) 70 #include <sys/hypervisor.h> 71 #endif 72 #include <sys/cpu_module.h> 73 74 struct cpu cpus[1]; /* CPU data */ 75 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 76 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 77 78 /* 79 * Useful for disabling MP bring-up on a MP capable system. 80 */ 81 int use_mp = 1; 82 83 /* 84 * to be set by a PSM to indicate what cpus 85 * are sitting around on the system. 86 */ 87 cpuset_t mp_cpus; 88 89 /* 90 * This variable is used by the hat layer to decide whether or not 91 * critical sections are needed to prevent race conditions. For sun4m, 92 * this variable is set once enough MP initialization has been done in 93 * order to allow cross calls. 94 */ 95 int flushes_require_xcalls; 96 cpuset_t cpu_ready_set = 1; 97 98 static void mp_startup(void); 99 100 static void cpu_sep_enable(void); 101 static void cpu_sep_disable(void); 102 static void cpu_asysc_enable(void); 103 static void cpu_asysc_disable(void); 104 105 /* 106 * Init CPU info - get CPU type info for processor_info system call. 107 */ 108 void 109 init_cpu_info(struct cpu *cp) 110 { 111 processor_info_t *pi = &cp->cpu_type_info; 112 char buf[CPU_IDSTRLEN]; 113 114 /* 115 * Get clock-frequency property for the CPU. 116 */ 117 pi->pi_clock = cpu_freq; 118 119 /* 120 * Current frequency in Hz. 121 */ 122 cp->cpu_curr_clock = cpu_freq_hz; 123 124 /* 125 * Supported frequencies. 126 */ 127 cpu_set_supp_freqs(cp, NULL); 128 129 (void) strcpy(pi->pi_processor_type, "i386"); 130 if (fpu_exists) 131 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 132 133 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 134 135 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 136 (void) strcpy(cp->cpu_idstr, buf); 137 138 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 139 140 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 141 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 142 (void) strcpy(cp->cpu_brandstr, buf); 143 144 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 145 } 146 147 /* 148 * Configure syscall support on this CPU. 149 */ 150 /*ARGSUSED*/ 151 void 152 init_cpu_syscall(struct cpu *cp) 153 { 154 kpreempt_disable(); 155 156 #if defined(__amd64) 157 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 158 159 #if !defined(__lint) 160 /* 161 * The syscall instruction imposes a certain ordering on 162 * segment selectors, so we double-check that ordering 163 * here. 164 */ 165 ASSERT(KDS_SEL == KCS_SEL + 8); 166 ASSERT(UDS_SEL == U32CS_SEL + 8); 167 ASSERT(UCS_SEL == U32CS_SEL + 16); 168 #endif 169 /* 170 * Turn syscall/sysret extensions on. 171 */ 172 cpu_asysc_enable(); 173 174 /* 175 * Program the magic registers .. 176 */ 177 wrmsr(MSR_AMD_STAR, 178 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 179 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 180 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 181 182 /* 183 * This list of flags is masked off the incoming 184 * %rfl when we enter the kernel. 185 */ 186 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 187 } 188 #endif 189 190 /* 191 * On 32-bit kernels, we use sysenter/sysexit because it's too 192 * hard to use syscall/sysret, and it is more portable anyway. 193 * 194 * On 64-bit kernels on Nocona machines, the 32-bit syscall 195 * variant isn't available to 32-bit applications, but sysenter is. 196 */ 197 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 198 199 #if !defined(__lint) 200 /* 201 * The sysenter instruction imposes a certain ordering on 202 * segment selectors, so we double-check that ordering 203 * here. See "sysenter" in Intel document 245471-012, "IA-32 204 * Intel Architecture Software Developer's Manual Volume 2: 205 * Instruction Set Reference" 206 */ 207 ASSERT(KDS_SEL == KCS_SEL + 8); 208 209 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 210 ASSERT32(UDS_SEL == UCS_SEL + 8); 211 212 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 213 ASSERT64(UDS_SEL == U32CS_SEL + 8); 214 #endif 215 216 cpu_sep_enable(); 217 218 /* 219 * resume() sets this value to the base of the threads stack 220 * via a context handler. 221 */ 222 wrmsr(MSR_INTC_SEP_ESP, 0); 223 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 224 } 225 226 kpreempt_enable(); 227 } 228 229 /* 230 * Multiprocessor initialization. 231 * 232 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 233 * startup and idle threads for the specified CPU. 234 */ 235 struct cpu * 236 mp_startup_init(int cpun) 237 { 238 struct cpu *cp; 239 kthread_id_t tp; 240 caddr_t sp; 241 proc_t *procp; 242 #if !defined(__xpv) 243 extern int idle_cpu_prefer_mwait; 244 #endif 245 extern void idle(); 246 247 #ifdef TRAPTRACE 248 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 249 #endif 250 251 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 252 253 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 254 #if !defined(__xpv) 255 if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) 256 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); 257 #endif 258 259 procp = curthread->t_procp; 260 261 mutex_enter(&cpu_lock); 262 /* 263 * Initialize the dispatcher first. 264 */ 265 disp_cpu_init(cp); 266 mutex_exit(&cpu_lock); 267 268 cpu_vm_data_init(cp); 269 270 /* 271 * Allocate and initialize the startup thread for this CPU. 272 * Interrupt and process switch stacks get allocated later 273 * when the CPU starts running. 274 */ 275 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 276 TS_STOPPED, maxclsyspri); 277 278 /* 279 * Set state to TS_ONPROC since this thread will start running 280 * as soon as the CPU comes online. 281 * 282 * All the other fields of the thread structure are setup by 283 * thread_create(). 284 */ 285 THREAD_ONPROC(tp, cp); 286 tp->t_preempt = 1; 287 tp->t_bound_cpu = cp; 288 tp->t_affinitycnt = 1; 289 tp->t_cpu = cp; 290 tp->t_disp_queue = cp->cpu_disp; 291 292 /* 293 * Setup thread to start in mp_startup. 294 */ 295 sp = tp->t_stk; 296 tp->t_pc = (uintptr_t)mp_startup; 297 tp->t_sp = (uintptr_t)(sp - MINFRAME); 298 #if defined(__amd64) 299 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 300 #endif 301 302 cp->cpu_id = cpun; 303 cp->cpu_self = cp; 304 cp->cpu_thread = tp; 305 cp->cpu_lwp = NULL; 306 cp->cpu_dispthread = tp; 307 cp->cpu_dispatch_pri = DISP_PRIO(tp); 308 309 /* 310 * cpu_base_spl must be set explicitly here to prevent any blocking 311 * operations in mp_startup from causing the spl of the cpu to drop 312 * to 0 (allowing device interrupts before we're ready) in resume(). 313 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 314 * As an extra bit of security on DEBUG kernels, this is enforced with 315 * an assertion in mp_startup() -- before cpu_base_spl is set to its 316 * proper value. 317 */ 318 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 319 320 /* 321 * Now, initialize per-CPU idle thread for this CPU. 322 */ 323 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 324 325 cp->cpu_idle_thread = tp; 326 327 tp->t_preempt = 1; 328 tp->t_bound_cpu = cp; 329 tp->t_affinitycnt = 1; 330 tp->t_cpu = cp; 331 tp->t_disp_queue = cp->cpu_disp; 332 333 /* 334 * Bootstrap the CPU's PG data 335 */ 336 pg_cpu_bootstrap(cp); 337 338 /* 339 * Perform CPC initialization on the new CPU. 340 */ 341 kcpc_hw_init(cp); 342 343 /* 344 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 345 * for each CPU. 346 */ 347 setup_vaddr_for_ppcopy(cp); 348 349 /* 350 * Allocate page for new GDT and initialize from current GDT. 351 */ 352 #if !defined(__lint) 353 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 354 #endif 355 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 356 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 357 358 #if defined(__i386) 359 /* 360 * setup kernel %gs. 361 */ 362 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 363 SEL_KPL, 0, 1); 364 #endif 365 366 /* 367 * If we have more than one node, each cpu gets a copy of IDT 368 * local to its node. If this is a Pentium box, we use cpu 0's 369 * IDT. cpu 0's IDT has been made read-only to workaround the 370 * cmpxchgl register bug 371 */ 372 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 373 #if !defined(__lint) 374 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 375 #endif 376 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 377 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 378 } else { 379 cp->cpu_idt = CPU->cpu_idt; 380 } 381 382 /* 383 * Get interrupt priority data from cpu 0. 384 */ 385 cp->cpu_pri_data = CPU->cpu_pri_data; 386 387 /* 388 * alloc space for cpuid info 389 */ 390 cpuid_alloc_space(cp); 391 392 #if !defined(__xpv) 393 /* 394 * alloc space for ucode_info 395 */ 396 ucode_alloc_space(cp); 397 #endif 398 399 hat_cpu_online(cp); 400 401 #ifdef TRAPTRACE 402 /* 403 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 404 */ 405 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 406 ttc->ttc_next = ttc->ttc_first; 407 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 408 #endif 409 /* 410 * Record that we have another CPU. 411 */ 412 mutex_enter(&cpu_lock); 413 /* 414 * Initialize the interrupt threads for this CPU 415 */ 416 cpu_intr_alloc(cp, NINTR_THREADS); 417 /* 418 * Add CPU to list of available CPUs. It'll be on the active list 419 * after mp_startup(). 420 */ 421 cpu_add_unit(cp); 422 mutex_exit(&cpu_lock); 423 424 return (cp); 425 } 426 427 /* 428 * Undo what was done in mp_startup_init 429 */ 430 static void 431 mp_startup_fini(struct cpu *cp, int error) 432 { 433 mutex_enter(&cpu_lock); 434 435 /* 436 * Remove the CPU from the list of available CPUs. 437 */ 438 cpu_del_unit(cp->cpu_id); 439 440 if (error == ETIMEDOUT) { 441 /* 442 * The cpu was started, but never *seemed* to run any 443 * code in the kernel; it's probably off spinning in its 444 * own private world, though with potential references to 445 * our kmem-allocated IDTs and GDTs (for example). 446 * 447 * Worse still, it may actually wake up some time later, 448 * so rather than guess what it might or might not do, we 449 * leave the fundamental data structures intact. 450 */ 451 cp->cpu_flags = 0; 452 mutex_exit(&cpu_lock); 453 return; 454 } 455 456 /* 457 * At this point, the only threads bound to this CPU should 458 * special per-cpu threads: it's idle thread, it's pause threads, 459 * and it's interrupt threads. Clean these up. 460 */ 461 cpu_destroy_bound_threads(cp); 462 cp->cpu_idle_thread = NULL; 463 464 /* 465 * Free the interrupt stack. 466 */ 467 segkp_release(segkp, 468 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 469 470 mutex_exit(&cpu_lock); 471 472 #ifdef TRAPTRACE 473 /* 474 * Discard the trap trace buffer 475 */ 476 { 477 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 478 479 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 480 ttc->ttc_first = NULL; 481 } 482 #endif 483 484 hat_cpu_offline(cp); 485 486 cpuid_free_space(cp); 487 488 #if !defined(__xpv) 489 ucode_free_space(cp); 490 #endif 491 492 if (cp->cpu_idt != CPU->cpu_idt) 493 kmem_free(cp->cpu_idt, PAGESIZE); 494 cp->cpu_idt = NULL; 495 496 kmem_free(cp->cpu_gdt, PAGESIZE); 497 cp->cpu_gdt = NULL; 498 499 teardown_vaddr_for_ppcopy(cp); 500 501 kcpc_hw_fini(cp); 502 503 cp->cpu_dispthread = NULL; 504 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 505 506 cpu_vm_data_destroy(cp); 507 508 mutex_enter(&cpu_lock); 509 disp_cpu_fini(cp); 510 mutex_exit(&cpu_lock); 511 512 #if !defined(__xpv) 513 if (cp->cpu_m.mcpu_mwait != NULL) 514 cpuid_mwait_free(cp); 515 #endif 516 kmem_free(cp, sizeof (*cp)); 517 } 518 519 /* 520 * Apply workarounds for known errata, and warn about those that are absent. 521 * 522 * System vendors occasionally create configurations which contain different 523 * revisions of the CPUs that are almost but not exactly the same. At the 524 * time of writing, this meant that their clock rates were the same, their 525 * feature sets were the same, but the required workaround were -not- 526 * necessarily the same. So, this routine is invoked on -every- CPU soon 527 * after starting to make sure that the resulting system contains the most 528 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 529 * system. 530 * 531 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 532 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 533 * to acknowledging their readiness to the master, so this routine will 534 * never be executed by multiple CPUs in parallel, thus making updates to 535 * global data safe. 536 * 537 * These workarounds are based on Rev 3.57 of the Revision Guide for 538 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 539 */ 540 541 #if defined(OPTERON_ERRATUM_88) 542 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 543 #endif 544 545 #if defined(OPTERON_ERRATUM_91) 546 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 547 #endif 548 549 #if defined(OPTERON_ERRATUM_93) 550 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 551 #endif 552 553 #if defined(OPTERON_ERRATUM_95) 554 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 555 #endif 556 557 #if defined(OPTERON_ERRATUM_100) 558 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 559 #endif 560 561 #if defined(OPTERON_ERRATUM_108) 562 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 563 #endif 564 565 #if defined(OPTERON_ERRATUM_109) 566 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 567 #endif 568 569 #if defined(OPTERON_ERRATUM_121) 570 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 571 #endif 572 573 #if defined(OPTERON_ERRATUM_122) 574 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 575 #endif 576 577 #if defined(OPTERON_ERRATUM_123) 578 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 579 #endif 580 581 #if defined(OPTERON_ERRATUM_131) 582 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 583 #endif 584 585 #if defined(OPTERON_WORKAROUND_6336786) 586 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 587 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 588 #endif 589 590 #if defined(OPTERON_WORKAROUND_6323525) 591 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 592 #endif 593 594 static void 595 workaround_warning(cpu_t *cp, uint_t erratum) 596 { 597 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 598 cp->cpu_id, erratum); 599 } 600 601 static void 602 workaround_applied(uint_t erratum) 603 { 604 if (erratum > 1000000) 605 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 606 erratum); 607 else 608 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 609 erratum); 610 } 611 612 static void 613 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 614 { 615 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 616 cp->cpu_id, rw, msr, error); 617 } 618 619 #if defined(__xpv) 620 621 /* 622 * On dom0, we can determine the number of physical cpus on the machine. 623 * This number is important when figuring out what workarounds are 624 * appropriate, so compute it now. 625 */ 626 static uint_t 627 xen_get_nphyscpus(void) 628 { 629 static uint_t nphyscpus = 0; 630 631 ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); 632 633 if (nphyscpus == 0) { 634 xen_sysctl_t op; 635 xen_sysctl_physinfo_t *pi = &op.u.physinfo; 636 637 op.cmd = XEN_SYSCTL_physinfo; 638 op.interface_version = XEN_SYSCTL_INTERFACE_VERSION; 639 if (HYPERVISOR_sysctl(&op) == 0) 640 nphyscpus = pi->threads_per_core * 641 pi->cores_per_socket * pi->sockets_per_node * 642 pi->nr_nodes; 643 } 644 return (nphyscpus); 645 } 646 #endif 647 648 uint_t 649 workaround_errata(struct cpu *cpu) 650 { 651 uint_t missing = 0; 652 653 ASSERT(cpu == CPU); 654 655 /*LINTED*/ 656 if (cpuid_opteron_erratum(cpu, 88) > 0) { 657 /* 658 * SWAPGS May Fail To Read Correct GS Base 659 */ 660 #if defined(OPTERON_ERRATUM_88) 661 /* 662 * The workaround is an mfence in the relevant assembler code 663 */ 664 opteron_erratum_88++; 665 #else 666 workaround_warning(cpu, 88); 667 missing++; 668 #endif 669 } 670 671 if (cpuid_opteron_erratum(cpu, 91) > 0) { 672 /* 673 * Software Prefetches May Report A Page Fault 674 */ 675 #if defined(OPTERON_ERRATUM_91) 676 /* 677 * fix is in trap.c 678 */ 679 opteron_erratum_91++; 680 #else 681 workaround_warning(cpu, 91); 682 missing++; 683 #endif 684 } 685 686 if (cpuid_opteron_erratum(cpu, 93) > 0) { 687 /* 688 * RSM Auto-Halt Restart Returns to Incorrect RIP 689 */ 690 #if defined(OPTERON_ERRATUM_93) 691 /* 692 * fix is in trap.c 693 */ 694 opteron_erratum_93++; 695 #else 696 workaround_warning(cpu, 93); 697 missing++; 698 #endif 699 } 700 701 /*LINTED*/ 702 if (cpuid_opteron_erratum(cpu, 95) > 0) { 703 /* 704 * RET Instruction May Return to Incorrect EIP 705 */ 706 #if defined(OPTERON_ERRATUM_95) 707 #if defined(_LP64) 708 /* 709 * Workaround this by ensuring that 32-bit user code and 710 * 64-bit kernel code never occupy the same address 711 * range mod 4G. 712 */ 713 if (_userlimit32 > 0xc0000000ul) 714 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 715 716 /*LINTED*/ 717 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 718 opteron_erratum_95++; 719 #endif /* _LP64 */ 720 #else 721 workaround_warning(cpu, 95); 722 missing++; 723 #endif 724 } 725 726 if (cpuid_opteron_erratum(cpu, 100) > 0) { 727 /* 728 * Compatibility Mode Branches Transfer to Illegal Address 729 */ 730 #if defined(OPTERON_ERRATUM_100) 731 /* 732 * fix is in trap.c 733 */ 734 opteron_erratum_100++; 735 #else 736 workaround_warning(cpu, 100); 737 missing++; 738 #endif 739 } 740 741 /*LINTED*/ 742 if (cpuid_opteron_erratum(cpu, 108) > 0) { 743 /* 744 * CPUID Instruction May Return Incorrect Model Number In 745 * Some Processors 746 */ 747 #if defined(OPTERON_ERRATUM_108) 748 /* 749 * (Our cpuid-handling code corrects the model number on 750 * those processors) 751 */ 752 #else 753 workaround_warning(cpu, 108); 754 missing++; 755 #endif 756 } 757 758 /*LINTED*/ 759 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 760 /* 761 * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 762 */ 763 #if defined(OPTERON_ERRATUM_109) 764 /* 765 * The "workaround" is to print a warning to upgrade the BIOS 766 */ 767 uint64_t value; 768 const uint_t msr = MSR_AMD_PATCHLEVEL; 769 int err; 770 771 if ((err = checked_rdmsr(msr, &value)) != 0) { 772 msr_warning(cpu, "rd", msr, err); 773 workaround_warning(cpu, 109); 774 missing++; 775 } 776 if (value == 0) 777 opteron_erratum_109++; 778 #else 779 workaround_warning(cpu, 109); 780 missing++; 781 #endif 782 /*CONSTANTCONDITION*/ 783 } while (0); 784 785 /*LINTED*/ 786 if (cpuid_opteron_erratum(cpu, 121) > 0) { 787 /* 788 * Sequential Execution Across Non_Canonical Boundary Caused 789 * Processor Hang 790 */ 791 #if defined(OPTERON_ERRATUM_121) 792 #if defined(_LP64) 793 /* 794 * Erratum 121 is only present in long (64 bit) mode. 795 * Workaround is to include the page immediately before the 796 * va hole to eliminate the possibility of system hangs due to 797 * sequential execution across the va hole boundary. 798 */ 799 if (opteron_erratum_121) 800 opteron_erratum_121++; 801 else { 802 if (hole_start) { 803 hole_start -= PAGESIZE; 804 } else { 805 /* 806 * hole_start not yet initialized by 807 * mmu_init. Initialize hole_start 808 * with value to be subtracted. 809 */ 810 hole_start = PAGESIZE; 811 } 812 opteron_erratum_121++; 813 } 814 #endif /* _LP64 */ 815 #else 816 workaround_warning(cpu, 121); 817 missing++; 818 #endif 819 } 820 821 /*LINTED*/ 822 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 823 /* 824 * TLB Flush Filter May Cause Coherency Problem in 825 * Multiprocessor Systems 826 */ 827 #if defined(OPTERON_ERRATUM_122) 828 uint64_t value; 829 const uint_t msr = MSR_AMD_HWCR; 830 int error; 831 832 /* 833 * Erratum 122 is only present in MP configurations (multi-core 834 * or multi-processor). 835 */ 836 #if defined(__xpv) 837 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 838 break; 839 if (!opteron_erratum_122 && xen_get_nphyscpus() == 1) 840 break; 841 #else 842 if (!opteron_erratum_122 && lgrp_plat_node_cnt == 1 && 843 cpuid_get_ncpu_per_chip(cpu) == 1) 844 break; 845 #endif 846 /* disable TLB Flush Filter */ 847 848 if ((error = checked_rdmsr(msr, &value)) != 0) { 849 msr_warning(cpu, "rd", msr, error); 850 workaround_warning(cpu, 122); 851 missing++; 852 } else { 853 value |= (uint64_t)AMD_HWCR_FFDIS; 854 if ((error = checked_wrmsr(msr, value)) != 0) { 855 msr_warning(cpu, "wr", msr, error); 856 workaround_warning(cpu, 122); 857 missing++; 858 } 859 } 860 opteron_erratum_122++; 861 #else 862 workaround_warning(cpu, 122); 863 missing++; 864 #endif 865 /*CONSTANTCONDITION*/ 866 } while (0); 867 868 /*LINTED*/ 869 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 870 /* 871 * Bypassed Reads May Cause Data Corruption of System Hang in 872 * Dual Core Processors 873 */ 874 #if defined(OPTERON_ERRATUM_123) 875 uint64_t value; 876 const uint_t msr = MSR_AMD_PATCHLEVEL; 877 int err; 878 879 /* 880 * Erratum 123 applies only to multi-core cpus. 881 */ 882 if (cpuid_get_ncpu_per_chip(cpu) < 2) 883 break; 884 #if defined(__xpv) 885 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 886 break; 887 #endif 888 /* 889 * The "workaround" is to print a warning to upgrade the BIOS 890 */ 891 if ((err = checked_rdmsr(msr, &value)) != 0) { 892 msr_warning(cpu, "rd", msr, err); 893 workaround_warning(cpu, 123); 894 missing++; 895 } 896 if (value == 0) 897 opteron_erratum_123++; 898 #else 899 workaround_warning(cpu, 123); 900 missing++; 901 902 #endif 903 /*CONSTANTCONDITION*/ 904 } while (0); 905 906 /*LINTED*/ 907 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 908 /* 909 * Multiprocessor Systems with Four or More Cores May Deadlock 910 * Waiting for a Probe Response 911 */ 912 #if defined(OPTERON_ERRATUM_131) 913 uint64_t nbcfg; 914 const uint_t msr = MSR_AMD_NB_CFG; 915 const uint64_t wabits = 916 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 917 int error; 918 919 /* 920 * Erratum 131 applies to any system with four or more cores. 921 */ 922 if (opteron_erratum_131) 923 break; 924 #if defined(__xpv) 925 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 926 break; 927 if (xen_get_nphyscpus() < 4) 928 break; 929 #else 930 if (lgrp_plat_node_cnt * cpuid_get_ncpu_per_chip(cpu) < 4) 931 break; 932 #endif 933 /* 934 * Print a warning if neither of the workarounds for 935 * erratum 131 is present. 936 */ 937 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 938 msr_warning(cpu, "rd", msr, error); 939 workaround_warning(cpu, 131); 940 missing++; 941 } else if ((nbcfg & wabits) == 0) { 942 opteron_erratum_131++; 943 } else { 944 /* cannot have both workarounds set */ 945 ASSERT((nbcfg & wabits) != wabits); 946 } 947 #else 948 workaround_warning(cpu, 131); 949 missing++; 950 #endif 951 /*CONSTANTCONDITION*/ 952 } while (0); 953 954 /* 955 * This isn't really an erratum, but for convenience the 956 * detection/workaround code lives here and in cpuid_opteron_erratum. 957 */ 958 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 959 #if defined(OPTERON_WORKAROUND_6336786) 960 /* 961 * Disable C1-Clock ramping on multi-core/multi-processor 962 * K8 platforms to guard against TSC drift. 963 */ 964 if (opteron_workaround_6336786) { 965 opteron_workaround_6336786++; 966 #if defined(__xpv) 967 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 968 xen_get_nphyscpus() > 1) || 969 opteron_workaround_6336786_UP) { 970 /* 971 * XXPV Hmm. We can't walk the set of lgrps on 972 * the hypervisor; so just complain and drive 973 * on. This probably needs to be fixed in 974 * the hypervisor itself. 975 */ 976 opteron_workaround_6336786++; 977 workaround_warning(cpu, 6336786); 978 #else /* __xpv */ 979 } else if ((lgrp_plat_node_cnt * 980 cpuid_get_ncpu_per_chip(cpu) > 1) || 981 opteron_workaround_6336786_UP) { 982 int node; 983 uint8_t data; 984 985 for (node = 0; node < lgrp_plat_node_cnt; node++) { 986 /* 987 * Clear PMM7[1:0] (function 3, offset 0x87) 988 * Northbridge device is the node id + 24. 989 */ 990 data = pci_getb_func(0, node + 24, 3, 0x87); 991 data &= 0xFC; 992 pci_putb_func(0, node + 24, 3, 0x87, data); 993 } 994 opteron_workaround_6336786++; 995 #endif /* __xpv */ 996 } 997 #else 998 workaround_warning(cpu, 6336786); 999 missing++; 1000 #endif 1001 } 1002 1003 /*LINTED*/ 1004 /* 1005 * Mutex primitives don't work as expected. 1006 */ 1007 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1008 #if defined(OPTERON_WORKAROUND_6323525) 1009 /* 1010 * This problem only occurs with 2 or more cores. If bit in 1011 * MSR_BU_CFG set, then not applicable. The workaround 1012 * is to patch the semaphone routines with the lfence 1013 * instruction to provide necessary load memory barrier with 1014 * possible subsequent read-modify-write ops. 1015 * 1016 * It is too early in boot to call the patch routine so 1017 * set erratum variable to be done in startup_end(). 1018 */ 1019 if (opteron_workaround_6323525) { 1020 opteron_workaround_6323525++; 1021 #if defined(__xpv) 1022 } else if (x86_feature & X86_SSE2) { 1023 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1024 /* 1025 * XXPV Use dom0_msr here when extended 1026 * operations are supported? 1027 */ 1028 if (xen_get_nphyscpus() > 1) 1029 opteron_workaround_6323525++; 1030 } else { 1031 /* 1032 * We have no way to tell how many physical 1033 * cpus there are, or even if this processor 1034 * has the problem, so enable the workaround 1035 * unconditionally (at some performance cost). 1036 */ 1037 opteron_workaround_6323525++; 1038 } 1039 #else /* __xpv */ 1040 } else if ((x86_feature & X86_SSE2) && ((lgrp_plat_node_cnt * 1041 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 1042 if ((xrdmsr(MSR_BU_CFG) & 0x02) == 0) 1043 opteron_workaround_6323525++; 1044 #endif /* __xpv */ 1045 } 1046 #else 1047 workaround_warning(cpu, 6323525); 1048 missing++; 1049 #endif 1050 } 1051 1052 #ifdef __xpv 1053 return (0); 1054 #else 1055 return (missing); 1056 #endif 1057 } 1058 1059 void 1060 workaround_errata_end() 1061 { 1062 #if defined(OPTERON_ERRATUM_88) 1063 if (opteron_erratum_88) 1064 workaround_applied(88); 1065 #endif 1066 #if defined(OPTERON_ERRATUM_91) 1067 if (opteron_erratum_91) 1068 workaround_applied(91); 1069 #endif 1070 #if defined(OPTERON_ERRATUM_93) 1071 if (opteron_erratum_93) 1072 workaround_applied(93); 1073 #endif 1074 #if defined(OPTERON_ERRATUM_95) 1075 if (opteron_erratum_95) 1076 workaround_applied(95); 1077 #endif 1078 #if defined(OPTERON_ERRATUM_100) 1079 if (opteron_erratum_100) 1080 workaround_applied(100); 1081 #endif 1082 #if defined(OPTERON_ERRATUM_108) 1083 if (opteron_erratum_108) 1084 workaround_applied(108); 1085 #endif 1086 #if defined(OPTERON_ERRATUM_109) 1087 if (opteron_erratum_109) { 1088 cmn_err(CE_WARN, 1089 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1090 " processor\nerratum 109 was not detected; updating your" 1091 " system's BIOS to a version\ncontaining this" 1092 " microcode patch is HIGHLY recommended or erroneous" 1093 " system\noperation may occur.\n"); 1094 } 1095 #endif 1096 #if defined(OPTERON_ERRATUM_121) 1097 if (opteron_erratum_121) 1098 workaround_applied(121); 1099 #endif 1100 #if defined(OPTERON_ERRATUM_122) 1101 if (opteron_erratum_122) 1102 workaround_applied(122); 1103 #endif 1104 #if defined(OPTERON_ERRATUM_123) 1105 if (opteron_erratum_123) { 1106 cmn_err(CE_WARN, 1107 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1108 " processor\nerratum 123 was not detected; updating your" 1109 " system's BIOS to a version\ncontaining this" 1110 " microcode patch is HIGHLY recommended or erroneous" 1111 " system\noperation may occur.\n"); 1112 } 1113 #endif 1114 #if defined(OPTERON_ERRATUM_131) 1115 if (opteron_erratum_131) { 1116 cmn_err(CE_WARN, 1117 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1118 " processor\nerratum 131 was not detected; updating your" 1119 " system's BIOS to a version\ncontaining this" 1120 " microcode patch is HIGHLY recommended or erroneous" 1121 " system\noperation may occur.\n"); 1122 } 1123 #endif 1124 #if defined(OPTERON_WORKAROUND_6336786) 1125 if (opteron_workaround_6336786) 1126 workaround_applied(6336786); 1127 #endif 1128 #if defined(OPTERON_WORKAROUND_6323525) 1129 if (opteron_workaround_6323525) 1130 workaround_applied(6323525); 1131 #endif 1132 } 1133 1134 static cpuset_t procset; 1135 1136 /* 1137 * Start a single cpu, assuming that the kernel context is available 1138 * to successfully start another cpu. 1139 * 1140 * (For example, real mode code is mapped into the right place 1141 * in memory and is ready to be run.) 1142 */ 1143 int 1144 start_cpu(processorid_t who) 1145 { 1146 void *ctx; 1147 cpu_t *cp; 1148 int delays; 1149 int error = 0; 1150 1151 ASSERT(who != 0); 1152 1153 /* 1154 * Check if there's at least a Mbyte of kmem available 1155 * before attempting to start the cpu. 1156 */ 1157 if (kmem_avail() < 1024 * 1024) { 1158 /* 1159 * Kick off a reap in case that helps us with 1160 * later attempts .. 1161 */ 1162 kmem_reap(); 1163 return (ENOMEM); 1164 } 1165 1166 cp = mp_startup_init(who); 1167 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1168 (error = mach_cpu_start(cp, ctx)) != 0) { 1169 1170 /* 1171 * Something went wrong before we even started it 1172 */ 1173 if (ctx) 1174 cmn_err(CE_WARN, 1175 "cpu%d: failed to start error %d", 1176 cp->cpu_id, error); 1177 else 1178 cmn_err(CE_WARN, 1179 "cpu%d: failed to allocate context", cp->cpu_id); 1180 1181 if (ctx) 1182 mach_cpucontext_free(cp, ctx, error); 1183 else 1184 error = EAGAIN; /* hmm. */ 1185 mp_startup_fini(cp, error); 1186 return (error); 1187 } 1188 1189 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1190 if (delays == 500) { 1191 /* 1192 * After five seconds, things are probably looking 1193 * a bit bleak - explain the hang. 1194 */ 1195 cmn_err(CE_NOTE, "cpu%d: started, " 1196 "but not running in the kernel yet", who); 1197 } else if (delays > 2000) { 1198 /* 1199 * We waited at least 20 seconds, bail .. 1200 */ 1201 error = ETIMEDOUT; 1202 cmn_err(CE_WARN, "cpu%d: timed out", who); 1203 mach_cpucontext_free(cp, ctx, error); 1204 mp_startup_fini(cp, error); 1205 return (error); 1206 } 1207 1208 /* 1209 * wait at least 10ms, then check again.. 1210 */ 1211 delay(USEC_TO_TICK_ROUNDUP(10000)); 1212 } 1213 1214 mach_cpucontext_free(cp, ctx, 0); 1215 1216 #ifndef __xpv 1217 if (tsc_gethrtime_enable) 1218 tsc_sync_master(who); 1219 #endif 1220 1221 if (dtrace_cpu_init != NULL) { 1222 /* 1223 * DTrace CPU initialization expects cpu_lock to be held. 1224 */ 1225 mutex_enter(&cpu_lock); 1226 (*dtrace_cpu_init)(who); 1227 mutex_exit(&cpu_lock); 1228 } 1229 1230 while (!CPU_IN_SET(cpu_ready_set, who)) 1231 delay(1); 1232 1233 return (0); 1234 } 1235 1236 1237 /*ARGSUSED*/ 1238 void 1239 start_other_cpus(int cprboot) 1240 { 1241 uint_t who; 1242 uint_t skipped = 0; 1243 uint_t bootcpuid = 0; 1244 1245 /* 1246 * Initialize our own cpu_info. 1247 */ 1248 init_cpu_info(CPU); 1249 1250 /* 1251 * Initialize our syscall handlers 1252 */ 1253 init_cpu_syscall(CPU); 1254 1255 /* 1256 * Take the boot cpu out of the mp_cpus set because we know 1257 * it's already running. Add it to the cpu_ready_set for 1258 * precisely the same reason. 1259 */ 1260 CPUSET_DEL(mp_cpus, bootcpuid); 1261 CPUSET_ADD(cpu_ready_set, bootcpuid); 1262 1263 /* 1264 * if only 1 cpu or not using MP, skip the rest of this 1265 */ 1266 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1267 if (use_mp == 0) 1268 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1269 goto done; 1270 } 1271 1272 /* 1273 * perform such initialization as is needed 1274 * to be able to take CPUs on- and off-line. 1275 */ 1276 cpu_pause_init(); 1277 1278 xc_init(); /* initialize processor crosscalls */ 1279 1280 if (mach_cpucontext_init() != 0) 1281 goto done; 1282 1283 flushes_require_xcalls = 1; 1284 1285 /* 1286 * We lock our affinity to the master CPU to ensure that all slave CPUs 1287 * do their TSC syncs with the same CPU. 1288 */ 1289 affinity_set(CPU_CURRENT); 1290 1291 for (who = 0; who < NCPU; who++) { 1292 1293 if (!CPU_IN_SET(mp_cpus, who)) 1294 continue; 1295 ASSERT(who != bootcpuid); 1296 if (ncpus >= max_ncpus) { 1297 skipped = who; 1298 continue; 1299 } 1300 if (start_cpu(who) != 0) 1301 CPUSET_DEL(mp_cpus, who); 1302 } 1303 1304 #if !defined(__xpv) 1305 /* Free the space allocated to hold the microcode file */ 1306 ucode_free(); 1307 #endif 1308 1309 affinity_clear(); 1310 1311 if (skipped) { 1312 cmn_err(CE_NOTE, 1313 "System detected %d cpus, but " 1314 "only %d cpu(s) were enabled during boot.", 1315 skipped + 1, ncpus); 1316 cmn_err(CE_NOTE, 1317 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1318 "See eeprom(1M)."); 1319 } 1320 1321 done: 1322 workaround_errata_end(); 1323 mach_cpucontext_fini(); 1324 1325 cmi_post_mpstartup(); 1326 } 1327 1328 /* 1329 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1330 */ 1331 /*ARGSUSED*/ 1332 int 1333 mp_cpu_configure(int cpuid) 1334 { 1335 return (ENOTSUP); /* not supported */ 1336 } 1337 1338 /*ARGSUSED*/ 1339 int 1340 mp_cpu_unconfigure(int cpuid) 1341 { 1342 return (ENOTSUP); /* not supported */ 1343 } 1344 1345 /* 1346 * Startup function for 'other' CPUs (besides boot cpu). 1347 * Called from real_mode_start. 1348 * 1349 * WARNING: until CPU_READY is set, mp_startup and routines called by 1350 * mp_startup should not call routines (e.g. kmem_free) that could call 1351 * hat_unload which requires CPU_READY to be set. 1352 */ 1353 void 1354 mp_startup(void) 1355 { 1356 struct cpu *cp = CPU; 1357 uint_t new_x86_feature; 1358 1359 /* 1360 * We need to get TSC on this proc synced (i.e., any delta 1361 * from cpu0 accounted for) as soon as we can, because many 1362 * many things use gethrtime/pc_gethrestime, including 1363 * interrupts, cmn_err, etc. 1364 */ 1365 1366 /* Let cpu0 continue into tsc_sync_master() */ 1367 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1368 1369 #ifndef __xpv 1370 if (tsc_gethrtime_enable) 1371 tsc_sync_slave(); 1372 #endif 1373 1374 /* 1375 * Once this was done from assembly, but it's safer here; if 1376 * it blocks, we need to be able to swtch() to and from, and 1377 * since we get here by calling t_pc, we need to do that call 1378 * before swtch() overwrites it. 1379 */ 1380 1381 (void) (*ap_mlsetup)(); 1382 1383 new_x86_feature = cpuid_pass1(cp); 1384 1385 #ifndef __xpv 1386 /* 1387 * Program this cpu's PAT 1388 */ 1389 if (x86_feature & X86_PAT) 1390 pat_sync(); 1391 #endif 1392 1393 /* 1394 * Set up TSC_AUX to contain the cpuid for this processor 1395 * for the rdtscp instruction. 1396 */ 1397 if (x86_feature & X86_TSCP) 1398 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1399 1400 /* 1401 * Initialize this CPU's syscall handlers 1402 */ 1403 init_cpu_syscall(cp); 1404 1405 /* 1406 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1407 * highest level at which a routine is permitted to block on 1408 * an adaptive mutex (allows for cpu poke interrupt in case 1409 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1410 * device interrupts that may end up in the hat layer issuing cross 1411 * calls before CPU_READY is set. 1412 */ 1413 splx(ipltospl(LOCK_LEVEL)); 1414 sti(); 1415 1416 /* 1417 * Do a sanity check to make sure this new CPU is a sane thing 1418 * to add to the collection of processors running this system. 1419 * 1420 * XXX Clearly this needs to get more sophisticated, if x86 1421 * systems start to get built out of heterogenous CPUs; as is 1422 * likely to happen once the number of processors in a configuration 1423 * gets large enough. 1424 */ 1425 if ((x86_feature & new_x86_feature) != x86_feature) { 1426 cmn_err(CE_CONT, "?cpu%d: %b\n", 1427 cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 1428 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1429 } 1430 1431 /* 1432 * We do not support cpus with mixed monitor/mwait support if the 1433 * boot cpu supports monitor/mwait. 1434 */ 1435 if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1436 panic("unsupported mixed cpu monitor/mwait support detected"); 1437 1438 /* 1439 * We could be more sophisticated here, and just mark the CPU 1440 * as "faulted" but at this point we'll opt for the easier 1441 * answer of dieing horribly. Provided the boot cpu is ok, 1442 * the system can be recovered by booting with use_mp set to zero. 1443 */ 1444 if (workaround_errata(cp) != 0) 1445 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1446 1447 cpuid_pass2(cp); 1448 cpuid_pass3(cp); 1449 (void) cpuid_pass4(cp); 1450 1451 init_cpu_info(cp); 1452 1453 mutex_enter(&cpu_lock); 1454 /* 1455 * Processor group initialization for this CPU is dependent on the 1456 * cpuid probing, which must be done in the context of the current 1457 * CPU. 1458 */ 1459 pghw_physid_create(cp); 1460 pg_cpu_init(cp); 1461 pg_cmt_cpu_startup(cp); 1462 1463 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_ENABLE | CPU_EXISTS; 1464 cpu_add_active(cp); 1465 1466 if (dtrace_cpu_init != NULL) { 1467 (*dtrace_cpu_init)(cp->cpu_id); 1468 } 1469 1470 #if !defined(__xpv) 1471 /* 1472 * Fill out cpu_ucode_info. Update microcode if necessary. 1473 */ 1474 ucode_check(cp); 1475 #endif 1476 1477 mutex_exit(&cpu_lock); 1478 1479 /* 1480 * Enable preemption here so that contention for any locks acquired 1481 * later in mp_startup may be preempted if the thread owning those 1482 * locks is continously executing on other CPUs (for example, this 1483 * CPU must be preemptible to allow other CPUs to pause it during their 1484 * startup phases). It's safe to enable preemption here because the 1485 * CPU state is pretty-much fully constructed. 1486 */ 1487 curthread->t_preempt = 0; 1488 1489 add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 1490 1491 /* The base spl should still be at LOCK LEVEL here */ 1492 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1493 set_base_spl(); /* Restore the spl to its proper value */ 1494 1495 (void) spl0(); /* enable interrupts */ 1496 1497 #ifndef __xpv 1498 { 1499 /* 1500 * Set up the CPU module for this CPU. This can't be done 1501 * before this CPU is made CPU_READY, because we may (in 1502 * heterogeneous systems) need to go load another CPU module. 1503 * The act of attempting to load a module may trigger a 1504 * cross-call, which will ASSERT unless this cpu is CPU_READY. 1505 */ 1506 cmi_hdl_t hdl; 1507 1508 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1509 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 1510 if (x86_feature & X86_MCA) 1511 cmi_mca_init(hdl); 1512 } 1513 } 1514 #endif /* __xpv */ 1515 1516 if (boothowto & RB_DEBUG) 1517 kdi_cpu_init(); 1518 1519 /* 1520 * Setting the bit in cpu_ready_set must be the last operation in 1521 * processor initialization; the boot CPU will continue to boot once 1522 * it sees this bit set for all active CPUs. 1523 */ 1524 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1525 1526 /* 1527 * Because mp_startup() gets fired off after init() starts, we 1528 * can't use the '?' trick to do 'boot -v' printing - so we 1529 * always direct the 'cpu .. online' messages to the log. 1530 */ 1531 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1532 cp->cpu_id); 1533 1534 /* 1535 * Now we are done with the startup thread, so free it up. 1536 */ 1537 thread_exit(); 1538 panic("mp_startup: cannot return"); 1539 /*NOTREACHED*/ 1540 } 1541 1542 1543 /* 1544 * Start CPU on user request. 1545 */ 1546 /* ARGSUSED */ 1547 int 1548 mp_cpu_start(struct cpu *cp) 1549 { 1550 ASSERT(MUTEX_HELD(&cpu_lock)); 1551 return (0); 1552 } 1553 1554 /* 1555 * Stop CPU on user request. 1556 */ 1557 /* ARGSUSED */ 1558 int 1559 mp_cpu_stop(struct cpu *cp) 1560 { 1561 extern int cbe_psm_timer_mode; 1562 ASSERT(MUTEX_HELD(&cpu_lock)); 1563 1564 #ifdef __xpv 1565 /* 1566 * We can't offline vcpu0. 1567 */ 1568 if (cp->cpu_id == 0) 1569 return (EBUSY); 1570 #endif 1571 1572 /* 1573 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1574 * can't stop it. (This is true only for machines with no TSC.) 1575 */ 1576 1577 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1578 return (EBUSY); 1579 1580 return (0); 1581 } 1582 1583 /* 1584 * Take the specified CPU out of participation in interrupts. 1585 */ 1586 int 1587 cpu_disable_intr(struct cpu *cp) 1588 { 1589 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1590 return (EBUSY); 1591 1592 cp->cpu_flags &= ~CPU_ENABLE; 1593 return (0); 1594 } 1595 1596 /* 1597 * Allow the specified CPU to participate in interrupts. 1598 */ 1599 void 1600 cpu_enable_intr(struct cpu *cp) 1601 { 1602 ASSERT(MUTEX_HELD(&cpu_lock)); 1603 cp->cpu_flags |= CPU_ENABLE; 1604 psm_enable_intr(cp->cpu_id); 1605 } 1606 1607 1608 /*ARGSUSED*/ 1609 void 1610 mp_cpu_faulted_enter(struct cpu *cp) 1611 { 1612 #ifndef __xpv 1613 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1614 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1615 1616 if (hdl != NULL) { 1617 cmi_faulted_enter(hdl); 1618 cmi_hdl_rele(hdl); 1619 } 1620 #endif 1621 } 1622 1623 /*ARGSUSED*/ 1624 void 1625 mp_cpu_faulted_exit(struct cpu *cp) 1626 { 1627 #ifndef __xpv 1628 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1629 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1630 1631 if (hdl != NULL) { 1632 cmi_faulted_exit(hdl); 1633 cmi_hdl_rele(hdl); 1634 } 1635 #endif 1636 } 1637 1638 /* 1639 * The following two routines are used as context operators on threads belonging 1640 * to processes with a private LDT (see sysi86). Due to the rarity of such 1641 * processes, these routines are currently written for best code readability and 1642 * organization rather than speed. We could avoid checking x86_feature at every 1643 * context switch by installing different context ops, depending on the 1644 * x86_feature flags, at LDT creation time -- one for each combination of fast 1645 * syscall feature flags. 1646 */ 1647 1648 /*ARGSUSED*/ 1649 void 1650 cpu_fast_syscall_disable(void *arg) 1651 { 1652 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1653 cpu_sep_disable(); 1654 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1655 cpu_asysc_disable(); 1656 } 1657 1658 /*ARGSUSED*/ 1659 void 1660 cpu_fast_syscall_enable(void *arg) 1661 { 1662 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1663 cpu_sep_enable(); 1664 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1665 cpu_asysc_enable(); 1666 } 1667 1668 static void 1669 cpu_sep_enable(void) 1670 { 1671 ASSERT(x86_feature & X86_SEP); 1672 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1673 1674 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1675 } 1676 1677 static void 1678 cpu_sep_disable(void) 1679 { 1680 ASSERT(x86_feature & X86_SEP); 1681 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1682 1683 /* 1684 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1685 * the sysenter or sysexit instruction to trigger a #gp fault. 1686 */ 1687 wrmsr(MSR_INTC_SEP_CS, 0); 1688 } 1689 1690 static void 1691 cpu_asysc_enable(void) 1692 { 1693 ASSERT(x86_feature & X86_ASYSC); 1694 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1695 1696 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1697 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1698 } 1699 1700 static void 1701 cpu_asysc_disable(void) 1702 { 1703 ASSERT(x86_feature & X86_ASYSC); 1704 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1705 1706 /* 1707 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1708 * executing syscall or sysret with this bit off will incur a #ud trap. 1709 */ 1710 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1711 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1712 } 1713