1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 30 #include <sys/archsystm.h> /* for {in,out}{b,w,l}() */ 31 #include <sys/cmn_err.h> 32 #include <sys/cpupart.h> 33 #include <sys/cpuvar.h> 34 #include <sys/lgrp.h> 35 #include <sys/machsystm.h> 36 #include <sys/memlist.h> 37 #include <sys/memnode.h> 38 #include <sys/mman.h> 39 #include <sys/pci_impl.h> /* for PCI configuration space macros */ 40 #include <sys/param.h> 41 #include <sys/promif.h> /* for prom_printf() */ 42 #include <sys/systm.h> 43 #include <sys/thread.h> 44 #include <sys/types.h> 45 #include <sys/var.h> 46 #include <sys/x86_archext.h> /* for x86_feature and X86_AMD */ 47 #include <vm/hat_i86.h> 48 #include <vm/seg_kmem.h> 49 50 51 52 /* 53 * lgroup platform support for x86 platforms. 54 */ 55 56 #define MAX_NODES 8 57 #define NLGRP (MAX_NODES * (MAX_NODES - 1) + 1) 58 59 #define LGRP_PLAT_CPU_TO_NODE(cpu) (chip_plat_get_chipid(cpu)) 60 61 #define LGRP_PLAT_PROBE_NROUNDS 64 /* default laps for probing */ 62 #define LGRP_PLAT_PROBE_NSAMPLES 1 /* default samples to take */ 63 64 65 /* 66 * Multiprocessor Opteron machines have Non Uniform Memory Access (NUMA). 67 * 68 * Until System Affinity Resource Table (SRAT) becomes part of ACPI standard, 69 * we need to examine registers in PCI configuration space to determine how 70 * many nodes are in the system and which CPUs and memory are in each node. 71 * This could be determined by probing all memory from each CPU, but that is 72 * too expensive to do while booting the kernel. 73 * 74 * NOTE: Using these PCI configuration space registers to determine this 75 * locality info is Opteron K8 specific and not guaranteed to work on 76 * the next generation Opteron processor. Furthermore, we assume that 77 * there is one CPU per node and CPU 0 is in node 0, CPU 1 is in node 1, 78 * etc. which should be true for Opteron K8.... 79 */ 80 81 /* 82 * Opteron DRAM Address Map in PCI configuration space gives base and limit 83 * of physical memory in each node for Opteron K8. The following constants 84 * and macros define their contents, structure, and access. 85 */ 86 87 /* 88 * How many bits to shift Opteron DRAM Address Map base and limit registers 89 * to get actual value 90 */ 91 #define OPT_DRAMADDR_LSHIFT_ADDR 8 /* shift left for address */ 92 93 #define OPT_DRAMADDR_MASK_OFF 0xFFFFFF /* offset for address */ 94 95 /* 96 * Bit masks defining what's in Opteron DRAM Address Map base register 97 */ 98 #define OPT_DRAMBASE_MASK_RE 0x1 /* read enable */ 99 #define OPT_DRAMBASE_MASK_WE 0x2 /* write enable */ 100 #define OPT_DRAMBASE_MASK_INTRLVEN 0x700 /* interleave */ 101 102 #define OPT_DRAMBASE_MASK_ADDR 0xFFFF0000 /* address bits 39-24 */ 103 104 /* 105 * Macros to get values from Opteron DRAM Address Map base register 106 */ 107 #define OPT_DRAMBASE(reg) \ 108 (((u_longlong_t)reg & OPT_DRAMBASE_MASK_ADDR) << \ 109 OPT_DRAMADDR_LSHIFT_ADDR) 110 111 112 /* 113 * Bit masks defining what's in Opteron DRAM Address Map limit register 114 */ 115 #define OPT_DRAMLIMIT_MASK_DSTNODE 0x7 /* destination node */ 116 #define OPT_DRAMLIMIT_MASK_INTRLVSEL 0x70 /* interleave select */ 117 #define OPT_DRAMLIMIT_MASK_ADDR 0xFFFF0000 /* addr bits 39-24 */ 118 119 /* 120 * Macros to get values from Opteron DRAM Address Map limit register 121 */ 122 #define OPT_DRAMLIMIT(reg) \ 123 (((u_longlong_t)reg & OPT_DRAMLIMIT_MASK_ADDR) << \ 124 OPT_DRAMADDR_LSHIFT_ADDR) 125 126 127 /* 128 * Opteron Node ID register in PCI configuration space contains 129 * number of nodes in system, etc. for Opteron K8. The following 130 * constants and macros define its contents, structure, and access. 131 */ 132 133 /* 134 * Bit masks defining what's in Opteron Node ID register 135 */ 136 #define OPT_NODE_MASK_ID 0x7 /* node ID */ 137 #define OPT_NODE_MASK_CNT 0x70 /* node count */ 138 #define OPT_NODE_MASK_IONODE 0x700 /* Hypertransport I/O hub node ID */ 139 #define OPT_NODE_MASK_LCKNODE 0x7000 /* lock controller node ID */ 140 #define OPT_NODE_MASK_CPUCNT 0xF0000 /* CPUs in system (0 means 1 CPU) */ 141 142 /* 143 * How many bits in Opteron Node ID register to shift right to get actual value 144 */ 145 #define OPT_NODE_RSHIFT_CNT 0x4 /* shift right for node count value */ 146 147 /* 148 * Macros to get values from Opteron Node ID register 149 */ 150 #define OPT_NODE_CNT(reg) \ 151 ((reg & OPT_NODE_MASK_CNT) >> OPT_NODE_RSHIFT_CNT) 152 153 154 /* 155 * PCI configuration space registers accessed by specifying 156 * a bus, device, function, and offset. The following constants 157 * define the values needed to access Opteron K8 configuration 158 * info to determine its node topology 159 */ 160 161 #define OPT_PCS_BUS_CONFIG 0 /* Hypertransport config space bus */ 162 163 /* 164 * Opteron PCI configuration space register function values 165 */ 166 #define OPT_PCS_FUNC_HT 0 /* Hypertransport configuration */ 167 #define OPT_PCS_FUNC_ADDRMAP 1 /* Address map configuration */ 168 #define OPT_PCS_FUNC_DRAM 2 /* DRAM configuration */ 169 #define OPT_PCS_FUNC_MISC 3 /* Miscellaneous configuration */ 170 171 /* 172 * PCI Configuration Space register offsets 173 */ 174 #define OPT_PCS_OFF_VENDOR 0x0 /* device/vendor ID register */ 175 #define OPT_PCS_OFF_DRAMBASE 0x40 /* DRAM Base register (node 0) */ 176 #define OPT_PCS_OFF_NODEID 0x60 /* Node ID register */ 177 178 /* 179 * Opteron PCI Configuration Space device IDs for nodes 180 */ 181 #define OPT_PCS_DEV_NODE0 24 /* device number for node 0 */ 182 183 184 /* 185 * Bookkeeping for latencies seen during probing (used for verification) 186 */ 187 typedef struct lgrp_plat_latency_acct { 188 hrtime_t la_value; /* latency value */ 189 int la_count; /* occurrences */ 190 } lgrp_plat_latency_acct_t; 191 192 193 /* 194 * Choices for probing to determine lgroup topology 195 */ 196 typedef enum lgrp_plat_probe_op { 197 LGRP_PLAT_PROBE_PGCPY, /* Use page copy */ 198 LGRP_PLAT_PROBE_VENDOR /* Read vendor ID on Northbridge */ 199 } lgrp_plat_probe_op_t; 200 201 202 /* 203 * Opteron DRAM address map gives base and limit for physical memory in a node 204 */ 205 typedef struct opt_dram_addr_map { 206 uint32_t base; 207 uint32_t limit; 208 } opt_dram_addr_map_t; 209 210 211 /* 212 * Starting and ending page for physical memory in node 213 */ 214 typedef struct phys_addr_map { 215 pfn_t start; 216 pfn_t end; 217 } phys_addr_map_t; 218 219 220 /* 221 * Opteron DRAM address map for each node 222 */ 223 struct opt_dram_addr_map opt_dram_map[MAX_NODES]; 224 225 /* 226 * Node ID register contents for each node 227 */ 228 uint_t opt_node_info[MAX_NODES]; 229 230 /* 231 * Whether memory is interleaved across nodes causing MPO to be disabled 232 */ 233 int lgrp_plat_mem_intrlv = 0; 234 235 /* 236 * Number of nodes in system 237 */ 238 uint_t lgrp_plat_node_cnt = 1; 239 240 /* 241 * Physical address range for memory in each node 242 */ 243 phys_addr_map_t lgrp_plat_node_memory[MAX_NODES]; 244 245 /* 246 * Probe costs (individual and total) and flush cost 247 */ 248 hrtime_t lgrp_plat_flush_cost = 0; 249 hrtime_t lgrp_plat_probe_cost = 0; 250 hrtime_t lgrp_plat_probe_cost_total = 0; 251 252 /* 253 * Error code for latency adjustment and verification 254 */ 255 int lgrp_plat_probe_error_code = 0; 256 257 /* 258 * How much latencies were off from minimum values gotten 259 */ 260 hrtime_t lgrp_plat_probe_errors[MAX_NODES][MAX_NODES]; 261 262 /* 263 * Unique probe latencies and number of occurrences of each 264 */ 265 lgrp_plat_latency_acct_t lgrp_plat_probe_lat_acct[MAX_NODES]; 266 267 /* 268 * Size of memory buffer in each node for probing 269 */ 270 size_t lgrp_plat_probe_memsize = 0; 271 272 /* 273 * Virtual address of page in each node for probing 274 */ 275 caddr_t lgrp_plat_probe_memory[MAX_NODES]; 276 277 /* 278 * Number of unique latencies in probe times 279 */ 280 int lgrp_plat_probe_nlatencies = 0; 281 282 /* 283 * How many rounds of probing to do 284 */ 285 int lgrp_plat_probe_nrounds = LGRP_PLAT_PROBE_NROUNDS; 286 287 /* 288 * Number of samples to take when probing each node 289 */ 290 int lgrp_plat_probe_nsamples = LGRP_PLAT_PROBE_NSAMPLES; 291 292 /* 293 * How to probe to determine lgroup topology 294 */ 295 lgrp_plat_probe_op_t lgrp_plat_probe_op = LGRP_PLAT_PROBE_VENDOR; 296 297 /* 298 * PFN of page in each node for probing 299 */ 300 pfn_t lgrp_plat_probe_pfn[MAX_NODES]; 301 302 /* 303 * Whether probe time was suspect (ie. not within tolerance of value that it 304 * should match) 305 */ 306 int lgrp_plat_probe_suspect[MAX_NODES][MAX_NODES]; 307 308 /* 309 * How long it takes to access memory from each node 310 */ 311 hrtime_t lgrp_plat_probe_times[MAX_NODES][MAX_NODES]; 312 313 /* 314 * Min and max node memory probe times seen 315 */ 316 hrtime_t lgrp_plat_probe_time_max = 0; 317 hrtime_t lgrp_plat_probe_time_min = -1; 318 hrtime_t lgrp_plat_probe_max[MAX_NODES][MAX_NODES]; 319 hrtime_t lgrp_plat_probe_min[MAX_NODES][MAX_NODES]; 320 321 322 /* 323 * Allocate lgrp and lgrp stat arrays statically. 324 */ 325 static lgrp_t lgrp_space[NLGRP]; 326 static int nlgrps_alloc; 327 328 struct lgrp_stats lgrp_stats[NLGRP]; 329 330 #define CPUID_FAMILY_OPTERON 15 331 332 uint_t opt_family = 0; 333 uint_t opt_model = 0; 334 uint_t opt_probe_func = OPT_PCS_FUNC_DRAM; 335 336 337 /* 338 * Determine whether we're running on an AMD Opteron K8 machine 339 */ 340 int 341 is_opteron(void) 342 { 343 if (x86_vendor != X86_VENDOR_AMD) 344 return (0); 345 346 if (cpuid_getfamily(CPU) == CPUID_FAMILY_OPTERON) 347 return (1); 348 else 349 return (0); 350 } 351 352 int 353 plat_lgrphand_to_mem_node(lgrp_handle_t hand) 354 { 355 if (max_mem_nodes == 1) 356 return (0); 357 358 return ((int)hand); 359 } 360 361 lgrp_handle_t 362 plat_mem_node_to_lgrphand(int mnode) 363 { 364 if (max_mem_nodes == 1) 365 return (LGRP_DEFAULT_HANDLE); 366 367 return ((lgrp_handle_t)mnode); 368 } 369 370 int 371 plat_pfn_to_mem_node(pfn_t pfn) 372 { 373 int node; 374 375 if (max_mem_nodes == 1) 376 return (0); 377 378 for (node = 0; node < lgrp_plat_node_cnt; node++) { 379 if (pfn >= lgrp_plat_node_memory[node].start && 380 pfn <= lgrp_plat_node_memory[node].end) 381 return (node); 382 } 383 384 ASSERT(node < lgrp_plat_node_cnt); 385 return (-1); 386 } 387 388 /* 389 * Configure memory nodes for machines with more than one node (ie NUMA) 390 */ 391 void 392 plat_build_mem_nodes(struct memlist *list) 393 { 394 pfn_t cur_start, cur_end; /* start & end addr of subrange */ 395 pfn_t start, end; /* start & end addr of whole range */ 396 397 /* 398 * Boot install lists are arranged <addr, len>, ... 399 */ 400 while (list) { 401 int node; 402 403 start = list->address >> PAGESHIFT; 404 end = (list->address + list->size - 1) >> PAGESHIFT; 405 406 if (start > physmax) { 407 list = list->next; 408 continue; 409 } 410 if (end > physmax) 411 end = physmax; 412 413 /* 414 * When there is only one memnode, just add memory to memnode 415 */ 416 if (max_mem_nodes == 1) { 417 mem_node_add_slice(start, end); 418 list = list->next; 419 continue; 420 } 421 422 /* 423 * mem_node_add_slice() expects to get a memory range that 424 * is within one memnode, so need to split any memory range 425 * that spans multiple memnodes into subranges that are each 426 * contained within one memnode when feeding them to 427 * mem_node_add_slice() 428 */ 429 cur_start = start; 430 do { 431 node = plat_pfn_to_mem_node(cur_start); 432 ASSERT(cur_start >= 433 lgrp_plat_node_memory[node].start && 434 cur_start <= lgrp_plat_node_memory[node].end); 435 436 cur_end = end; 437 438 /* 439 * End of current subrange should not span memnodes 440 */ 441 if (cur_end > lgrp_plat_node_memory[node].end) 442 cur_end = lgrp_plat_node_memory[node].end; 443 444 mem_node_add_slice(cur_start, cur_end); 445 446 /* 447 * Next subrange starts after end of current one 448 */ 449 cur_start = cur_end + 1; 450 } while (cur_end < end); 451 452 list = list->next; 453 } 454 mem_node_physalign = 0; 455 mem_node_pfn_shift = 0; 456 } 457 458 459 /* 460 * Platform-specific initialization of lgroups 461 */ 462 void 463 lgrp_plat_init(void) 464 { 465 uint_t bus; 466 uint_t dev; 467 uint_t node; 468 uint_t off; 469 470 extern lgrp_load_t lgrp_expand_proc_thresh; 471 extern lgrp_load_t lgrp_expand_proc_diff; 472 473 /* 474 * Initialize as a UMA machine if this isn't an Opteron 475 */ 476 if (!is_opteron() || lgrp_topo_ht_limit() == 1) { 477 lgrp_plat_node_cnt = max_mem_nodes = 1; 478 return; 479 } 480 481 /* 482 * Read configuration registers from PCI configuration space to 483 * determine node information, which memory is in each node, etc. 484 * 485 * Write to PCI configuration space address register to specify 486 * which configuration register to read and read/write PCI 487 * configuration space data register to get/set contents 488 */ 489 bus = OPT_PCS_BUS_CONFIG; 490 dev = OPT_PCS_DEV_NODE0; 491 off = OPT_PCS_OFF_DRAMBASE; 492 493 /* 494 * Read node ID register for node 0 to get node count 495 */ 496 outl(PCI_CONFADD, PCI_CADDR1(bus, dev, OPT_PCS_FUNC_HT, 497 OPT_PCS_OFF_NODEID)); 498 opt_node_info[0] = inl(PCI_CONFDATA); 499 lgrp_plat_node_cnt = OPT_NODE_CNT(opt_node_info[0]) + 1; 500 501 for (node = 0; node < lgrp_plat_node_cnt; node++) { 502 /* 503 * Read node ID register (except for node 0 which we just read) 504 */ 505 if (node > 0) { 506 outl(PCI_CONFADD, PCI_CADDR1(bus, dev, 507 OPT_PCS_FUNC_HT, OPT_PCS_OFF_NODEID)); 508 opt_node_info[node] = inl(PCI_CONFDATA); 509 } 510 511 /* 512 * Read DRAM base and limit registers which specify 513 * physical memory range of each node 514 */ 515 outl(PCI_CONFADD, PCI_CADDR1(bus, dev, OPT_PCS_FUNC_ADDRMAP, 516 off)); 517 opt_dram_map[node].base = inl(PCI_CONFDATA); 518 if (opt_dram_map[node].base & OPT_DRAMBASE_MASK_INTRLVEN) 519 lgrp_plat_mem_intrlv++; 520 521 off += 4; /* limit register offset */ 522 outl(PCI_CONFADD, PCI_CADDR1(bus, dev, OPT_PCS_FUNC_ADDRMAP, 523 off)); 524 opt_dram_map[node].limit = inl(PCI_CONFDATA); 525 526 /* 527 * Increment device number to next node and register offset for 528 * DRAM base register of next node 529 */ 530 off += 4; 531 dev++; 532 533 /* 534 * Get PFN for first page in each node, 535 * so we can probe memory to determine latency topology 536 */ 537 lgrp_plat_probe_pfn[node] = 538 btop(OPT_DRAMBASE(opt_dram_map[node].base)); 539 540 /* 541 * Remember physical address range of each node for use later 542 */ 543 lgrp_plat_node_memory[node].start = 544 btop(OPT_DRAMBASE(opt_dram_map[node].base)); 545 lgrp_plat_node_memory[node].end = 546 btop(OPT_DRAMLIMIT(opt_dram_map[node].limit) | 547 OPT_DRAMADDR_MASK_OFF); 548 } 549 550 /* 551 * Only use one memory node if memory is interleaved between any nodes 552 */ 553 if (lgrp_plat_mem_intrlv) { 554 lgrp_plat_node_cnt = max_mem_nodes = 1; 555 (void) lgrp_topo_ht_limit_set(1); 556 } else { 557 max_mem_nodes = lgrp_plat_node_cnt; 558 559 /* 560 * Probing errors can mess up the lgroup topology and force us 561 * fall back to a 2 level lgroup topology. Here we bound how 562 * tall the lgroup topology can grow in hopes of avoiding any 563 * anamolies in probing from messing up the lgroup topology 564 * by limiting the accuracy of the latency topology. 565 * 566 * Assume that nodes will at least be configured in a ring, 567 * so limit height of lgroup topology to be less than number 568 * of nodes on a system with 4 or more nodes 569 */ 570 if (lgrp_plat_node_cnt >= 4 && 571 lgrp_topo_ht_limit() == lgrp_topo_ht_limit_default()) 572 (void) lgrp_topo_ht_limit_set(lgrp_plat_node_cnt - 1); 573 } 574 575 /* 576 * Lgroups on Opteron architectures have but a single physical 577 * processor. Tune lgrp_expand_proc_thresh and lgrp_expand_proc_diff 578 * so that lgrp_choose() will spread things out aggressively. 579 */ 580 lgrp_expand_proc_thresh = LGRP_LOADAVG_THREAD_MAX / 2; 581 lgrp_expand_proc_diff = 0; 582 } 583 584 585 /* 586 * Latencies must be within 1/(2**LGRP_LAT_TOLERANCE_SHIFT) of each other to 587 * be considered same 588 */ 589 #define LGRP_LAT_TOLERANCE_SHIFT 4 590 591 int lgrp_plat_probe_lt_shift = LGRP_LAT_TOLERANCE_SHIFT; 592 593 594 /* 595 * Adjust latencies between nodes to be symmetric, normalize latencies between 596 * any nodes that are within some tolerance to be same, and make local 597 * latencies be same 598 */ 599 static void 600 lgrp_plat_latency_adjust(void) 601 { 602 int i; 603 int j; 604 int k; 605 int l; 606 u_longlong_t max; 607 u_longlong_t min; 608 u_longlong_t t; 609 u_longlong_t t1; 610 u_longlong_t t2; 611 const lgrp_config_flag_t cflag = LGRP_CONFIG_LATENCY_CHANGE; 612 int lat_corrected[MAX_NODES][MAX_NODES]; 613 614 /* 615 * Nothing to do when this is an UMA machine 616 */ 617 if (max_mem_nodes == 1) 618 return; 619 620 /* 621 * Make sure that latencies are symmetric between any two nodes 622 * (ie. latency(node0, node1) == latency(node1, node0)) 623 */ 624 for (i = 0; i < lgrp_plat_node_cnt; i++) 625 for (j = 0; j < lgrp_plat_node_cnt; j++) { 626 t1 = lgrp_plat_probe_times[i][j]; 627 t2 = lgrp_plat_probe_times[j][i]; 628 629 if (t1 == 0 || t2 == 0 || t1 == t2) 630 continue; 631 632 /* 633 * Latencies should be same 634 * - Use minimum of two latencies which should be same 635 * - Track suspect probe times not within tolerance of 636 * min value 637 * - Remember how much values are corrected by 638 */ 639 if (t1 > t2) { 640 t = t2; 641 lgrp_plat_probe_errors[i][j] += t1 - t2; 642 if (t1 - t2 > t2 >> lgrp_plat_probe_lt_shift) { 643 lgrp_plat_probe_suspect[i][j]++; 644 lgrp_plat_probe_suspect[j][i]++; 645 } 646 } else if (t2 > t1) { 647 t = t1; 648 lgrp_plat_probe_errors[j][i] += t2 - t1; 649 if (t2 - t1 > t1 >> lgrp_plat_probe_lt_shift) { 650 lgrp_plat_probe_suspect[i][j]++; 651 lgrp_plat_probe_suspect[j][i]++; 652 } 653 } 654 655 lgrp_plat_probe_times[i][j] = 656 lgrp_plat_probe_times[j][i] = t; 657 lgrp_config(cflag, t1, t); 658 lgrp_config(cflag, t2, t); 659 } 660 661 /* 662 * Keep track of which latencies get corrected 663 */ 664 for (i = 0; i < MAX_NODES; i++) 665 for (j = 0; j < MAX_NODES; j++) 666 lat_corrected[i][j] = 0; 667 668 /* 669 * For every two nodes, see whether there is another pair of nodes which 670 * are about the same distance apart and make the latencies be the same 671 * if they are close enough together 672 */ 673 for (i = 0; i < lgrp_plat_node_cnt; i++) 674 for (j = 0; j < lgrp_plat_node_cnt; j++) { 675 /* 676 * Pick one pair of nodes (i, j) 677 * and get latency between them 678 */ 679 t1 = lgrp_plat_probe_times[i][j]; 680 681 /* 682 * Skip this pair of nodes if there isn't a latency 683 * for it yet 684 */ 685 if (t1 == 0) 686 continue; 687 688 for (k = 0; k < lgrp_plat_node_cnt; k++) 689 for (l = 0; l < lgrp_plat_node_cnt; l++) { 690 /* 691 * Pick another pair of nodes (k, l) 692 * not same as (i, j) and get latency 693 * between them 694 */ 695 if (k == i && l == j) 696 continue; 697 698 t2 = lgrp_plat_probe_times[k][l]; 699 700 /* 701 * Skip this pair of nodes if there 702 * isn't a latency for it yet 703 */ 704 705 if (t2 == 0) 706 continue; 707 708 /* 709 * Skip nodes (k, l) if they already 710 * have same latency as (i, j) or 711 * their latency isn't close enough to 712 * be considered/made the same 713 */ 714 if (t1 == t2 || (t1 > t2 && t1 - t2 > 715 t1 >> lgrp_plat_probe_lt_shift) || 716 (t2 > t1 && t2 - t1 > 717 t2 >> lgrp_plat_probe_lt_shift)) 718 continue; 719 720 /* 721 * Make latency(i, j) same as 722 * latency(k, l), try to use latency 723 * that has been adjusted already to get 724 * more consistency (if possible), and 725 * remember which latencies were 726 * adjusted for next time 727 */ 728 if (lat_corrected[i][j]) { 729 t = t1; 730 lgrp_config(cflag, t2, t); 731 t2 = t; 732 } else if (lat_corrected[k][l]) { 733 t = t2; 734 lgrp_config(cflag, t1, t); 735 t1 = t; 736 } else { 737 if (t1 > t2) 738 t = t2; 739 else 740 t = t1; 741 lgrp_config(cflag, t1, t); 742 lgrp_config(cflag, t2, t); 743 t1 = t2 = t; 744 } 745 746 lgrp_plat_probe_times[i][j] = 747 lgrp_plat_probe_times[k][l] = t; 748 749 lat_corrected[i][j] = 750 lat_corrected[k][l] = 1; 751 } 752 } 753 754 /* 755 * Local latencies should be same 756 * - Find min and max local latencies 757 * - Make all local latencies be minimum 758 */ 759 min = -1; 760 max = 0; 761 for (i = 0; i < lgrp_plat_node_cnt; i++) { 762 t = lgrp_plat_probe_times[i][i]; 763 if (t == 0) 764 continue; 765 if (min == -1 || t < min) 766 min = t; 767 if (t > max) 768 max = t; 769 } 770 if (min != max) { 771 for (i = 0; i < lgrp_plat_node_cnt; i++) { 772 int local; 773 774 local = lgrp_plat_probe_times[i][i]; 775 if (local == 0) 776 continue; 777 778 /* 779 * Track suspect probe times that aren't within 780 * tolerance of minimum local latency and how much 781 * probe times are corrected by 782 */ 783 if (local - min > min >> lgrp_plat_probe_lt_shift) 784 lgrp_plat_probe_suspect[i][i]++; 785 786 lgrp_plat_probe_errors[i][i] += local - min; 787 788 /* 789 * Make local latencies be minimum 790 */ 791 lgrp_config(cflag, local, min); 792 lgrp_plat_probe_times[i][i] = min; 793 } 794 } 795 796 /* 797 * Determine max probe time again since just adjusted latencies 798 */ 799 lgrp_plat_probe_time_max = 0; 800 for (i = 0; i < lgrp_plat_node_cnt; i++) 801 for (j = 0; j < lgrp_plat_node_cnt; j++) { 802 t = lgrp_plat_probe_times[i][j]; 803 if (t > lgrp_plat_probe_time_max) 804 lgrp_plat_probe_time_max = t; 805 } 806 } 807 808 809 /* 810 * Verify following about latencies between nodes: 811 * 812 * - Latencies should be symmetric (ie. latency(a, b) == latency(b, a)) 813 * - Local latencies same 814 * - Local < remote 815 * - Number of latencies seen is reasonable 816 * - Number of occurrences of a given latency should be more than 1 817 * 818 * Returns: 819 * 0 Success 820 * -1 Not symmetric 821 * -2 Local latencies not same 822 * -3 Local >= remote 823 * -4 Wrong number of latencies 824 * -5 Not enough occurrences of given latency 825 */ 826 static int 827 lgrp_plat_latency_verify(void) 828 { 829 int i; 830 int j; 831 lgrp_plat_latency_acct_t *l; 832 int probed; 833 u_longlong_t t1; 834 u_longlong_t t2; 835 836 /* 837 * Nothing to do when this is an UMA machine 838 */ 839 if (max_mem_nodes == 1 || lgrp_topo_levels < 2 || 840 lgrp_plat_probe_times[0][0] == 0) 841 return (0); 842 843 /* 844 * Make sure that latencies are symmetric between any two nodes 845 * (ie. latency(node0, node1) == latency(node1, node0)) 846 */ 847 for (i = 0; i < lgrp_plat_node_cnt; i++) 848 for (j = 0; j < lgrp_plat_node_cnt; j++) { 849 t1 = lgrp_plat_probe_times[i][j]; 850 t2 = lgrp_plat_probe_times[j][i]; 851 852 if (t1 == 0 || t2 == 0 || t1 == t2) 853 continue; 854 855 return (-1); 856 } 857 858 /* 859 * Local latencies should be same 860 */ 861 t1 = lgrp_plat_probe_times[0][0]; 862 for (i = 1; i < lgrp_plat_node_cnt; i++) { 863 t2 = lgrp_plat_probe_times[i][i]; 864 if (t2 == 0) 865 continue; 866 867 if (t1 != t2) 868 return (-2); 869 } 870 871 /* 872 * Local latencies should be less than remote 873 */ 874 t1 = lgrp_plat_probe_times[0][0]; 875 for (i = 0; i < lgrp_plat_node_cnt; i++) 876 for (j = 0; j < lgrp_plat_node_cnt; j++) { 877 if (i == j || t2 == 0) 878 continue; 879 880 t2 = lgrp_plat_probe_times[i][j]; 881 if (t1 >= t2) 882 return (-3); 883 } 884 885 /* 886 * Rest of checks are not very useful for machines with less than 887 * 4 nodes (which means less than 3 latencies on Opteron) 888 */ 889 if (lgrp_plat_node_cnt < 4) 890 return (0); 891 892 /* 893 * Need to see whether done probing in order to verify number of 894 * latencies are correct 895 */ 896 probed = 0; 897 for (i = 0; i < lgrp_plat_node_cnt; i++) 898 if (lgrp_plat_probe_times[i][i]) 899 probed++; 900 901 if (probed != lgrp_plat_node_cnt) 902 return (0); 903 904 /* 905 * Determine number of unique latencies seen in probe times, 906 * their values, and number of occurrences of each 907 */ 908 lgrp_plat_probe_nlatencies = 0; 909 bzero(lgrp_plat_probe_lat_acct, 910 MAX_NODES * sizeof (lgrp_plat_latency_acct_t)); 911 for (i = 0; i < lgrp_plat_node_cnt; i++) { 912 for (j = 0; j < lgrp_plat_node_cnt; j++) { 913 int k; 914 915 /* 916 * Look at each probe time 917 */ 918 t1 = lgrp_plat_probe_times[i][j]; 919 if (t1 == 0) 920 continue; 921 922 /* 923 * Account for unique latencies 924 */ 925 for (k = 0; k < lgrp_plat_node_cnt; k++) { 926 l = &lgrp_plat_probe_lat_acct[k]; 927 if (t1 == l->la_value) { 928 /* 929 * Increment number of occurrences 930 * if seen before 931 */ 932 l->la_count++; 933 break; 934 } else if (l->la_value == 0) { 935 /* 936 * Record latency if haven't seen before 937 */ 938 l->la_value = t1; 939 l->la_count++; 940 lgrp_plat_probe_nlatencies++; 941 break; 942 } 943 } 944 } 945 } 946 947 /* 948 * Number of latencies should be relative to number of 949 * nodes in system: 950 * - Same as nodes when nodes <= 2 951 * - Less than nodes when nodes > 2 952 * - Greater than 2 when nodes >= 4 953 */ 954 if ((lgrp_plat_node_cnt <= 2 && 955 lgrp_plat_probe_nlatencies != lgrp_plat_node_cnt) || 956 (lgrp_plat_node_cnt > 2 && 957 lgrp_plat_probe_nlatencies >= lgrp_plat_node_cnt) || 958 (lgrp_plat_node_cnt >= 4 && lgrp_topo_levels >= 3 && 959 lgrp_plat_probe_nlatencies <= 2)) 960 return (-4); 961 962 /* 963 * There should be more than one occurrence of every latency 964 * as long as probing is complete 965 */ 966 for (i = 0; i < lgrp_plat_probe_nlatencies; i++) { 967 l = &lgrp_plat_probe_lat_acct[i]; 968 if (l->la_count <= 1) 969 return (-5); 970 } 971 return (0); 972 } 973 974 975 /* 976 * Set lgroup latencies for 2 level lgroup topology 977 */ 978 static void 979 lgrp_plat_2level_setup(void) 980 { 981 int i; 982 983 if (lgrp_plat_node_cnt >= 4) 984 cmn_err(CE_NOTE, 985 "MPO only optimizing for local and remote\n"); 986 for (i = 0; i < lgrp_plat_node_cnt; i++) { 987 int j; 988 989 for (j = 0; j < lgrp_plat_node_cnt; j++) { 990 if (i == j) 991 lgrp_plat_probe_times[i][j] = 2; 992 else 993 lgrp_plat_probe_times[i][j] = 3; 994 } 995 } 996 lgrp_plat_probe_time_min = 2; 997 lgrp_plat_probe_time_max = 3; 998 lgrp_config(LGRP_CONFIG_FLATTEN, 2, 0); 999 } 1000 1001 1002 /* 1003 * Return time needed to probe from current CPU to memory in given node 1004 */ 1005 static hrtime_t 1006 lgrp_plat_probe_time(int to) 1007 { 1008 caddr_t buf; 1009 uint_t dev; 1010 /* LINTED: set but not used in function */ 1011 volatile uint_t dev_vendor; 1012 hrtime_t elapsed; 1013 hrtime_t end; 1014 int from; 1015 int i; 1016 int ipl; 1017 hrtime_t max; 1018 hrtime_t min; 1019 hrtime_t start; 1020 extern int use_sse_pagecopy; 1021 1022 /* 1023 * Determine ID of node containing current CPU 1024 */ 1025 from = LGRP_PLAT_CPU_TO_NODE(CPU); 1026 1027 /* 1028 * Do common work for probing main memory 1029 */ 1030 if (lgrp_plat_probe_op == LGRP_PLAT_PROBE_PGCPY) { 1031 /* 1032 * Skip probing any nodes without memory and 1033 * set probe time to 0 1034 */ 1035 if (lgrp_plat_probe_memory[to] == NULL) { 1036 lgrp_plat_probe_times[from][to] = 0; 1037 return (0); 1038 } 1039 1040 /* 1041 * Invalidate caches once instead of once every sample 1042 * which should cut cost of probing by a lot 1043 */ 1044 lgrp_plat_flush_cost = gethrtime(); 1045 invalidate_cache(); 1046 lgrp_plat_flush_cost = gethrtime() - lgrp_plat_flush_cost; 1047 lgrp_plat_probe_cost_total += lgrp_plat_flush_cost; 1048 } 1049 1050 /* 1051 * Probe from current CPU to given memory using specified operation 1052 * and take specified number of samples 1053 */ 1054 max = 0; 1055 min = -1; 1056 for (i = 0; i < lgrp_plat_probe_nsamples; i++) { 1057 lgrp_plat_probe_cost = gethrtime(); 1058 1059 /* 1060 * Can't measure probe time if gethrtime() isn't working yet 1061 */ 1062 if (lgrp_plat_probe_cost == 0 && gethrtime() == 0) 1063 return (0); 1064 1065 switch (lgrp_plat_probe_op) { 1066 1067 case LGRP_PLAT_PROBE_PGCPY: 1068 default: 1069 /* 1070 * Measure how long it takes to copy page 1071 * on top of itself 1072 */ 1073 buf = lgrp_plat_probe_memory[to] + (i * PAGESIZE); 1074 1075 kpreempt_disable(); 1076 ipl = splhigh(); 1077 start = gethrtime(); 1078 if (use_sse_pagecopy) 1079 hwblkpagecopy(buf, buf); 1080 else 1081 bcopy(buf, buf, PAGESIZE); 1082 end = gethrtime(); 1083 elapsed = end - start; 1084 splx(ipl); 1085 kpreempt_enable(); 1086 break; 1087 1088 case LGRP_PLAT_PROBE_VENDOR: 1089 /* 1090 * Measure how long it takes to read vendor ID from 1091 * Northbridge 1092 */ 1093 dev = OPT_PCS_DEV_NODE0 + to; 1094 kpreempt_disable(); 1095 ipl = spl8(); 1096 outl(PCI_CONFADD, PCI_CADDR1(0, dev, opt_probe_func, 1097 OPT_PCS_OFF_VENDOR)); 1098 start = gethrtime(); 1099 dev_vendor = inl(PCI_CONFDATA); 1100 end = gethrtime(); 1101 elapsed = end - start; 1102 splx(ipl); 1103 kpreempt_enable(); 1104 break; 1105 } 1106 1107 lgrp_plat_probe_cost = gethrtime() - lgrp_plat_probe_cost; 1108 lgrp_plat_probe_cost_total += lgrp_plat_probe_cost; 1109 1110 if (min == -1 || elapsed < min) 1111 min = elapsed; 1112 if (elapsed > max) 1113 max = elapsed; 1114 } 1115 1116 /* 1117 * Update minimum and maximum probe times between 1118 * these two nodes 1119 */ 1120 if (min < lgrp_plat_probe_min[from][to] || 1121 lgrp_plat_probe_min[from][to] == 0) 1122 lgrp_plat_probe_min[from][to] = min; 1123 1124 if (max > lgrp_plat_probe_max[from][to]) 1125 lgrp_plat_probe_max[from][to] = max; 1126 1127 return (min); 1128 } 1129 1130 1131 /* 1132 * Probe memory in each node from current CPU to determine latency topology 1133 */ 1134 void 1135 lgrp_plat_probe(void) 1136 { 1137 int from; 1138 int i; 1139 hrtime_t probe_time; 1140 int to; 1141 1142 if (max_mem_nodes == 1 || lgrp_topo_ht_limit() <= 2) 1143 return; 1144 1145 /* 1146 * Determine ID of node containing current CPU 1147 */ 1148 from = LGRP_PLAT_CPU_TO_NODE(CPU); 1149 1150 /* 1151 * Don't need to probe if got times already 1152 */ 1153 if (lgrp_plat_probe_times[from][from] != 0) 1154 return; 1155 1156 /* 1157 * Read vendor ID in Northbridge or read and write page(s) 1158 * in each node from current CPU and remember how long it takes, 1159 * so we can build latency topology of machine later. 1160 * This should approximate the memory latency between each node. 1161 */ 1162 for (i = 0; i < lgrp_plat_probe_nrounds; i++) 1163 for (to = 0; to < lgrp_plat_node_cnt; to++) { 1164 /* 1165 * Get probe time and bail out if can't get it yet 1166 */ 1167 probe_time = lgrp_plat_probe_time(to); 1168 if (probe_time == 0) 1169 return; 1170 1171 /* 1172 * Keep lowest probe time as latency between nodes 1173 */ 1174 if (lgrp_plat_probe_times[from][to] == 0 || 1175 probe_time < lgrp_plat_probe_times[from][to]) 1176 lgrp_plat_probe_times[from][to] = probe_time; 1177 1178 /* 1179 * Update overall minimum and maximum probe times 1180 * across all nodes 1181 */ 1182 if (probe_time < lgrp_plat_probe_time_min || 1183 lgrp_plat_probe_time_min == -1) 1184 lgrp_plat_probe_time_min = probe_time; 1185 if (probe_time > lgrp_plat_probe_time_max) 1186 lgrp_plat_probe_time_max = probe_time; 1187 } 1188 1189 /* 1190 * - Fix up latencies such that local latencies are same, 1191 * latency(i, j) == latency(j, i), etc. (if possible) 1192 * 1193 * - Verify that latencies look ok 1194 * 1195 * - Fallback to just optimizing for local and remote if 1196 * latencies didn't look right 1197 */ 1198 lgrp_plat_latency_adjust(); 1199 lgrp_plat_probe_error_code = lgrp_plat_latency_verify(); 1200 if (lgrp_plat_probe_error_code) 1201 lgrp_plat_2level_setup(); 1202 } 1203 1204 1205 /* 1206 * Platform-specific initialization 1207 */ 1208 void 1209 lgrp_plat_main_init(void) 1210 { 1211 int curnode; 1212 int ht_limit; 1213 int i; 1214 1215 /* 1216 * Print a notice that MPO is disabled when memory is interleaved 1217 * across nodes....Would do this when it is discovered, but can't 1218 * because it happens way too early during boot.... 1219 */ 1220 if (lgrp_plat_mem_intrlv) 1221 cmn_err(CE_NOTE, 1222 "MPO disabled because memory is interleaved\n"); 1223 1224 /* 1225 * Don't bother to do any probing if there is only one node or the 1226 * height of the lgroup topology less than or equal to 2 1227 */ 1228 ht_limit = lgrp_topo_ht_limit(); 1229 if (max_mem_nodes == 1 || ht_limit <= 2) { 1230 /* 1231 * Setup lgroup latencies for 2 level lgroup topology 1232 * (ie. local and remote only) if they haven't been set yet 1233 */ 1234 if (ht_limit == 2 && lgrp_plat_probe_time_min == -1 && 1235 lgrp_plat_probe_time_max == 0) 1236 lgrp_plat_2level_setup(); 1237 return; 1238 } 1239 1240 if (lgrp_plat_probe_op == LGRP_PLAT_PROBE_VENDOR) { 1241 /* 1242 * Should have been able to probe from CPU 0 when it was added 1243 * to lgroup hierarchy, but may not have been able to then 1244 * because it happens so early in boot that gethrtime() hasn't 1245 * been initialized. (:-( 1246 */ 1247 curnode = LGRP_PLAT_CPU_TO_NODE(CPU); 1248 if (lgrp_plat_probe_times[curnode][curnode] == 0) 1249 lgrp_plat_probe(); 1250 1251 return; 1252 } 1253 1254 /* 1255 * When probing memory, use one page for every sample to determine 1256 * lgroup topology and taking multiple samples 1257 */ 1258 if (lgrp_plat_probe_memsize == 0) 1259 lgrp_plat_probe_memsize = PAGESIZE * 1260 lgrp_plat_probe_nsamples; 1261 1262 /* 1263 * Map memory in each node needed for probing to determine latency 1264 * topology 1265 */ 1266 for (i = 0; i < lgrp_plat_node_cnt; i++) { 1267 int mnode; 1268 1269 /* 1270 * Skip this node and leave its probe page NULL 1271 * if it doesn't have any memory 1272 */ 1273 mnode = plat_lgrphand_to_mem_node((lgrp_handle_t)i); 1274 if (!mem_node_config[mnode].exists) { 1275 lgrp_plat_probe_memory[i] = NULL; 1276 continue; 1277 } 1278 1279 /* 1280 * Allocate one kernel virtual page 1281 */ 1282 lgrp_plat_probe_memory[i] = vmem_alloc(heap_arena, 1283 lgrp_plat_probe_memsize, VM_NOSLEEP); 1284 if (lgrp_plat_probe_memory[i] == NULL) { 1285 cmn_err(CE_WARN, 1286 "lgrp_plat_main_init: couldn't allocate memory"); 1287 return; 1288 } 1289 1290 /* 1291 * Map virtual page to first page in node 1292 */ 1293 hat_devload(kas.a_hat, lgrp_plat_probe_memory[i], 1294 lgrp_plat_probe_memsize, 1295 lgrp_plat_probe_pfn[i], 1296 PROT_READ | PROT_WRITE | HAT_PLAT_NOCACHE, 1297 HAT_LOAD_NOCONSIST); 1298 } 1299 1300 /* 1301 * Probe from current CPU 1302 */ 1303 lgrp_plat_probe(); 1304 } 1305 1306 /* 1307 * Allocate additional space for an lgroup. 1308 */ 1309 /* ARGSUSED */ 1310 lgrp_t * 1311 lgrp_plat_alloc(lgrp_id_t lgrpid) 1312 { 1313 lgrp_t *lgrp; 1314 1315 lgrp = &lgrp_space[nlgrps_alloc++]; 1316 if (lgrpid >= NLGRP || nlgrps_alloc > NLGRP) 1317 return (NULL); 1318 return (lgrp); 1319 } 1320 1321 /* 1322 * Platform handling for (re)configuration changes 1323 */ 1324 /* ARGSUSED */ 1325 void 1326 lgrp_plat_config(lgrp_config_flag_t flag, uintptr_t arg) 1327 { 1328 } 1329 1330 /* 1331 * Return the platform handle for the lgroup containing the given CPU 1332 */ 1333 /* ARGSUSED */ 1334 lgrp_handle_t 1335 lgrp_plat_cpu_to_hand(processorid_t id) 1336 { 1337 if (lgrp_plat_node_cnt == 1) 1338 return (LGRP_DEFAULT_HANDLE); 1339 1340 return ((lgrp_handle_t)LGRP_PLAT_CPU_TO_NODE(cpu[id])); 1341 } 1342 1343 /* 1344 * Return the platform handle of the lgroup that contains the physical memory 1345 * corresponding to the given page frame number 1346 */ 1347 /* ARGSUSED */ 1348 lgrp_handle_t 1349 lgrp_plat_pfn_to_hand(pfn_t pfn) 1350 { 1351 int mnode; 1352 1353 if (max_mem_nodes == 1) 1354 return (LGRP_DEFAULT_HANDLE); 1355 1356 mnode = plat_pfn_to_mem_node(pfn); 1357 return (MEM_NODE_2_LGRPHAND(mnode)); 1358 } 1359 1360 /* 1361 * Return the maximum number of lgrps supported by the platform. 1362 * Before lgrp topology is known it returns an estimate based on the number of 1363 * nodes. Once topology is known it returns the actual maximim number of lgrps 1364 * created. Since x86 doesn't support dynamic addition of new nodes, this number 1365 * may not grow during system lifetime. 1366 */ 1367 int 1368 lgrp_plat_max_lgrps() 1369 { 1370 return (lgrp_topo_initialized ? 1371 lgrp_alloc_max + 1 : 1372 lgrp_plat_node_cnt * (lgrp_plat_node_cnt - 1) + 1); 1373 } 1374 1375 /* 1376 * Return the number of free, allocatable, or installed 1377 * pages in an lgroup 1378 * This is a copy of the MAX_MEM_NODES == 1 version of the routine 1379 * used when MPO is disabled (i.e. single lgroup) or this is the root lgroup 1380 */ 1381 /* ARGSUSED */ 1382 static pgcnt_t 1383 lgrp_plat_mem_size_default(lgrp_handle_t lgrphand, lgrp_mem_query_t query) 1384 { 1385 struct memlist *mlist; 1386 pgcnt_t npgs = 0; 1387 extern struct memlist *phys_avail; 1388 extern struct memlist *phys_install; 1389 1390 switch (query) { 1391 case LGRP_MEM_SIZE_FREE: 1392 return ((pgcnt_t)freemem); 1393 case LGRP_MEM_SIZE_AVAIL: 1394 memlist_read_lock(); 1395 for (mlist = phys_avail; mlist; mlist = mlist->next) 1396 npgs += btop(mlist->size); 1397 memlist_read_unlock(); 1398 return (npgs); 1399 case LGRP_MEM_SIZE_INSTALL: 1400 memlist_read_lock(); 1401 for (mlist = phys_install; mlist; mlist = mlist->next) 1402 npgs += btop(mlist->size); 1403 memlist_read_unlock(); 1404 return (npgs); 1405 default: 1406 return ((pgcnt_t)0); 1407 } 1408 } 1409 1410 /* 1411 * Return the number of free pages in an lgroup. 1412 * 1413 * For query of LGRP_MEM_SIZE_FREE, return the number of base pagesize 1414 * pages on freelists. For query of LGRP_MEM_SIZE_AVAIL, return the 1415 * number of allocatable base pagesize pages corresponding to the 1416 * lgroup (e.g. do not include page_t's, BOP_ALLOC()'ed memory, ..) 1417 * For query of LGRP_MEM_SIZE_INSTALL, return the amount of physical 1418 * memory installed, regardless of whether or not it's usable. 1419 */ 1420 pgcnt_t 1421 lgrp_plat_mem_size(lgrp_handle_t plathand, lgrp_mem_query_t query) 1422 { 1423 int mnode; 1424 pgcnt_t npgs = (pgcnt_t)0; 1425 extern struct memlist *phys_avail; 1426 extern struct memlist *phys_install; 1427 1428 1429 if (plathand == LGRP_DEFAULT_HANDLE) 1430 return (lgrp_plat_mem_size_default(plathand, query)); 1431 1432 if (plathand != LGRP_NULL_HANDLE) { 1433 mnode = plat_lgrphand_to_mem_node(plathand); 1434 if (mnode >= 0 && mem_node_config[mnode].exists) { 1435 switch (query) { 1436 case LGRP_MEM_SIZE_FREE: 1437 npgs = mem_node_config[mnode].cursize; 1438 break; 1439 case LGRP_MEM_SIZE_AVAIL: 1440 npgs = mem_node_memlist_pages(mnode, 1441 phys_avail); 1442 break; 1443 case LGRP_MEM_SIZE_INSTALL: 1444 npgs = mem_node_memlist_pages(mnode, 1445 phys_install); 1446 break; 1447 default: 1448 break; 1449 } 1450 } 1451 } 1452 return (npgs); 1453 } 1454 1455 /* 1456 * Return latency between "from" and "to" lgroups 1457 * 1458 * This latency number can only be used for relative comparison 1459 * between lgroups on the running system, cannot be used across platforms, 1460 * and may not reflect the actual latency. It is platform and implementation 1461 * specific, so platform gets to decide its value. It would be nice if the 1462 * number was at least proportional to make comparisons more meaningful though. 1463 */ 1464 /* ARGSUSED */ 1465 int 1466 lgrp_plat_latency(lgrp_handle_t from, lgrp_handle_t to) 1467 { 1468 lgrp_handle_t src, dest; 1469 1470 if (max_mem_nodes == 1) 1471 return (0); 1472 1473 /* 1474 * Return max latency for root lgroup 1475 */ 1476 if (from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE) 1477 return (lgrp_plat_probe_time_max); 1478 1479 src = from; 1480 dest = to; 1481 1482 /* 1483 * Return 0 for nodes (lgroup platform handles) out of range 1484 */ 1485 if (src < 0 || src >= MAX_NODES || dest < 0 || dest >= MAX_NODES) 1486 return (0); 1487 1488 /* 1489 * Probe from current CPU if its lgroup latencies haven't been set yet 1490 * and we are trying to get latency from current CPU to some node 1491 */ 1492 if (lgrp_plat_probe_times[src][src] == 0 && 1493 LGRP_PLAT_CPU_TO_NODE(CPU) == src) 1494 lgrp_plat_probe(); 1495 1496 return (lgrp_plat_probe_times[src][dest]); 1497 } 1498 1499 /* 1500 * Return platform handle for root lgroup 1501 */ 1502 lgrp_handle_t 1503 lgrp_plat_root_hand(void) 1504 { 1505 return (LGRP_DEFAULT_HANDLE); 1506 } 1507