1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/pg.h> 44 #include <sys/fp.h> 45 #include <sys/controlregs.h> 46 #include <sys/auxv_386.h> 47 #include <sys/bitmap.h> 48 #include <sys/memnode.h> 49 50 /* 51 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 52 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 53 * them accordingly. For most modern processors, feature detection occurs here 54 * in pass 1. 55 * 56 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 57 * for the boot CPU and does the basic analysis that the early kernel needs. 58 * x86_feature is set based on the return value of cpuid_pass1() of the boot 59 * CPU. 60 * 61 * Pass 1 includes: 62 * 63 * o Determining vendor/model/family/stepping and setting x86_type and 64 * x86_vendor accordingly. 65 * o Processing the feature flags returned by the cpuid instruction while 66 * applying any workarounds or tricks for the specific processor. 67 * o Mapping the feature flags into Solaris feature bits (X86_*). 68 * o Processing extended feature flags if supported by the processor, 69 * again while applying specific processor knowledge. 70 * o Determining the CMT characteristics of the system. 71 * 72 * Pass 1 is done on non-boot CPUs during their initialization and the results 73 * are used only as a meager attempt at ensuring that all processors within the 74 * system support the same features. 75 * 76 * Pass 2 of cpuid feature analysis happens just at the beginning 77 * of startup(). It just copies in and corrects the remainder 78 * of the cpuid data we depend on: standard cpuid functions that we didn't 79 * need for pass1 feature analysis, and extended cpuid functions beyond the 80 * simple feature processing done in pass1. 81 * 82 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 83 * particular kernel memory allocation has been made available. It creates a 84 * readable brand string based on the data collected in the first two passes. 85 * 86 * Pass 4 of cpuid analysis is invoked after post_startup() when all 87 * the support infrastructure for various hardware features has been 88 * initialized. It determines which processor features will be reported 89 * to userland via the aux vector. 90 * 91 * All passes are executed on all CPUs, but only the boot CPU determines what 92 * features the kernel will use. 93 * 94 * Much of the worst junk in this file is for the support of processors 95 * that didn't really implement the cpuid instruction properly. 96 * 97 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 98 * the pass numbers. Accordingly, changes to the pass code may require changes 99 * to the accessor code. 100 */ 101 102 uint_t x86_feature = 0; 103 uint_t x86_vendor = X86_VENDOR_IntelClone; 104 uint_t x86_type = X86_TYPE_OTHER; 105 106 uint_t pentiumpro_bug4046376; 107 uint_t pentiumpro_bug4064495; 108 109 uint_t enable486; 110 111 /* 112 * This set of strings are for processors rumored to support the cpuid 113 * instruction, and is used by locore.s to figure out how to set x86_vendor 114 */ 115 const char CyrixInstead[] = "CyrixInstead"; 116 117 /* 118 * monitor/mwait info. 119 */ 120 struct mwait_info { 121 size_t mon_min; /* min size to avoid missed wakeups */ 122 size_t mon_max; /* size to avoid false wakeups */ 123 uint32_t support; /* processor support of monitor/mwait */ 124 }; 125 126 /* 127 * These constants determine how many of the elements of the 128 * cpuid we cache in the cpuid_info data structure; the 129 * remaining elements are accessible via the cpuid instruction. 130 */ 131 132 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 133 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 134 135 struct cpuid_info { 136 uint_t cpi_pass; /* last pass completed */ 137 /* 138 * standard function information 139 */ 140 uint_t cpi_maxeax; /* fn 0: %eax */ 141 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 142 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 143 144 uint_t cpi_family; /* fn 1: extended family */ 145 uint_t cpi_model; /* fn 1: extended model */ 146 uint_t cpi_step; /* fn 1: stepping */ 147 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 148 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 149 int cpi_clogid; /* fn 1: %ebx: thread # */ 150 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 151 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 152 uint_t cpi_ncache; /* fn 2: number of elements */ 153 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 154 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 155 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 156 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 157 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 158 /* 159 * extended function information 160 */ 161 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 162 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 163 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 164 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 165 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 166 id_t cpi_coreid; 167 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 168 /* Intel: fn 4: %eax[31-26] */ 169 /* 170 * supported feature information 171 */ 172 uint32_t cpi_support[5]; 173 #define STD_EDX_FEATURES 0 174 #define AMD_EDX_FEATURES 1 175 #define TM_EDX_FEATURES 2 176 #define STD_ECX_FEATURES 3 177 #define AMD_ECX_FEATURES 4 178 /* 179 * Synthesized information, where known. 180 */ 181 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 182 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 183 uint32_t cpi_socket; /* Chip package/socket type */ 184 185 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 186 }; 187 188 189 static struct cpuid_info cpuid_info0; 190 191 /* 192 * These bit fields are defined by the Intel Application Note AP-485 193 * "Intel Processor Identification and the CPUID Instruction" 194 */ 195 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 196 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 197 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 198 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 199 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 200 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 201 202 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 203 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 204 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 205 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 206 207 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 208 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 209 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 210 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 211 212 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 213 #define CPI_XMAXEAX_MAX 0x80000100 214 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 215 216 /* 217 * Function 4 (Deterministic Cache Parameters) macros 218 * Defined by Intel Application Note AP-485 219 */ 220 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 221 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 222 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 223 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 224 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 225 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 226 227 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 228 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 229 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 230 231 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 232 233 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 234 235 236 /* 237 * A couple of shorthand macros to identify "later" P6-family chips 238 * like the Pentium M and Core. First, the "older" P6-based stuff 239 * (loosely defined as "pre-Pentium-4"): 240 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 241 */ 242 243 #define IS_LEGACY_P6(cpi) ( \ 244 cpi->cpi_family == 6 && \ 245 (cpi->cpi_model == 1 || \ 246 cpi->cpi_model == 3 || \ 247 cpi->cpi_model == 5 || \ 248 cpi->cpi_model == 6 || \ 249 cpi->cpi_model == 7 || \ 250 cpi->cpi_model == 8 || \ 251 cpi->cpi_model == 0xA || \ 252 cpi->cpi_model == 0xB) \ 253 ) 254 255 /* A "new F6" is everything with family 6 that's not the above */ 256 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 257 258 /* 259 * AMD family 0xf socket types. 260 * First index is 0 for revs B thru E, 1 for F and G. 261 * Second index by (model & 0x3) 262 */ 263 static uint32_t amd_skts[2][4] = { 264 { 265 X86_SOCKET_754, /* 0b00 */ 266 X86_SOCKET_940, /* 0b01 */ 267 X86_SOCKET_754, /* 0b10 */ 268 X86_SOCKET_939 /* 0b11 */ 269 }, 270 { 271 X86_SOCKET_S1g1, /* 0b00 */ 272 X86_SOCKET_F1207, /* 0b01 */ 273 X86_SOCKET_UNKNOWN, /* 0b10 */ 274 X86_SOCKET_AM2 /* 0b11 */ 275 } 276 }; 277 278 /* 279 * Table for mapping AMD Family 0xf model/stepping combination to 280 * chip "revision" and socket type. Only rm_family 0xf is used at the 281 * moment, but AMD family 0x10 will extend the exsiting revision names 282 * so will likely also use this table. 283 * 284 * The first member of this array that matches a given family, extended model 285 * plus model range, and stepping range will be considered a match. 286 */ 287 static const struct amd_rev_mapent { 288 uint_t rm_family; 289 uint_t rm_modello; 290 uint_t rm_modelhi; 291 uint_t rm_steplo; 292 uint_t rm_stephi; 293 uint32_t rm_chiprev; 294 const char *rm_chiprevstr; 295 int rm_sktidx; 296 } amd_revmap[] = { 297 /* 298 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 299 */ 300 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, 301 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, 302 /* 303 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 304 */ 305 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", 0 }, 306 /* 307 * Rev CG is the rest of extended model 0x0 - i.e., everything 308 * but the rev B and C0 combinations covered above. 309 */ 310 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", 0 }, 311 /* 312 * Rev D has extended model 0x1. 313 */ 314 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", 0 }, 315 /* 316 * Rev E has extended model 0x2. 317 * Extended model 0x3 is unused but available to grow into. 318 */ 319 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", 0 }, 320 /* 321 * Rev F has extended models 0x4 and 0x5. 322 */ 323 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", 1 }, 324 /* 325 * Rev G has extended model 0x6. 326 */ 327 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", 1 }, 328 }; 329 330 /* 331 * Info for monitor/mwait idle loop. 332 * 333 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 334 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 335 * 2006. 336 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 337 * Documentation Updates" #33633, Rev 2.05, December 2006. 338 */ 339 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 340 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 341 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 342 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 343 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 344 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 345 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 346 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 347 /* 348 * Number of sub-cstates for a given c-state. 349 */ 350 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 351 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 352 353 static void intel_cpuid_4_cache_info(void *, struct cpuid_info *); 354 355 static void 356 synth_amd_info(struct cpuid_info *cpi) 357 { 358 const struct amd_rev_mapent *rmp; 359 uint_t family, model, step; 360 int i; 361 362 /* 363 * Currently only AMD family 0xf uses these fields. 364 */ 365 if (cpi->cpi_family != 0xf) 366 return; 367 368 family = cpi->cpi_family; 369 model = cpi->cpi_model; 370 step = cpi->cpi_step; 371 372 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); 373 i++, rmp++) { 374 if (family == rmp->rm_family && 375 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 376 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 377 cpi->cpi_chiprev = rmp->rm_chiprev; 378 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; 379 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; 380 return; 381 } 382 } 383 } 384 385 static void 386 synth_info(struct cpuid_info *cpi) 387 { 388 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; 389 cpi->cpi_chiprevstr = "Unknown"; 390 cpi->cpi_socket = X86_SOCKET_UNKNOWN; 391 392 switch (cpi->cpi_vendor) { 393 case X86_VENDOR_AMD: 394 synth_amd_info(cpi); 395 break; 396 397 default: 398 break; 399 400 } 401 } 402 403 /* 404 * Apply up various platform-dependent restrictions where the 405 * underlying platform restrictions mean the CPU can be marked 406 * as less capable than its cpuid instruction would imply. 407 */ 408 409 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 410 411 /* 412 * Some undocumented ways of patching the results of the cpuid 413 * instruction to permit running Solaris 10 on future cpus that 414 * we don't currently support. Could be set to non-zero values 415 * via settings in eeprom. 416 */ 417 418 uint32_t cpuid_feature_ecx_include; 419 uint32_t cpuid_feature_ecx_exclude; 420 uint32_t cpuid_feature_edx_include; 421 uint32_t cpuid_feature_edx_exclude; 422 423 void 424 cpuid_alloc_space(cpu_t *cpu) 425 { 426 /* 427 * By convention, cpu0 is the boot cpu, which is set up 428 * before memory allocation is available. All other cpus get 429 * their cpuid_info struct allocated here. 430 */ 431 ASSERT(cpu->cpu_id != 0); 432 cpu->cpu_m.mcpu_cpi = 433 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 434 } 435 436 void 437 cpuid_free_space(cpu_t *cpu) 438 { 439 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 440 int i; 441 442 ASSERT(cpu->cpu_id != 0); 443 444 /* 445 * Free up any function 4 related dynamic storage 446 */ 447 for (i = 1; i < cpi->cpi_std_4_size; i++) 448 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 449 if (cpi->cpi_std_4_size > 0) 450 kmem_free(cpi->cpi_std_4, 451 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 452 453 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 454 } 455 456 uint_t 457 cpuid_pass1(cpu_t *cpu) 458 { 459 uint32_t mask_ecx, mask_edx; 460 uint_t feature = X86_CPUID; 461 struct cpuid_info *cpi; 462 struct cpuid_regs *cp; 463 int xcpuid; 464 465 466 /* 467 * Space statically allocated for cpu0, ensure pointer is set 468 */ 469 if (cpu->cpu_id == 0) 470 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 471 cpi = cpu->cpu_m.mcpu_cpi; 472 ASSERT(cpi != NULL); 473 cp = &cpi->cpi_std[0]; 474 cp->cp_eax = 0; 475 cpi->cpi_maxeax = __cpuid_insn(cp); 476 { 477 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 478 *iptr++ = cp->cp_ebx; 479 *iptr++ = cp->cp_edx; 480 *iptr++ = cp->cp_ecx; 481 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 482 } 483 484 /* 485 * Map the vendor string to a type code 486 */ 487 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 488 cpi->cpi_vendor = X86_VENDOR_Intel; 489 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 490 cpi->cpi_vendor = X86_VENDOR_AMD; 491 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 492 cpi->cpi_vendor = X86_VENDOR_TM; 493 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 494 /* 495 * CyrixInstead is a variable used by the Cyrix detection code 496 * in locore. 497 */ 498 cpi->cpi_vendor = X86_VENDOR_Cyrix; 499 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 500 cpi->cpi_vendor = X86_VENDOR_UMC; 501 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 502 cpi->cpi_vendor = X86_VENDOR_NexGen; 503 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 504 cpi->cpi_vendor = X86_VENDOR_Centaur; 505 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 506 cpi->cpi_vendor = X86_VENDOR_Rise; 507 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 508 cpi->cpi_vendor = X86_VENDOR_SiS; 509 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 510 cpi->cpi_vendor = X86_VENDOR_NSC; 511 else 512 cpi->cpi_vendor = X86_VENDOR_IntelClone; 513 514 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 515 516 /* 517 * Limit the range in case of weird hardware 518 */ 519 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 520 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 521 if (cpi->cpi_maxeax < 1) 522 goto pass1_done; 523 524 cp = &cpi->cpi_std[1]; 525 cp->cp_eax = 1; 526 (void) __cpuid_insn(cp); 527 528 /* 529 * Extract identifying constants for easy access. 530 */ 531 cpi->cpi_model = CPI_MODEL(cpi); 532 cpi->cpi_family = CPI_FAMILY(cpi); 533 534 if (cpi->cpi_family == 0xf) 535 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 536 537 /* 538 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 539 * Intel, and presumably everyone else, uses model == 0xf, as 540 * one would expect (max value means possible overflow). Sigh. 541 */ 542 543 switch (cpi->cpi_vendor) { 544 case X86_VENDOR_AMD: 545 if (CPI_FAMILY(cpi) == 0xf) 546 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 547 break; 548 default: 549 if (cpi->cpi_model == 0xf) 550 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 551 break; 552 } 553 554 cpi->cpi_step = CPI_STEP(cpi); 555 cpi->cpi_brandid = CPI_BRANDID(cpi); 556 557 /* 558 * *default* assumptions: 559 * - believe %edx feature word 560 * - ignore %ecx feature word 561 * - 32-bit virtual and physical addressing 562 */ 563 mask_edx = 0xffffffff; 564 mask_ecx = 0; 565 566 cpi->cpi_pabits = cpi->cpi_vabits = 32; 567 568 switch (cpi->cpi_vendor) { 569 case X86_VENDOR_Intel: 570 if (cpi->cpi_family == 5) 571 x86_type = X86_TYPE_P5; 572 else if (IS_LEGACY_P6(cpi)) { 573 x86_type = X86_TYPE_P6; 574 pentiumpro_bug4046376 = 1; 575 pentiumpro_bug4064495 = 1; 576 /* 577 * Clear the SEP bit when it was set erroneously 578 */ 579 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 580 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 581 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 582 x86_type = X86_TYPE_P4; 583 /* 584 * We don't currently depend on any of the %ecx 585 * features until Prescott, so we'll only check 586 * this from P4 onwards. We might want to revisit 587 * that idea later. 588 */ 589 mask_ecx = 0xffffffff; 590 } else if (cpi->cpi_family > 0xf) 591 mask_ecx = 0xffffffff; 592 /* 593 * We don't support MONITOR/MWAIT if leaf 5 is not available 594 * to obtain the monitor linesize. 595 */ 596 if (cpi->cpi_maxeax < 5) 597 mask_ecx &= ~CPUID_INTC_ECX_MON; 598 break; 599 case X86_VENDOR_IntelClone: 600 default: 601 break; 602 case X86_VENDOR_AMD: 603 #if defined(OPTERON_ERRATUM_108) 604 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 605 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 606 cpi->cpi_model = 0xc; 607 } else 608 #endif 609 if (cpi->cpi_family == 5) { 610 /* 611 * AMD K5 and K6 612 * 613 * These CPUs have an incomplete implementation 614 * of MCA/MCE which we mask away. 615 */ 616 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 617 618 /* 619 * Model 0 uses the wrong (APIC) bit 620 * to indicate PGE. Fix it here. 621 */ 622 if (cpi->cpi_model == 0) { 623 if (cp->cp_edx & 0x200) { 624 cp->cp_edx &= ~0x200; 625 cp->cp_edx |= CPUID_INTC_EDX_PGE; 626 } 627 } 628 629 /* 630 * Early models had problems w/ MMX; disable. 631 */ 632 if (cpi->cpi_model < 6) 633 mask_edx &= ~CPUID_INTC_EDX_MMX; 634 } 635 636 /* 637 * For newer families, SSE3 and CX16, at least, are valid; 638 * enable all 639 */ 640 if (cpi->cpi_family >= 0xf) 641 mask_ecx = 0xffffffff; 642 /* 643 * We don't support MONITOR/MWAIT if leaf 5 is not available 644 * to obtain the monitor linesize. 645 */ 646 if (cpi->cpi_maxeax < 5) 647 mask_ecx &= ~CPUID_INTC_ECX_MON; 648 break; 649 case X86_VENDOR_TM: 650 /* 651 * workaround the NT workaround in CMS 4.1 652 */ 653 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 654 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 655 cp->cp_edx |= CPUID_INTC_EDX_CX8; 656 break; 657 case X86_VENDOR_Centaur: 658 /* 659 * workaround the NT workarounds again 660 */ 661 if (cpi->cpi_family == 6) 662 cp->cp_edx |= CPUID_INTC_EDX_CX8; 663 break; 664 case X86_VENDOR_Cyrix: 665 /* 666 * We rely heavily on the probing in locore 667 * to actually figure out what parts, if any, 668 * of the Cyrix cpuid instruction to believe. 669 */ 670 switch (x86_type) { 671 case X86_TYPE_CYRIX_486: 672 mask_edx = 0; 673 break; 674 case X86_TYPE_CYRIX_6x86: 675 mask_edx = 0; 676 break; 677 case X86_TYPE_CYRIX_6x86L: 678 mask_edx = 679 CPUID_INTC_EDX_DE | 680 CPUID_INTC_EDX_CX8; 681 break; 682 case X86_TYPE_CYRIX_6x86MX: 683 mask_edx = 684 CPUID_INTC_EDX_DE | 685 CPUID_INTC_EDX_MSR | 686 CPUID_INTC_EDX_CX8 | 687 CPUID_INTC_EDX_PGE | 688 CPUID_INTC_EDX_CMOV | 689 CPUID_INTC_EDX_MMX; 690 break; 691 case X86_TYPE_CYRIX_GXm: 692 mask_edx = 693 CPUID_INTC_EDX_MSR | 694 CPUID_INTC_EDX_CX8 | 695 CPUID_INTC_EDX_CMOV | 696 CPUID_INTC_EDX_MMX; 697 break; 698 case X86_TYPE_CYRIX_MediaGX: 699 break; 700 case X86_TYPE_CYRIX_MII: 701 case X86_TYPE_VIA_CYRIX_III: 702 mask_edx = 703 CPUID_INTC_EDX_DE | 704 CPUID_INTC_EDX_TSC | 705 CPUID_INTC_EDX_MSR | 706 CPUID_INTC_EDX_CX8 | 707 CPUID_INTC_EDX_PGE | 708 CPUID_INTC_EDX_CMOV | 709 CPUID_INTC_EDX_MMX; 710 break; 711 default: 712 break; 713 } 714 break; 715 } 716 717 /* 718 * Now we've figured out the masks that determine 719 * which bits we choose to believe, apply the masks 720 * to the feature words, then map the kernel's view 721 * of these feature words into its feature word. 722 */ 723 cp->cp_edx &= mask_edx; 724 cp->cp_ecx &= mask_ecx; 725 726 /* 727 * apply any platform restrictions (we don't call this 728 * immediately after __cpuid_insn here, because we need the 729 * workarounds applied above first) 730 */ 731 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 732 733 /* 734 * fold in overrides from the "eeprom" mechanism 735 */ 736 cp->cp_edx |= cpuid_feature_edx_include; 737 cp->cp_edx &= ~cpuid_feature_edx_exclude; 738 739 cp->cp_ecx |= cpuid_feature_ecx_include; 740 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 741 742 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 743 feature |= X86_LARGEPAGE; 744 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 745 feature |= X86_TSC; 746 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 747 feature |= X86_MSR; 748 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 749 feature |= X86_MTRR; 750 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 751 feature |= X86_PGE; 752 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 753 feature |= X86_CMOV; 754 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 755 feature |= X86_MMX; 756 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 757 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 758 feature |= X86_MCA; 759 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 760 feature |= X86_PAE; 761 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 762 feature |= X86_CX8; 763 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 764 feature |= X86_CX16; 765 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 766 feature |= X86_PAT; 767 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 768 feature |= X86_SEP; 769 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 770 /* 771 * In our implementation, fxsave/fxrstor 772 * are prerequisites before we'll even 773 * try and do SSE things. 774 */ 775 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 776 feature |= X86_SSE; 777 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 778 feature |= X86_SSE2; 779 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 780 feature |= X86_SSE3; 781 } 782 if (cp->cp_edx & CPUID_INTC_EDX_DE) 783 feature |= X86_DE; 784 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 785 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 786 feature |= X86_MWAIT; 787 } 788 789 if (feature & X86_PAE) 790 cpi->cpi_pabits = 36; 791 792 /* 793 * Hyperthreading configuration is slightly tricky on Intel 794 * and pure clones, and even trickier on AMD. 795 * 796 * (AMD chose to set the HTT bit on their CMP processors, 797 * even though they're not actually hyperthreaded. Thus it 798 * takes a bit more work to figure out what's really going 799 * on ... see the handling of the CMP_LGCY bit below) 800 */ 801 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 802 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 803 if (cpi->cpi_ncpu_per_chip > 1) 804 feature |= X86_HTT; 805 } else { 806 cpi->cpi_ncpu_per_chip = 1; 807 } 808 809 /* 810 * Work on the "extended" feature information, doing 811 * some basic initialization for cpuid_pass2() 812 */ 813 xcpuid = 0; 814 switch (cpi->cpi_vendor) { 815 case X86_VENDOR_Intel: 816 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 817 xcpuid++; 818 break; 819 case X86_VENDOR_AMD: 820 if (cpi->cpi_family > 5 || 821 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 822 xcpuid++; 823 break; 824 case X86_VENDOR_Cyrix: 825 /* 826 * Only these Cyrix CPUs are -known- to support 827 * extended cpuid operations. 828 */ 829 if (x86_type == X86_TYPE_VIA_CYRIX_III || 830 x86_type == X86_TYPE_CYRIX_GXm) 831 xcpuid++; 832 break; 833 case X86_VENDOR_Centaur: 834 case X86_VENDOR_TM: 835 default: 836 xcpuid++; 837 break; 838 } 839 840 if (xcpuid) { 841 cp = &cpi->cpi_extd[0]; 842 cp->cp_eax = 0x80000000; 843 cpi->cpi_xmaxeax = __cpuid_insn(cp); 844 } 845 846 if (cpi->cpi_xmaxeax & 0x80000000) { 847 848 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 849 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 850 851 switch (cpi->cpi_vendor) { 852 case X86_VENDOR_Intel: 853 case X86_VENDOR_AMD: 854 if (cpi->cpi_xmaxeax < 0x80000001) 855 break; 856 cp = &cpi->cpi_extd[1]; 857 cp->cp_eax = 0x80000001; 858 (void) __cpuid_insn(cp); 859 860 if (cpi->cpi_vendor == X86_VENDOR_AMD && 861 cpi->cpi_family == 5 && 862 cpi->cpi_model == 6 && 863 cpi->cpi_step == 6) { 864 /* 865 * K6 model 6 uses bit 10 to indicate SYSC 866 * Later models use bit 11. Fix it here. 867 */ 868 if (cp->cp_edx & 0x400) { 869 cp->cp_edx &= ~0x400; 870 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 871 } 872 } 873 874 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 875 876 /* 877 * Compute the additions to the kernel's feature word. 878 */ 879 if (cp->cp_edx & CPUID_AMD_EDX_NX) 880 feature |= X86_NX; 881 882 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 883 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 884 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 885 feature |= X86_SSE4A; 886 887 /* 888 * If both the HTT and CMP_LGCY bits are set, 889 * then we're not actually HyperThreaded. Read 890 * "AMD CPUID Specification" for more details. 891 */ 892 if (cpi->cpi_vendor == X86_VENDOR_AMD && 893 (feature & X86_HTT) && 894 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 895 feature &= ~X86_HTT; 896 feature |= X86_CMP; 897 } 898 #if defined(__amd64) 899 /* 900 * It's really tricky to support syscall/sysret in 901 * the i386 kernel; we rely on sysenter/sysexit 902 * instead. In the amd64 kernel, things are -way- 903 * better. 904 */ 905 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 906 feature |= X86_ASYSC; 907 908 /* 909 * While we're thinking about system calls, note 910 * that AMD processors don't support sysenter 911 * in long mode at all, so don't try to program them. 912 */ 913 if (x86_vendor == X86_VENDOR_AMD) 914 feature &= ~X86_SEP; 915 #endif 916 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 917 feature |= X86_TSCP; 918 break; 919 default: 920 break; 921 } 922 923 /* 924 * Get CPUID data about processor cores and hyperthreads. 925 */ 926 switch (cpi->cpi_vendor) { 927 case X86_VENDOR_Intel: 928 if (cpi->cpi_maxeax >= 4) { 929 cp = &cpi->cpi_std[4]; 930 cp->cp_eax = 4; 931 cp->cp_ecx = 0; 932 (void) __cpuid_insn(cp); 933 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 934 } 935 /*FALLTHROUGH*/ 936 case X86_VENDOR_AMD: 937 if (cpi->cpi_xmaxeax < 0x80000008) 938 break; 939 cp = &cpi->cpi_extd[8]; 940 cp->cp_eax = 0x80000008; 941 (void) __cpuid_insn(cp); 942 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 943 944 /* 945 * Virtual and physical address limits from 946 * cpuid override previously guessed values. 947 */ 948 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 949 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 950 break; 951 default: 952 break; 953 } 954 955 /* 956 * Derive the number of cores per chip 957 */ 958 switch (cpi->cpi_vendor) { 959 case X86_VENDOR_Intel: 960 if (cpi->cpi_maxeax < 4) { 961 cpi->cpi_ncore_per_chip = 1; 962 break; 963 } else { 964 cpi->cpi_ncore_per_chip = 965 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 966 } 967 break; 968 case X86_VENDOR_AMD: 969 if (cpi->cpi_xmaxeax < 0x80000008) { 970 cpi->cpi_ncore_per_chip = 1; 971 break; 972 } else { 973 cpi->cpi_ncore_per_chip = 974 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 975 } 976 break; 977 default: 978 cpi->cpi_ncore_per_chip = 1; 979 break; 980 } 981 } 982 983 /* 984 * If more than one core, then this processor is CMP. 985 */ 986 if (cpi->cpi_ncore_per_chip > 1) 987 feature |= X86_CMP; 988 989 /* 990 * If the number of cores is the same as the number 991 * of CPUs, then we cannot have HyperThreading. 992 */ 993 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 994 feature &= ~X86_HTT; 995 996 if ((feature & (X86_HTT | X86_CMP)) == 0) { 997 /* 998 * Single-core single-threaded processors. 999 */ 1000 cpi->cpi_chipid = -1; 1001 cpi->cpi_clogid = 0; 1002 cpi->cpi_coreid = cpu->cpu_id; 1003 } else if (cpi->cpi_ncpu_per_chip > 1) { 1004 uint_t i; 1005 uint_t chipid_shift = 0; 1006 uint_t coreid_shift = 0; 1007 uint_t apic_id = CPI_APIC_ID(cpi); 1008 1009 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1010 chipid_shift++; 1011 cpi->cpi_chipid = apic_id >> chipid_shift; 1012 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1013 1014 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1015 if (feature & X86_CMP) { 1016 /* 1017 * Multi-core (and possibly multi-threaded) 1018 * processors. 1019 */ 1020 uint_t ncpu_per_core; 1021 if (cpi->cpi_ncore_per_chip == 1) 1022 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1023 else if (cpi->cpi_ncore_per_chip > 1) 1024 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1025 cpi->cpi_ncore_per_chip; 1026 /* 1027 * 8bit APIC IDs on dual core Pentiums 1028 * look like this: 1029 * 1030 * +-----------------------+------+------+ 1031 * | Physical Package ID | MC | HT | 1032 * +-----------------------+------+------+ 1033 * <------- chipid --------> 1034 * <------- coreid ---------------> 1035 * <--- clogid --> 1036 * 1037 * Where the number of bits necessary to 1038 * represent MC and HT fields together equals 1039 * to the minimum number of bits necessary to 1040 * store the value of cpi->cpi_ncpu_per_chip. 1041 * Of those bits, the MC part uses the number 1042 * of bits necessary to store the value of 1043 * cpi->cpi_ncore_per_chip. 1044 */ 1045 for (i = 1; i < ncpu_per_core; i <<= 1) 1046 coreid_shift++; 1047 cpi->cpi_coreid = apic_id >> coreid_shift; 1048 } else if (feature & X86_HTT) { 1049 /* 1050 * Single-core multi-threaded processors. 1051 */ 1052 cpi->cpi_coreid = cpi->cpi_chipid; 1053 } 1054 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1055 /* 1056 * AMD currently only has dual-core processors with 1057 * single-threaded cores. If they ever release 1058 * multi-threaded processors, then this code 1059 * will have to be updated. 1060 */ 1061 cpi->cpi_coreid = cpu->cpu_id; 1062 } else { 1063 /* 1064 * All other processors are currently 1065 * assumed to have single cores. 1066 */ 1067 cpi->cpi_coreid = cpi->cpi_chipid; 1068 } 1069 } 1070 1071 /* 1072 * Synthesize chip "revision" and socket type 1073 */ 1074 synth_info(cpi); 1075 1076 pass1_done: 1077 cpi->cpi_pass = 1; 1078 return (feature); 1079 } 1080 1081 /* 1082 * Make copies of the cpuid table entries we depend on, in 1083 * part for ease of parsing now, in part so that we have only 1084 * one place to correct any of it, in part for ease of 1085 * later export to userland, and in part so we can look at 1086 * this stuff in a crash dump. 1087 */ 1088 1089 /*ARGSUSED*/ 1090 void 1091 cpuid_pass2(cpu_t *cpu) 1092 { 1093 uint_t n, nmax; 1094 int i; 1095 struct cpuid_regs *cp; 1096 uint8_t *dp; 1097 uint32_t *iptr; 1098 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1099 1100 ASSERT(cpi->cpi_pass == 1); 1101 1102 if (cpi->cpi_maxeax < 1) 1103 goto pass2_done; 1104 1105 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1106 nmax = NMAX_CPI_STD; 1107 /* 1108 * (We already handled n == 0 and n == 1 in pass 1) 1109 */ 1110 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1111 cp->cp_eax = n; 1112 1113 /* 1114 * CPUID function 4 expects %ecx to be initialized 1115 * with an index which indicates which cache to return 1116 * information about. The OS is expected to call function 4 1117 * with %ecx set to 0, 1, 2, ... until it returns with 1118 * EAX[4:0] set to 0, which indicates there are no more 1119 * caches. 1120 * 1121 * Here, populate cpi_std[4] with the information returned by 1122 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1123 * when dynamic memory allocation becomes available. 1124 * 1125 * Note: we need to explicitly initialize %ecx here, since 1126 * function 4 may have been previously invoked. 1127 */ 1128 if (n == 4) 1129 cp->cp_ecx = 0; 1130 1131 (void) __cpuid_insn(cp); 1132 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1133 switch (n) { 1134 case 2: 1135 /* 1136 * "the lower 8 bits of the %eax register 1137 * contain a value that identifies the number 1138 * of times the cpuid [instruction] has to be 1139 * executed to obtain a complete image of the 1140 * processor's caching systems." 1141 * 1142 * How *do* they make this stuff up? 1143 */ 1144 cpi->cpi_ncache = sizeof (*cp) * 1145 BITX(cp->cp_eax, 7, 0); 1146 if (cpi->cpi_ncache == 0) 1147 break; 1148 cpi->cpi_ncache--; /* skip count byte */ 1149 1150 /* 1151 * Well, for now, rather than attempt to implement 1152 * this slightly dubious algorithm, we just look 1153 * at the first 15 .. 1154 */ 1155 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1156 cpi->cpi_ncache = sizeof (*cp) - 1; 1157 1158 dp = cpi->cpi_cacheinfo; 1159 if (BITX(cp->cp_eax, 31, 31) == 0) { 1160 uint8_t *p = (void *)&cp->cp_eax; 1161 for (i = 1; i < 3; i++) 1162 if (p[i] != 0) 1163 *dp++ = p[i]; 1164 } 1165 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1166 uint8_t *p = (void *)&cp->cp_ebx; 1167 for (i = 0; i < 4; i++) 1168 if (p[i] != 0) 1169 *dp++ = p[i]; 1170 } 1171 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1172 uint8_t *p = (void *)&cp->cp_ecx; 1173 for (i = 0; i < 4; i++) 1174 if (p[i] != 0) 1175 *dp++ = p[i]; 1176 } 1177 if (BITX(cp->cp_edx, 31, 31) == 0) { 1178 uint8_t *p = (void *)&cp->cp_edx; 1179 for (i = 0; i < 4; i++) 1180 if (p[i] != 0) 1181 *dp++ = p[i]; 1182 } 1183 break; 1184 1185 case 3: /* Processor serial number, if PSN supported */ 1186 break; 1187 1188 case 4: /* Deterministic cache parameters */ 1189 break; 1190 1191 case 5: /* Monitor/Mwait parameters */ 1192 1193 /* 1194 * check cpi_mwait.support which was set in cpuid_pass1 1195 */ 1196 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1197 break; 1198 1199 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1200 cpi->cpi_mwait.mon_max = (size_t)MWAIT_SIZE_MAX(cpi); 1201 if (MWAIT_EXTENSION(cpi)) { 1202 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1203 if (MWAIT_INT_ENABLE(cpi)) 1204 cpi->cpi_mwait.support |= 1205 MWAIT_ECX_INT_ENABLE; 1206 } 1207 break; 1208 default: 1209 break; 1210 } 1211 } 1212 1213 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1214 goto pass2_done; 1215 1216 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1217 nmax = NMAX_CPI_EXTD; 1218 /* 1219 * Copy the extended properties, fixing them as we go. 1220 * (We already handled n == 0 and n == 1 in pass 1) 1221 */ 1222 iptr = (void *)cpi->cpi_brandstr; 1223 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1224 cp->cp_eax = 0x80000000 + n; 1225 (void) __cpuid_insn(cp); 1226 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1227 switch (n) { 1228 case 2: 1229 case 3: 1230 case 4: 1231 /* 1232 * Extract the brand string 1233 */ 1234 *iptr++ = cp->cp_eax; 1235 *iptr++ = cp->cp_ebx; 1236 *iptr++ = cp->cp_ecx; 1237 *iptr++ = cp->cp_edx; 1238 break; 1239 case 5: 1240 switch (cpi->cpi_vendor) { 1241 case X86_VENDOR_AMD: 1242 /* 1243 * The Athlon and Duron were the first 1244 * parts to report the sizes of the 1245 * TLB for large pages. Before then, 1246 * we don't trust the data. 1247 */ 1248 if (cpi->cpi_family < 6 || 1249 (cpi->cpi_family == 6 && 1250 cpi->cpi_model < 1)) 1251 cp->cp_eax = 0; 1252 break; 1253 default: 1254 break; 1255 } 1256 break; 1257 case 6: 1258 switch (cpi->cpi_vendor) { 1259 case X86_VENDOR_AMD: 1260 /* 1261 * The Athlon and Duron were the first 1262 * AMD parts with L2 TLB's. 1263 * Before then, don't trust the data. 1264 */ 1265 if (cpi->cpi_family < 6 || 1266 cpi->cpi_family == 6 && 1267 cpi->cpi_model < 1) 1268 cp->cp_eax = cp->cp_ebx = 0; 1269 /* 1270 * AMD Duron rev A0 reports L2 1271 * cache size incorrectly as 1K 1272 * when it is really 64K 1273 */ 1274 if (cpi->cpi_family == 6 && 1275 cpi->cpi_model == 3 && 1276 cpi->cpi_step == 0) { 1277 cp->cp_ecx &= 0xffff; 1278 cp->cp_ecx |= 0x400000; 1279 } 1280 break; 1281 case X86_VENDOR_Cyrix: /* VIA C3 */ 1282 /* 1283 * VIA C3 processors are a bit messed 1284 * up w.r.t. encoding cache sizes in %ecx 1285 */ 1286 if (cpi->cpi_family != 6) 1287 break; 1288 /* 1289 * model 7 and 8 were incorrectly encoded 1290 * 1291 * xxx is model 8 really broken? 1292 */ 1293 if (cpi->cpi_model == 7 || 1294 cpi->cpi_model == 8) 1295 cp->cp_ecx = 1296 BITX(cp->cp_ecx, 31, 24) << 16 | 1297 BITX(cp->cp_ecx, 23, 16) << 12 | 1298 BITX(cp->cp_ecx, 15, 8) << 8 | 1299 BITX(cp->cp_ecx, 7, 0); 1300 /* 1301 * model 9 stepping 1 has wrong associativity 1302 */ 1303 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1304 cp->cp_ecx |= 8 << 12; 1305 break; 1306 case X86_VENDOR_Intel: 1307 /* 1308 * Extended L2 Cache features function. 1309 * First appeared on Prescott. 1310 */ 1311 default: 1312 break; 1313 } 1314 break; 1315 default: 1316 break; 1317 } 1318 } 1319 1320 pass2_done: 1321 cpi->cpi_pass = 2; 1322 } 1323 1324 static const char * 1325 intel_cpubrand(const struct cpuid_info *cpi) 1326 { 1327 int i; 1328 1329 if ((x86_feature & X86_CPUID) == 0 || 1330 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1331 return ("i486"); 1332 1333 switch (cpi->cpi_family) { 1334 case 5: 1335 return ("Intel Pentium(r)"); 1336 case 6: 1337 switch (cpi->cpi_model) { 1338 uint_t celeron, xeon; 1339 const struct cpuid_regs *cp; 1340 case 0: 1341 case 1: 1342 case 2: 1343 return ("Intel Pentium(r) Pro"); 1344 case 3: 1345 case 4: 1346 return ("Intel Pentium(r) II"); 1347 case 6: 1348 return ("Intel Celeron(r)"); 1349 case 5: 1350 case 7: 1351 celeron = xeon = 0; 1352 cp = &cpi->cpi_std[2]; /* cache info */ 1353 1354 for (i = 1; i < 3; i++) { 1355 uint_t tmp; 1356 1357 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1358 if (tmp == 0x40) 1359 celeron++; 1360 if (tmp >= 0x44 && tmp <= 0x45) 1361 xeon++; 1362 } 1363 1364 for (i = 0; i < 2; i++) { 1365 uint_t tmp; 1366 1367 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1368 if (tmp == 0x40) 1369 celeron++; 1370 else if (tmp >= 0x44 && tmp <= 0x45) 1371 xeon++; 1372 } 1373 1374 for (i = 0; i < 4; i++) { 1375 uint_t tmp; 1376 1377 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1378 if (tmp == 0x40) 1379 celeron++; 1380 else if (tmp >= 0x44 && tmp <= 0x45) 1381 xeon++; 1382 } 1383 1384 for (i = 0; i < 4; i++) { 1385 uint_t tmp; 1386 1387 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1388 if (tmp == 0x40) 1389 celeron++; 1390 else if (tmp >= 0x44 && tmp <= 0x45) 1391 xeon++; 1392 } 1393 1394 if (celeron) 1395 return ("Intel Celeron(r)"); 1396 if (xeon) 1397 return (cpi->cpi_model == 5 ? 1398 "Intel Pentium(r) II Xeon(tm)" : 1399 "Intel Pentium(r) III Xeon(tm)"); 1400 return (cpi->cpi_model == 5 ? 1401 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1402 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1403 default: 1404 break; 1405 } 1406 default: 1407 break; 1408 } 1409 1410 /* BrandID is present if the field is nonzero */ 1411 if (cpi->cpi_brandid != 0) { 1412 static const struct { 1413 uint_t bt_bid; 1414 const char *bt_str; 1415 } brand_tbl[] = { 1416 { 0x1, "Intel(r) Celeron(r)" }, 1417 { 0x2, "Intel(r) Pentium(r) III" }, 1418 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1419 { 0x4, "Intel(r) Pentium(r) III" }, 1420 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1421 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1422 { 0x8, "Intel(r) Pentium(r) 4" }, 1423 { 0x9, "Intel(r) Pentium(r) 4" }, 1424 { 0xa, "Intel(r) Celeron(r)" }, 1425 { 0xb, "Intel(r) Xeon(tm)" }, 1426 { 0xc, "Intel(r) Xeon(tm) MP" }, 1427 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1428 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1429 { 0x11, "Mobile Genuine Intel(r)" }, 1430 { 0x12, "Intel(r) Celeron(r) M" }, 1431 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1432 { 0x14, "Intel(r) Celeron(r)" }, 1433 { 0x15, "Mobile Genuine Intel(r)" }, 1434 { 0x16, "Intel(r) Pentium(r) M" }, 1435 { 0x17, "Mobile Intel(r) Celeron(r)" } 1436 }; 1437 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1438 uint_t sgn; 1439 1440 sgn = (cpi->cpi_family << 8) | 1441 (cpi->cpi_model << 4) | cpi->cpi_step; 1442 1443 for (i = 0; i < btblmax; i++) 1444 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1445 break; 1446 if (i < btblmax) { 1447 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1448 return ("Intel(r) Celeron(r)"); 1449 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1450 return ("Intel(r) Xeon(tm) MP"); 1451 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1452 return ("Intel(r) Xeon(tm)"); 1453 return (brand_tbl[i].bt_str); 1454 } 1455 } 1456 1457 return (NULL); 1458 } 1459 1460 static const char * 1461 amd_cpubrand(const struct cpuid_info *cpi) 1462 { 1463 if ((x86_feature & X86_CPUID) == 0 || 1464 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1465 return ("i486 compatible"); 1466 1467 switch (cpi->cpi_family) { 1468 case 5: 1469 switch (cpi->cpi_model) { 1470 case 0: 1471 case 1: 1472 case 2: 1473 case 3: 1474 case 4: 1475 case 5: 1476 return ("AMD-K5(r)"); 1477 case 6: 1478 case 7: 1479 return ("AMD-K6(r)"); 1480 case 8: 1481 return ("AMD-K6(r)-2"); 1482 case 9: 1483 return ("AMD-K6(r)-III"); 1484 default: 1485 return ("AMD (family 5)"); 1486 } 1487 case 6: 1488 switch (cpi->cpi_model) { 1489 case 1: 1490 return ("AMD-K7(tm)"); 1491 case 0: 1492 case 2: 1493 case 4: 1494 return ("AMD Athlon(tm)"); 1495 case 3: 1496 case 7: 1497 return ("AMD Duron(tm)"); 1498 case 6: 1499 case 8: 1500 case 10: 1501 /* 1502 * Use the L2 cache size to distinguish 1503 */ 1504 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1505 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1506 default: 1507 return ("AMD (family 6)"); 1508 } 1509 default: 1510 break; 1511 } 1512 1513 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1514 cpi->cpi_brandid != 0) { 1515 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1516 case 3: 1517 return ("AMD Opteron(tm) UP 1xx"); 1518 case 4: 1519 return ("AMD Opteron(tm) DP 2xx"); 1520 case 5: 1521 return ("AMD Opteron(tm) MP 8xx"); 1522 default: 1523 return ("AMD Opteron(tm)"); 1524 } 1525 } 1526 1527 return (NULL); 1528 } 1529 1530 static const char * 1531 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1532 { 1533 if ((x86_feature & X86_CPUID) == 0 || 1534 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1535 type == X86_TYPE_CYRIX_486) 1536 return ("i486 compatible"); 1537 1538 switch (type) { 1539 case X86_TYPE_CYRIX_6x86: 1540 return ("Cyrix 6x86"); 1541 case X86_TYPE_CYRIX_6x86L: 1542 return ("Cyrix 6x86L"); 1543 case X86_TYPE_CYRIX_6x86MX: 1544 return ("Cyrix 6x86MX"); 1545 case X86_TYPE_CYRIX_GXm: 1546 return ("Cyrix GXm"); 1547 case X86_TYPE_CYRIX_MediaGX: 1548 return ("Cyrix MediaGX"); 1549 case X86_TYPE_CYRIX_MII: 1550 return ("Cyrix M2"); 1551 case X86_TYPE_VIA_CYRIX_III: 1552 return ("VIA Cyrix M3"); 1553 default: 1554 /* 1555 * Have another wild guess .. 1556 */ 1557 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1558 return ("Cyrix 5x86"); 1559 else if (cpi->cpi_family == 5) { 1560 switch (cpi->cpi_model) { 1561 case 2: 1562 return ("Cyrix 6x86"); /* Cyrix M1 */ 1563 case 4: 1564 return ("Cyrix MediaGX"); 1565 default: 1566 break; 1567 } 1568 } else if (cpi->cpi_family == 6) { 1569 switch (cpi->cpi_model) { 1570 case 0: 1571 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1572 case 5: 1573 case 6: 1574 case 7: 1575 case 8: 1576 case 9: 1577 return ("VIA C3"); 1578 default: 1579 break; 1580 } 1581 } 1582 break; 1583 } 1584 return (NULL); 1585 } 1586 1587 /* 1588 * This only gets called in the case that the CPU extended 1589 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1590 * aren't available, or contain null bytes for some reason. 1591 */ 1592 static void 1593 fabricate_brandstr(struct cpuid_info *cpi) 1594 { 1595 const char *brand = NULL; 1596 1597 switch (cpi->cpi_vendor) { 1598 case X86_VENDOR_Intel: 1599 brand = intel_cpubrand(cpi); 1600 break; 1601 case X86_VENDOR_AMD: 1602 brand = amd_cpubrand(cpi); 1603 break; 1604 case X86_VENDOR_Cyrix: 1605 brand = cyrix_cpubrand(cpi, x86_type); 1606 break; 1607 case X86_VENDOR_NexGen: 1608 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1609 brand = "NexGen Nx586"; 1610 break; 1611 case X86_VENDOR_Centaur: 1612 if (cpi->cpi_family == 5) 1613 switch (cpi->cpi_model) { 1614 case 4: 1615 brand = "Centaur C6"; 1616 break; 1617 case 8: 1618 brand = "Centaur C2"; 1619 break; 1620 case 9: 1621 brand = "Centaur C3"; 1622 break; 1623 default: 1624 break; 1625 } 1626 break; 1627 case X86_VENDOR_Rise: 1628 if (cpi->cpi_family == 5 && 1629 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1630 brand = "Rise mP6"; 1631 break; 1632 case X86_VENDOR_SiS: 1633 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1634 brand = "SiS 55x"; 1635 break; 1636 case X86_VENDOR_TM: 1637 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1638 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1639 break; 1640 case X86_VENDOR_NSC: 1641 case X86_VENDOR_UMC: 1642 default: 1643 break; 1644 } 1645 if (brand) { 1646 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1647 return; 1648 } 1649 1650 /* 1651 * If all else fails ... 1652 */ 1653 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1654 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1655 cpi->cpi_model, cpi->cpi_step); 1656 } 1657 1658 /* 1659 * This routine is called just after kernel memory allocation 1660 * becomes available on cpu0, and as part of mp_startup() on 1661 * the other cpus. 1662 * 1663 * Fixup the brand string, and collect any information from cpuid 1664 * that requires dynamicically allocated storage to represent. 1665 */ 1666 /*ARGSUSED*/ 1667 void 1668 cpuid_pass3(cpu_t *cpu) 1669 { 1670 int i, max, shft, level, size; 1671 struct cpuid_regs regs; 1672 struct cpuid_regs *cp; 1673 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1674 1675 ASSERT(cpi->cpi_pass == 2); 1676 1677 /* 1678 * Function 4: Deterministic cache parameters 1679 * 1680 * Take this opportunity to detect the number of threads 1681 * sharing the last level cache, and construct a corresponding 1682 * cache id. The respective cpuid_info members are initialized 1683 * to the default case of "no last level cache sharing". 1684 */ 1685 cpi->cpi_ncpu_shr_last_cache = 1; 1686 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1687 1688 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1689 1690 /* 1691 * Find the # of elements (size) returned by fn 4, and along 1692 * the way detect last level cache sharing details. 1693 */ 1694 bzero(®s, sizeof (regs)); 1695 cp = ®s; 1696 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1697 cp->cp_eax = 4; 1698 cp->cp_ecx = i; 1699 1700 (void) __cpuid_insn(cp); 1701 1702 if (CPI_CACHE_TYPE(cp) == 0) 1703 break; 1704 level = CPI_CACHE_LVL(cp); 1705 if (level > max) { 1706 max = level; 1707 cpi->cpi_ncpu_shr_last_cache = 1708 CPI_NTHR_SHR_CACHE(cp) + 1; 1709 } 1710 } 1711 cpi->cpi_std_4_size = size = i; 1712 1713 /* 1714 * Allocate the cpi_std_4 array. The first element 1715 * references the regs for fn 4, %ecx == 0, which 1716 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1717 */ 1718 if (size > 0) { 1719 cpi->cpi_std_4 = 1720 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1721 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1722 1723 /* 1724 * Allocate storage to hold the additional regs 1725 * for function 4, %ecx == 1 .. cpi_std_4_size. 1726 * 1727 * The regs for fn 4, %ecx == 0 has already 1728 * been allocated as indicated above. 1729 */ 1730 for (i = 1; i < size; i++) { 1731 cp = cpi->cpi_std_4[i] = 1732 kmem_zalloc(sizeof (regs), KM_SLEEP); 1733 cp->cp_eax = 4; 1734 cp->cp_ecx = i; 1735 1736 (void) __cpuid_insn(cp); 1737 } 1738 } 1739 /* 1740 * Determine the number of bits needed to represent 1741 * the number of CPUs sharing the last level cache. 1742 * 1743 * Shift off that number of bits from the APIC id to 1744 * derive the cache id. 1745 */ 1746 shft = 0; 1747 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1748 shft++; 1749 cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft; 1750 } 1751 1752 /* 1753 * Now fixup the brand string 1754 */ 1755 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1756 fabricate_brandstr(cpi); 1757 } else { 1758 1759 /* 1760 * If we successfully extracted a brand string from the cpuid 1761 * instruction, clean it up by removing leading spaces and 1762 * similar junk. 1763 */ 1764 if (cpi->cpi_brandstr[0]) { 1765 size_t maxlen = sizeof (cpi->cpi_brandstr); 1766 char *src, *dst; 1767 1768 dst = src = (char *)cpi->cpi_brandstr; 1769 src[maxlen - 1] = '\0'; 1770 /* 1771 * strip leading spaces 1772 */ 1773 while (*src == ' ') 1774 src++; 1775 /* 1776 * Remove any 'Genuine' or "Authentic" prefixes 1777 */ 1778 if (strncmp(src, "Genuine ", 8) == 0) 1779 src += 8; 1780 if (strncmp(src, "Authentic ", 10) == 0) 1781 src += 10; 1782 1783 /* 1784 * Now do an in-place copy. 1785 * Map (R) to (r) and (TM) to (tm). 1786 * The era of teletypes is long gone, and there's 1787 * -really- no need to shout. 1788 */ 1789 while (*src != '\0') { 1790 if (src[0] == '(') { 1791 if (strncmp(src + 1, "R)", 2) == 0) { 1792 (void) strncpy(dst, "(r)", 3); 1793 src += 3; 1794 dst += 3; 1795 continue; 1796 } 1797 if (strncmp(src + 1, "TM)", 3) == 0) { 1798 (void) strncpy(dst, "(tm)", 4); 1799 src += 4; 1800 dst += 4; 1801 continue; 1802 } 1803 } 1804 *dst++ = *src++; 1805 } 1806 *dst = '\0'; 1807 1808 /* 1809 * Finally, remove any trailing spaces 1810 */ 1811 while (--dst > cpi->cpi_brandstr) 1812 if (*dst == ' ') 1813 *dst = '\0'; 1814 else 1815 break; 1816 } else 1817 fabricate_brandstr(cpi); 1818 } 1819 cpi->cpi_pass = 3; 1820 } 1821 1822 /* 1823 * This routine is called out of bind_hwcap() much later in the life 1824 * of the kernel (post_startup()). The job of this routine is to resolve 1825 * the hardware feature support and kernel support for those features into 1826 * what we're actually going to tell applications via the aux vector. 1827 */ 1828 uint_t 1829 cpuid_pass4(cpu_t *cpu) 1830 { 1831 struct cpuid_info *cpi; 1832 uint_t hwcap_flags = 0; 1833 1834 if (cpu == NULL) 1835 cpu = CPU; 1836 cpi = cpu->cpu_m.mcpu_cpi; 1837 1838 ASSERT(cpi->cpi_pass == 3); 1839 1840 if (cpi->cpi_maxeax >= 1) { 1841 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1842 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1843 1844 *edx = CPI_FEATURES_EDX(cpi); 1845 *ecx = CPI_FEATURES_ECX(cpi); 1846 1847 /* 1848 * [these require explicit kernel support] 1849 */ 1850 if ((x86_feature & X86_SEP) == 0) 1851 *edx &= ~CPUID_INTC_EDX_SEP; 1852 1853 if ((x86_feature & X86_SSE) == 0) 1854 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 1855 if ((x86_feature & X86_SSE2) == 0) 1856 *edx &= ~CPUID_INTC_EDX_SSE2; 1857 1858 if ((x86_feature & X86_HTT) == 0) 1859 *edx &= ~CPUID_INTC_EDX_HTT; 1860 1861 if ((x86_feature & X86_SSE3) == 0) 1862 *ecx &= ~CPUID_INTC_ECX_SSE3; 1863 1864 /* 1865 * [no explicit support required beyond x87 fp context] 1866 */ 1867 if (!fpu_exists) 1868 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 1869 1870 /* 1871 * Now map the supported feature vector to things that we 1872 * think userland will care about. 1873 */ 1874 if (*edx & CPUID_INTC_EDX_SEP) 1875 hwcap_flags |= AV_386_SEP; 1876 if (*edx & CPUID_INTC_EDX_SSE) 1877 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 1878 if (*edx & CPUID_INTC_EDX_SSE2) 1879 hwcap_flags |= AV_386_SSE2; 1880 if (*ecx & CPUID_INTC_ECX_SSE3) 1881 hwcap_flags |= AV_386_SSE3; 1882 if (*ecx & CPUID_INTC_ECX_POPCNT) 1883 hwcap_flags |= AV_386_POPCNT; 1884 if (*edx & CPUID_INTC_EDX_FPU) 1885 hwcap_flags |= AV_386_FPU; 1886 if (*edx & CPUID_INTC_EDX_MMX) 1887 hwcap_flags |= AV_386_MMX; 1888 1889 if (*edx & CPUID_INTC_EDX_TSC) 1890 hwcap_flags |= AV_386_TSC; 1891 if (*edx & CPUID_INTC_EDX_CX8) 1892 hwcap_flags |= AV_386_CX8; 1893 if (*edx & CPUID_INTC_EDX_CMOV) 1894 hwcap_flags |= AV_386_CMOV; 1895 if (*ecx & CPUID_INTC_ECX_MON) 1896 hwcap_flags |= AV_386_MON; 1897 if (*ecx & CPUID_INTC_ECX_CX16) 1898 hwcap_flags |= AV_386_CX16; 1899 } 1900 1901 if (x86_feature & X86_HTT) 1902 hwcap_flags |= AV_386_PAUSE; 1903 1904 if (cpi->cpi_xmaxeax < 0x80000001) 1905 goto pass4_done; 1906 1907 switch (cpi->cpi_vendor) { 1908 struct cpuid_regs cp; 1909 uint32_t *edx, *ecx; 1910 1911 case X86_VENDOR_Intel: 1912 /* 1913 * Seems like Intel duplicated what we necessary 1914 * here to make the initial crop of 64-bit OS's work. 1915 * Hopefully, those are the only "extended" bits 1916 * they'll add. 1917 */ 1918 /*FALLTHROUGH*/ 1919 1920 case X86_VENDOR_AMD: 1921 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 1922 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 1923 1924 *edx = CPI_FEATURES_XTD_EDX(cpi); 1925 *ecx = CPI_FEATURES_XTD_ECX(cpi); 1926 1927 /* 1928 * [these features require explicit kernel support] 1929 */ 1930 switch (cpi->cpi_vendor) { 1931 case X86_VENDOR_Intel: 1932 break; 1933 1934 case X86_VENDOR_AMD: 1935 if ((x86_feature & X86_TSCP) == 0) 1936 *edx &= ~CPUID_AMD_EDX_TSCP; 1937 if ((x86_feature & X86_SSE4A) == 0) 1938 *ecx &= ~CPUID_AMD_ECX_SSE4A; 1939 break; 1940 1941 default: 1942 break; 1943 } 1944 1945 /* 1946 * [no explicit support required beyond 1947 * x87 fp context and exception handlers] 1948 */ 1949 if (!fpu_exists) 1950 *edx &= ~(CPUID_AMD_EDX_MMXamd | 1951 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 1952 1953 if ((x86_feature & X86_NX) == 0) 1954 *edx &= ~CPUID_AMD_EDX_NX; 1955 #if !defined(__amd64) 1956 *edx &= ~CPUID_AMD_EDX_LM; 1957 #endif 1958 /* 1959 * Now map the supported feature vector to 1960 * things that we think userland will care about. 1961 */ 1962 #if defined(__amd64) 1963 if (*edx & CPUID_AMD_EDX_SYSC) 1964 hwcap_flags |= AV_386_AMD_SYSC; 1965 #endif 1966 if (*edx & CPUID_AMD_EDX_MMXamd) 1967 hwcap_flags |= AV_386_AMD_MMX; 1968 if (*edx & CPUID_AMD_EDX_3DNow) 1969 hwcap_flags |= AV_386_AMD_3DNow; 1970 if (*edx & CPUID_AMD_EDX_3DNowx) 1971 hwcap_flags |= AV_386_AMD_3DNowx; 1972 1973 switch (cpi->cpi_vendor) { 1974 case X86_VENDOR_AMD: 1975 if (*edx & CPUID_AMD_EDX_TSCP) 1976 hwcap_flags |= AV_386_TSCP; 1977 if (*ecx & CPUID_AMD_ECX_AHF64) 1978 hwcap_flags |= AV_386_AHF; 1979 if (*ecx & CPUID_AMD_ECX_SSE4A) 1980 hwcap_flags |= AV_386_AMD_SSE4A; 1981 if (*ecx & CPUID_AMD_ECX_LZCNT) 1982 hwcap_flags |= AV_386_AMD_LZCNT; 1983 break; 1984 1985 case X86_VENDOR_Intel: 1986 /* 1987 * Aarrgh. 1988 * Intel uses a different bit in the same word. 1989 */ 1990 if (*ecx & CPUID_INTC_ECX_AHF64) 1991 hwcap_flags |= AV_386_AHF; 1992 break; 1993 1994 default: 1995 break; 1996 } 1997 break; 1998 1999 case X86_VENDOR_TM: 2000 cp.cp_eax = 0x80860001; 2001 (void) __cpuid_insn(&cp); 2002 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2003 break; 2004 2005 default: 2006 break; 2007 } 2008 2009 pass4_done: 2010 cpi->cpi_pass = 4; 2011 return (hwcap_flags); 2012 } 2013 2014 2015 /* 2016 * Simulate the cpuid instruction using the data we previously 2017 * captured about this CPU. We try our best to return the truth 2018 * about the hardware, independently of kernel support. 2019 */ 2020 uint32_t 2021 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2022 { 2023 struct cpuid_info *cpi; 2024 struct cpuid_regs *xcp; 2025 2026 if (cpu == NULL) 2027 cpu = CPU; 2028 cpi = cpu->cpu_m.mcpu_cpi; 2029 2030 ASSERT(cpuid_checkpass(cpu, 3)); 2031 2032 /* 2033 * CPUID data is cached in two separate places: cpi_std for standard 2034 * CPUID functions, and cpi_extd for extended CPUID functions. 2035 */ 2036 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2037 xcp = &cpi->cpi_std[cp->cp_eax]; 2038 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2039 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2040 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2041 else 2042 /* 2043 * The caller is asking for data from an input parameter which 2044 * the kernel has not cached. In this case we go fetch from 2045 * the hardware and return the data directly to the user. 2046 */ 2047 return (__cpuid_insn(cp)); 2048 2049 cp->cp_eax = xcp->cp_eax; 2050 cp->cp_ebx = xcp->cp_ebx; 2051 cp->cp_ecx = xcp->cp_ecx; 2052 cp->cp_edx = xcp->cp_edx; 2053 return (cp->cp_eax); 2054 } 2055 2056 int 2057 cpuid_checkpass(cpu_t *cpu, int pass) 2058 { 2059 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2060 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2061 } 2062 2063 int 2064 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2065 { 2066 ASSERT(cpuid_checkpass(cpu, 3)); 2067 2068 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2069 } 2070 2071 int 2072 cpuid_is_cmt(cpu_t *cpu) 2073 { 2074 if (cpu == NULL) 2075 cpu = CPU; 2076 2077 ASSERT(cpuid_checkpass(cpu, 1)); 2078 2079 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2080 } 2081 2082 /* 2083 * AMD and Intel both implement the 64-bit variant of the syscall 2084 * instruction (syscallq), so if there's -any- support for syscall, 2085 * cpuid currently says "yes, we support this". 2086 * 2087 * However, Intel decided to -not- implement the 32-bit variant of the 2088 * syscall instruction, so we provide a predicate to allow our caller 2089 * to test that subtlety here. 2090 */ 2091 /*ARGSUSED*/ 2092 int 2093 cpuid_syscall32_insn(cpu_t *cpu) 2094 { 2095 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2096 2097 if (cpu == NULL) 2098 cpu = CPU; 2099 2100 /*CSTYLED*/ 2101 { 2102 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2103 2104 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2105 cpi->cpi_xmaxeax >= 0x80000001 && 2106 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2107 return (1); 2108 } 2109 return (0); 2110 } 2111 2112 int 2113 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2114 { 2115 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2116 2117 static const char fmt[] = 2118 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2119 static const char fmt_ht[] = 2120 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2121 2122 ASSERT(cpuid_checkpass(cpu, 1)); 2123 2124 if (cpuid_is_cmt(cpu)) 2125 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2126 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2127 cpi->cpi_family, cpi->cpi_model, 2128 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2129 return (snprintf(s, n, fmt, 2130 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2131 cpi->cpi_family, cpi->cpi_model, 2132 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2133 } 2134 2135 const char * 2136 cpuid_getvendorstr(cpu_t *cpu) 2137 { 2138 ASSERT(cpuid_checkpass(cpu, 1)); 2139 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2140 } 2141 2142 uint_t 2143 cpuid_getvendor(cpu_t *cpu) 2144 { 2145 ASSERT(cpuid_checkpass(cpu, 1)); 2146 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2147 } 2148 2149 uint_t 2150 cpuid_getfamily(cpu_t *cpu) 2151 { 2152 ASSERT(cpuid_checkpass(cpu, 1)); 2153 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2154 } 2155 2156 uint_t 2157 cpuid_getmodel(cpu_t *cpu) 2158 { 2159 ASSERT(cpuid_checkpass(cpu, 1)); 2160 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2161 } 2162 2163 uint_t 2164 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2165 { 2166 ASSERT(cpuid_checkpass(cpu, 1)); 2167 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2168 } 2169 2170 uint_t 2171 cpuid_get_ncore_per_chip(cpu_t *cpu) 2172 { 2173 ASSERT(cpuid_checkpass(cpu, 1)); 2174 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2175 } 2176 2177 uint_t 2178 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2179 { 2180 ASSERT(cpuid_checkpass(cpu, 2)); 2181 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2182 } 2183 2184 id_t 2185 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2186 { 2187 ASSERT(cpuid_checkpass(cpu, 2)); 2188 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2189 } 2190 2191 uint_t 2192 cpuid_getstep(cpu_t *cpu) 2193 { 2194 ASSERT(cpuid_checkpass(cpu, 1)); 2195 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2196 } 2197 2198 uint_t 2199 cpuid_getsig(struct cpu *cpu) 2200 { 2201 ASSERT(cpuid_checkpass(cpu, 1)); 2202 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2203 } 2204 2205 uint32_t 2206 cpuid_getchiprev(struct cpu *cpu) 2207 { 2208 ASSERT(cpuid_checkpass(cpu, 1)); 2209 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2210 } 2211 2212 const char * 2213 cpuid_getchiprevstr(struct cpu *cpu) 2214 { 2215 ASSERT(cpuid_checkpass(cpu, 1)); 2216 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2217 } 2218 2219 uint32_t 2220 cpuid_getsockettype(struct cpu *cpu) 2221 { 2222 ASSERT(cpuid_checkpass(cpu, 1)); 2223 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2224 } 2225 2226 int 2227 cpuid_get_chipid(cpu_t *cpu) 2228 { 2229 ASSERT(cpuid_checkpass(cpu, 1)); 2230 2231 if (cpuid_is_cmt(cpu)) 2232 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2233 return (cpu->cpu_id); 2234 } 2235 2236 id_t 2237 cpuid_get_coreid(cpu_t *cpu) 2238 { 2239 ASSERT(cpuid_checkpass(cpu, 1)); 2240 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2241 } 2242 2243 int 2244 cpuid_get_clogid(cpu_t *cpu) 2245 { 2246 ASSERT(cpuid_checkpass(cpu, 1)); 2247 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2248 } 2249 2250 void 2251 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2252 { 2253 struct cpuid_info *cpi; 2254 2255 if (cpu == NULL) 2256 cpu = CPU; 2257 cpi = cpu->cpu_m.mcpu_cpi; 2258 2259 ASSERT(cpuid_checkpass(cpu, 1)); 2260 2261 if (pabits) 2262 *pabits = cpi->cpi_pabits; 2263 if (vabits) 2264 *vabits = cpi->cpi_vabits; 2265 } 2266 2267 /* 2268 * Returns the number of data TLB entries for a corresponding 2269 * pagesize. If it can't be computed, or isn't known, the 2270 * routine returns zero. If you ask about an architecturally 2271 * impossible pagesize, the routine will panic (so that the 2272 * hat implementor knows that things are inconsistent.) 2273 */ 2274 uint_t 2275 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2276 { 2277 struct cpuid_info *cpi; 2278 uint_t dtlb_nent = 0; 2279 2280 if (cpu == NULL) 2281 cpu = CPU; 2282 cpi = cpu->cpu_m.mcpu_cpi; 2283 2284 ASSERT(cpuid_checkpass(cpu, 1)); 2285 2286 /* 2287 * Check the L2 TLB info 2288 */ 2289 if (cpi->cpi_xmaxeax >= 0x80000006) { 2290 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2291 2292 switch (pagesize) { 2293 2294 case 4 * 1024: 2295 /* 2296 * All zero in the top 16 bits of the register 2297 * indicates a unified TLB. Size is in low 16 bits. 2298 */ 2299 if ((cp->cp_ebx & 0xffff0000) == 0) 2300 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2301 else 2302 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2303 break; 2304 2305 case 2 * 1024 * 1024: 2306 if ((cp->cp_eax & 0xffff0000) == 0) 2307 dtlb_nent = cp->cp_eax & 0x0000ffff; 2308 else 2309 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2310 break; 2311 2312 default: 2313 panic("unknown L2 pagesize"); 2314 /*NOTREACHED*/ 2315 } 2316 } 2317 2318 if (dtlb_nent != 0) 2319 return (dtlb_nent); 2320 2321 /* 2322 * No L2 TLB support for this size, try L1. 2323 */ 2324 if (cpi->cpi_xmaxeax >= 0x80000005) { 2325 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2326 2327 switch (pagesize) { 2328 case 4 * 1024: 2329 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2330 break; 2331 case 2 * 1024 * 1024: 2332 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2333 break; 2334 default: 2335 panic("unknown L1 d-TLB pagesize"); 2336 /*NOTREACHED*/ 2337 } 2338 } 2339 2340 return (dtlb_nent); 2341 } 2342 2343 /* 2344 * Return 0 if the erratum is not present or not applicable, positive 2345 * if it is, and negative if the status of the erratum is unknown. 2346 * 2347 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2348 * Processors" #25759, Rev 3.57, August 2005 2349 */ 2350 int 2351 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2352 { 2353 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2354 uint_t eax; 2355 2356 /* 2357 * Bail out if this CPU isn't an AMD CPU, or if it's 2358 * a legacy (32-bit) AMD CPU. 2359 */ 2360 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2361 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2362 cpi->cpi_family == 6) 2363 2364 return (0); 2365 2366 eax = cpi->cpi_std[1].cp_eax; 2367 2368 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2369 #define SH_B3(eax) (eax == 0xf51) 2370 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2371 2372 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2373 2374 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2375 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2376 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2377 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2378 2379 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2380 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2381 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2382 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2383 2384 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2385 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2386 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2387 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2388 #define BH_E4(eax) (eax == 0x20fb1) 2389 #define SH_E5(eax) (eax == 0x20f42) 2390 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2391 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2392 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2393 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2394 DH_E6(eax) || JH_E6(eax)) 2395 2396 switch (erratum) { 2397 case 1: 2398 return (cpi->cpi_family < 0x10); 2399 case 51: /* what does the asterisk mean? */ 2400 return (B(eax) || SH_C0(eax) || CG(eax)); 2401 case 52: 2402 return (B(eax)); 2403 case 57: 2404 return (cpi->cpi_family <= 0x10); 2405 case 58: 2406 return (B(eax)); 2407 case 60: 2408 return (cpi->cpi_family <= 0x10); 2409 case 61: 2410 case 62: 2411 case 63: 2412 case 64: 2413 case 65: 2414 case 66: 2415 case 68: 2416 case 69: 2417 case 70: 2418 case 71: 2419 return (B(eax)); 2420 case 72: 2421 return (SH_B0(eax)); 2422 case 74: 2423 return (B(eax)); 2424 case 75: 2425 return (cpi->cpi_family < 0x10); 2426 case 76: 2427 return (B(eax)); 2428 case 77: 2429 return (cpi->cpi_family <= 0x10); 2430 case 78: 2431 return (B(eax) || SH_C0(eax)); 2432 case 79: 2433 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2434 case 80: 2435 case 81: 2436 case 82: 2437 return (B(eax)); 2438 case 83: 2439 return (B(eax) || SH_C0(eax) || CG(eax)); 2440 case 85: 2441 return (cpi->cpi_family < 0x10); 2442 case 86: 2443 return (SH_C0(eax) || CG(eax)); 2444 case 88: 2445 #if !defined(__amd64) 2446 return (0); 2447 #else 2448 return (B(eax) || SH_C0(eax)); 2449 #endif 2450 case 89: 2451 return (cpi->cpi_family < 0x10); 2452 case 90: 2453 return (B(eax) || SH_C0(eax) || CG(eax)); 2454 case 91: 2455 case 92: 2456 return (B(eax) || SH_C0(eax)); 2457 case 93: 2458 return (SH_C0(eax)); 2459 case 94: 2460 return (B(eax) || SH_C0(eax) || CG(eax)); 2461 case 95: 2462 #if !defined(__amd64) 2463 return (0); 2464 #else 2465 return (B(eax) || SH_C0(eax)); 2466 #endif 2467 case 96: 2468 return (B(eax) || SH_C0(eax) || CG(eax)); 2469 case 97: 2470 case 98: 2471 return (SH_C0(eax) || CG(eax)); 2472 case 99: 2473 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2474 case 100: 2475 return (B(eax) || SH_C0(eax)); 2476 case 101: 2477 case 103: 2478 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2479 case 104: 2480 return (SH_C0(eax) || CG(eax) || D0(eax)); 2481 case 105: 2482 case 106: 2483 case 107: 2484 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2485 case 108: 2486 return (DH_CG(eax)); 2487 case 109: 2488 return (SH_C0(eax) || CG(eax) || D0(eax)); 2489 case 110: 2490 return (D0(eax) || EX(eax)); 2491 case 111: 2492 return (CG(eax)); 2493 case 112: 2494 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2495 case 113: 2496 return (eax == 0x20fc0); 2497 case 114: 2498 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2499 case 115: 2500 return (SH_E0(eax) || JH_E1(eax)); 2501 case 116: 2502 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2503 case 117: 2504 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2505 case 118: 2506 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2507 JH_E6(eax)); 2508 case 121: 2509 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2510 case 122: 2511 return (cpi->cpi_family < 0x10); 2512 case 123: 2513 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2514 case 131: 2515 return (cpi->cpi_family < 0x10); 2516 case 6336786: 2517 /* 2518 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2519 * if this is a K8 family or newer processor 2520 */ 2521 if (CPI_FAMILY(cpi) == 0xf) { 2522 struct cpuid_regs regs; 2523 regs.cp_eax = 0x80000007; 2524 (void) __cpuid_insn(®s); 2525 return (!(regs.cp_edx & 0x100)); 2526 } 2527 return (0); 2528 case 6323525: 2529 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2530 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2531 2532 default: 2533 return (-1); 2534 } 2535 } 2536 2537 static const char assoc_str[] = "associativity"; 2538 static const char line_str[] = "line-size"; 2539 static const char size_str[] = "size"; 2540 2541 static void 2542 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2543 uint32_t val) 2544 { 2545 char buf[128]; 2546 2547 /* 2548 * ndi_prop_update_int() is used because it is desirable for 2549 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2550 */ 2551 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2552 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2553 } 2554 2555 /* 2556 * Intel-style cache/tlb description 2557 * 2558 * Standard cpuid level 2 gives a randomly ordered 2559 * selection of tags that index into a table that describes 2560 * cache and tlb properties. 2561 */ 2562 2563 static const char l1_icache_str[] = "l1-icache"; 2564 static const char l1_dcache_str[] = "l1-dcache"; 2565 static const char l2_cache_str[] = "l2-cache"; 2566 static const char l3_cache_str[] = "l3-cache"; 2567 static const char itlb4k_str[] = "itlb-4K"; 2568 static const char dtlb4k_str[] = "dtlb-4K"; 2569 static const char itlb4M_str[] = "itlb-4M"; 2570 static const char dtlb4M_str[] = "dtlb-4M"; 2571 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2572 static const char dtlb44_str[] = "dtlb-4K-4M"; 2573 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2574 static const char sl2_cache_str[] = "sectored-l2-cache"; 2575 static const char itrace_str[] = "itrace-cache"; 2576 static const char sl3_cache_str[] = "sectored-l3-cache"; 2577 2578 static const struct cachetab { 2579 uint8_t ct_code; 2580 uint8_t ct_assoc; 2581 uint16_t ct_line_size; 2582 size_t ct_size; 2583 const char *ct_label; 2584 } intel_ctab[] = { 2585 /* maintain descending order! */ 2586 { 0xb4, 4, 0, 256, dtlb4k_str }, 2587 { 0xb3, 4, 0, 128, dtlb4k_str }, 2588 { 0xb0, 4, 0, 128, itlb4k_str }, 2589 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2590 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2591 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2592 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2593 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2594 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2595 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2596 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2597 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2598 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2599 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2600 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2601 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2602 { 0x73, 8, 0, 64*1024, itrace_str}, 2603 { 0x72, 8, 0, 32*1024, itrace_str}, 2604 { 0x71, 8, 0, 16*1024, itrace_str}, 2605 { 0x70, 8, 0, 12*1024, itrace_str}, 2606 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2607 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2608 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2609 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2610 { 0x5d, 0, 0, 256, dtlb44_str}, 2611 { 0x5c, 0, 0, 128, dtlb44_str}, 2612 { 0x5b, 0, 0, 64, dtlb44_str}, 2613 { 0x52, 0, 0, 256, itlb424_str}, 2614 { 0x51, 0, 0, 128, itlb424_str}, 2615 { 0x50, 0, 0, 64, itlb424_str}, 2616 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2617 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2618 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2619 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2620 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2621 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2622 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2623 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2624 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2625 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2626 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2627 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2628 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2629 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2630 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2631 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2632 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2633 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2634 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2635 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2636 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2637 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2638 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2639 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2640 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2641 { 0x0b, 4, 0, 4, itlb4M_str}, 2642 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2643 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2644 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2645 { 0x04, 4, 0, 8, dtlb4M_str}, 2646 { 0x03, 4, 0, 64, dtlb4k_str}, 2647 { 0x02, 4, 0, 2, itlb4M_str}, 2648 { 0x01, 4, 0, 32, itlb4k_str}, 2649 { 0 } 2650 }; 2651 2652 static const struct cachetab cyrix_ctab[] = { 2653 { 0x70, 4, 0, 32, "tlb-4K" }, 2654 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2655 { 0 } 2656 }; 2657 2658 /* 2659 * Search a cache table for a matching entry 2660 */ 2661 static const struct cachetab * 2662 find_cacheent(const struct cachetab *ct, uint_t code) 2663 { 2664 if (code != 0) { 2665 for (; ct->ct_code != 0; ct++) 2666 if (ct->ct_code <= code) 2667 break; 2668 if (ct->ct_code == code) 2669 return (ct); 2670 } 2671 return (NULL); 2672 } 2673 2674 /* 2675 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2676 * The walk is terminated if the walker returns non-zero. 2677 */ 2678 static void 2679 intel_walk_cacheinfo(struct cpuid_info *cpi, 2680 void *arg, int (*func)(void *, const struct cachetab *)) 2681 { 2682 const struct cachetab *ct; 2683 uint8_t *dp; 2684 int i; 2685 2686 if ((dp = cpi->cpi_cacheinfo) == NULL) 2687 return; 2688 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2689 /* 2690 * For overloaded descriptor 0x49 we use cpuid function 4 2691 * if supported by the current processor, to update 2692 * cache information. 2693 */ 2694 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4) { 2695 intel_cpuid_4_cache_info(arg, cpi); 2696 continue; 2697 } 2698 2699 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2700 if (func(arg, ct) != 0) 2701 break; 2702 } 2703 } 2704 } 2705 2706 /* 2707 * (Like the Intel one, except for Cyrix CPUs) 2708 */ 2709 static void 2710 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2711 void *arg, int (*func)(void *, const struct cachetab *)) 2712 { 2713 const struct cachetab *ct; 2714 uint8_t *dp; 2715 int i; 2716 2717 if ((dp = cpi->cpi_cacheinfo) == NULL) 2718 return; 2719 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2720 /* 2721 * Search Cyrix-specific descriptor table first .. 2722 */ 2723 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2724 if (func(arg, ct) != 0) 2725 break; 2726 continue; 2727 } 2728 /* 2729 * .. else fall back to the Intel one 2730 */ 2731 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2732 if (func(arg, ct) != 0) 2733 break; 2734 continue; 2735 } 2736 } 2737 } 2738 2739 /* 2740 * A cacheinfo walker that adds associativity, line-size, and size properties 2741 * to the devinfo node it is passed as an argument. 2742 */ 2743 static int 2744 add_cacheent_props(void *arg, const struct cachetab *ct) 2745 { 2746 dev_info_t *devi = arg; 2747 2748 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2749 if (ct->ct_line_size != 0) 2750 add_cache_prop(devi, ct->ct_label, line_str, 2751 ct->ct_line_size); 2752 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2753 return (0); 2754 } 2755 2756 /* 2757 * Add L2 or L3 cache-information using cpuid function 4. This 2758 * function is called from intel_walk_cacheinfo() when descriptor 2759 * 0x49 is encountered. 2760 */ 2761 static void 2762 intel_cpuid_4_cache_info(void *arg, struct cpuid_info *cpi) 2763 { 2764 uint32_t level, i; 2765 2766 struct cachetab ct; 2767 2768 for (i = 0; i < cpi->cpi_std_4_size; i++) { 2769 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 2770 2771 if (level == 2 || level == 3) { 2772 ct.ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 2773 ct.ct_line_size = 2774 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 2775 ct.ct_size = ct.ct_assoc * 2776 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 2777 ct.ct_line_size * 2778 (cpi->cpi_std_4[i]->cp_ecx + 1); 2779 2780 if (level == 2) { 2781 ct.ct_label = l2_cache_str; 2782 } else if (level == 3) { 2783 ct.ct_label = l3_cache_str; 2784 } 2785 2786 (void) add_cacheent_props(arg, 2787 (const struct cachetab *) (&ct)); 2788 } 2789 } 2790 } 2791 2792 static const char fully_assoc[] = "fully-associative?"; 2793 2794 /* 2795 * AMD style cache/tlb description 2796 * 2797 * Extended functions 5 and 6 directly describe properties of 2798 * tlbs and various cache levels. 2799 */ 2800 static void 2801 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2802 { 2803 switch (assoc) { 2804 case 0: /* reserved; ignore */ 2805 break; 2806 default: 2807 add_cache_prop(devi, label, assoc_str, assoc); 2808 break; 2809 case 0xff: 2810 add_cache_prop(devi, label, fully_assoc, 1); 2811 break; 2812 } 2813 } 2814 2815 static void 2816 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2817 { 2818 if (size == 0) 2819 return; 2820 add_cache_prop(devi, label, size_str, size); 2821 add_amd_assoc(devi, label, assoc); 2822 } 2823 2824 static void 2825 add_amd_cache(dev_info_t *devi, const char *label, 2826 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2827 { 2828 if (size == 0 || line_size == 0) 2829 return; 2830 add_amd_assoc(devi, label, assoc); 2831 /* 2832 * Most AMD parts have a sectored cache. Multiple cache lines are 2833 * associated with each tag. A sector consists of all cache lines 2834 * associated with a tag. For example, the AMD K6-III has a sector 2835 * size of 2 cache lines per tag. 2836 */ 2837 if (lines_per_tag != 0) 2838 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2839 add_cache_prop(devi, label, line_str, line_size); 2840 add_cache_prop(devi, label, size_str, size * 1024); 2841 } 2842 2843 static void 2844 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2845 { 2846 switch (assoc) { 2847 case 0: /* off */ 2848 break; 2849 case 1: 2850 case 2: 2851 case 4: 2852 add_cache_prop(devi, label, assoc_str, assoc); 2853 break; 2854 case 6: 2855 add_cache_prop(devi, label, assoc_str, 8); 2856 break; 2857 case 8: 2858 add_cache_prop(devi, label, assoc_str, 16); 2859 break; 2860 case 0xf: 2861 add_cache_prop(devi, label, fully_assoc, 1); 2862 break; 2863 default: /* reserved; ignore */ 2864 break; 2865 } 2866 } 2867 2868 static void 2869 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2870 { 2871 if (size == 0 || assoc == 0) 2872 return; 2873 add_amd_l2_assoc(devi, label, assoc); 2874 add_cache_prop(devi, label, size_str, size); 2875 } 2876 2877 static void 2878 add_amd_l2_cache(dev_info_t *devi, const char *label, 2879 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2880 { 2881 if (size == 0 || assoc == 0 || line_size == 0) 2882 return; 2883 add_amd_l2_assoc(devi, label, assoc); 2884 if (lines_per_tag != 0) 2885 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2886 add_cache_prop(devi, label, line_str, line_size); 2887 add_cache_prop(devi, label, size_str, size * 1024); 2888 } 2889 2890 static void 2891 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 2892 { 2893 struct cpuid_regs *cp; 2894 2895 if (cpi->cpi_xmaxeax < 0x80000005) 2896 return; 2897 cp = &cpi->cpi_extd[5]; 2898 2899 /* 2900 * 4M/2M L1 TLB configuration 2901 * 2902 * We report the size for 2M pages because AMD uses two 2903 * TLB entries for one 4M page. 2904 */ 2905 add_amd_tlb(devi, "dtlb-2M", 2906 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 2907 add_amd_tlb(devi, "itlb-2M", 2908 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 2909 2910 /* 2911 * 4K L1 TLB configuration 2912 */ 2913 2914 switch (cpi->cpi_vendor) { 2915 uint_t nentries; 2916 case X86_VENDOR_TM: 2917 if (cpi->cpi_family >= 5) { 2918 /* 2919 * Crusoe processors have 256 TLB entries, but 2920 * cpuid data format constrains them to only 2921 * reporting 255 of them. 2922 */ 2923 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 2924 nentries = 256; 2925 /* 2926 * Crusoe processors also have a unified TLB 2927 */ 2928 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 2929 nentries); 2930 break; 2931 } 2932 /*FALLTHROUGH*/ 2933 default: 2934 add_amd_tlb(devi, itlb4k_str, 2935 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 2936 add_amd_tlb(devi, dtlb4k_str, 2937 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 2938 break; 2939 } 2940 2941 /* 2942 * data L1 cache configuration 2943 */ 2944 2945 add_amd_cache(devi, l1_dcache_str, 2946 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 2947 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 2948 2949 /* 2950 * code L1 cache configuration 2951 */ 2952 2953 add_amd_cache(devi, l1_icache_str, 2954 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 2955 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 2956 2957 if (cpi->cpi_xmaxeax < 0x80000006) 2958 return; 2959 cp = &cpi->cpi_extd[6]; 2960 2961 /* Check for a unified L2 TLB for large pages */ 2962 2963 if (BITX(cp->cp_eax, 31, 16) == 0) 2964 add_amd_l2_tlb(devi, "l2-tlb-2M", 2965 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2966 else { 2967 add_amd_l2_tlb(devi, "l2-dtlb-2M", 2968 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2969 add_amd_l2_tlb(devi, "l2-itlb-2M", 2970 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2971 } 2972 2973 /* Check for a unified L2 TLB for 4K pages */ 2974 2975 if (BITX(cp->cp_ebx, 31, 16) == 0) { 2976 add_amd_l2_tlb(devi, "l2-tlb-4K", 2977 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2978 } else { 2979 add_amd_l2_tlb(devi, "l2-dtlb-4K", 2980 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2981 add_amd_l2_tlb(devi, "l2-itlb-4K", 2982 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2983 } 2984 2985 add_amd_l2_cache(devi, l2_cache_str, 2986 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 2987 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 2988 } 2989 2990 /* 2991 * There are two basic ways that the x86 world describes it cache 2992 * and tlb architecture - Intel's way and AMD's way. 2993 * 2994 * Return which flavor of cache architecture we should use 2995 */ 2996 static int 2997 x86_which_cacheinfo(struct cpuid_info *cpi) 2998 { 2999 switch (cpi->cpi_vendor) { 3000 case X86_VENDOR_Intel: 3001 if (cpi->cpi_maxeax >= 2) 3002 return (X86_VENDOR_Intel); 3003 break; 3004 case X86_VENDOR_AMD: 3005 /* 3006 * The K5 model 1 was the first part from AMD that reported 3007 * cache sizes via extended cpuid functions. 3008 */ 3009 if (cpi->cpi_family > 5 || 3010 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3011 return (X86_VENDOR_AMD); 3012 break; 3013 case X86_VENDOR_TM: 3014 if (cpi->cpi_family >= 5) 3015 return (X86_VENDOR_AMD); 3016 /*FALLTHROUGH*/ 3017 default: 3018 /* 3019 * If they have extended CPU data for 0x80000005 3020 * then we assume they have AMD-format cache 3021 * information. 3022 * 3023 * If not, and the vendor happens to be Cyrix, 3024 * then try our-Cyrix specific handler. 3025 * 3026 * If we're not Cyrix, then assume we're using Intel's 3027 * table-driven format instead. 3028 */ 3029 if (cpi->cpi_xmaxeax >= 0x80000005) 3030 return (X86_VENDOR_AMD); 3031 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3032 return (X86_VENDOR_Cyrix); 3033 else if (cpi->cpi_maxeax >= 2) 3034 return (X86_VENDOR_Intel); 3035 break; 3036 } 3037 return (-1); 3038 } 3039 3040 /* 3041 * create a node for the given cpu under the prom root node. 3042 * Also, create a cpu node in the device tree. 3043 */ 3044 static dev_info_t *cpu_nex_devi = NULL; 3045 static kmutex_t cpu_node_lock; 3046 3047 /* 3048 * Called from post_startup() and mp_startup() 3049 */ 3050 void 3051 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3052 { 3053 dev_info_t *cpu_devi; 3054 int create; 3055 3056 mutex_enter(&cpu_node_lock); 3057 3058 /* 3059 * create a nexus node for all cpus identified as 'cpu_id' under 3060 * the root node. 3061 */ 3062 if (cpu_nex_devi == NULL) { 3063 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3064 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3065 mutex_exit(&cpu_node_lock); 3066 return; 3067 } 3068 (void) ndi_devi_online(cpu_nex_devi, 0); 3069 } 3070 3071 /* 3072 * create a child node for cpu identified as 'cpu_id' 3073 */ 3074 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3075 cpu_id); 3076 if (cpu_devi == NULL) { 3077 mutex_exit(&cpu_node_lock); 3078 return; 3079 } 3080 3081 /* device_type */ 3082 3083 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3084 "device_type", "cpu"); 3085 3086 /* reg */ 3087 3088 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3089 "reg", cpu_id); 3090 3091 /* cpu-mhz, and clock-frequency */ 3092 3093 if (cpu_freq > 0) { 3094 long long mul; 3095 3096 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3097 "cpu-mhz", cpu_freq); 3098 3099 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3100 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3101 "clock-frequency", (int)mul); 3102 } 3103 3104 (void) ndi_devi_online(cpu_devi, 0); 3105 3106 if ((x86_feature & X86_CPUID) == 0) { 3107 mutex_exit(&cpu_node_lock); 3108 return; 3109 } 3110 3111 /* vendor-id */ 3112 3113 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3114 "vendor-id", cpi->cpi_vendorstr); 3115 3116 if (cpi->cpi_maxeax == 0) { 3117 mutex_exit(&cpu_node_lock); 3118 return; 3119 } 3120 3121 /* 3122 * family, model, and step 3123 */ 3124 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3125 "family", CPI_FAMILY(cpi)); 3126 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3127 "cpu-model", CPI_MODEL(cpi)); 3128 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3129 "stepping-id", CPI_STEP(cpi)); 3130 3131 /* type */ 3132 3133 switch (cpi->cpi_vendor) { 3134 case X86_VENDOR_Intel: 3135 create = 1; 3136 break; 3137 default: 3138 create = 0; 3139 break; 3140 } 3141 if (create) 3142 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3143 "type", CPI_TYPE(cpi)); 3144 3145 /* ext-family */ 3146 3147 switch (cpi->cpi_vendor) { 3148 case X86_VENDOR_Intel: 3149 case X86_VENDOR_AMD: 3150 create = cpi->cpi_family >= 0xf; 3151 break; 3152 default: 3153 create = 0; 3154 break; 3155 } 3156 if (create) 3157 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3158 "ext-family", CPI_FAMILY_XTD(cpi)); 3159 3160 /* ext-model */ 3161 3162 switch (cpi->cpi_vendor) { 3163 case X86_VENDOR_Intel: 3164 create = CPI_MODEL(cpi) == 0xf; 3165 break; 3166 case X86_VENDOR_AMD: 3167 create = CPI_FAMILY(cpi) == 0xf; 3168 break; 3169 default: 3170 create = 0; 3171 break; 3172 } 3173 if (create) 3174 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3175 "ext-model", CPI_MODEL_XTD(cpi)); 3176 3177 /* generation */ 3178 3179 switch (cpi->cpi_vendor) { 3180 case X86_VENDOR_AMD: 3181 /* 3182 * AMD K5 model 1 was the first part to support this 3183 */ 3184 create = cpi->cpi_xmaxeax >= 0x80000001; 3185 break; 3186 default: 3187 create = 0; 3188 break; 3189 } 3190 if (create) 3191 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3192 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3193 3194 /* brand-id */ 3195 3196 switch (cpi->cpi_vendor) { 3197 case X86_VENDOR_Intel: 3198 /* 3199 * brand id first appeared on Pentium III Xeon model 8, 3200 * and Celeron model 8 processors and Opteron 3201 */ 3202 create = cpi->cpi_family > 6 || 3203 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3204 break; 3205 case X86_VENDOR_AMD: 3206 create = cpi->cpi_family >= 0xf; 3207 break; 3208 default: 3209 create = 0; 3210 break; 3211 } 3212 if (create && cpi->cpi_brandid != 0) { 3213 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3214 "brand-id", cpi->cpi_brandid); 3215 } 3216 3217 /* chunks, and apic-id */ 3218 3219 switch (cpi->cpi_vendor) { 3220 /* 3221 * first available on Pentium IV and Opteron (K8) 3222 */ 3223 case X86_VENDOR_Intel: 3224 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3225 break; 3226 case X86_VENDOR_AMD: 3227 create = cpi->cpi_family >= 0xf; 3228 break; 3229 default: 3230 create = 0; 3231 break; 3232 } 3233 if (create) { 3234 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3235 "chunks", CPI_CHUNKS(cpi)); 3236 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3237 "apic-id", CPI_APIC_ID(cpi)); 3238 if (cpi->cpi_chipid >= 0) { 3239 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3240 "chip#", cpi->cpi_chipid); 3241 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3242 "clog#", cpi->cpi_clogid); 3243 } 3244 } 3245 3246 /* cpuid-features */ 3247 3248 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3249 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3250 3251 3252 /* cpuid-features-ecx */ 3253 3254 switch (cpi->cpi_vendor) { 3255 case X86_VENDOR_Intel: 3256 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3257 break; 3258 default: 3259 create = 0; 3260 break; 3261 } 3262 if (create) 3263 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3264 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3265 3266 /* ext-cpuid-features */ 3267 3268 switch (cpi->cpi_vendor) { 3269 case X86_VENDOR_Intel: 3270 case X86_VENDOR_AMD: 3271 case X86_VENDOR_Cyrix: 3272 case X86_VENDOR_TM: 3273 case X86_VENDOR_Centaur: 3274 create = cpi->cpi_xmaxeax >= 0x80000001; 3275 break; 3276 default: 3277 create = 0; 3278 break; 3279 } 3280 if (create) { 3281 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3282 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3283 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3284 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3285 } 3286 3287 /* 3288 * Brand String first appeared in Intel Pentium IV, AMD K5 3289 * model 1, and Cyrix GXm. On earlier models we try and 3290 * simulate something similar .. so this string should always 3291 * same -something- about the processor, however lame. 3292 */ 3293 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3294 "brand-string", cpi->cpi_brandstr); 3295 3296 /* 3297 * Finally, cache and tlb information 3298 */ 3299 switch (x86_which_cacheinfo(cpi)) { 3300 case X86_VENDOR_Intel: 3301 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3302 break; 3303 case X86_VENDOR_Cyrix: 3304 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3305 break; 3306 case X86_VENDOR_AMD: 3307 amd_cache_info(cpi, cpu_devi); 3308 break; 3309 default: 3310 break; 3311 } 3312 3313 mutex_exit(&cpu_node_lock); 3314 } 3315 3316 struct l2info { 3317 int *l2i_csz; 3318 int *l2i_lsz; 3319 int *l2i_assoc; 3320 int l2i_ret; 3321 }; 3322 3323 /* 3324 * A cacheinfo walker that fetches the size, line-size and associativity 3325 * of the L2 cache 3326 */ 3327 static int 3328 intel_l2cinfo(void *arg, const struct cachetab *ct) 3329 { 3330 struct l2info *l2i = arg; 3331 int *ip; 3332 3333 if (ct->ct_label != l2_cache_str && 3334 ct->ct_label != sl2_cache_str) 3335 return (0); /* not an L2 -- keep walking */ 3336 3337 if ((ip = l2i->l2i_csz) != NULL) 3338 *ip = ct->ct_size; 3339 if ((ip = l2i->l2i_lsz) != NULL) 3340 *ip = ct->ct_line_size; 3341 if ((ip = l2i->l2i_assoc) != NULL) 3342 *ip = ct->ct_assoc; 3343 l2i->l2i_ret = ct->ct_size; 3344 return (1); /* was an L2 -- terminate walk */ 3345 } 3346 3347 static void 3348 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3349 { 3350 struct cpuid_regs *cp; 3351 uint_t size, assoc; 3352 int *ip; 3353 3354 if (cpi->cpi_xmaxeax < 0x80000006) 3355 return; 3356 cp = &cpi->cpi_extd[6]; 3357 3358 if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && 3359 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3360 uint_t cachesz = size * 1024; 3361 3362 3363 if ((ip = l2i->l2i_csz) != NULL) 3364 *ip = cachesz; 3365 if ((ip = l2i->l2i_lsz) != NULL) 3366 *ip = BITX(cp->cp_ecx, 7, 0); 3367 if ((ip = l2i->l2i_assoc) != NULL) 3368 *ip = assoc; 3369 l2i->l2i_ret = cachesz; 3370 } 3371 } 3372 3373 int 3374 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3375 { 3376 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3377 struct l2info __l2info, *l2i = &__l2info; 3378 3379 l2i->l2i_csz = csz; 3380 l2i->l2i_lsz = lsz; 3381 l2i->l2i_assoc = assoc; 3382 l2i->l2i_ret = -1; 3383 3384 switch (x86_which_cacheinfo(cpi)) { 3385 case X86_VENDOR_Intel: 3386 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3387 break; 3388 case X86_VENDOR_Cyrix: 3389 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3390 break; 3391 case X86_VENDOR_AMD: 3392 amd_l2cacheinfo(cpi, l2i); 3393 break; 3394 default: 3395 break; 3396 } 3397 return (l2i->l2i_ret); 3398 } 3399 3400 size_t 3401 cpuid_get_mwait_size(cpu_t *cpu) 3402 { 3403 ASSERT(cpuid_checkpass(cpu, 2)); 3404 return (cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max); 3405 } 3406