1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Various routines to handle identification 28 * and classification of x86 processors. 29 */ 30 31 #include <sys/types.h> 32 #include <sys/archsystm.h> 33 #include <sys/x86_archext.h> 34 #include <sys/kmem.h> 35 #include <sys/systm.h> 36 #include <sys/cmn_err.h> 37 #include <sys/sunddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/cpuvar.h> 40 #include <sys/processor.h> 41 #include <sys/sysmacros.h> 42 #include <sys/pg.h> 43 #include <sys/fp.h> 44 #include <sys/controlregs.h> 45 #include <sys/auxv_386.h> 46 #include <sys/bitmap.h> 47 #include <sys/memnode.h> 48 49 #ifdef __xpv 50 #include <sys/hypervisor.h> 51 #else 52 #include <sys/ontrap.h> 53 #endif 54 55 /* 56 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 57 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 58 * them accordingly. For most modern processors, feature detection occurs here 59 * in pass 1. 60 * 61 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 62 * for the boot CPU and does the basic analysis that the early kernel needs. 63 * x86_feature is set based on the return value of cpuid_pass1() of the boot 64 * CPU. 65 * 66 * Pass 1 includes: 67 * 68 * o Determining vendor/model/family/stepping and setting x86_type and 69 * x86_vendor accordingly. 70 * o Processing the feature flags returned by the cpuid instruction while 71 * applying any workarounds or tricks for the specific processor. 72 * o Mapping the feature flags into Solaris feature bits (X86_*). 73 * o Processing extended feature flags if supported by the processor, 74 * again while applying specific processor knowledge. 75 * o Determining the CMT characteristics of the system. 76 * 77 * Pass 1 is done on non-boot CPUs during their initialization and the results 78 * are used only as a meager attempt at ensuring that all processors within the 79 * system support the same features. 80 * 81 * Pass 2 of cpuid feature analysis happens just at the beginning 82 * of startup(). It just copies in and corrects the remainder 83 * of the cpuid data we depend on: standard cpuid functions that we didn't 84 * need for pass1 feature analysis, and extended cpuid functions beyond the 85 * simple feature processing done in pass1. 86 * 87 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 88 * particular kernel memory allocation has been made available. It creates a 89 * readable brand string based on the data collected in the first two passes. 90 * 91 * Pass 4 of cpuid analysis is invoked after post_startup() when all 92 * the support infrastructure for various hardware features has been 93 * initialized. It determines which processor features will be reported 94 * to userland via the aux vector. 95 * 96 * All passes are executed on all CPUs, but only the boot CPU determines what 97 * features the kernel will use. 98 * 99 * Much of the worst junk in this file is for the support of processors 100 * that didn't really implement the cpuid instruction properly. 101 * 102 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 103 * the pass numbers. Accordingly, changes to the pass code may require changes 104 * to the accessor code. 105 */ 106 107 uint_t x86_feature = 0; 108 uint_t x86_vendor = X86_VENDOR_IntelClone; 109 uint_t x86_type = X86_TYPE_OTHER; 110 uint_t x86_clflush_size = 0; 111 112 uint_t pentiumpro_bug4046376; 113 uint_t pentiumpro_bug4064495; 114 115 uint_t enable486; 116 /* 117 * This is set if Solaris is booted in a fully virtualized mode: 118 * - as HVM guest under xVM 119 * - as guest under VMware 120 * check_for_hvm() has the logic to detect these 2 cases. 121 * This is not applicable if Solaris is booted as a para virtual guest. 122 */ 123 int platform_is_virt = 0; 124 125 /* 126 * monitor/mwait info. 127 * 128 * size_actual and buf_actual are the real address and size allocated to get 129 * proper mwait_buf alignement. buf_actual and size_actual should be passed 130 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 131 * processor cache-line alignment, but this is not guarantied in the furture. 132 */ 133 struct mwait_info { 134 size_t mon_min; /* min size to avoid missed wakeups */ 135 size_t mon_max; /* size to avoid false wakeups */ 136 size_t size_actual; /* size actually allocated */ 137 void *buf_actual; /* memory actually allocated */ 138 uint32_t support; /* processor support of monitor/mwait */ 139 }; 140 141 /* 142 * These constants determine how many of the elements of the 143 * cpuid we cache in the cpuid_info data structure; the 144 * remaining elements are accessible via the cpuid instruction. 145 */ 146 147 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 148 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 149 150 struct cpuid_info { 151 uint_t cpi_pass; /* last pass completed */ 152 /* 153 * standard function information 154 */ 155 uint_t cpi_maxeax; /* fn 0: %eax */ 156 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 157 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 158 159 uint_t cpi_family; /* fn 1: extended family */ 160 uint_t cpi_model; /* fn 1: extended model */ 161 uint_t cpi_step; /* fn 1: stepping */ 162 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 163 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 164 int cpi_clogid; /* fn 1: %ebx: thread # */ 165 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 166 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 167 uint_t cpi_ncache; /* fn 2: number of elements */ 168 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 169 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 170 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 171 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 172 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 173 /* 174 * extended function information 175 */ 176 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 177 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 178 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 179 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 180 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 181 id_t cpi_coreid; /* same coreid => strands share core */ 182 int cpi_pkgcoreid; /* core number within single package */ 183 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 184 /* Intel: fn 4: %eax[31-26] */ 185 /* 186 * supported feature information 187 */ 188 uint32_t cpi_support[5]; 189 #define STD_EDX_FEATURES 0 190 #define AMD_EDX_FEATURES 1 191 #define TM_EDX_FEATURES 2 192 #define STD_ECX_FEATURES 3 193 #define AMD_ECX_FEATURES 4 194 /* 195 * Synthesized information, where known. 196 */ 197 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 198 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 199 uint32_t cpi_socket; /* Chip package/socket type */ 200 201 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 202 uint32_t cpi_apicid; 203 }; 204 205 206 static struct cpuid_info cpuid_info0; 207 208 /* 209 * These bit fields are defined by the Intel Application Note AP-485 210 * "Intel Processor Identification and the CPUID Instruction" 211 */ 212 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 213 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 214 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 215 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 216 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 217 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 218 219 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 220 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 221 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 222 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 223 224 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 225 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 226 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 227 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 228 229 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 230 #define CPI_XMAXEAX_MAX 0x80000100 231 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 232 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 233 234 /* 235 * Function 4 (Deterministic Cache Parameters) macros 236 * Defined by Intel Application Note AP-485 237 */ 238 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 239 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 240 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 241 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 242 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 243 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 244 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 245 246 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 247 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 248 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 249 250 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 251 252 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 253 254 255 /* 256 * A couple of shorthand macros to identify "later" P6-family chips 257 * like the Pentium M and Core. First, the "older" P6-based stuff 258 * (loosely defined as "pre-Pentium-4"): 259 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 260 */ 261 262 #define IS_LEGACY_P6(cpi) ( \ 263 cpi->cpi_family == 6 && \ 264 (cpi->cpi_model == 1 || \ 265 cpi->cpi_model == 3 || \ 266 cpi->cpi_model == 5 || \ 267 cpi->cpi_model == 6 || \ 268 cpi->cpi_model == 7 || \ 269 cpi->cpi_model == 8 || \ 270 cpi->cpi_model == 0xA || \ 271 cpi->cpi_model == 0xB) \ 272 ) 273 274 /* A "new F6" is everything with family 6 that's not the above */ 275 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 276 277 /* Extended family/model support */ 278 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 279 cpi->cpi_family >= 0xf) 280 281 /* 282 * Info for monitor/mwait idle loop. 283 * 284 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 285 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 286 * 2006. 287 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 288 * Documentation Updates" #33633, Rev 2.05, December 2006. 289 */ 290 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 291 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 292 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 293 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 294 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 295 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 296 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 297 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 298 /* 299 * Number of sub-cstates for a given c-state. 300 */ 301 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 302 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 303 304 /* 305 * Functions we consune from cpuid_subr.c; don't publish these in a header 306 * file to try and keep people using the expected cpuid_* interfaces. 307 */ 308 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 309 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 310 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 311 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 312 313 /* 314 * Apply up various platform-dependent restrictions where the 315 * underlying platform restrictions mean the CPU can be marked 316 * as less capable than its cpuid instruction would imply. 317 */ 318 #if defined(__xpv) 319 static void 320 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 321 { 322 switch (eax) { 323 case 1: { 324 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 325 0 : CPUID_INTC_EDX_MCA; 326 cp->cp_edx &= 327 ~(mcamask | 328 CPUID_INTC_EDX_PSE | 329 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 330 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 331 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 332 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 333 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 334 break; 335 } 336 337 case 0x80000001: 338 cp->cp_edx &= 339 ~(CPUID_AMD_EDX_PSE | 340 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 341 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 342 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 343 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 344 CPUID_AMD_EDX_TSCP); 345 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 346 break; 347 default: 348 break; 349 } 350 351 switch (vendor) { 352 case X86_VENDOR_Intel: 353 switch (eax) { 354 case 4: 355 /* 356 * Zero out the (ncores-per-chip - 1) field 357 */ 358 cp->cp_eax &= 0x03fffffff; 359 break; 360 default: 361 break; 362 } 363 break; 364 case X86_VENDOR_AMD: 365 switch (eax) { 366 case 0x80000008: 367 /* 368 * Zero out the (ncores-per-chip - 1) field 369 */ 370 cp->cp_ecx &= 0xffffff00; 371 break; 372 default: 373 break; 374 } 375 break; 376 default: 377 break; 378 } 379 } 380 #else 381 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 382 #endif 383 384 /* 385 * Some undocumented ways of patching the results of the cpuid 386 * instruction to permit running Solaris 10 on future cpus that 387 * we don't currently support. Could be set to non-zero values 388 * via settings in eeprom. 389 */ 390 391 uint32_t cpuid_feature_ecx_include; 392 uint32_t cpuid_feature_ecx_exclude; 393 uint32_t cpuid_feature_edx_include; 394 uint32_t cpuid_feature_edx_exclude; 395 396 void 397 cpuid_alloc_space(cpu_t *cpu) 398 { 399 /* 400 * By convention, cpu0 is the boot cpu, which is set up 401 * before memory allocation is available. All other cpus get 402 * their cpuid_info struct allocated here. 403 */ 404 ASSERT(cpu->cpu_id != 0); 405 cpu->cpu_m.mcpu_cpi = 406 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 407 } 408 409 void 410 cpuid_free_space(cpu_t *cpu) 411 { 412 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 413 int i; 414 415 ASSERT(cpu->cpu_id != 0); 416 417 /* 418 * Free up any function 4 related dynamic storage 419 */ 420 for (i = 1; i < cpi->cpi_std_4_size; i++) 421 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 422 if (cpi->cpi_std_4_size > 0) 423 kmem_free(cpi->cpi_std_4, 424 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 425 426 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 427 } 428 429 #if !defined(__xpv) 430 431 static void 432 check_for_hvm() 433 { 434 struct cpuid_regs cp; 435 char *xen_str; 436 uint32_t xen_signature[4]; 437 extern int xpv_is_hvm; 438 439 /* 440 * In a fully virtualized domain, Xen's pseudo-cpuid function 441 * 0x40000000 returns a string representing the Xen signature in 442 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid 443 * function. 444 */ 445 cp.cp_eax = 0x40000000; 446 (void) __cpuid_insn(&cp); 447 xen_signature[0] = cp.cp_ebx; 448 xen_signature[1] = cp.cp_ecx; 449 xen_signature[2] = cp.cp_edx; 450 xen_signature[3] = 0; 451 xen_str = (char *)xen_signature; 452 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) 453 xpv_is_hvm = 1; 454 455 /* could we be running under vmware hypervisor */ 456 if (xpv_is_hvm || vmware_platform()) 457 platform_is_virt = 1; 458 } 459 #endif /* __xpv */ 460 461 uint_t 462 cpuid_pass1(cpu_t *cpu) 463 { 464 uint32_t mask_ecx, mask_edx; 465 uint_t feature = X86_CPUID; 466 struct cpuid_info *cpi; 467 struct cpuid_regs *cp; 468 int xcpuid; 469 #if !defined(__xpv) 470 extern int idle_cpu_prefer_mwait; 471 #endif 472 473 /* 474 * Space statically allocated for cpu0, ensure pointer is set 475 */ 476 if (cpu->cpu_id == 0) 477 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 478 cpi = cpu->cpu_m.mcpu_cpi; 479 ASSERT(cpi != NULL); 480 cp = &cpi->cpi_std[0]; 481 cp->cp_eax = 0; 482 cpi->cpi_maxeax = __cpuid_insn(cp); 483 { 484 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 485 *iptr++ = cp->cp_ebx; 486 *iptr++ = cp->cp_edx; 487 *iptr++ = cp->cp_ecx; 488 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 489 } 490 491 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 492 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 493 494 /* 495 * Limit the range in case of weird hardware 496 */ 497 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 498 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 499 if (cpi->cpi_maxeax < 1) 500 goto pass1_done; 501 502 cp = &cpi->cpi_std[1]; 503 cp->cp_eax = 1; 504 (void) __cpuid_insn(cp); 505 506 /* 507 * Extract identifying constants for easy access. 508 */ 509 cpi->cpi_model = CPI_MODEL(cpi); 510 cpi->cpi_family = CPI_FAMILY(cpi); 511 512 if (cpi->cpi_family == 0xf) 513 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 514 515 /* 516 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 517 * Intel, and presumably everyone else, uses model == 0xf, as 518 * one would expect (max value means possible overflow). Sigh. 519 */ 520 521 switch (cpi->cpi_vendor) { 522 case X86_VENDOR_Intel: 523 if (IS_EXTENDED_MODEL_INTEL(cpi)) 524 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 525 break; 526 case X86_VENDOR_AMD: 527 if (CPI_FAMILY(cpi) == 0xf) 528 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 529 break; 530 default: 531 if (cpi->cpi_model == 0xf) 532 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 533 break; 534 } 535 536 cpi->cpi_step = CPI_STEP(cpi); 537 cpi->cpi_brandid = CPI_BRANDID(cpi); 538 539 /* 540 * *default* assumptions: 541 * - believe %edx feature word 542 * - ignore %ecx feature word 543 * - 32-bit virtual and physical addressing 544 */ 545 mask_edx = 0xffffffff; 546 mask_ecx = 0; 547 548 cpi->cpi_pabits = cpi->cpi_vabits = 32; 549 550 switch (cpi->cpi_vendor) { 551 case X86_VENDOR_Intel: 552 if (cpi->cpi_family == 5) 553 x86_type = X86_TYPE_P5; 554 else if (IS_LEGACY_P6(cpi)) { 555 x86_type = X86_TYPE_P6; 556 pentiumpro_bug4046376 = 1; 557 pentiumpro_bug4064495 = 1; 558 /* 559 * Clear the SEP bit when it was set erroneously 560 */ 561 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 562 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 563 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 564 x86_type = X86_TYPE_P4; 565 /* 566 * We don't currently depend on any of the %ecx 567 * features until Prescott, so we'll only check 568 * this from P4 onwards. We might want to revisit 569 * that idea later. 570 */ 571 mask_ecx = 0xffffffff; 572 } else if (cpi->cpi_family > 0xf) 573 mask_ecx = 0xffffffff; 574 /* 575 * We don't support MONITOR/MWAIT if leaf 5 is not available 576 * to obtain the monitor linesize. 577 */ 578 if (cpi->cpi_maxeax < 5) 579 mask_ecx &= ~CPUID_INTC_ECX_MON; 580 break; 581 case X86_VENDOR_IntelClone: 582 default: 583 break; 584 case X86_VENDOR_AMD: 585 #if defined(OPTERON_ERRATUM_108) 586 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 587 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 588 cpi->cpi_model = 0xc; 589 } else 590 #endif 591 if (cpi->cpi_family == 5) { 592 /* 593 * AMD K5 and K6 594 * 595 * These CPUs have an incomplete implementation 596 * of MCA/MCE which we mask away. 597 */ 598 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 599 600 /* 601 * Model 0 uses the wrong (APIC) bit 602 * to indicate PGE. Fix it here. 603 */ 604 if (cpi->cpi_model == 0) { 605 if (cp->cp_edx & 0x200) { 606 cp->cp_edx &= ~0x200; 607 cp->cp_edx |= CPUID_INTC_EDX_PGE; 608 } 609 } 610 611 /* 612 * Early models had problems w/ MMX; disable. 613 */ 614 if (cpi->cpi_model < 6) 615 mask_edx &= ~CPUID_INTC_EDX_MMX; 616 } 617 618 /* 619 * For newer families, SSE3 and CX16, at least, are valid; 620 * enable all 621 */ 622 if (cpi->cpi_family >= 0xf) 623 mask_ecx = 0xffffffff; 624 /* 625 * We don't support MONITOR/MWAIT if leaf 5 is not available 626 * to obtain the monitor linesize. 627 */ 628 if (cpi->cpi_maxeax < 5) 629 mask_ecx &= ~CPUID_INTC_ECX_MON; 630 631 #if !defined(__xpv) 632 /* 633 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 634 * processors. AMD does not intend MWAIT to be used in the cpu 635 * idle loop on current and future processors. 10h and future 636 * AMD processors use more power in MWAIT than HLT. 637 * Pre-family-10h Opterons do not have the MWAIT instruction. 638 */ 639 idle_cpu_prefer_mwait = 0; 640 #endif 641 642 break; 643 case X86_VENDOR_TM: 644 /* 645 * workaround the NT workaround in CMS 4.1 646 */ 647 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 648 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 649 cp->cp_edx |= CPUID_INTC_EDX_CX8; 650 break; 651 case X86_VENDOR_Centaur: 652 /* 653 * workaround the NT workarounds again 654 */ 655 if (cpi->cpi_family == 6) 656 cp->cp_edx |= CPUID_INTC_EDX_CX8; 657 break; 658 case X86_VENDOR_Cyrix: 659 /* 660 * We rely heavily on the probing in locore 661 * to actually figure out what parts, if any, 662 * of the Cyrix cpuid instruction to believe. 663 */ 664 switch (x86_type) { 665 case X86_TYPE_CYRIX_486: 666 mask_edx = 0; 667 break; 668 case X86_TYPE_CYRIX_6x86: 669 mask_edx = 0; 670 break; 671 case X86_TYPE_CYRIX_6x86L: 672 mask_edx = 673 CPUID_INTC_EDX_DE | 674 CPUID_INTC_EDX_CX8; 675 break; 676 case X86_TYPE_CYRIX_6x86MX: 677 mask_edx = 678 CPUID_INTC_EDX_DE | 679 CPUID_INTC_EDX_MSR | 680 CPUID_INTC_EDX_CX8 | 681 CPUID_INTC_EDX_PGE | 682 CPUID_INTC_EDX_CMOV | 683 CPUID_INTC_EDX_MMX; 684 break; 685 case X86_TYPE_CYRIX_GXm: 686 mask_edx = 687 CPUID_INTC_EDX_MSR | 688 CPUID_INTC_EDX_CX8 | 689 CPUID_INTC_EDX_CMOV | 690 CPUID_INTC_EDX_MMX; 691 break; 692 case X86_TYPE_CYRIX_MediaGX: 693 break; 694 case X86_TYPE_CYRIX_MII: 695 case X86_TYPE_VIA_CYRIX_III: 696 mask_edx = 697 CPUID_INTC_EDX_DE | 698 CPUID_INTC_EDX_TSC | 699 CPUID_INTC_EDX_MSR | 700 CPUID_INTC_EDX_CX8 | 701 CPUID_INTC_EDX_PGE | 702 CPUID_INTC_EDX_CMOV | 703 CPUID_INTC_EDX_MMX; 704 break; 705 default: 706 break; 707 } 708 break; 709 } 710 711 #if defined(__xpv) 712 /* 713 * Do not support MONITOR/MWAIT under a hypervisor 714 */ 715 mask_ecx &= ~CPUID_INTC_ECX_MON; 716 #endif /* __xpv */ 717 718 /* 719 * Now we've figured out the masks that determine 720 * which bits we choose to believe, apply the masks 721 * to the feature words, then map the kernel's view 722 * of these feature words into its feature word. 723 */ 724 cp->cp_edx &= mask_edx; 725 cp->cp_ecx &= mask_ecx; 726 727 /* 728 * apply any platform restrictions (we don't call this 729 * immediately after __cpuid_insn here, because we need the 730 * workarounds applied above first) 731 */ 732 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 733 734 /* 735 * fold in overrides from the "eeprom" mechanism 736 */ 737 cp->cp_edx |= cpuid_feature_edx_include; 738 cp->cp_edx &= ~cpuid_feature_edx_exclude; 739 740 cp->cp_ecx |= cpuid_feature_ecx_include; 741 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 742 743 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 744 feature |= X86_LARGEPAGE; 745 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 746 feature |= X86_TSC; 747 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 748 feature |= X86_MSR; 749 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 750 feature |= X86_MTRR; 751 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 752 feature |= X86_PGE; 753 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 754 feature |= X86_CMOV; 755 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 756 feature |= X86_MMX; 757 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 758 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 759 feature |= X86_MCA; 760 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 761 feature |= X86_PAE; 762 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 763 feature |= X86_CX8; 764 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 765 feature |= X86_CX16; 766 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 767 feature |= X86_PAT; 768 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 769 feature |= X86_SEP; 770 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 771 /* 772 * In our implementation, fxsave/fxrstor 773 * are prerequisites before we'll even 774 * try and do SSE things. 775 */ 776 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 777 feature |= X86_SSE; 778 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 779 feature |= X86_SSE2; 780 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 781 feature |= X86_SSE3; 782 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 783 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 784 feature |= X86_SSSE3; 785 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 786 feature |= X86_SSE4_1; 787 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 788 feature |= X86_SSE4_2; 789 } 790 } 791 if (cp->cp_edx & CPUID_INTC_EDX_DE) 792 feature |= X86_DE; 793 #if !defined(__xpv) 794 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 795 796 /* 797 * We require the CLFLUSH instruction for erratum workaround 798 * to use MONITOR/MWAIT. 799 */ 800 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 801 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 802 feature |= X86_MWAIT; 803 } else { 804 extern int idle_cpu_assert_cflush_monitor; 805 806 /* 807 * All processors we are aware of which have 808 * MONITOR/MWAIT also have CLFLUSH. 809 */ 810 if (idle_cpu_assert_cflush_monitor) { 811 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && 812 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); 813 } 814 } 815 } 816 #endif /* __xpv */ 817 818 /* 819 * Only need it first time, rest of the cpus would follow suite. 820 * we only capture this for the bootcpu. 821 */ 822 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 823 feature |= X86_CLFSH; 824 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 825 } 826 827 if (feature & X86_PAE) 828 cpi->cpi_pabits = 36; 829 830 /* 831 * Hyperthreading configuration is slightly tricky on Intel 832 * and pure clones, and even trickier on AMD. 833 * 834 * (AMD chose to set the HTT bit on their CMP processors, 835 * even though they're not actually hyperthreaded. Thus it 836 * takes a bit more work to figure out what's really going 837 * on ... see the handling of the CMP_LGCY bit below) 838 */ 839 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 840 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 841 if (cpi->cpi_ncpu_per_chip > 1) 842 feature |= X86_HTT; 843 } else { 844 cpi->cpi_ncpu_per_chip = 1; 845 } 846 847 /* 848 * Work on the "extended" feature information, doing 849 * some basic initialization for cpuid_pass2() 850 */ 851 xcpuid = 0; 852 switch (cpi->cpi_vendor) { 853 case X86_VENDOR_Intel: 854 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 855 xcpuid++; 856 break; 857 case X86_VENDOR_AMD: 858 if (cpi->cpi_family > 5 || 859 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 860 xcpuid++; 861 break; 862 case X86_VENDOR_Cyrix: 863 /* 864 * Only these Cyrix CPUs are -known- to support 865 * extended cpuid operations. 866 */ 867 if (x86_type == X86_TYPE_VIA_CYRIX_III || 868 x86_type == X86_TYPE_CYRIX_GXm) 869 xcpuid++; 870 break; 871 case X86_VENDOR_Centaur: 872 case X86_VENDOR_TM: 873 default: 874 xcpuid++; 875 break; 876 } 877 878 if (xcpuid) { 879 cp = &cpi->cpi_extd[0]; 880 cp->cp_eax = 0x80000000; 881 cpi->cpi_xmaxeax = __cpuid_insn(cp); 882 } 883 884 if (cpi->cpi_xmaxeax & 0x80000000) { 885 886 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 887 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 888 889 switch (cpi->cpi_vendor) { 890 case X86_VENDOR_Intel: 891 case X86_VENDOR_AMD: 892 if (cpi->cpi_xmaxeax < 0x80000001) 893 break; 894 cp = &cpi->cpi_extd[1]; 895 cp->cp_eax = 0x80000001; 896 (void) __cpuid_insn(cp); 897 898 if (cpi->cpi_vendor == X86_VENDOR_AMD && 899 cpi->cpi_family == 5 && 900 cpi->cpi_model == 6 && 901 cpi->cpi_step == 6) { 902 /* 903 * K6 model 6 uses bit 10 to indicate SYSC 904 * Later models use bit 11. Fix it here. 905 */ 906 if (cp->cp_edx & 0x400) { 907 cp->cp_edx &= ~0x400; 908 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 909 } 910 } 911 912 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 913 914 /* 915 * Compute the additions to the kernel's feature word. 916 */ 917 if (cp->cp_edx & CPUID_AMD_EDX_NX) 918 feature |= X86_NX; 919 920 /* 921 * Regardless whether or not we boot 64-bit, 922 * we should have a way to identify whether 923 * the CPU is capable of running 64-bit. 924 */ 925 if (cp->cp_edx & CPUID_AMD_EDX_LM) 926 feature |= X86_64; 927 928 #if defined(__amd64) 929 /* 1 GB large page - enable only for 64 bit kernel */ 930 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) 931 feature |= X86_1GPG; 932 #endif 933 934 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 935 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 936 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 937 feature |= X86_SSE4A; 938 939 /* 940 * If both the HTT and CMP_LGCY bits are set, 941 * then we're not actually HyperThreaded. Read 942 * "AMD CPUID Specification" for more details. 943 */ 944 if (cpi->cpi_vendor == X86_VENDOR_AMD && 945 (feature & X86_HTT) && 946 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 947 feature &= ~X86_HTT; 948 feature |= X86_CMP; 949 } 950 #if defined(__amd64) 951 /* 952 * It's really tricky to support syscall/sysret in 953 * the i386 kernel; we rely on sysenter/sysexit 954 * instead. In the amd64 kernel, things are -way- 955 * better. 956 */ 957 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 958 feature |= X86_ASYSC; 959 960 /* 961 * While we're thinking about system calls, note 962 * that AMD processors don't support sysenter 963 * in long mode at all, so don't try to program them. 964 */ 965 if (x86_vendor == X86_VENDOR_AMD) 966 feature &= ~X86_SEP; 967 #endif 968 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 969 feature |= X86_TSCP; 970 break; 971 default: 972 break; 973 } 974 975 /* 976 * Get CPUID data about processor cores and hyperthreads. 977 */ 978 switch (cpi->cpi_vendor) { 979 case X86_VENDOR_Intel: 980 if (cpi->cpi_maxeax >= 4) { 981 cp = &cpi->cpi_std[4]; 982 cp->cp_eax = 4; 983 cp->cp_ecx = 0; 984 (void) __cpuid_insn(cp); 985 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 986 } 987 /*FALLTHROUGH*/ 988 case X86_VENDOR_AMD: 989 if (cpi->cpi_xmaxeax < 0x80000008) 990 break; 991 cp = &cpi->cpi_extd[8]; 992 cp->cp_eax = 0x80000008; 993 (void) __cpuid_insn(cp); 994 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 995 996 /* 997 * Virtual and physical address limits from 998 * cpuid override previously guessed values. 999 */ 1000 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1001 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1002 break; 1003 default: 1004 break; 1005 } 1006 1007 /* 1008 * Derive the number of cores per chip 1009 */ 1010 switch (cpi->cpi_vendor) { 1011 case X86_VENDOR_Intel: 1012 if (cpi->cpi_maxeax < 4) { 1013 cpi->cpi_ncore_per_chip = 1; 1014 break; 1015 } else { 1016 cpi->cpi_ncore_per_chip = 1017 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1018 } 1019 break; 1020 case X86_VENDOR_AMD: 1021 if (cpi->cpi_xmaxeax < 0x80000008) { 1022 cpi->cpi_ncore_per_chip = 1; 1023 break; 1024 } else { 1025 /* 1026 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 1027 * 1 less than the number of physical cores on 1028 * the chip. In family 0x10 this value can 1029 * be affected by "downcoring" - it reflects 1030 * 1 less than the number of cores actually 1031 * enabled on this node. 1032 */ 1033 cpi->cpi_ncore_per_chip = 1034 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1035 } 1036 break; 1037 default: 1038 cpi->cpi_ncore_per_chip = 1; 1039 break; 1040 } 1041 1042 /* 1043 * Get CPUID data about TSC Invariance in Deep C-State. 1044 */ 1045 switch (cpi->cpi_vendor) { 1046 case X86_VENDOR_Intel: 1047 if (cpi->cpi_maxeax >= 7) { 1048 cp = &cpi->cpi_extd[7]; 1049 cp->cp_eax = 0x80000007; 1050 cp->cp_ecx = 0; 1051 (void) __cpuid_insn(cp); 1052 } 1053 break; 1054 default: 1055 break; 1056 } 1057 } else { 1058 cpi->cpi_ncore_per_chip = 1; 1059 } 1060 1061 /* 1062 * If more than one core, then this processor is CMP. 1063 */ 1064 if (cpi->cpi_ncore_per_chip > 1) 1065 feature |= X86_CMP; 1066 1067 /* 1068 * If the number of cores is the same as the number 1069 * of CPUs, then we cannot have HyperThreading. 1070 */ 1071 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1072 feature &= ~X86_HTT; 1073 1074 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1075 /* 1076 * Single-core single-threaded processors. 1077 */ 1078 cpi->cpi_chipid = -1; 1079 cpi->cpi_clogid = 0; 1080 cpi->cpi_coreid = cpu->cpu_id; 1081 cpi->cpi_pkgcoreid = 0; 1082 } else if (cpi->cpi_ncpu_per_chip > 1) { 1083 uint_t i; 1084 uint_t chipid_shift = 0; 1085 uint_t coreid_shift = 0; 1086 uint_t apic_id = CPI_APIC_ID(cpi); 1087 1088 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1089 chipid_shift++; 1090 cpi->cpi_chipid = apic_id >> chipid_shift; 1091 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1092 1093 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1094 if (feature & X86_CMP) { 1095 /* 1096 * Multi-core (and possibly multi-threaded) 1097 * processors. 1098 */ 1099 uint_t ncpu_per_core; 1100 if (cpi->cpi_ncore_per_chip == 1) 1101 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1102 else if (cpi->cpi_ncore_per_chip > 1) 1103 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1104 cpi->cpi_ncore_per_chip; 1105 /* 1106 * 8bit APIC IDs on dual core Pentiums 1107 * look like this: 1108 * 1109 * +-----------------------+------+------+ 1110 * | Physical Package ID | MC | HT | 1111 * +-----------------------+------+------+ 1112 * <------- chipid --------> 1113 * <------- coreid ---------------> 1114 * <--- clogid --> 1115 * <------> 1116 * pkgcoreid 1117 * 1118 * Where the number of bits necessary to 1119 * represent MC and HT fields together equals 1120 * to the minimum number of bits necessary to 1121 * store the value of cpi->cpi_ncpu_per_chip. 1122 * Of those bits, the MC part uses the number 1123 * of bits necessary to store the value of 1124 * cpi->cpi_ncore_per_chip. 1125 */ 1126 for (i = 1; i < ncpu_per_core; i <<= 1) 1127 coreid_shift++; 1128 cpi->cpi_coreid = apic_id >> coreid_shift; 1129 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> 1130 coreid_shift; 1131 } else if (feature & X86_HTT) { 1132 /* 1133 * Single-core multi-threaded processors. 1134 */ 1135 cpi->cpi_coreid = cpi->cpi_chipid; 1136 cpi->cpi_pkgcoreid = 0; 1137 } 1138 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1139 /* 1140 * AMD CMP chips currently have a single thread per 1141 * core, with 2 cores on family 0xf and 2, 3 or 4 1142 * cores on family 0x10. 1143 * 1144 * Since no two cpus share a core we must assign a 1145 * distinct coreid per cpu, and we do this by using 1146 * the cpu_id. This scheme does not, however, 1147 * guarantee that sibling cores of a chip will have 1148 * sequential coreids starting at a multiple of the 1149 * number of cores per chip - that is usually the 1150 * case, but if the ACPI MADT table is presented 1151 * in a different order then we need to perform a 1152 * few more gymnastics for the pkgcoreid. 1153 * 1154 * In family 0xf CMPs there are 2 cores on all nodes 1155 * present - no mixing of single and dual core parts. 1156 * 1157 * In family 0x10 CMPs cpuid fn 2 ECX[15:12] 1158 * "ApicIdCoreIdSize[3:0]" tells us how 1159 * many least-significant bits in the ApicId 1160 * are used to represent the core number 1161 * within the node. Cores are always 1162 * numbered sequentially from 0 regardless 1163 * of how many or which are disabled, and 1164 * there seems to be no way to discover the 1165 * real core id when some are disabled. 1166 */ 1167 cpi->cpi_coreid = cpu->cpu_id; 1168 1169 if (cpi->cpi_family == 0x10 && 1170 cpi->cpi_xmaxeax >= 0x80000008) { 1171 int coreidsz = 1172 BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 1173 1174 cpi->cpi_pkgcoreid = 1175 apic_id & ((1 << coreidsz) - 1); 1176 } else { 1177 cpi->cpi_pkgcoreid = cpi->cpi_clogid; 1178 } 1179 } else { 1180 /* 1181 * All other processors are currently 1182 * assumed to have single cores. 1183 */ 1184 cpi->cpi_coreid = cpi->cpi_chipid; 1185 cpi->cpi_pkgcoreid = 0; 1186 } 1187 } 1188 1189 cpi->cpi_apicid = CPI_APIC_ID(cpi); 1190 1191 /* 1192 * Synthesize chip "revision" and socket type 1193 */ 1194 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1195 cpi->cpi_model, cpi->cpi_step); 1196 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1197 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1198 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1199 cpi->cpi_model, cpi->cpi_step); 1200 1201 pass1_done: 1202 #if !defined(__xpv) 1203 check_for_hvm(); 1204 #endif 1205 cpi->cpi_pass = 1; 1206 return (feature); 1207 } 1208 1209 /* 1210 * Make copies of the cpuid table entries we depend on, in 1211 * part for ease of parsing now, in part so that we have only 1212 * one place to correct any of it, in part for ease of 1213 * later export to userland, and in part so we can look at 1214 * this stuff in a crash dump. 1215 */ 1216 1217 /*ARGSUSED*/ 1218 void 1219 cpuid_pass2(cpu_t *cpu) 1220 { 1221 uint_t n, nmax; 1222 int i; 1223 struct cpuid_regs *cp; 1224 uint8_t *dp; 1225 uint32_t *iptr; 1226 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1227 1228 ASSERT(cpi->cpi_pass == 1); 1229 1230 if (cpi->cpi_maxeax < 1) 1231 goto pass2_done; 1232 1233 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1234 nmax = NMAX_CPI_STD; 1235 /* 1236 * (We already handled n == 0 and n == 1 in pass 1) 1237 */ 1238 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1239 cp->cp_eax = n; 1240 1241 /* 1242 * CPUID function 4 expects %ecx to be initialized 1243 * with an index which indicates which cache to return 1244 * information about. The OS is expected to call function 4 1245 * with %ecx set to 0, 1, 2, ... until it returns with 1246 * EAX[4:0] set to 0, which indicates there are no more 1247 * caches. 1248 * 1249 * Here, populate cpi_std[4] with the information returned by 1250 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1251 * when dynamic memory allocation becomes available. 1252 * 1253 * Note: we need to explicitly initialize %ecx here, since 1254 * function 4 may have been previously invoked. 1255 */ 1256 if (n == 4) 1257 cp->cp_ecx = 0; 1258 1259 (void) __cpuid_insn(cp); 1260 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1261 switch (n) { 1262 case 2: 1263 /* 1264 * "the lower 8 bits of the %eax register 1265 * contain a value that identifies the number 1266 * of times the cpuid [instruction] has to be 1267 * executed to obtain a complete image of the 1268 * processor's caching systems." 1269 * 1270 * How *do* they make this stuff up? 1271 */ 1272 cpi->cpi_ncache = sizeof (*cp) * 1273 BITX(cp->cp_eax, 7, 0); 1274 if (cpi->cpi_ncache == 0) 1275 break; 1276 cpi->cpi_ncache--; /* skip count byte */ 1277 1278 /* 1279 * Well, for now, rather than attempt to implement 1280 * this slightly dubious algorithm, we just look 1281 * at the first 15 .. 1282 */ 1283 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1284 cpi->cpi_ncache = sizeof (*cp) - 1; 1285 1286 dp = cpi->cpi_cacheinfo; 1287 if (BITX(cp->cp_eax, 31, 31) == 0) { 1288 uint8_t *p = (void *)&cp->cp_eax; 1289 for (i = 1; i < 4; i++) 1290 if (p[i] != 0) 1291 *dp++ = p[i]; 1292 } 1293 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1294 uint8_t *p = (void *)&cp->cp_ebx; 1295 for (i = 0; i < 4; i++) 1296 if (p[i] != 0) 1297 *dp++ = p[i]; 1298 } 1299 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1300 uint8_t *p = (void *)&cp->cp_ecx; 1301 for (i = 0; i < 4; i++) 1302 if (p[i] != 0) 1303 *dp++ = p[i]; 1304 } 1305 if (BITX(cp->cp_edx, 31, 31) == 0) { 1306 uint8_t *p = (void *)&cp->cp_edx; 1307 for (i = 0; i < 4; i++) 1308 if (p[i] != 0) 1309 *dp++ = p[i]; 1310 } 1311 break; 1312 1313 case 3: /* Processor serial number, if PSN supported */ 1314 break; 1315 1316 case 4: /* Deterministic cache parameters */ 1317 break; 1318 1319 case 5: /* Monitor/Mwait parameters */ 1320 { 1321 size_t mwait_size; 1322 1323 /* 1324 * check cpi_mwait.support which was set in cpuid_pass1 1325 */ 1326 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1327 break; 1328 1329 /* 1330 * Protect ourself from insane mwait line size. 1331 * Workaround for incomplete hardware emulator(s). 1332 */ 1333 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1334 if (mwait_size < sizeof (uint32_t) || 1335 !ISP2(mwait_size)) { 1336 #if DEBUG 1337 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1338 "size %ld", cpu->cpu_id, (long)mwait_size); 1339 #endif 1340 break; 1341 } 1342 1343 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1344 cpi->cpi_mwait.mon_max = mwait_size; 1345 if (MWAIT_EXTENSION(cpi)) { 1346 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1347 if (MWAIT_INT_ENABLE(cpi)) 1348 cpi->cpi_mwait.support |= 1349 MWAIT_ECX_INT_ENABLE; 1350 } 1351 break; 1352 } 1353 default: 1354 break; 1355 } 1356 } 1357 1358 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 1359 struct cpuid_regs regs; 1360 1361 cp = ®s; 1362 cp->cp_eax = 0xB; 1363 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1364 1365 (void) __cpuid_insn(cp); 1366 1367 /* 1368 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1369 * indicates that the extended topology enumeration leaf is 1370 * available. 1371 */ 1372 if (cp->cp_ebx) { 1373 uint32_t x2apic_id; 1374 uint_t coreid_shift = 0; 1375 uint_t ncpu_per_core = 1; 1376 uint_t chipid_shift = 0; 1377 uint_t ncpu_per_chip = 1; 1378 uint_t i; 1379 uint_t level; 1380 1381 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1382 cp->cp_eax = 0xB; 1383 cp->cp_ecx = i; 1384 1385 (void) __cpuid_insn(cp); 1386 level = CPI_CPU_LEVEL_TYPE(cp); 1387 1388 if (level == 1) { 1389 x2apic_id = cp->cp_edx; 1390 coreid_shift = BITX(cp->cp_eax, 4, 0); 1391 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1392 } else if (level == 2) { 1393 x2apic_id = cp->cp_edx; 1394 chipid_shift = BITX(cp->cp_eax, 4, 0); 1395 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1396 } 1397 } 1398 1399 cpi->cpi_apicid = x2apic_id; 1400 cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1401 cpi->cpi_ncore_per_chip = ncpu_per_chip / 1402 ncpu_per_core; 1403 cpi->cpi_chipid = x2apic_id >> chipid_shift; 1404 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1405 cpi->cpi_coreid = x2apic_id >> coreid_shift; 1406 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1407 } 1408 1409 /* Make cp NULL so that we don't stumble on others */ 1410 cp = NULL; 1411 } 1412 1413 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1414 goto pass2_done; 1415 1416 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1417 nmax = NMAX_CPI_EXTD; 1418 /* 1419 * Copy the extended properties, fixing them as we go. 1420 * (We already handled n == 0 and n == 1 in pass 1) 1421 */ 1422 iptr = (void *)cpi->cpi_brandstr; 1423 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1424 cp->cp_eax = 0x80000000 + n; 1425 (void) __cpuid_insn(cp); 1426 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1427 switch (n) { 1428 case 2: 1429 case 3: 1430 case 4: 1431 /* 1432 * Extract the brand string 1433 */ 1434 *iptr++ = cp->cp_eax; 1435 *iptr++ = cp->cp_ebx; 1436 *iptr++ = cp->cp_ecx; 1437 *iptr++ = cp->cp_edx; 1438 break; 1439 case 5: 1440 switch (cpi->cpi_vendor) { 1441 case X86_VENDOR_AMD: 1442 /* 1443 * The Athlon and Duron were the first 1444 * parts to report the sizes of the 1445 * TLB for large pages. Before then, 1446 * we don't trust the data. 1447 */ 1448 if (cpi->cpi_family < 6 || 1449 (cpi->cpi_family == 6 && 1450 cpi->cpi_model < 1)) 1451 cp->cp_eax = 0; 1452 break; 1453 default: 1454 break; 1455 } 1456 break; 1457 case 6: 1458 switch (cpi->cpi_vendor) { 1459 case X86_VENDOR_AMD: 1460 /* 1461 * The Athlon and Duron were the first 1462 * AMD parts with L2 TLB's. 1463 * Before then, don't trust the data. 1464 */ 1465 if (cpi->cpi_family < 6 || 1466 cpi->cpi_family == 6 && 1467 cpi->cpi_model < 1) 1468 cp->cp_eax = cp->cp_ebx = 0; 1469 /* 1470 * AMD Duron rev A0 reports L2 1471 * cache size incorrectly as 1K 1472 * when it is really 64K 1473 */ 1474 if (cpi->cpi_family == 6 && 1475 cpi->cpi_model == 3 && 1476 cpi->cpi_step == 0) { 1477 cp->cp_ecx &= 0xffff; 1478 cp->cp_ecx |= 0x400000; 1479 } 1480 break; 1481 case X86_VENDOR_Cyrix: /* VIA C3 */ 1482 /* 1483 * VIA C3 processors are a bit messed 1484 * up w.r.t. encoding cache sizes in %ecx 1485 */ 1486 if (cpi->cpi_family != 6) 1487 break; 1488 /* 1489 * model 7 and 8 were incorrectly encoded 1490 * 1491 * xxx is model 8 really broken? 1492 */ 1493 if (cpi->cpi_model == 7 || 1494 cpi->cpi_model == 8) 1495 cp->cp_ecx = 1496 BITX(cp->cp_ecx, 31, 24) << 16 | 1497 BITX(cp->cp_ecx, 23, 16) << 12 | 1498 BITX(cp->cp_ecx, 15, 8) << 8 | 1499 BITX(cp->cp_ecx, 7, 0); 1500 /* 1501 * model 9 stepping 1 has wrong associativity 1502 */ 1503 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1504 cp->cp_ecx |= 8 << 12; 1505 break; 1506 case X86_VENDOR_Intel: 1507 /* 1508 * Extended L2 Cache features function. 1509 * First appeared on Prescott. 1510 */ 1511 default: 1512 break; 1513 } 1514 break; 1515 default: 1516 break; 1517 } 1518 } 1519 1520 pass2_done: 1521 cpi->cpi_pass = 2; 1522 } 1523 1524 static const char * 1525 intel_cpubrand(const struct cpuid_info *cpi) 1526 { 1527 int i; 1528 1529 if ((x86_feature & X86_CPUID) == 0 || 1530 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1531 return ("i486"); 1532 1533 switch (cpi->cpi_family) { 1534 case 5: 1535 return ("Intel Pentium(r)"); 1536 case 6: 1537 switch (cpi->cpi_model) { 1538 uint_t celeron, xeon; 1539 const struct cpuid_regs *cp; 1540 case 0: 1541 case 1: 1542 case 2: 1543 return ("Intel Pentium(r) Pro"); 1544 case 3: 1545 case 4: 1546 return ("Intel Pentium(r) II"); 1547 case 6: 1548 return ("Intel Celeron(r)"); 1549 case 5: 1550 case 7: 1551 celeron = xeon = 0; 1552 cp = &cpi->cpi_std[2]; /* cache info */ 1553 1554 for (i = 1; i < 4; i++) { 1555 uint_t tmp; 1556 1557 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1558 if (tmp == 0x40) 1559 celeron++; 1560 if (tmp >= 0x44 && tmp <= 0x45) 1561 xeon++; 1562 } 1563 1564 for (i = 0; i < 2; i++) { 1565 uint_t tmp; 1566 1567 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1568 if (tmp == 0x40) 1569 celeron++; 1570 else if (tmp >= 0x44 && tmp <= 0x45) 1571 xeon++; 1572 } 1573 1574 for (i = 0; i < 4; i++) { 1575 uint_t tmp; 1576 1577 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1578 if (tmp == 0x40) 1579 celeron++; 1580 else if (tmp >= 0x44 && tmp <= 0x45) 1581 xeon++; 1582 } 1583 1584 for (i = 0; i < 4; i++) { 1585 uint_t tmp; 1586 1587 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1588 if (tmp == 0x40) 1589 celeron++; 1590 else if (tmp >= 0x44 && tmp <= 0x45) 1591 xeon++; 1592 } 1593 1594 if (celeron) 1595 return ("Intel Celeron(r)"); 1596 if (xeon) 1597 return (cpi->cpi_model == 5 ? 1598 "Intel Pentium(r) II Xeon(tm)" : 1599 "Intel Pentium(r) III Xeon(tm)"); 1600 return (cpi->cpi_model == 5 ? 1601 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1602 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1603 default: 1604 break; 1605 } 1606 default: 1607 break; 1608 } 1609 1610 /* BrandID is present if the field is nonzero */ 1611 if (cpi->cpi_brandid != 0) { 1612 static const struct { 1613 uint_t bt_bid; 1614 const char *bt_str; 1615 } brand_tbl[] = { 1616 { 0x1, "Intel(r) Celeron(r)" }, 1617 { 0x2, "Intel(r) Pentium(r) III" }, 1618 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1619 { 0x4, "Intel(r) Pentium(r) III" }, 1620 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1621 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1622 { 0x8, "Intel(r) Pentium(r) 4" }, 1623 { 0x9, "Intel(r) Pentium(r) 4" }, 1624 { 0xa, "Intel(r) Celeron(r)" }, 1625 { 0xb, "Intel(r) Xeon(tm)" }, 1626 { 0xc, "Intel(r) Xeon(tm) MP" }, 1627 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1628 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1629 { 0x11, "Mobile Genuine Intel(r)" }, 1630 { 0x12, "Intel(r) Celeron(r) M" }, 1631 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1632 { 0x14, "Intel(r) Celeron(r)" }, 1633 { 0x15, "Mobile Genuine Intel(r)" }, 1634 { 0x16, "Intel(r) Pentium(r) M" }, 1635 { 0x17, "Mobile Intel(r) Celeron(r)" } 1636 }; 1637 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1638 uint_t sgn; 1639 1640 sgn = (cpi->cpi_family << 8) | 1641 (cpi->cpi_model << 4) | cpi->cpi_step; 1642 1643 for (i = 0; i < btblmax; i++) 1644 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1645 break; 1646 if (i < btblmax) { 1647 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1648 return ("Intel(r) Celeron(r)"); 1649 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1650 return ("Intel(r) Xeon(tm) MP"); 1651 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1652 return ("Intel(r) Xeon(tm)"); 1653 return (brand_tbl[i].bt_str); 1654 } 1655 } 1656 1657 return (NULL); 1658 } 1659 1660 static const char * 1661 amd_cpubrand(const struct cpuid_info *cpi) 1662 { 1663 if ((x86_feature & X86_CPUID) == 0 || 1664 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1665 return ("i486 compatible"); 1666 1667 switch (cpi->cpi_family) { 1668 case 5: 1669 switch (cpi->cpi_model) { 1670 case 0: 1671 case 1: 1672 case 2: 1673 case 3: 1674 case 4: 1675 case 5: 1676 return ("AMD-K5(r)"); 1677 case 6: 1678 case 7: 1679 return ("AMD-K6(r)"); 1680 case 8: 1681 return ("AMD-K6(r)-2"); 1682 case 9: 1683 return ("AMD-K6(r)-III"); 1684 default: 1685 return ("AMD (family 5)"); 1686 } 1687 case 6: 1688 switch (cpi->cpi_model) { 1689 case 1: 1690 return ("AMD-K7(tm)"); 1691 case 0: 1692 case 2: 1693 case 4: 1694 return ("AMD Athlon(tm)"); 1695 case 3: 1696 case 7: 1697 return ("AMD Duron(tm)"); 1698 case 6: 1699 case 8: 1700 case 10: 1701 /* 1702 * Use the L2 cache size to distinguish 1703 */ 1704 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1705 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1706 default: 1707 return ("AMD (family 6)"); 1708 } 1709 default: 1710 break; 1711 } 1712 1713 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1714 cpi->cpi_brandid != 0) { 1715 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1716 case 3: 1717 return ("AMD Opteron(tm) UP 1xx"); 1718 case 4: 1719 return ("AMD Opteron(tm) DP 2xx"); 1720 case 5: 1721 return ("AMD Opteron(tm) MP 8xx"); 1722 default: 1723 return ("AMD Opteron(tm)"); 1724 } 1725 } 1726 1727 return (NULL); 1728 } 1729 1730 static const char * 1731 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1732 { 1733 if ((x86_feature & X86_CPUID) == 0 || 1734 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1735 type == X86_TYPE_CYRIX_486) 1736 return ("i486 compatible"); 1737 1738 switch (type) { 1739 case X86_TYPE_CYRIX_6x86: 1740 return ("Cyrix 6x86"); 1741 case X86_TYPE_CYRIX_6x86L: 1742 return ("Cyrix 6x86L"); 1743 case X86_TYPE_CYRIX_6x86MX: 1744 return ("Cyrix 6x86MX"); 1745 case X86_TYPE_CYRIX_GXm: 1746 return ("Cyrix GXm"); 1747 case X86_TYPE_CYRIX_MediaGX: 1748 return ("Cyrix MediaGX"); 1749 case X86_TYPE_CYRIX_MII: 1750 return ("Cyrix M2"); 1751 case X86_TYPE_VIA_CYRIX_III: 1752 return ("VIA Cyrix M3"); 1753 default: 1754 /* 1755 * Have another wild guess .. 1756 */ 1757 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1758 return ("Cyrix 5x86"); 1759 else if (cpi->cpi_family == 5) { 1760 switch (cpi->cpi_model) { 1761 case 2: 1762 return ("Cyrix 6x86"); /* Cyrix M1 */ 1763 case 4: 1764 return ("Cyrix MediaGX"); 1765 default: 1766 break; 1767 } 1768 } else if (cpi->cpi_family == 6) { 1769 switch (cpi->cpi_model) { 1770 case 0: 1771 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1772 case 5: 1773 case 6: 1774 case 7: 1775 case 8: 1776 case 9: 1777 return ("VIA C3"); 1778 default: 1779 break; 1780 } 1781 } 1782 break; 1783 } 1784 return (NULL); 1785 } 1786 1787 /* 1788 * This only gets called in the case that the CPU extended 1789 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1790 * aren't available, or contain null bytes for some reason. 1791 */ 1792 static void 1793 fabricate_brandstr(struct cpuid_info *cpi) 1794 { 1795 const char *brand = NULL; 1796 1797 switch (cpi->cpi_vendor) { 1798 case X86_VENDOR_Intel: 1799 brand = intel_cpubrand(cpi); 1800 break; 1801 case X86_VENDOR_AMD: 1802 brand = amd_cpubrand(cpi); 1803 break; 1804 case X86_VENDOR_Cyrix: 1805 brand = cyrix_cpubrand(cpi, x86_type); 1806 break; 1807 case X86_VENDOR_NexGen: 1808 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1809 brand = "NexGen Nx586"; 1810 break; 1811 case X86_VENDOR_Centaur: 1812 if (cpi->cpi_family == 5) 1813 switch (cpi->cpi_model) { 1814 case 4: 1815 brand = "Centaur C6"; 1816 break; 1817 case 8: 1818 brand = "Centaur C2"; 1819 break; 1820 case 9: 1821 brand = "Centaur C3"; 1822 break; 1823 default: 1824 break; 1825 } 1826 break; 1827 case X86_VENDOR_Rise: 1828 if (cpi->cpi_family == 5 && 1829 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1830 brand = "Rise mP6"; 1831 break; 1832 case X86_VENDOR_SiS: 1833 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1834 brand = "SiS 55x"; 1835 break; 1836 case X86_VENDOR_TM: 1837 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1838 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1839 break; 1840 case X86_VENDOR_NSC: 1841 case X86_VENDOR_UMC: 1842 default: 1843 break; 1844 } 1845 if (brand) { 1846 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1847 return; 1848 } 1849 1850 /* 1851 * If all else fails ... 1852 */ 1853 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1854 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1855 cpi->cpi_model, cpi->cpi_step); 1856 } 1857 1858 /* 1859 * This routine is called just after kernel memory allocation 1860 * becomes available on cpu0, and as part of mp_startup() on 1861 * the other cpus. 1862 * 1863 * Fixup the brand string, and collect any information from cpuid 1864 * that requires dynamicically allocated storage to represent. 1865 */ 1866 /*ARGSUSED*/ 1867 void 1868 cpuid_pass3(cpu_t *cpu) 1869 { 1870 int i, max, shft, level, size; 1871 struct cpuid_regs regs; 1872 struct cpuid_regs *cp; 1873 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1874 1875 ASSERT(cpi->cpi_pass == 2); 1876 1877 /* 1878 * Function 4: Deterministic cache parameters 1879 * 1880 * Take this opportunity to detect the number of threads 1881 * sharing the last level cache, and construct a corresponding 1882 * cache id. The respective cpuid_info members are initialized 1883 * to the default case of "no last level cache sharing". 1884 */ 1885 cpi->cpi_ncpu_shr_last_cache = 1; 1886 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1887 1888 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1889 1890 /* 1891 * Find the # of elements (size) returned by fn 4, and along 1892 * the way detect last level cache sharing details. 1893 */ 1894 bzero(®s, sizeof (regs)); 1895 cp = ®s; 1896 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1897 cp->cp_eax = 4; 1898 cp->cp_ecx = i; 1899 1900 (void) __cpuid_insn(cp); 1901 1902 if (CPI_CACHE_TYPE(cp) == 0) 1903 break; 1904 level = CPI_CACHE_LVL(cp); 1905 if (level > max) { 1906 max = level; 1907 cpi->cpi_ncpu_shr_last_cache = 1908 CPI_NTHR_SHR_CACHE(cp) + 1; 1909 } 1910 } 1911 cpi->cpi_std_4_size = size = i; 1912 1913 /* 1914 * Allocate the cpi_std_4 array. The first element 1915 * references the regs for fn 4, %ecx == 0, which 1916 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1917 */ 1918 if (size > 0) { 1919 cpi->cpi_std_4 = 1920 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1921 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1922 1923 /* 1924 * Allocate storage to hold the additional regs 1925 * for function 4, %ecx == 1 .. cpi_std_4_size. 1926 * 1927 * The regs for fn 4, %ecx == 0 has already 1928 * been allocated as indicated above. 1929 */ 1930 for (i = 1; i < size; i++) { 1931 cp = cpi->cpi_std_4[i] = 1932 kmem_zalloc(sizeof (regs), KM_SLEEP); 1933 cp->cp_eax = 4; 1934 cp->cp_ecx = i; 1935 1936 (void) __cpuid_insn(cp); 1937 } 1938 } 1939 /* 1940 * Determine the number of bits needed to represent 1941 * the number of CPUs sharing the last level cache. 1942 * 1943 * Shift off that number of bits from the APIC id to 1944 * derive the cache id. 1945 */ 1946 shft = 0; 1947 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1948 shft++; 1949 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 1950 } 1951 1952 /* 1953 * Now fixup the brand string 1954 */ 1955 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1956 fabricate_brandstr(cpi); 1957 } else { 1958 1959 /* 1960 * If we successfully extracted a brand string from the cpuid 1961 * instruction, clean it up by removing leading spaces and 1962 * similar junk. 1963 */ 1964 if (cpi->cpi_brandstr[0]) { 1965 size_t maxlen = sizeof (cpi->cpi_brandstr); 1966 char *src, *dst; 1967 1968 dst = src = (char *)cpi->cpi_brandstr; 1969 src[maxlen - 1] = '\0'; 1970 /* 1971 * strip leading spaces 1972 */ 1973 while (*src == ' ') 1974 src++; 1975 /* 1976 * Remove any 'Genuine' or "Authentic" prefixes 1977 */ 1978 if (strncmp(src, "Genuine ", 8) == 0) 1979 src += 8; 1980 if (strncmp(src, "Authentic ", 10) == 0) 1981 src += 10; 1982 1983 /* 1984 * Now do an in-place copy. 1985 * Map (R) to (r) and (TM) to (tm). 1986 * The era of teletypes is long gone, and there's 1987 * -really- no need to shout. 1988 */ 1989 while (*src != '\0') { 1990 if (src[0] == '(') { 1991 if (strncmp(src + 1, "R)", 2) == 0) { 1992 (void) strncpy(dst, "(r)", 3); 1993 src += 3; 1994 dst += 3; 1995 continue; 1996 } 1997 if (strncmp(src + 1, "TM)", 3) == 0) { 1998 (void) strncpy(dst, "(tm)", 4); 1999 src += 4; 2000 dst += 4; 2001 continue; 2002 } 2003 } 2004 *dst++ = *src++; 2005 } 2006 *dst = '\0'; 2007 2008 /* 2009 * Finally, remove any trailing spaces 2010 */ 2011 while (--dst > cpi->cpi_brandstr) 2012 if (*dst == ' ') 2013 *dst = '\0'; 2014 else 2015 break; 2016 } else 2017 fabricate_brandstr(cpi); 2018 } 2019 cpi->cpi_pass = 3; 2020 } 2021 2022 /* 2023 * This routine is called out of bind_hwcap() much later in the life 2024 * of the kernel (post_startup()). The job of this routine is to resolve 2025 * the hardware feature support and kernel support for those features into 2026 * what we're actually going to tell applications via the aux vector. 2027 */ 2028 uint_t 2029 cpuid_pass4(cpu_t *cpu) 2030 { 2031 struct cpuid_info *cpi; 2032 uint_t hwcap_flags = 0; 2033 2034 if (cpu == NULL) 2035 cpu = CPU; 2036 cpi = cpu->cpu_m.mcpu_cpi; 2037 2038 ASSERT(cpi->cpi_pass == 3); 2039 2040 if (cpi->cpi_maxeax >= 1) { 2041 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2042 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2043 2044 *edx = CPI_FEATURES_EDX(cpi); 2045 *ecx = CPI_FEATURES_ECX(cpi); 2046 2047 /* 2048 * [these require explicit kernel support] 2049 */ 2050 if ((x86_feature & X86_SEP) == 0) 2051 *edx &= ~CPUID_INTC_EDX_SEP; 2052 2053 if ((x86_feature & X86_SSE) == 0) 2054 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2055 if ((x86_feature & X86_SSE2) == 0) 2056 *edx &= ~CPUID_INTC_EDX_SSE2; 2057 2058 if ((x86_feature & X86_HTT) == 0) 2059 *edx &= ~CPUID_INTC_EDX_HTT; 2060 2061 if ((x86_feature & X86_SSE3) == 0) 2062 *ecx &= ~CPUID_INTC_ECX_SSE3; 2063 2064 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2065 if ((x86_feature & X86_SSSE3) == 0) 2066 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2067 if ((x86_feature & X86_SSE4_1) == 0) 2068 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2069 if ((x86_feature & X86_SSE4_2) == 0) 2070 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2071 } 2072 2073 /* 2074 * [no explicit support required beyond x87 fp context] 2075 */ 2076 if (!fpu_exists) 2077 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2078 2079 /* 2080 * Now map the supported feature vector to things that we 2081 * think userland will care about. 2082 */ 2083 if (*edx & CPUID_INTC_EDX_SEP) 2084 hwcap_flags |= AV_386_SEP; 2085 if (*edx & CPUID_INTC_EDX_SSE) 2086 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2087 if (*edx & CPUID_INTC_EDX_SSE2) 2088 hwcap_flags |= AV_386_SSE2; 2089 if (*ecx & CPUID_INTC_ECX_SSE3) 2090 hwcap_flags |= AV_386_SSE3; 2091 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2092 if (*ecx & CPUID_INTC_ECX_SSSE3) 2093 hwcap_flags |= AV_386_SSSE3; 2094 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2095 hwcap_flags |= AV_386_SSE4_1; 2096 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2097 hwcap_flags |= AV_386_SSE4_2; 2098 if (*ecx & CPUID_INTC_ECX_MOVBE) 2099 hwcap_flags |= AV_386_MOVBE; 2100 } 2101 if (*ecx & CPUID_INTC_ECX_POPCNT) 2102 hwcap_flags |= AV_386_POPCNT; 2103 if (*edx & CPUID_INTC_EDX_FPU) 2104 hwcap_flags |= AV_386_FPU; 2105 if (*edx & CPUID_INTC_EDX_MMX) 2106 hwcap_flags |= AV_386_MMX; 2107 2108 if (*edx & CPUID_INTC_EDX_TSC) 2109 hwcap_flags |= AV_386_TSC; 2110 if (*edx & CPUID_INTC_EDX_CX8) 2111 hwcap_flags |= AV_386_CX8; 2112 if (*edx & CPUID_INTC_EDX_CMOV) 2113 hwcap_flags |= AV_386_CMOV; 2114 if (*ecx & CPUID_INTC_ECX_MON) 2115 hwcap_flags |= AV_386_MON; 2116 if (*ecx & CPUID_INTC_ECX_CX16) 2117 hwcap_flags |= AV_386_CX16; 2118 } 2119 2120 if (x86_feature & X86_HTT) 2121 hwcap_flags |= AV_386_PAUSE; 2122 2123 if (cpi->cpi_xmaxeax < 0x80000001) 2124 goto pass4_done; 2125 2126 switch (cpi->cpi_vendor) { 2127 struct cpuid_regs cp; 2128 uint32_t *edx, *ecx; 2129 2130 case X86_VENDOR_Intel: 2131 /* 2132 * Seems like Intel duplicated what we necessary 2133 * here to make the initial crop of 64-bit OS's work. 2134 * Hopefully, those are the only "extended" bits 2135 * they'll add. 2136 */ 2137 /*FALLTHROUGH*/ 2138 2139 case X86_VENDOR_AMD: 2140 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2141 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2142 2143 *edx = CPI_FEATURES_XTD_EDX(cpi); 2144 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2145 2146 /* 2147 * [these features require explicit kernel support] 2148 */ 2149 switch (cpi->cpi_vendor) { 2150 case X86_VENDOR_Intel: 2151 if ((x86_feature & X86_TSCP) == 0) 2152 *edx &= ~CPUID_AMD_EDX_TSCP; 2153 break; 2154 2155 case X86_VENDOR_AMD: 2156 if ((x86_feature & X86_TSCP) == 0) 2157 *edx &= ~CPUID_AMD_EDX_TSCP; 2158 if ((x86_feature & X86_SSE4A) == 0) 2159 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2160 break; 2161 2162 default: 2163 break; 2164 } 2165 2166 /* 2167 * [no explicit support required beyond 2168 * x87 fp context and exception handlers] 2169 */ 2170 if (!fpu_exists) 2171 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2172 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2173 2174 if ((x86_feature & X86_NX) == 0) 2175 *edx &= ~CPUID_AMD_EDX_NX; 2176 #if !defined(__amd64) 2177 *edx &= ~CPUID_AMD_EDX_LM; 2178 #endif 2179 /* 2180 * Now map the supported feature vector to 2181 * things that we think userland will care about. 2182 */ 2183 #if defined(__amd64) 2184 if (*edx & CPUID_AMD_EDX_SYSC) 2185 hwcap_flags |= AV_386_AMD_SYSC; 2186 #endif 2187 if (*edx & CPUID_AMD_EDX_MMXamd) 2188 hwcap_flags |= AV_386_AMD_MMX; 2189 if (*edx & CPUID_AMD_EDX_3DNow) 2190 hwcap_flags |= AV_386_AMD_3DNow; 2191 if (*edx & CPUID_AMD_EDX_3DNowx) 2192 hwcap_flags |= AV_386_AMD_3DNowx; 2193 2194 switch (cpi->cpi_vendor) { 2195 case X86_VENDOR_AMD: 2196 if (*edx & CPUID_AMD_EDX_TSCP) 2197 hwcap_flags |= AV_386_TSCP; 2198 if (*ecx & CPUID_AMD_ECX_AHF64) 2199 hwcap_flags |= AV_386_AHF; 2200 if (*ecx & CPUID_AMD_ECX_SSE4A) 2201 hwcap_flags |= AV_386_AMD_SSE4A; 2202 if (*ecx & CPUID_AMD_ECX_LZCNT) 2203 hwcap_flags |= AV_386_AMD_LZCNT; 2204 break; 2205 2206 case X86_VENDOR_Intel: 2207 if (*edx & CPUID_AMD_EDX_TSCP) 2208 hwcap_flags |= AV_386_TSCP; 2209 /* 2210 * Aarrgh. 2211 * Intel uses a different bit in the same word. 2212 */ 2213 if (*ecx & CPUID_INTC_ECX_AHF64) 2214 hwcap_flags |= AV_386_AHF; 2215 break; 2216 2217 default: 2218 break; 2219 } 2220 break; 2221 2222 case X86_VENDOR_TM: 2223 cp.cp_eax = 0x80860001; 2224 (void) __cpuid_insn(&cp); 2225 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2226 break; 2227 2228 default: 2229 break; 2230 } 2231 2232 pass4_done: 2233 cpi->cpi_pass = 4; 2234 return (hwcap_flags); 2235 } 2236 2237 2238 /* 2239 * Simulate the cpuid instruction using the data we previously 2240 * captured about this CPU. We try our best to return the truth 2241 * about the hardware, independently of kernel support. 2242 */ 2243 uint32_t 2244 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2245 { 2246 struct cpuid_info *cpi; 2247 struct cpuid_regs *xcp; 2248 2249 if (cpu == NULL) 2250 cpu = CPU; 2251 cpi = cpu->cpu_m.mcpu_cpi; 2252 2253 ASSERT(cpuid_checkpass(cpu, 3)); 2254 2255 /* 2256 * CPUID data is cached in two separate places: cpi_std for standard 2257 * CPUID functions, and cpi_extd for extended CPUID functions. 2258 */ 2259 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2260 xcp = &cpi->cpi_std[cp->cp_eax]; 2261 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2262 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2263 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2264 else 2265 /* 2266 * The caller is asking for data from an input parameter which 2267 * the kernel has not cached. In this case we go fetch from 2268 * the hardware and return the data directly to the user. 2269 */ 2270 return (__cpuid_insn(cp)); 2271 2272 cp->cp_eax = xcp->cp_eax; 2273 cp->cp_ebx = xcp->cp_ebx; 2274 cp->cp_ecx = xcp->cp_ecx; 2275 cp->cp_edx = xcp->cp_edx; 2276 return (cp->cp_eax); 2277 } 2278 2279 int 2280 cpuid_checkpass(cpu_t *cpu, int pass) 2281 { 2282 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2283 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2284 } 2285 2286 int 2287 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2288 { 2289 ASSERT(cpuid_checkpass(cpu, 3)); 2290 2291 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2292 } 2293 2294 int 2295 cpuid_is_cmt(cpu_t *cpu) 2296 { 2297 if (cpu == NULL) 2298 cpu = CPU; 2299 2300 ASSERT(cpuid_checkpass(cpu, 1)); 2301 2302 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2303 } 2304 2305 /* 2306 * AMD and Intel both implement the 64-bit variant of the syscall 2307 * instruction (syscallq), so if there's -any- support for syscall, 2308 * cpuid currently says "yes, we support this". 2309 * 2310 * However, Intel decided to -not- implement the 32-bit variant of the 2311 * syscall instruction, so we provide a predicate to allow our caller 2312 * to test that subtlety here. 2313 * 2314 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2315 * even in the case where the hardware would in fact support it. 2316 */ 2317 /*ARGSUSED*/ 2318 int 2319 cpuid_syscall32_insn(cpu_t *cpu) 2320 { 2321 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2322 2323 #if !defined(__xpv) 2324 if (cpu == NULL) 2325 cpu = CPU; 2326 2327 /*CSTYLED*/ 2328 { 2329 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2330 2331 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2332 cpi->cpi_xmaxeax >= 0x80000001 && 2333 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2334 return (1); 2335 } 2336 #endif 2337 return (0); 2338 } 2339 2340 int 2341 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2342 { 2343 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2344 2345 static const char fmt[] = 2346 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2347 static const char fmt_ht[] = 2348 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2349 2350 ASSERT(cpuid_checkpass(cpu, 1)); 2351 2352 if (cpuid_is_cmt(cpu)) 2353 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2354 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2355 cpi->cpi_family, cpi->cpi_model, 2356 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2357 return (snprintf(s, n, fmt, 2358 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2359 cpi->cpi_family, cpi->cpi_model, 2360 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2361 } 2362 2363 const char * 2364 cpuid_getvendorstr(cpu_t *cpu) 2365 { 2366 ASSERT(cpuid_checkpass(cpu, 1)); 2367 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2368 } 2369 2370 uint_t 2371 cpuid_getvendor(cpu_t *cpu) 2372 { 2373 ASSERT(cpuid_checkpass(cpu, 1)); 2374 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2375 } 2376 2377 uint_t 2378 cpuid_getfamily(cpu_t *cpu) 2379 { 2380 ASSERT(cpuid_checkpass(cpu, 1)); 2381 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2382 } 2383 2384 uint_t 2385 cpuid_getmodel(cpu_t *cpu) 2386 { 2387 ASSERT(cpuid_checkpass(cpu, 1)); 2388 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2389 } 2390 2391 uint_t 2392 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2393 { 2394 ASSERT(cpuid_checkpass(cpu, 1)); 2395 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2396 } 2397 2398 uint_t 2399 cpuid_get_ncore_per_chip(cpu_t *cpu) 2400 { 2401 ASSERT(cpuid_checkpass(cpu, 1)); 2402 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2403 } 2404 2405 uint_t 2406 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2407 { 2408 ASSERT(cpuid_checkpass(cpu, 2)); 2409 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2410 } 2411 2412 id_t 2413 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2414 { 2415 ASSERT(cpuid_checkpass(cpu, 2)); 2416 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2417 } 2418 2419 uint_t 2420 cpuid_getstep(cpu_t *cpu) 2421 { 2422 ASSERT(cpuid_checkpass(cpu, 1)); 2423 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2424 } 2425 2426 uint_t 2427 cpuid_getsig(struct cpu *cpu) 2428 { 2429 ASSERT(cpuid_checkpass(cpu, 1)); 2430 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2431 } 2432 2433 uint32_t 2434 cpuid_getchiprev(struct cpu *cpu) 2435 { 2436 ASSERT(cpuid_checkpass(cpu, 1)); 2437 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2438 } 2439 2440 const char * 2441 cpuid_getchiprevstr(struct cpu *cpu) 2442 { 2443 ASSERT(cpuid_checkpass(cpu, 1)); 2444 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2445 } 2446 2447 uint32_t 2448 cpuid_getsockettype(struct cpu *cpu) 2449 { 2450 ASSERT(cpuid_checkpass(cpu, 1)); 2451 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2452 } 2453 2454 int 2455 cpuid_get_chipid(cpu_t *cpu) 2456 { 2457 ASSERT(cpuid_checkpass(cpu, 1)); 2458 2459 if (cpuid_is_cmt(cpu)) 2460 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2461 return (cpu->cpu_id); 2462 } 2463 2464 id_t 2465 cpuid_get_coreid(cpu_t *cpu) 2466 { 2467 ASSERT(cpuid_checkpass(cpu, 1)); 2468 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2469 } 2470 2471 int 2472 cpuid_get_pkgcoreid(cpu_t *cpu) 2473 { 2474 ASSERT(cpuid_checkpass(cpu, 1)); 2475 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 2476 } 2477 2478 int 2479 cpuid_get_clogid(cpu_t *cpu) 2480 { 2481 ASSERT(cpuid_checkpass(cpu, 1)); 2482 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2483 } 2484 2485 void 2486 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2487 { 2488 struct cpuid_info *cpi; 2489 2490 if (cpu == NULL) 2491 cpu = CPU; 2492 cpi = cpu->cpu_m.mcpu_cpi; 2493 2494 ASSERT(cpuid_checkpass(cpu, 1)); 2495 2496 if (pabits) 2497 *pabits = cpi->cpi_pabits; 2498 if (vabits) 2499 *vabits = cpi->cpi_vabits; 2500 } 2501 2502 /* 2503 * Returns the number of data TLB entries for a corresponding 2504 * pagesize. If it can't be computed, or isn't known, the 2505 * routine returns zero. If you ask about an architecturally 2506 * impossible pagesize, the routine will panic (so that the 2507 * hat implementor knows that things are inconsistent.) 2508 */ 2509 uint_t 2510 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2511 { 2512 struct cpuid_info *cpi; 2513 uint_t dtlb_nent = 0; 2514 2515 if (cpu == NULL) 2516 cpu = CPU; 2517 cpi = cpu->cpu_m.mcpu_cpi; 2518 2519 ASSERT(cpuid_checkpass(cpu, 1)); 2520 2521 /* 2522 * Check the L2 TLB info 2523 */ 2524 if (cpi->cpi_xmaxeax >= 0x80000006) { 2525 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2526 2527 switch (pagesize) { 2528 2529 case 4 * 1024: 2530 /* 2531 * All zero in the top 16 bits of the register 2532 * indicates a unified TLB. Size is in low 16 bits. 2533 */ 2534 if ((cp->cp_ebx & 0xffff0000) == 0) 2535 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2536 else 2537 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2538 break; 2539 2540 case 2 * 1024 * 1024: 2541 if ((cp->cp_eax & 0xffff0000) == 0) 2542 dtlb_nent = cp->cp_eax & 0x0000ffff; 2543 else 2544 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2545 break; 2546 2547 default: 2548 panic("unknown L2 pagesize"); 2549 /*NOTREACHED*/ 2550 } 2551 } 2552 2553 if (dtlb_nent != 0) 2554 return (dtlb_nent); 2555 2556 /* 2557 * No L2 TLB support for this size, try L1. 2558 */ 2559 if (cpi->cpi_xmaxeax >= 0x80000005) { 2560 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2561 2562 switch (pagesize) { 2563 case 4 * 1024: 2564 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2565 break; 2566 case 2 * 1024 * 1024: 2567 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2568 break; 2569 default: 2570 panic("unknown L1 d-TLB pagesize"); 2571 /*NOTREACHED*/ 2572 } 2573 } 2574 2575 return (dtlb_nent); 2576 } 2577 2578 /* 2579 * Return 0 if the erratum is not present or not applicable, positive 2580 * if it is, and negative if the status of the erratum is unknown. 2581 * 2582 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2583 * Processors" #25759, Rev 3.57, August 2005 2584 */ 2585 int 2586 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2587 { 2588 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2589 uint_t eax; 2590 2591 /* 2592 * Bail out if this CPU isn't an AMD CPU, or if it's 2593 * a legacy (32-bit) AMD CPU. 2594 */ 2595 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2596 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2597 cpi->cpi_family == 6) 2598 2599 return (0); 2600 2601 eax = cpi->cpi_std[1].cp_eax; 2602 2603 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2604 #define SH_B3(eax) (eax == 0xf51) 2605 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2606 2607 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2608 2609 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2610 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2611 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2612 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2613 2614 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2615 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2616 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2617 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2618 2619 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2620 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2621 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2622 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2623 #define BH_E4(eax) (eax == 0x20fb1) 2624 #define SH_E5(eax) (eax == 0x20f42) 2625 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2626 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2627 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2628 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2629 DH_E6(eax) || JH_E6(eax)) 2630 2631 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 2632 #define DR_B0(eax) (eax == 0x100f20) 2633 #define DR_B1(eax) (eax == 0x100f21) 2634 #define DR_BA(eax) (eax == 0x100f2a) 2635 #define DR_B2(eax) (eax == 0x100f22) 2636 #define DR_B3(eax) (eax == 0x100f23) 2637 #define RB_C0(eax) (eax == 0x100f40) 2638 2639 switch (erratum) { 2640 case 1: 2641 return (cpi->cpi_family < 0x10); 2642 case 51: /* what does the asterisk mean? */ 2643 return (B(eax) || SH_C0(eax) || CG(eax)); 2644 case 52: 2645 return (B(eax)); 2646 case 57: 2647 return (cpi->cpi_family <= 0x11); 2648 case 58: 2649 return (B(eax)); 2650 case 60: 2651 return (cpi->cpi_family <= 0x11); 2652 case 61: 2653 case 62: 2654 case 63: 2655 case 64: 2656 case 65: 2657 case 66: 2658 case 68: 2659 case 69: 2660 case 70: 2661 case 71: 2662 return (B(eax)); 2663 case 72: 2664 return (SH_B0(eax)); 2665 case 74: 2666 return (B(eax)); 2667 case 75: 2668 return (cpi->cpi_family < 0x10); 2669 case 76: 2670 return (B(eax)); 2671 case 77: 2672 return (cpi->cpi_family <= 0x11); 2673 case 78: 2674 return (B(eax) || SH_C0(eax)); 2675 case 79: 2676 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2677 case 80: 2678 case 81: 2679 case 82: 2680 return (B(eax)); 2681 case 83: 2682 return (B(eax) || SH_C0(eax) || CG(eax)); 2683 case 85: 2684 return (cpi->cpi_family < 0x10); 2685 case 86: 2686 return (SH_C0(eax) || CG(eax)); 2687 case 88: 2688 #if !defined(__amd64) 2689 return (0); 2690 #else 2691 return (B(eax) || SH_C0(eax)); 2692 #endif 2693 case 89: 2694 return (cpi->cpi_family < 0x10); 2695 case 90: 2696 return (B(eax) || SH_C0(eax) || CG(eax)); 2697 case 91: 2698 case 92: 2699 return (B(eax) || SH_C0(eax)); 2700 case 93: 2701 return (SH_C0(eax)); 2702 case 94: 2703 return (B(eax) || SH_C0(eax) || CG(eax)); 2704 case 95: 2705 #if !defined(__amd64) 2706 return (0); 2707 #else 2708 return (B(eax) || SH_C0(eax)); 2709 #endif 2710 case 96: 2711 return (B(eax) || SH_C0(eax) || CG(eax)); 2712 case 97: 2713 case 98: 2714 return (SH_C0(eax) || CG(eax)); 2715 case 99: 2716 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2717 case 100: 2718 return (B(eax) || SH_C0(eax)); 2719 case 101: 2720 case 103: 2721 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2722 case 104: 2723 return (SH_C0(eax) || CG(eax) || D0(eax)); 2724 case 105: 2725 case 106: 2726 case 107: 2727 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2728 case 108: 2729 return (DH_CG(eax)); 2730 case 109: 2731 return (SH_C0(eax) || CG(eax) || D0(eax)); 2732 case 110: 2733 return (D0(eax) || EX(eax)); 2734 case 111: 2735 return (CG(eax)); 2736 case 112: 2737 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2738 case 113: 2739 return (eax == 0x20fc0); 2740 case 114: 2741 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2742 case 115: 2743 return (SH_E0(eax) || JH_E1(eax)); 2744 case 116: 2745 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2746 case 117: 2747 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2748 case 118: 2749 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2750 JH_E6(eax)); 2751 case 121: 2752 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2753 case 122: 2754 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 2755 case 123: 2756 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2757 case 131: 2758 return (cpi->cpi_family < 0x10); 2759 case 6336786: 2760 /* 2761 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2762 * if this is a K8 family or newer processor 2763 */ 2764 if (CPI_FAMILY(cpi) == 0xf) { 2765 struct cpuid_regs regs; 2766 regs.cp_eax = 0x80000007; 2767 (void) __cpuid_insn(®s); 2768 return (!(regs.cp_edx & 0x100)); 2769 } 2770 return (0); 2771 case 6323525: 2772 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2773 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2774 2775 case 6671130: 2776 /* 2777 * check for processors (pre-Shanghai) that do not provide 2778 * optimal management of 1gb ptes in its tlb. 2779 */ 2780 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 2781 2782 case 298: 2783 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 2784 DR_B2(eax) || RB_C0(eax)); 2785 2786 default: 2787 return (-1); 2788 2789 } 2790 } 2791 2792 /* 2793 * Determine if specified erratum is present via OSVW (OS Visible Workaround). 2794 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 2795 */ 2796 int 2797 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 2798 { 2799 struct cpuid_info *cpi; 2800 uint_t osvwid; 2801 static int osvwfeature = -1; 2802 uint64_t osvwlength; 2803 2804 2805 cpi = cpu->cpu_m.mcpu_cpi; 2806 2807 /* confirm OSVW supported */ 2808 if (osvwfeature == -1) { 2809 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 2810 } else { 2811 /* assert that osvw feature setting is consistent on all cpus */ 2812 ASSERT(osvwfeature == 2813 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 2814 } 2815 if (!osvwfeature) 2816 return (-1); 2817 2818 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 2819 2820 switch (erratum) { 2821 case 298: /* osvwid is 0 */ 2822 osvwid = 0; 2823 if (osvwlength <= (uint64_t)osvwid) { 2824 /* osvwid 0 is unknown */ 2825 return (-1); 2826 } 2827 2828 /* 2829 * Check the OSVW STATUS MSR to determine the state 2830 * of the erratum where: 2831 * 0 - fixed by HW 2832 * 1 - BIOS has applied the workaround when BIOS 2833 * workaround is available. (Or for other errata, 2834 * OS workaround is required.) 2835 * For a value of 1, caller will confirm that the 2836 * erratum 298 workaround has indeed been applied by BIOS. 2837 * 2838 * A 1 may be set in cpus that have a HW fix 2839 * in a mixed cpu system. Regarding erratum 298: 2840 * In a multiprocessor platform, the workaround above 2841 * should be applied to all processors regardless of 2842 * silicon revision when an affected processor is 2843 * present. 2844 */ 2845 2846 return (rdmsr(MSR_AMD_OSVW_STATUS + 2847 (osvwid / OSVW_ID_CNT_PER_MSR)) & 2848 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 2849 2850 default: 2851 return (-1); 2852 } 2853 } 2854 2855 static const char assoc_str[] = "associativity"; 2856 static const char line_str[] = "line-size"; 2857 static const char size_str[] = "size"; 2858 2859 static void 2860 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2861 uint32_t val) 2862 { 2863 char buf[128]; 2864 2865 /* 2866 * ndi_prop_update_int() is used because it is desirable for 2867 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2868 */ 2869 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2870 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2871 } 2872 2873 /* 2874 * Intel-style cache/tlb description 2875 * 2876 * Standard cpuid level 2 gives a randomly ordered 2877 * selection of tags that index into a table that describes 2878 * cache and tlb properties. 2879 */ 2880 2881 static const char l1_icache_str[] = "l1-icache"; 2882 static const char l1_dcache_str[] = "l1-dcache"; 2883 static const char l2_cache_str[] = "l2-cache"; 2884 static const char l3_cache_str[] = "l3-cache"; 2885 static const char itlb4k_str[] = "itlb-4K"; 2886 static const char dtlb4k_str[] = "dtlb-4K"; 2887 static const char itlb2M_str[] = "itlb-2M"; 2888 static const char itlb4M_str[] = "itlb-4M"; 2889 static const char dtlb4M_str[] = "dtlb-4M"; 2890 static const char dtlb24_str[] = "dtlb0-2M-4M"; 2891 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2892 static const char itlb24_str[] = "itlb-2M-4M"; 2893 static const char dtlb44_str[] = "dtlb-4K-4M"; 2894 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2895 static const char sl2_cache_str[] = "sectored-l2-cache"; 2896 static const char itrace_str[] = "itrace-cache"; 2897 static const char sl3_cache_str[] = "sectored-l3-cache"; 2898 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 2899 2900 static const struct cachetab { 2901 uint8_t ct_code; 2902 uint8_t ct_assoc; 2903 uint16_t ct_line_size; 2904 size_t ct_size; 2905 const char *ct_label; 2906 } intel_ctab[] = { 2907 /* 2908 * maintain descending order! 2909 * 2910 * Codes ignored - Reason 2911 * ---------------------- 2912 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 2913 * f0H/f1H - Currently we do not interpret prefetch size by design 2914 */ 2915 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 2916 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 2917 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 2918 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 2919 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 2920 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 2921 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 2922 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 2923 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 2924 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 2925 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 2926 { 0xd0, 4, 64, 512*1024, l3_cache_str}, 2927 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 2928 { 0xc0, 4, 0, 8, dtlb44_str }, 2929 { 0xba, 4, 0, 64, dtlb4k_str }, 2930 { 0xb4, 4, 0, 256, dtlb4k_str }, 2931 { 0xb3, 4, 0, 128, dtlb4k_str }, 2932 { 0xb2, 4, 0, 64, itlb4k_str }, 2933 { 0xb0, 4, 0, 128, itlb4k_str }, 2934 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2935 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2936 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2937 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2938 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2939 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2940 { 0x80, 8, 64, 512*1024, l2_cache_str}, 2941 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2942 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2943 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2944 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2945 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2946 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2947 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2948 { 0x73, 8, 0, 64*1024, itrace_str}, 2949 { 0x72, 8, 0, 32*1024, itrace_str}, 2950 { 0x71, 8, 0, 16*1024, itrace_str}, 2951 { 0x70, 8, 0, 12*1024, itrace_str}, 2952 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2953 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2954 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2955 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2956 { 0x5d, 0, 0, 256, dtlb44_str}, 2957 { 0x5c, 0, 0, 128, dtlb44_str}, 2958 { 0x5b, 0, 0, 64, dtlb44_str}, 2959 { 0x5a, 4, 0, 32, dtlb24_str}, 2960 { 0x59, 0, 0, 16, dtlb4k_str}, 2961 { 0x57, 4, 0, 16, dtlb4k_str}, 2962 { 0x56, 4, 0, 16, dtlb4M_str}, 2963 { 0x55, 0, 0, 7, itlb24_str}, 2964 { 0x52, 0, 0, 256, itlb424_str}, 2965 { 0x51, 0, 0, 128, itlb424_str}, 2966 { 0x50, 0, 0, 64, itlb424_str}, 2967 { 0x4f, 0, 0, 32, itlb4k_str}, 2968 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 2969 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2970 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2971 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2972 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2973 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2974 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 2975 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2976 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2977 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2978 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2979 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2980 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2981 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2982 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2983 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2984 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2985 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2986 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2987 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2988 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2989 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2990 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2991 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2992 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2993 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2994 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 2995 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 2996 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2997 { 0x0b, 4, 0, 4, itlb4M_str}, 2998 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2999 { 0x08, 4, 32, 16*1024, l1_icache_str}, 3000 { 0x06, 4, 32, 8*1024, l1_icache_str}, 3001 { 0x05, 4, 0, 32, dtlb4M_str}, 3002 { 0x04, 4, 0, 8, dtlb4M_str}, 3003 { 0x03, 4, 0, 64, dtlb4k_str}, 3004 { 0x02, 4, 0, 2, itlb4M_str}, 3005 { 0x01, 4, 0, 32, itlb4k_str}, 3006 { 0 } 3007 }; 3008 3009 static const struct cachetab cyrix_ctab[] = { 3010 { 0x70, 4, 0, 32, "tlb-4K" }, 3011 { 0x80, 4, 16, 16*1024, "l1-cache" }, 3012 { 0 } 3013 }; 3014 3015 /* 3016 * Search a cache table for a matching entry 3017 */ 3018 static const struct cachetab * 3019 find_cacheent(const struct cachetab *ct, uint_t code) 3020 { 3021 if (code != 0) { 3022 for (; ct->ct_code != 0; ct++) 3023 if (ct->ct_code <= code) 3024 break; 3025 if (ct->ct_code == code) 3026 return (ct); 3027 } 3028 return (NULL); 3029 } 3030 3031 /* 3032 * Populate cachetab entry with L2 or L3 cache-information using 3033 * cpuid function 4. This function is called from intel_walk_cacheinfo() 3034 * when descriptor 0x49 is encountered. It returns 0 if no such cache 3035 * information is found. 3036 */ 3037 static int 3038 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 3039 { 3040 uint32_t level, i; 3041 int ret = 0; 3042 3043 for (i = 0; i < cpi->cpi_std_4_size; i++) { 3044 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 3045 3046 if (level == 2 || level == 3) { 3047 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 3048 ct->ct_line_size = 3049 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 3050 ct->ct_size = ct->ct_assoc * 3051 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 3052 ct->ct_line_size * 3053 (cpi->cpi_std_4[i]->cp_ecx + 1); 3054 3055 if (level == 2) { 3056 ct->ct_label = l2_cache_str; 3057 } else if (level == 3) { 3058 ct->ct_label = l3_cache_str; 3059 } 3060 ret = 1; 3061 } 3062 } 3063 3064 return (ret); 3065 } 3066 3067 /* 3068 * Walk the cacheinfo descriptor, applying 'func' to every valid element 3069 * The walk is terminated if the walker returns non-zero. 3070 */ 3071 static void 3072 intel_walk_cacheinfo(struct cpuid_info *cpi, 3073 void *arg, int (*func)(void *, const struct cachetab *)) 3074 { 3075 const struct cachetab *ct; 3076 struct cachetab des_49_ct, des_b1_ct; 3077 uint8_t *dp; 3078 int i; 3079 3080 if ((dp = cpi->cpi_cacheinfo) == NULL) 3081 return; 3082 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3083 /* 3084 * For overloaded descriptor 0x49 we use cpuid function 4 3085 * if supported by the current processor, to create 3086 * cache information. 3087 * For overloaded descriptor 0xb1 we use X86_PAE flag 3088 * to disambiguate the cache information. 3089 */ 3090 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 3091 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 3092 ct = &des_49_ct; 3093 } else if (*dp == 0xb1) { 3094 des_b1_ct.ct_code = 0xb1; 3095 des_b1_ct.ct_assoc = 4; 3096 des_b1_ct.ct_line_size = 0; 3097 if (x86_feature & X86_PAE) { 3098 des_b1_ct.ct_size = 8; 3099 des_b1_ct.ct_label = itlb2M_str; 3100 } else { 3101 des_b1_ct.ct_size = 4; 3102 des_b1_ct.ct_label = itlb4M_str; 3103 } 3104 ct = &des_b1_ct; 3105 } else { 3106 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3107 continue; 3108 } 3109 } 3110 3111 if (func(arg, ct) != 0) { 3112 break; 3113 } 3114 } 3115 } 3116 3117 /* 3118 * (Like the Intel one, except for Cyrix CPUs) 3119 */ 3120 static void 3121 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 3122 void *arg, int (*func)(void *, const struct cachetab *)) 3123 { 3124 const struct cachetab *ct; 3125 uint8_t *dp; 3126 int i; 3127 3128 if ((dp = cpi->cpi_cacheinfo) == NULL) 3129 return; 3130 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3131 /* 3132 * Search Cyrix-specific descriptor table first .. 3133 */ 3134 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 3135 if (func(arg, ct) != 0) 3136 break; 3137 continue; 3138 } 3139 /* 3140 * .. else fall back to the Intel one 3141 */ 3142 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 3143 if (func(arg, ct) != 0) 3144 break; 3145 continue; 3146 } 3147 } 3148 } 3149 3150 /* 3151 * A cacheinfo walker that adds associativity, line-size, and size properties 3152 * to the devinfo node it is passed as an argument. 3153 */ 3154 static int 3155 add_cacheent_props(void *arg, const struct cachetab *ct) 3156 { 3157 dev_info_t *devi = arg; 3158 3159 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 3160 if (ct->ct_line_size != 0) 3161 add_cache_prop(devi, ct->ct_label, line_str, 3162 ct->ct_line_size); 3163 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 3164 return (0); 3165 } 3166 3167 3168 static const char fully_assoc[] = "fully-associative?"; 3169 3170 /* 3171 * AMD style cache/tlb description 3172 * 3173 * Extended functions 5 and 6 directly describe properties of 3174 * tlbs and various cache levels. 3175 */ 3176 static void 3177 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3178 { 3179 switch (assoc) { 3180 case 0: /* reserved; ignore */ 3181 break; 3182 default: 3183 add_cache_prop(devi, label, assoc_str, assoc); 3184 break; 3185 case 0xff: 3186 add_cache_prop(devi, label, fully_assoc, 1); 3187 break; 3188 } 3189 } 3190 3191 static void 3192 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3193 { 3194 if (size == 0) 3195 return; 3196 add_cache_prop(devi, label, size_str, size); 3197 add_amd_assoc(devi, label, assoc); 3198 } 3199 3200 static void 3201 add_amd_cache(dev_info_t *devi, const char *label, 3202 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3203 { 3204 if (size == 0 || line_size == 0) 3205 return; 3206 add_amd_assoc(devi, label, assoc); 3207 /* 3208 * Most AMD parts have a sectored cache. Multiple cache lines are 3209 * associated with each tag. A sector consists of all cache lines 3210 * associated with a tag. For example, the AMD K6-III has a sector 3211 * size of 2 cache lines per tag. 3212 */ 3213 if (lines_per_tag != 0) 3214 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3215 add_cache_prop(devi, label, line_str, line_size); 3216 add_cache_prop(devi, label, size_str, size * 1024); 3217 } 3218 3219 static void 3220 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3221 { 3222 switch (assoc) { 3223 case 0: /* off */ 3224 break; 3225 case 1: 3226 case 2: 3227 case 4: 3228 add_cache_prop(devi, label, assoc_str, assoc); 3229 break; 3230 case 6: 3231 add_cache_prop(devi, label, assoc_str, 8); 3232 break; 3233 case 8: 3234 add_cache_prop(devi, label, assoc_str, 16); 3235 break; 3236 case 0xf: 3237 add_cache_prop(devi, label, fully_assoc, 1); 3238 break; 3239 default: /* reserved; ignore */ 3240 break; 3241 } 3242 } 3243 3244 static void 3245 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3246 { 3247 if (size == 0 || assoc == 0) 3248 return; 3249 add_amd_l2_assoc(devi, label, assoc); 3250 add_cache_prop(devi, label, size_str, size); 3251 } 3252 3253 static void 3254 add_amd_l2_cache(dev_info_t *devi, const char *label, 3255 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3256 { 3257 if (size == 0 || assoc == 0 || line_size == 0) 3258 return; 3259 add_amd_l2_assoc(devi, label, assoc); 3260 if (lines_per_tag != 0) 3261 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3262 add_cache_prop(devi, label, line_str, line_size); 3263 add_cache_prop(devi, label, size_str, size * 1024); 3264 } 3265 3266 static void 3267 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3268 { 3269 struct cpuid_regs *cp; 3270 3271 if (cpi->cpi_xmaxeax < 0x80000005) 3272 return; 3273 cp = &cpi->cpi_extd[5]; 3274 3275 /* 3276 * 4M/2M L1 TLB configuration 3277 * 3278 * We report the size for 2M pages because AMD uses two 3279 * TLB entries for one 4M page. 3280 */ 3281 add_amd_tlb(devi, "dtlb-2M", 3282 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3283 add_amd_tlb(devi, "itlb-2M", 3284 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3285 3286 /* 3287 * 4K L1 TLB configuration 3288 */ 3289 3290 switch (cpi->cpi_vendor) { 3291 uint_t nentries; 3292 case X86_VENDOR_TM: 3293 if (cpi->cpi_family >= 5) { 3294 /* 3295 * Crusoe processors have 256 TLB entries, but 3296 * cpuid data format constrains them to only 3297 * reporting 255 of them. 3298 */ 3299 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3300 nentries = 256; 3301 /* 3302 * Crusoe processors also have a unified TLB 3303 */ 3304 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3305 nentries); 3306 break; 3307 } 3308 /*FALLTHROUGH*/ 3309 default: 3310 add_amd_tlb(devi, itlb4k_str, 3311 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3312 add_amd_tlb(devi, dtlb4k_str, 3313 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3314 break; 3315 } 3316 3317 /* 3318 * data L1 cache configuration 3319 */ 3320 3321 add_amd_cache(devi, l1_dcache_str, 3322 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3323 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3324 3325 /* 3326 * code L1 cache configuration 3327 */ 3328 3329 add_amd_cache(devi, l1_icache_str, 3330 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3331 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3332 3333 if (cpi->cpi_xmaxeax < 0x80000006) 3334 return; 3335 cp = &cpi->cpi_extd[6]; 3336 3337 /* Check for a unified L2 TLB for large pages */ 3338 3339 if (BITX(cp->cp_eax, 31, 16) == 0) 3340 add_amd_l2_tlb(devi, "l2-tlb-2M", 3341 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3342 else { 3343 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3344 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3345 add_amd_l2_tlb(devi, "l2-itlb-2M", 3346 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3347 } 3348 3349 /* Check for a unified L2 TLB for 4K pages */ 3350 3351 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3352 add_amd_l2_tlb(devi, "l2-tlb-4K", 3353 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3354 } else { 3355 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3356 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3357 add_amd_l2_tlb(devi, "l2-itlb-4K", 3358 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3359 } 3360 3361 add_amd_l2_cache(devi, l2_cache_str, 3362 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3363 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3364 } 3365 3366 /* 3367 * There are two basic ways that the x86 world describes it cache 3368 * and tlb architecture - Intel's way and AMD's way. 3369 * 3370 * Return which flavor of cache architecture we should use 3371 */ 3372 static int 3373 x86_which_cacheinfo(struct cpuid_info *cpi) 3374 { 3375 switch (cpi->cpi_vendor) { 3376 case X86_VENDOR_Intel: 3377 if (cpi->cpi_maxeax >= 2) 3378 return (X86_VENDOR_Intel); 3379 break; 3380 case X86_VENDOR_AMD: 3381 /* 3382 * The K5 model 1 was the first part from AMD that reported 3383 * cache sizes via extended cpuid functions. 3384 */ 3385 if (cpi->cpi_family > 5 || 3386 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3387 return (X86_VENDOR_AMD); 3388 break; 3389 case X86_VENDOR_TM: 3390 if (cpi->cpi_family >= 5) 3391 return (X86_VENDOR_AMD); 3392 /*FALLTHROUGH*/ 3393 default: 3394 /* 3395 * If they have extended CPU data for 0x80000005 3396 * then we assume they have AMD-format cache 3397 * information. 3398 * 3399 * If not, and the vendor happens to be Cyrix, 3400 * then try our-Cyrix specific handler. 3401 * 3402 * If we're not Cyrix, then assume we're using Intel's 3403 * table-driven format instead. 3404 */ 3405 if (cpi->cpi_xmaxeax >= 0x80000005) 3406 return (X86_VENDOR_AMD); 3407 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3408 return (X86_VENDOR_Cyrix); 3409 else if (cpi->cpi_maxeax >= 2) 3410 return (X86_VENDOR_Intel); 3411 break; 3412 } 3413 return (-1); 3414 } 3415 3416 /* 3417 * create a node for the given cpu under the prom root node. 3418 * Also, create a cpu node in the device tree. 3419 */ 3420 static dev_info_t *cpu_nex_devi = NULL; 3421 static kmutex_t cpu_node_lock; 3422 3423 /* 3424 * Called from post_startup() and mp_startup() 3425 */ 3426 void 3427 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3428 { 3429 dev_info_t *cpu_devi; 3430 int create; 3431 3432 mutex_enter(&cpu_node_lock); 3433 3434 /* 3435 * create a nexus node for all cpus identified as 'cpu_id' under 3436 * the root node. 3437 */ 3438 if (cpu_nex_devi == NULL) { 3439 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3440 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3441 mutex_exit(&cpu_node_lock); 3442 return; 3443 } 3444 (void) ndi_devi_online(cpu_nex_devi, 0); 3445 } 3446 3447 /* 3448 * create a child node for cpu identified as 'cpu_id' 3449 */ 3450 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3451 cpu_id); 3452 if (cpu_devi == NULL) { 3453 mutex_exit(&cpu_node_lock); 3454 return; 3455 } 3456 3457 /* device_type */ 3458 3459 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3460 "device_type", "cpu"); 3461 3462 /* reg */ 3463 3464 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3465 "reg", cpu_id); 3466 3467 /* cpu-mhz, and clock-frequency */ 3468 3469 if (cpu_freq > 0) { 3470 long long mul; 3471 3472 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3473 "cpu-mhz", cpu_freq); 3474 3475 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3476 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3477 "clock-frequency", (int)mul); 3478 } 3479 3480 (void) ndi_devi_online(cpu_devi, 0); 3481 3482 if ((x86_feature & X86_CPUID) == 0) { 3483 mutex_exit(&cpu_node_lock); 3484 return; 3485 } 3486 3487 /* vendor-id */ 3488 3489 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3490 "vendor-id", cpi->cpi_vendorstr); 3491 3492 if (cpi->cpi_maxeax == 0) { 3493 mutex_exit(&cpu_node_lock); 3494 return; 3495 } 3496 3497 /* 3498 * family, model, and step 3499 */ 3500 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3501 "family", CPI_FAMILY(cpi)); 3502 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3503 "cpu-model", CPI_MODEL(cpi)); 3504 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3505 "stepping-id", CPI_STEP(cpi)); 3506 3507 /* type */ 3508 3509 switch (cpi->cpi_vendor) { 3510 case X86_VENDOR_Intel: 3511 create = 1; 3512 break; 3513 default: 3514 create = 0; 3515 break; 3516 } 3517 if (create) 3518 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3519 "type", CPI_TYPE(cpi)); 3520 3521 /* ext-family */ 3522 3523 switch (cpi->cpi_vendor) { 3524 case X86_VENDOR_Intel: 3525 case X86_VENDOR_AMD: 3526 create = cpi->cpi_family >= 0xf; 3527 break; 3528 default: 3529 create = 0; 3530 break; 3531 } 3532 if (create) 3533 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3534 "ext-family", CPI_FAMILY_XTD(cpi)); 3535 3536 /* ext-model */ 3537 3538 switch (cpi->cpi_vendor) { 3539 case X86_VENDOR_Intel: 3540 create = IS_EXTENDED_MODEL_INTEL(cpi); 3541 break; 3542 case X86_VENDOR_AMD: 3543 create = CPI_FAMILY(cpi) == 0xf; 3544 break; 3545 default: 3546 create = 0; 3547 break; 3548 } 3549 if (create) 3550 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3551 "ext-model", CPI_MODEL_XTD(cpi)); 3552 3553 /* generation */ 3554 3555 switch (cpi->cpi_vendor) { 3556 case X86_VENDOR_AMD: 3557 /* 3558 * AMD K5 model 1 was the first part to support this 3559 */ 3560 create = cpi->cpi_xmaxeax >= 0x80000001; 3561 break; 3562 default: 3563 create = 0; 3564 break; 3565 } 3566 if (create) 3567 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3568 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3569 3570 /* brand-id */ 3571 3572 switch (cpi->cpi_vendor) { 3573 case X86_VENDOR_Intel: 3574 /* 3575 * brand id first appeared on Pentium III Xeon model 8, 3576 * and Celeron model 8 processors and Opteron 3577 */ 3578 create = cpi->cpi_family > 6 || 3579 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3580 break; 3581 case X86_VENDOR_AMD: 3582 create = cpi->cpi_family >= 0xf; 3583 break; 3584 default: 3585 create = 0; 3586 break; 3587 } 3588 if (create && cpi->cpi_brandid != 0) { 3589 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3590 "brand-id", cpi->cpi_brandid); 3591 } 3592 3593 /* chunks, and apic-id */ 3594 3595 switch (cpi->cpi_vendor) { 3596 /* 3597 * first available on Pentium IV and Opteron (K8) 3598 */ 3599 case X86_VENDOR_Intel: 3600 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3601 break; 3602 case X86_VENDOR_AMD: 3603 create = cpi->cpi_family >= 0xf; 3604 break; 3605 default: 3606 create = 0; 3607 break; 3608 } 3609 if (create) { 3610 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3611 "chunks", CPI_CHUNKS(cpi)); 3612 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3613 "apic-id", cpi->cpi_apicid); 3614 if (cpi->cpi_chipid >= 0) { 3615 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3616 "chip#", cpi->cpi_chipid); 3617 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3618 "clog#", cpi->cpi_clogid); 3619 } 3620 } 3621 3622 /* cpuid-features */ 3623 3624 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3625 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3626 3627 3628 /* cpuid-features-ecx */ 3629 3630 switch (cpi->cpi_vendor) { 3631 case X86_VENDOR_Intel: 3632 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3633 break; 3634 default: 3635 create = 0; 3636 break; 3637 } 3638 if (create) 3639 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3640 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3641 3642 /* ext-cpuid-features */ 3643 3644 switch (cpi->cpi_vendor) { 3645 case X86_VENDOR_Intel: 3646 case X86_VENDOR_AMD: 3647 case X86_VENDOR_Cyrix: 3648 case X86_VENDOR_TM: 3649 case X86_VENDOR_Centaur: 3650 create = cpi->cpi_xmaxeax >= 0x80000001; 3651 break; 3652 default: 3653 create = 0; 3654 break; 3655 } 3656 if (create) { 3657 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3658 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3659 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3660 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3661 } 3662 3663 /* 3664 * Brand String first appeared in Intel Pentium IV, AMD K5 3665 * model 1, and Cyrix GXm. On earlier models we try and 3666 * simulate something similar .. so this string should always 3667 * same -something- about the processor, however lame. 3668 */ 3669 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3670 "brand-string", cpi->cpi_brandstr); 3671 3672 /* 3673 * Finally, cache and tlb information 3674 */ 3675 switch (x86_which_cacheinfo(cpi)) { 3676 case X86_VENDOR_Intel: 3677 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3678 break; 3679 case X86_VENDOR_Cyrix: 3680 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3681 break; 3682 case X86_VENDOR_AMD: 3683 amd_cache_info(cpi, cpu_devi); 3684 break; 3685 default: 3686 break; 3687 } 3688 3689 mutex_exit(&cpu_node_lock); 3690 } 3691 3692 struct l2info { 3693 int *l2i_csz; 3694 int *l2i_lsz; 3695 int *l2i_assoc; 3696 int l2i_ret; 3697 }; 3698 3699 /* 3700 * A cacheinfo walker that fetches the size, line-size and associativity 3701 * of the L2 cache 3702 */ 3703 static int 3704 intel_l2cinfo(void *arg, const struct cachetab *ct) 3705 { 3706 struct l2info *l2i = arg; 3707 int *ip; 3708 3709 if (ct->ct_label != l2_cache_str && 3710 ct->ct_label != sl2_cache_str) 3711 return (0); /* not an L2 -- keep walking */ 3712 3713 if ((ip = l2i->l2i_csz) != NULL) 3714 *ip = ct->ct_size; 3715 if ((ip = l2i->l2i_lsz) != NULL) 3716 *ip = ct->ct_line_size; 3717 if ((ip = l2i->l2i_assoc) != NULL) 3718 *ip = ct->ct_assoc; 3719 l2i->l2i_ret = ct->ct_size; 3720 return (1); /* was an L2 -- terminate walk */ 3721 } 3722 3723 /* 3724 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3725 * 3726 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3727 * value is the associativity, the associativity for the L2 cache and 3728 * tlb is encoded in the following table. The 4 bit L2 value serves as 3729 * an index into the amd_afd[] array to determine the associativity. 3730 * -1 is undefined. 0 is fully associative. 3731 */ 3732 3733 static int amd_afd[] = 3734 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3735 3736 static void 3737 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3738 { 3739 struct cpuid_regs *cp; 3740 uint_t size, assoc; 3741 int i; 3742 int *ip; 3743 3744 if (cpi->cpi_xmaxeax < 0x80000006) 3745 return; 3746 cp = &cpi->cpi_extd[6]; 3747 3748 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3749 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3750 uint_t cachesz = size * 1024; 3751 assoc = amd_afd[i]; 3752 3753 ASSERT(assoc != -1); 3754 3755 if ((ip = l2i->l2i_csz) != NULL) 3756 *ip = cachesz; 3757 if ((ip = l2i->l2i_lsz) != NULL) 3758 *ip = BITX(cp->cp_ecx, 7, 0); 3759 if ((ip = l2i->l2i_assoc) != NULL) 3760 *ip = assoc; 3761 l2i->l2i_ret = cachesz; 3762 } 3763 } 3764 3765 int 3766 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3767 { 3768 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3769 struct l2info __l2info, *l2i = &__l2info; 3770 3771 l2i->l2i_csz = csz; 3772 l2i->l2i_lsz = lsz; 3773 l2i->l2i_assoc = assoc; 3774 l2i->l2i_ret = -1; 3775 3776 switch (x86_which_cacheinfo(cpi)) { 3777 case X86_VENDOR_Intel: 3778 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3779 break; 3780 case X86_VENDOR_Cyrix: 3781 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3782 break; 3783 case X86_VENDOR_AMD: 3784 amd_l2cacheinfo(cpi, l2i); 3785 break; 3786 default: 3787 break; 3788 } 3789 return (l2i->l2i_ret); 3790 } 3791 3792 #if !defined(__xpv) 3793 3794 uint32_t * 3795 cpuid_mwait_alloc(cpu_t *cpu) 3796 { 3797 uint32_t *ret; 3798 size_t mwait_size; 3799 3800 ASSERT(cpuid_checkpass(cpu, 2)); 3801 3802 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3803 if (mwait_size == 0) 3804 return (NULL); 3805 3806 /* 3807 * kmem_alloc() returns cache line size aligned data for mwait_size 3808 * allocations. mwait_size is currently cache line sized. Neither 3809 * of these implementation details are guarantied to be true in the 3810 * future. 3811 * 3812 * First try allocating mwait_size as kmem_alloc() currently returns 3813 * correctly aligned memory. If kmem_alloc() does not return 3814 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3815 * 3816 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3817 * decide to free this memory. 3818 */ 3819 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3820 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3821 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3822 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3823 *ret = MWAIT_RUNNING; 3824 return (ret); 3825 } else { 3826 kmem_free(ret, mwait_size); 3827 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3828 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3829 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3830 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3831 *ret = MWAIT_RUNNING; 3832 return (ret); 3833 } 3834 } 3835 3836 void 3837 cpuid_mwait_free(cpu_t *cpu) 3838 { 3839 ASSERT(cpuid_checkpass(cpu, 2)); 3840 3841 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3842 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3843 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3844 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3845 } 3846 3847 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3848 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3849 } 3850 3851 void 3852 patch_tsc_read(int flag) 3853 { 3854 size_t cnt; 3855 3856 switch (flag) { 3857 case X86_NO_TSC: 3858 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 3859 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 3860 break; 3861 case X86_HAVE_TSCP: 3862 cnt = &_tscp_end - &_tscp_start; 3863 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 3864 break; 3865 case X86_TSC_MFENCE: 3866 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 3867 (void) memcpy((void *)tsc_read, 3868 (void *)&_tsc_mfence_start, cnt); 3869 break; 3870 case X86_TSC_LFENCE: 3871 cnt = &_tsc_lfence_end - &_tsc_lfence_start; 3872 (void) memcpy((void *)tsc_read, 3873 (void *)&_tsc_lfence_start, cnt); 3874 break; 3875 default: 3876 break; 3877 } 3878 } 3879 3880 int 3881 cpuid_deep_cstates_supported(void) 3882 { 3883 struct cpuid_info *cpi; 3884 struct cpuid_regs regs; 3885 3886 ASSERT(cpuid_checkpass(CPU, 1)); 3887 3888 cpi = CPU->cpu_m.mcpu_cpi; 3889 3890 if (!(x86_feature & X86_CPUID)) 3891 return (0); 3892 3893 switch (cpi->cpi_vendor) { 3894 case X86_VENDOR_Intel: 3895 if (cpi->cpi_xmaxeax < 0x80000007) 3896 return (0); 3897 3898 /* 3899 * TSC run at a constant rate in all ACPI C-states? 3900 */ 3901 regs.cp_eax = 0x80000007; 3902 (void) __cpuid_insn(®s); 3903 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); 3904 3905 default: 3906 return (0); 3907 } 3908 } 3909 3910 #endif /* !__xpv */ 3911 3912 void 3913 post_startup_cpu_fixups(void) 3914 { 3915 #ifndef __xpv 3916 /* 3917 * Some AMD processors support C1E state. Entering this state will 3918 * cause the local APIC timer to stop, which we can't deal with at 3919 * this time. 3920 */ 3921 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { 3922 on_trap_data_t otd; 3923 uint64_t reg; 3924 3925 if (!on_trap(&otd, OT_DATA_ACCESS)) { 3926 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); 3927 /* Disable C1E state if it is enabled by BIOS */ 3928 if ((reg >> AMD_ACTONCMPHALT_SHIFT) & 3929 AMD_ACTONCMPHALT_MASK) { 3930 reg &= ~(AMD_ACTONCMPHALT_MASK << 3931 AMD_ACTONCMPHALT_SHIFT); 3932 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); 3933 } 3934 } 3935 no_trap(); 3936 } 3937 #endif /* !__xpv */ 3938 } 3939 3940 #if defined(__amd64) && !defined(__xpv) 3941 /* 3942 * Patch in versions of bcopy for high performance Intel Nhm processors 3943 * and later... 3944 */ 3945 void 3946 patch_memops(uint_t vendor) 3947 { 3948 size_t cnt, i; 3949 caddr_t to, from; 3950 3951 if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) { 3952 cnt = &bcopy_patch_end - &bcopy_patch_start; 3953 to = &bcopy_ck_size; 3954 from = &bcopy_patch_start; 3955 for (i = 0; i < cnt; i++) { 3956 *to++ = *from++; 3957 } 3958 } 3959 } 3960 #endif /* __amd64 && !__xpv */ 3961