1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/sysmacros.h> 44 #include <sys/pg.h> 45 #include <sys/fp.h> 46 #include <sys/controlregs.h> 47 #include <sys/auxv_386.h> 48 #include <sys/bitmap.h> 49 #include <sys/memnode.h> 50 51 /* 52 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 53 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 54 * them accordingly. For most modern processors, feature detection occurs here 55 * in pass 1. 56 * 57 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 58 * for the boot CPU and does the basic analysis that the early kernel needs. 59 * x86_feature is set based on the return value of cpuid_pass1() of the boot 60 * CPU. 61 * 62 * Pass 1 includes: 63 * 64 * o Determining vendor/model/family/stepping and setting x86_type and 65 * x86_vendor accordingly. 66 * o Processing the feature flags returned by the cpuid instruction while 67 * applying any workarounds or tricks for the specific processor. 68 * o Mapping the feature flags into Solaris feature bits (X86_*). 69 * o Processing extended feature flags if supported by the processor, 70 * again while applying specific processor knowledge. 71 * o Determining the CMT characteristics of the system. 72 * 73 * Pass 1 is done on non-boot CPUs during their initialization and the results 74 * are used only as a meager attempt at ensuring that all processors within the 75 * system support the same features. 76 * 77 * Pass 2 of cpuid feature analysis happens just at the beginning 78 * of startup(). It just copies in and corrects the remainder 79 * of the cpuid data we depend on: standard cpuid functions that we didn't 80 * need for pass1 feature analysis, and extended cpuid functions beyond the 81 * simple feature processing done in pass1. 82 * 83 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 84 * particular kernel memory allocation has been made available. It creates a 85 * readable brand string based on the data collected in the first two passes. 86 * 87 * Pass 4 of cpuid analysis is invoked after post_startup() when all 88 * the support infrastructure for various hardware features has been 89 * initialized. It determines which processor features will be reported 90 * to userland via the aux vector. 91 * 92 * All passes are executed on all CPUs, but only the boot CPU determines what 93 * features the kernel will use. 94 * 95 * Much of the worst junk in this file is for the support of processors 96 * that didn't really implement the cpuid instruction properly. 97 * 98 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 99 * the pass numbers. Accordingly, changes to the pass code may require changes 100 * to the accessor code. 101 */ 102 103 uint_t x86_feature = 0; 104 uint_t x86_vendor = X86_VENDOR_IntelClone; 105 uint_t x86_type = X86_TYPE_OTHER; 106 107 uint_t pentiumpro_bug4046376; 108 uint_t pentiumpro_bug4064495; 109 110 uint_t enable486; 111 112 /* 113 * This set of strings are for processors rumored to support the cpuid 114 * instruction, and is used by locore.s to figure out how to set x86_vendor 115 */ 116 const char CyrixInstead[] = "CyrixInstead"; 117 118 /* 119 * monitor/mwait info. 120 * 121 * size_actual and buf_actual are the real address and size allocated to get 122 * proper mwait_buf alignement. buf_actual and size_actual should be passed 123 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 124 * processor cache-line alignment, but this is not guarantied in the furture. 125 */ 126 struct mwait_info { 127 size_t mon_min; /* min size to avoid missed wakeups */ 128 size_t mon_max; /* size to avoid false wakeups */ 129 size_t size_actual; /* size actually allocated */ 130 void *buf_actual; /* memory actually allocated */ 131 uint32_t support; /* processor support of monitor/mwait */ 132 }; 133 134 /* 135 * These constants determine how many of the elements of the 136 * cpuid we cache in the cpuid_info data structure; the 137 * remaining elements are accessible via the cpuid instruction. 138 */ 139 140 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 141 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 142 143 struct cpuid_info { 144 uint_t cpi_pass; /* last pass completed */ 145 /* 146 * standard function information 147 */ 148 uint_t cpi_maxeax; /* fn 0: %eax */ 149 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 150 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 151 152 uint_t cpi_family; /* fn 1: extended family */ 153 uint_t cpi_model; /* fn 1: extended model */ 154 uint_t cpi_step; /* fn 1: stepping */ 155 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 156 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 157 int cpi_clogid; /* fn 1: %ebx: thread # */ 158 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 159 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 160 uint_t cpi_ncache; /* fn 2: number of elements */ 161 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 162 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 163 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 164 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 165 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 166 /* 167 * extended function information 168 */ 169 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 170 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 171 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 172 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 173 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 174 id_t cpi_coreid; 175 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 176 /* Intel: fn 4: %eax[31-26] */ 177 /* 178 * supported feature information 179 */ 180 uint32_t cpi_support[5]; 181 #define STD_EDX_FEATURES 0 182 #define AMD_EDX_FEATURES 1 183 #define TM_EDX_FEATURES 2 184 #define STD_ECX_FEATURES 3 185 #define AMD_ECX_FEATURES 4 186 /* 187 * Synthesized information, where known. 188 */ 189 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 190 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 191 uint32_t cpi_socket; /* Chip package/socket type */ 192 193 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 194 }; 195 196 197 static struct cpuid_info cpuid_info0; 198 199 /* 200 * These bit fields are defined by the Intel Application Note AP-485 201 * "Intel Processor Identification and the CPUID Instruction" 202 */ 203 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 204 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 205 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 206 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 207 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 208 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 209 210 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 211 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 212 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 213 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 214 215 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 216 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 217 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 218 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 219 220 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 221 #define CPI_XMAXEAX_MAX 0x80000100 222 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 223 224 /* 225 * Function 4 (Deterministic Cache Parameters) macros 226 * Defined by Intel Application Note AP-485 227 */ 228 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 229 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 230 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 231 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 232 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 233 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 234 235 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 236 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 237 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 238 239 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 240 241 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 242 243 244 /* 245 * A couple of shorthand macros to identify "later" P6-family chips 246 * like the Pentium M and Core. First, the "older" P6-based stuff 247 * (loosely defined as "pre-Pentium-4"): 248 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 249 */ 250 251 #define IS_LEGACY_P6(cpi) ( \ 252 cpi->cpi_family == 6 && \ 253 (cpi->cpi_model == 1 || \ 254 cpi->cpi_model == 3 || \ 255 cpi->cpi_model == 5 || \ 256 cpi->cpi_model == 6 || \ 257 cpi->cpi_model == 7 || \ 258 cpi->cpi_model == 8 || \ 259 cpi->cpi_model == 0xA || \ 260 cpi->cpi_model == 0xB) \ 261 ) 262 263 /* A "new F6" is everything with family 6 that's not the above */ 264 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 265 266 /* Extended family/model support */ 267 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 268 cpi->cpi_family >= 0xf) 269 270 /* 271 * AMD family 0xf and family 0x10 socket types. 272 * First index : 273 * 0 for family 0xf, revs B thru E 274 * 1 for family 0xf, revs F and G 275 * 2 for family 0x10, rev B 276 * Second index by (model & 0x3) 277 */ 278 static uint32_t amd_skts[3][4] = { 279 /* 280 * Family 0xf revisions B through E 281 */ 282 #define A_SKTS_0 0 283 { 284 X86_SOCKET_754, /* 0b00 */ 285 X86_SOCKET_940, /* 0b01 */ 286 X86_SOCKET_754, /* 0b10 */ 287 X86_SOCKET_939 /* 0b11 */ 288 }, 289 /* 290 * Family 0xf revisions F and G 291 */ 292 #define A_SKTS_1 1 293 { 294 X86_SOCKET_S1g1, /* 0b00 */ 295 X86_SOCKET_F1207, /* 0b01 */ 296 X86_SOCKET_UNKNOWN, /* 0b10 */ 297 X86_SOCKET_AM2 /* 0b11 */ 298 }, 299 /* 300 * Family 0x10 revisions A and B 301 * It is not clear whether, as new sockets release, that 302 * model & 0x3 will id socket for this family 303 */ 304 #define A_SKTS_2 2 305 { 306 X86_SOCKET_F1207, /* 0b00 */ 307 X86_SOCKET_F1207, /* 0b01 */ 308 X86_SOCKET_F1207, /* 0b10 */ 309 X86_SOCKET_F1207, /* 0b11 */ 310 } 311 }; 312 313 /* 314 * Table for mapping AMD Family 0xf and AMD Family 0x10 model/stepping 315 * combination to chip "revision" and socket type. 316 * 317 * The first member of this array that matches a given family, extended model 318 * plus model range, and stepping range will be considered a match. 319 */ 320 static const struct amd_rev_mapent { 321 uint_t rm_family; 322 uint_t rm_modello; 323 uint_t rm_modelhi; 324 uint_t rm_steplo; 325 uint_t rm_stephi; 326 uint32_t rm_chiprev; 327 const char *rm_chiprevstr; 328 int rm_sktidx; 329 } amd_revmap[] = { 330 /* 331 * =============== AuthenticAMD Family 0xf =============== 332 */ 333 334 /* 335 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 336 */ 337 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 338 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 339 /* 340 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 341 */ 342 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", A_SKTS_0 }, 343 /* 344 * Rev CG is the rest of extended model 0x0 - i.e., everything 345 * but the rev B and C0 combinations covered above. 346 */ 347 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", A_SKTS_0 }, 348 /* 349 * Rev D has extended model 0x1. 350 */ 351 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", A_SKTS_0 }, 352 /* 353 * Rev E has extended model 0x2. 354 * Extended model 0x3 is unused but available to grow into. 355 */ 356 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", A_SKTS_0 }, 357 /* 358 * Rev F has extended models 0x4 and 0x5. 359 */ 360 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", A_SKTS_1 }, 361 /* 362 * Rev G has extended model 0x6. 363 */ 364 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", A_SKTS_1 }, 365 366 /* 367 * =============== AuthenticAMD Family 0x10 =============== 368 */ 369 370 /* 371 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}. 372 * Give all of model 0 stepping range to rev A. 373 */ 374 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_A, "A", A_SKTS_2 }, 375 376 /* 377 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}. 378 * Give all of model 2 stepping range to rev B. 379 */ 380 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_B, "B", A_SKTS_2 }, 381 }; 382 383 /* 384 * Info for monitor/mwait idle loop. 385 * 386 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 387 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 388 * 2006. 389 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 390 * Documentation Updates" #33633, Rev 2.05, December 2006. 391 */ 392 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 393 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 394 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 395 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 396 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 397 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 398 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 399 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 400 /* 401 * Number of sub-cstates for a given c-state. 402 */ 403 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 404 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 405 406 static void intel_cpuid_4_cache_info(void *, struct cpuid_info *); 407 408 static void 409 synth_amd_info(struct cpuid_info *cpi) 410 { 411 const struct amd_rev_mapent *rmp; 412 uint_t family, model, step; 413 int i; 414 415 /* 416 * Currently only AMD family 0xf and family 0x10 use these fields. 417 */ 418 if (cpi->cpi_family != 0xf && cpi->cpi_family != 0x10) 419 return; 420 421 family = cpi->cpi_family; 422 model = cpi->cpi_model; 423 step = cpi->cpi_step; 424 425 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); 426 i++, rmp++) { 427 if (family == rmp->rm_family && 428 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 429 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 430 cpi->cpi_chiprev = rmp->rm_chiprev; 431 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; 432 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; 433 return; 434 } 435 } 436 } 437 438 static void 439 synth_info(struct cpuid_info *cpi) 440 { 441 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; 442 cpi->cpi_chiprevstr = "Unknown"; 443 cpi->cpi_socket = X86_SOCKET_UNKNOWN; 444 445 switch (cpi->cpi_vendor) { 446 case X86_VENDOR_AMD: 447 synth_amd_info(cpi); 448 break; 449 450 default: 451 break; 452 453 } 454 } 455 456 /* 457 * Apply up various platform-dependent restrictions where the 458 * underlying platform restrictions mean the CPU can be marked 459 * as less capable than its cpuid instruction would imply. 460 */ 461 #if defined(__xpv) 462 static void 463 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 464 { 465 switch (eax) { 466 case 1: 467 cp->cp_edx &= 468 ~(CPUID_INTC_EDX_PSE | 469 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 470 CPUID_INTC_EDX_MCA | /* XXPV true on dom0? */ 471 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 472 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 473 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 474 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 475 break; 476 477 case 0x80000001: 478 cp->cp_edx &= 479 ~(CPUID_AMD_EDX_PSE | 480 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 481 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 482 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 483 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 484 CPUID_AMD_EDX_TSCP); 485 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 486 break; 487 default: 488 break; 489 } 490 491 switch (vendor) { 492 case X86_VENDOR_Intel: 493 switch (eax) { 494 case 4: 495 /* 496 * Zero out the (ncores-per-chip - 1) field 497 */ 498 cp->cp_eax &= 0x03fffffff; 499 break; 500 default: 501 break; 502 } 503 break; 504 case X86_VENDOR_AMD: 505 switch (eax) { 506 case 0x80000008: 507 /* 508 * Zero out the (ncores-per-chip - 1) field 509 */ 510 cp->cp_ecx &= 0xffffff00; 511 break; 512 default: 513 break; 514 } 515 break; 516 default: 517 break; 518 } 519 } 520 #else 521 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 522 #endif 523 524 /* 525 * Some undocumented ways of patching the results of the cpuid 526 * instruction to permit running Solaris 10 on future cpus that 527 * we don't currently support. Could be set to non-zero values 528 * via settings in eeprom. 529 */ 530 531 uint32_t cpuid_feature_ecx_include; 532 uint32_t cpuid_feature_ecx_exclude; 533 uint32_t cpuid_feature_edx_include; 534 uint32_t cpuid_feature_edx_exclude; 535 536 void 537 cpuid_alloc_space(cpu_t *cpu) 538 { 539 /* 540 * By convention, cpu0 is the boot cpu, which is set up 541 * before memory allocation is available. All other cpus get 542 * their cpuid_info struct allocated here. 543 */ 544 ASSERT(cpu->cpu_id != 0); 545 cpu->cpu_m.mcpu_cpi = 546 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 547 } 548 549 void 550 cpuid_free_space(cpu_t *cpu) 551 { 552 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 553 int i; 554 555 ASSERT(cpu->cpu_id != 0); 556 557 /* 558 * Free up any function 4 related dynamic storage 559 */ 560 for (i = 1; i < cpi->cpi_std_4_size; i++) 561 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 562 if (cpi->cpi_std_4_size > 0) 563 kmem_free(cpi->cpi_std_4, 564 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 565 566 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 567 } 568 569 uint_t 570 cpuid_pass1(cpu_t *cpu) 571 { 572 uint32_t mask_ecx, mask_edx; 573 uint_t feature = X86_CPUID; 574 struct cpuid_info *cpi; 575 struct cpuid_regs *cp; 576 int xcpuid; 577 #if !defined(__xpv) 578 extern int idle_cpu_prefer_mwait; 579 #endif 580 581 /* 582 * Space statically allocated for cpu0, ensure pointer is set 583 */ 584 if (cpu->cpu_id == 0) 585 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 586 cpi = cpu->cpu_m.mcpu_cpi; 587 ASSERT(cpi != NULL); 588 cp = &cpi->cpi_std[0]; 589 cp->cp_eax = 0; 590 cpi->cpi_maxeax = __cpuid_insn(cp); 591 { 592 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 593 *iptr++ = cp->cp_ebx; 594 *iptr++ = cp->cp_edx; 595 *iptr++ = cp->cp_ecx; 596 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 597 } 598 599 /* 600 * Map the vendor string to a type code 601 */ 602 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 603 cpi->cpi_vendor = X86_VENDOR_Intel; 604 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 605 cpi->cpi_vendor = X86_VENDOR_AMD; 606 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 607 cpi->cpi_vendor = X86_VENDOR_TM; 608 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 609 /* 610 * CyrixInstead is a variable used by the Cyrix detection code 611 * in locore. 612 */ 613 cpi->cpi_vendor = X86_VENDOR_Cyrix; 614 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 615 cpi->cpi_vendor = X86_VENDOR_UMC; 616 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 617 cpi->cpi_vendor = X86_VENDOR_NexGen; 618 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 619 cpi->cpi_vendor = X86_VENDOR_Centaur; 620 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 621 cpi->cpi_vendor = X86_VENDOR_Rise; 622 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 623 cpi->cpi_vendor = X86_VENDOR_SiS; 624 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 625 cpi->cpi_vendor = X86_VENDOR_NSC; 626 else 627 cpi->cpi_vendor = X86_VENDOR_IntelClone; 628 629 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 630 631 /* 632 * Limit the range in case of weird hardware 633 */ 634 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 635 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 636 if (cpi->cpi_maxeax < 1) 637 goto pass1_done; 638 639 cp = &cpi->cpi_std[1]; 640 cp->cp_eax = 1; 641 (void) __cpuid_insn(cp); 642 643 /* 644 * Extract identifying constants for easy access. 645 */ 646 cpi->cpi_model = CPI_MODEL(cpi); 647 cpi->cpi_family = CPI_FAMILY(cpi); 648 649 if (cpi->cpi_family == 0xf) 650 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 651 652 /* 653 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 654 * Intel, and presumably everyone else, uses model == 0xf, as 655 * one would expect (max value means possible overflow). Sigh. 656 */ 657 658 switch (cpi->cpi_vendor) { 659 case X86_VENDOR_Intel: 660 if (IS_EXTENDED_MODEL_INTEL(cpi)) 661 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 662 break; 663 case X86_VENDOR_AMD: 664 if (CPI_FAMILY(cpi) == 0xf) 665 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 666 break; 667 default: 668 if (cpi->cpi_model == 0xf) 669 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 670 break; 671 } 672 673 cpi->cpi_step = CPI_STEP(cpi); 674 cpi->cpi_brandid = CPI_BRANDID(cpi); 675 676 /* 677 * *default* assumptions: 678 * - believe %edx feature word 679 * - ignore %ecx feature word 680 * - 32-bit virtual and physical addressing 681 */ 682 mask_edx = 0xffffffff; 683 mask_ecx = 0; 684 685 cpi->cpi_pabits = cpi->cpi_vabits = 32; 686 687 switch (cpi->cpi_vendor) { 688 case X86_VENDOR_Intel: 689 if (cpi->cpi_family == 5) 690 x86_type = X86_TYPE_P5; 691 else if (IS_LEGACY_P6(cpi)) { 692 x86_type = X86_TYPE_P6; 693 pentiumpro_bug4046376 = 1; 694 pentiumpro_bug4064495 = 1; 695 /* 696 * Clear the SEP bit when it was set erroneously 697 */ 698 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 699 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 700 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 701 x86_type = X86_TYPE_P4; 702 /* 703 * We don't currently depend on any of the %ecx 704 * features until Prescott, so we'll only check 705 * this from P4 onwards. We might want to revisit 706 * that idea later. 707 */ 708 mask_ecx = 0xffffffff; 709 } else if (cpi->cpi_family > 0xf) 710 mask_ecx = 0xffffffff; 711 /* 712 * We don't support MONITOR/MWAIT if leaf 5 is not available 713 * to obtain the monitor linesize. 714 */ 715 if (cpi->cpi_maxeax < 5) 716 mask_ecx &= ~CPUID_INTC_ECX_MON; 717 break; 718 case X86_VENDOR_IntelClone: 719 default: 720 break; 721 case X86_VENDOR_AMD: 722 #if defined(OPTERON_ERRATUM_108) 723 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 724 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 725 cpi->cpi_model = 0xc; 726 } else 727 #endif 728 if (cpi->cpi_family == 5) { 729 /* 730 * AMD K5 and K6 731 * 732 * These CPUs have an incomplete implementation 733 * of MCA/MCE which we mask away. 734 */ 735 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 736 737 /* 738 * Model 0 uses the wrong (APIC) bit 739 * to indicate PGE. Fix it here. 740 */ 741 if (cpi->cpi_model == 0) { 742 if (cp->cp_edx & 0x200) { 743 cp->cp_edx &= ~0x200; 744 cp->cp_edx |= CPUID_INTC_EDX_PGE; 745 } 746 } 747 748 /* 749 * Early models had problems w/ MMX; disable. 750 */ 751 if (cpi->cpi_model < 6) 752 mask_edx &= ~CPUID_INTC_EDX_MMX; 753 } 754 755 /* 756 * For newer families, SSE3 and CX16, at least, are valid; 757 * enable all 758 */ 759 if (cpi->cpi_family >= 0xf) 760 mask_ecx = 0xffffffff; 761 /* 762 * We don't support MONITOR/MWAIT if leaf 5 is not available 763 * to obtain the monitor linesize. 764 */ 765 if (cpi->cpi_maxeax < 5) 766 mask_ecx &= ~CPUID_INTC_ECX_MON; 767 768 #if !defined(__xpv) 769 /* 770 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 771 * processors. AMD does not intend MWAIT to be used in the cpu 772 * idle loop on current and future processors. 10h and future 773 * AMD processors use more power in MWAIT than HLT. 774 * Pre-family-10h Opterons do not have the MWAIT instruction. 775 */ 776 idle_cpu_prefer_mwait = 0; 777 #endif 778 779 break; 780 case X86_VENDOR_TM: 781 /* 782 * workaround the NT workaround in CMS 4.1 783 */ 784 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 785 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 786 cp->cp_edx |= CPUID_INTC_EDX_CX8; 787 break; 788 case X86_VENDOR_Centaur: 789 /* 790 * workaround the NT workarounds again 791 */ 792 if (cpi->cpi_family == 6) 793 cp->cp_edx |= CPUID_INTC_EDX_CX8; 794 break; 795 case X86_VENDOR_Cyrix: 796 /* 797 * We rely heavily on the probing in locore 798 * to actually figure out what parts, if any, 799 * of the Cyrix cpuid instruction to believe. 800 */ 801 switch (x86_type) { 802 case X86_TYPE_CYRIX_486: 803 mask_edx = 0; 804 break; 805 case X86_TYPE_CYRIX_6x86: 806 mask_edx = 0; 807 break; 808 case X86_TYPE_CYRIX_6x86L: 809 mask_edx = 810 CPUID_INTC_EDX_DE | 811 CPUID_INTC_EDX_CX8; 812 break; 813 case X86_TYPE_CYRIX_6x86MX: 814 mask_edx = 815 CPUID_INTC_EDX_DE | 816 CPUID_INTC_EDX_MSR | 817 CPUID_INTC_EDX_CX8 | 818 CPUID_INTC_EDX_PGE | 819 CPUID_INTC_EDX_CMOV | 820 CPUID_INTC_EDX_MMX; 821 break; 822 case X86_TYPE_CYRIX_GXm: 823 mask_edx = 824 CPUID_INTC_EDX_MSR | 825 CPUID_INTC_EDX_CX8 | 826 CPUID_INTC_EDX_CMOV | 827 CPUID_INTC_EDX_MMX; 828 break; 829 case X86_TYPE_CYRIX_MediaGX: 830 break; 831 case X86_TYPE_CYRIX_MII: 832 case X86_TYPE_VIA_CYRIX_III: 833 mask_edx = 834 CPUID_INTC_EDX_DE | 835 CPUID_INTC_EDX_TSC | 836 CPUID_INTC_EDX_MSR | 837 CPUID_INTC_EDX_CX8 | 838 CPUID_INTC_EDX_PGE | 839 CPUID_INTC_EDX_CMOV | 840 CPUID_INTC_EDX_MMX; 841 break; 842 default: 843 break; 844 } 845 break; 846 } 847 848 #if defined(__xpv) 849 /* 850 * Do not support MONITOR/MWAIT under a hypervisor 851 */ 852 mask_ecx &= ~CPUID_INTC_ECX_MON; 853 #endif /* __xpv */ 854 855 /* 856 * Now we've figured out the masks that determine 857 * which bits we choose to believe, apply the masks 858 * to the feature words, then map the kernel's view 859 * of these feature words into its feature word. 860 */ 861 cp->cp_edx &= mask_edx; 862 cp->cp_ecx &= mask_ecx; 863 864 /* 865 * apply any platform restrictions (we don't call this 866 * immediately after __cpuid_insn here, because we need the 867 * workarounds applied above first) 868 */ 869 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 870 871 /* 872 * fold in overrides from the "eeprom" mechanism 873 */ 874 cp->cp_edx |= cpuid_feature_edx_include; 875 cp->cp_edx &= ~cpuid_feature_edx_exclude; 876 877 cp->cp_ecx |= cpuid_feature_ecx_include; 878 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 879 880 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 881 feature |= X86_LARGEPAGE; 882 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 883 feature |= X86_TSC; 884 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 885 feature |= X86_MSR; 886 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 887 feature |= X86_MTRR; 888 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 889 feature |= X86_PGE; 890 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 891 feature |= X86_CMOV; 892 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 893 feature |= X86_MMX; 894 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 895 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 896 feature |= X86_MCA; 897 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 898 feature |= X86_PAE; 899 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 900 feature |= X86_CX8; 901 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 902 feature |= X86_CX16; 903 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 904 feature |= X86_PAT; 905 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 906 feature |= X86_SEP; 907 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 908 /* 909 * In our implementation, fxsave/fxrstor 910 * are prerequisites before we'll even 911 * try and do SSE things. 912 */ 913 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 914 feature |= X86_SSE; 915 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 916 feature |= X86_SSE2; 917 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 918 feature |= X86_SSE3; 919 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 920 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 921 feature |= X86_SSSE3; 922 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 923 feature |= X86_SSE4_1; 924 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 925 feature |= X86_SSE4_2; 926 } 927 } 928 if (cp->cp_edx & CPUID_INTC_EDX_DE) 929 feature |= X86_DE; 930 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 931 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 932 feature |= X86_MWAIT; 933 } 934 935 if (feature & X86_PAE) 936 cpi->cpi_pabits = 36; 937 938 /* 939 * Hyperthreading configuration is slightly tricky on Intel 940 * and pure clones, and even trickier on AMD. 941 * 942 * (AMD chose to set the HTT bit on their CMP processors, 943 * even though they're not actually hyperthreaded. Thus it 944 * takes a bit more work to figure out what's really going 945 * on ... see the handling of the CMP_LGCY bit below) 946 */ 947 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 948 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 949 if (cpi->cpi_ncpu_per_chip > 1) 950 feature |= X86_HTT; 951 } else { 952 cpi->cpi_ncpu_per_chip = 1; 953 } 954 955 /* 956 * Work on the "extended" feature information, doing 957 * some basic initialization for cpuid_pass2() 958 */ 959 xcpuid = 0; 960 switch (cpi->cpi_vendor) { 961 case X86_VENDOR_Intel: 962 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 963 xcpuid++; 964 break; 965 case X86_VENDOR_AMD: 966 if (cpi->cpi_family > 5 || 967 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 968 xcpuid++; 969 break; 970 case X86_VENDOR_Cyrix: 971 /* 972 * Only these Cyrix CPUs are -known- to support 973 * extended cpuid operations. 974 */ 975 if (x86_type == X86_TYPE_VIA_CYRIX_III || 976 x86_type == X86_TYPE_CYRIX_GXm) 977 xcpuid++; 978 break; 979 case X86_VENDOR_Centaur: 980 case X86_VENDOR_TM: 981 default: 982 xcpuid++; 983 break; 984 } 985 986 if (xcpuid) { 987 cp = &cpi->cpi_extd[0]; 988 cp->cp_eax = 0x80000000; 989 cpi->cpi_xmaxeax = __cpuid_insn(cp); 990 } 991 992 if (cpi->cpi_xmaxeax & 0x80000000) { 993 994 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 995 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 996 997 switch (cpi->cpi_vendor) { 998 case X86_VENDOR_Intel: 999 case X86_VENDOR_AMD: 1000 if (cpi->cpi_xmaxeax < 0x80000001) 1001 break; 1002 cp = &cpi->cpi_extd[1]; 1003 cp->cp_eax = 0x80000001; 1004 (void) __cpuid_insn(cp); 1005 1006 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1007 cpi->cpi_family == 5 && 1008 cpi->cpi_model == 6 && 1009 cpi->cpi_step == 6) { 1010 /* 1011 * K6 model 6 uses bit 10 to indicate SYSC 1012 * Later models use bit 11. Fix it here. 1013 */ 1014 if (cp->cp_edx & 0x400) { 1015 cp->cp_edx &= ~0x400; 1016 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 1017 } 1018 } 1019 1020 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 1021 1022 /* 1023 * Compute the additions to the kernel's feature word. 1024 */ 1025 if (cp->cp_edx & CPUID_AMD_EDX_NX) 1026 feature |= X86_NX; 1027 1028 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 1029 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 1030 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 1031 feature |= X86_SSE4A; 1032 1033 /* 1034 * If both the HTT and CMP_LGCY bits are set, 1035 * then we're not actually HyperThreaded. Read 1036 * "AMD CPUID Specification" for more details. 1037 */ 1038 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1039 (feature & X86_HTT) && 1040 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 1041 feature &= ~X86_HTT; 1042 feature |= X86_CMP; 1043 } 1044 #if defined(__amd64) 1045 /* 1046 * It's really tricky to support syscall/sysret in 1047 * the i386 kernel; we rely on sysenter/sysexit 1048 * instead. In the amd64 kernel, things are -way- 1049 * better. 1050 */ 1051 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 1052 feature |= X86_ASYSC; 1053 1054 /* 1055 * While we're thinking about system calls, note 1056 * that AMD processors don't support sysenter 1057 * in long mode at all, so don't try to program them. 1058 */ 1059 if (x86_vendor == X86_VENDOR_AMD) 1060 feature &= ~X86_SEP; 1061 #endif 1062 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 1063 feature |= X86_TSCP; 1064 break; 1065 default: 1066 break; 1067 } 1068 1069 /* 1070 * Get CPUID data about processor cores and hyperthreads. 1071 */ 1072 switch (cpi->cpi_vendor) { 1073 case X86_VENDOR_Intel: 1074 if (cpi->cpi_maxeax >= 4) { 1075 cp = &cpi->cpi_std[4]; 1076 cp->cp_eax = 4; 1077 cp->cp_ecx = 0; 1078 (void) __cpuid_insn(cp); 1079 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 1080 } 1081 /*FALLTHROUGH*/ 1082 case X86_VENDOR_AMD: 1083 if (cpi->cpi_xmaxeax < 0x80000008) 1084 break; 1085 cp = &cpi->cpi_extd[8]; 1086 cp->cp_eax = 0x80000008; 1087 (void) __cpuid_insn(cp); 1088 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1089 1090 /* 1091 * Virtual and physical address limits from 1092 * cpuid override previously guessed values. 1093 */ 1094 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1095 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1096 break; 1097 default: 1098 break; 1099 } 1100 1101 /* 1102 * Derive the number of cores per chip 1103 */ 1104 switch (cpi->cpi_vendor) { 1105 case X86_VENDOR_Intel: 1106 if (cpi->cpi_maxeax < 4) { 1107 cpi->cpi_ncore_per_chip = 1; 1108 break; 1109 } else { 1110 cpi->cpi_ncore_per_chip = 1111 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1112 } 1113 break; 1114 case X86_VENDOR_AMD: 1115 if (cpi->cpi_xmaxeax < 0x80000008) { 1116 cpi->cpi_ncore_per_chip = 1; 1117 break; 1118 } else { 1119 cpi->cpi_ncore_per_chip = 1120 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1121 } 1122 break; 1123 default: 1124 cpi->cpi_ncore_per_chip = 1; 1125 break; 1126 } 1127 } 1128 1129 /* 1130 * If more than one core, then this processor is CMP. 1131 */ 1132 if (cpi->cpi_ncore_per_chip > 1) 1133 feature |= X86_CMP; 1134 1135 /* 1136 * If the number of cores is the same as the number 1137 * of CPUs, then we cannot have HyperThreading. 1138 */ 1139 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1140 feature &= ~X86_HTT; 1141 1142 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1143 /* 1144 * Single-core single-threaded processors. 1145 */ 1146 cpi->cpi_chipid = -1; 1147 cpi->cpi_clogid = 0; 1148 cpi->cpi_coreid = cpu->cpu_id; 1149 } else if (cpi->cpi_ncpu_per_chip > 1) { 1150 uint_t i; 1151 uint_t chipid_shift = 0; 1152 uint_t coreid_shift = 0; 1153 uint_t apic_id = CPI_APIC_ID(cpi); 1154 1155 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1156 chipid_shift++; 1157 cpi->cpi_chipid = apic_id >> chipid_shift; 1158 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1159 1160 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1161 if (feature & X86_CMP) { 1162 /* 1163 * Multi-core (and possibly multi-threaded) 1164 * processors. 1165 */ 1166 uint_t ncpu_per_core; 1167 if (cpi->cpi_ncore_per_chip == 1) 1168 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1169 else if (cpi->cpi_ncore_per_chip > 1) 1170 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1171 cpi->cpi_ncore_per_chip; 1172 /* 1173 * 8bit APIC IDs on dual core Pentiums 1174 * look like this: 1175 * 1176 * +-----------------------+------+------+ 1177 * | Physical Package ID | MC | HT | 1178 * +-----------------------+------+------+ 1179 * <------- chipid --------> 1180 * <------- coreid ---------------> 1181 * <--- clogid --> 1182 * 1183 * Where the number of bits necessary to 1184 * represent MC and HT fields together equals 1185 * to the minimum number of bits necessary to 1186 * store the value of cpi->cpi_ncpu_per_chip. 1187 * Of those bits, the MC part uses the number 1188 * of bits necessary to store the value of 1189 * cpi->cpi_ncore_per_chip. 1190 */ 1191 for (i = 1; i < ncpu_per_core; i <<= 1) 1192 coreid_shift++; 1193 cpi->cpi_coreid = apic_id >> coreid_shift; 1194 } else if (feature & X86_HTT) { 1195 /* 1196 * Single-core multi-threaded processors. 1197 */ 1198 cpi->cpi_coreid = cpi->cpi_chipid; 1199 } 1200 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1201 /* 1202 * AMD currently only has dual-core processors with 1203 * single-threaded cores. If they ever release 1204 * multi-threaded processors, then this code 1205 * will have to be updated. 1206 */ 1207 cpi->cpi_coreid = cpu->cpu_id; 1208 } else { 1209 /* 1210 * All other processors are currently 1211 * assumed to have single cores. 1212 */ 1213 cpi->cpi_coreid = cpi->cpi_chipid; 1214 } 1215 } 1216 1217 /* 1218 * Synthesize chip "revision" and socket type 1219 */ 1220 synth_info(cpi); 1221 1222 pass1_done: 1223 cpi->cpi_pass = 1; 1224 return (feature); 1225 } 1226 1227 /* 1228 * Make copies of the cpuid table entries we depend on, in 1229 * part for ease of parsing now, in part so that we have only 1230 * one place to correct any of it, in part for ease of 1231 * later export to userland, and in part so we can look at 1232 * this stuff in a crash dump. 1233 */ 1234 1235 /*ARGSUSED*/ 1236 void 1237 cpuid_pass2(cpu_t *cpu) 1238 { 1239 uint_t n, nmax; 1240 int i; 1241 struct cpuid_regs *cp; 1242 uint8_t *dp; 1243 uint32_t *iptr; 1244 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1245 1246 ASSERT(cpi->cpi_pass == 1); 1247 1248 if (cpi->cpi_maxeax < 1) 1249 goto pass2_done; 1250 1251 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1252 nmax = NMAX_CPI_STD; 1253 /* 1254 * (We already handled n == 0 and n == 1 in pass 1) 1255 */ 1256 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1257 cp->cp_eax = n; 1258 1259 /* 1260 * CPUID function 4 expects %ecx to be initialized 1261 * with an index which indicates which cache to return 1262 * information about. The OS is expected to call function 4 1263 * with %ecx set to 0, 1, 2, ... until it returns with 1264 * EAX[4:0] set to 0, which indicates there are no more 1265 * caches. 1266 * 1267 * Here, populate cpi_std[4] with the information returned by 1268 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1269 * when dynamic memory allocation becomes available. 1270 * 1271 * Note: we need to explicitly initialize %ecx here, since 1272 * function 4 may have been previously invoked. 1273 */ 1274 if (n == 4) 1275 cp->cp_ecx = 0; 1276 1277 (void) __cpuid_insn(cp); 1278 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1279 switch (n) { 1280 case 2: 1281 /* 1282 * "the lower 8 bits of the %eax register 1283 * contain a value that identifies the number 1284 * of times the cpuid [instruction] has to be 1285 * executed to obtain a complete image of the 1286 * processor's caching systems." 1287 * 1288 * How *do* they make this stuff up? 1289 */ 1290 cpi->cpi_ncache = sizeof (*cp) * 1291 BITX(cp->cp_eax, 7, 0); 1292 if (cpi->cpi_ncache == 0) 1293 break; 1294 cpi->cpi_ncache--; /* skip count byte */ 1295 1296 /* 1297 * Well, for now, rather than attempt to implement 1298 * this slightly dubious algorithm, we just look 1299 * at the first 15 .. 1300 */ 1301 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1302 cpi->cpi_ncache = sizeof (*cp) - 1; 1303 1304 dp = cpi->cpi_cacheinfo; 1305 if (BITX(cp->cp_eax, 31, 31) == 0) { 1306 uint8_t *p = (void *)&cp->cp_eax; 1307 for (i = 1; i < 3; i++) 1308 if (p[i] != 0) 1309 *dp++ = p[i]; 1310 } 1311 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1312 uint8_t *p = (void *)&cp->cp_ebx; 1313 for (i = 0; i < 4; i++) 1314 if (p[i] != 0) 1315 *dp++ = p[i]; 1316 } 1317 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1318 uint8_t *p = (void *)&cp->cp_ecx; 1319 for (i = 0; i < 4; i++) 1320 if (p[i] != 0) 1321 *dp++ = p[i]; 1322 } 1323 if (BITX(cp->cp_edx, 31, 31) == 0) { 1324 uint8_t *p = (void *)&cp->cp_edx; 1325 for (i = 0; i < 4; i++) 1326 if (p[i] != 0) 1327 *dp++ = p[i]; 1328 } 1329 break; 1330 1331 case 3: /* Processor serial number, if PSN supported */ 1332 break; 1333 1334 case 4: /* Deterministic cache parameters */ 1335 break; 1336 1337 case 5: /* Monitor/Mwait parameters */ 1338 { 1339 size_t mwait_size; 1340 1341 /* 1342 * check cpi_mwait.support which was set in cpuid_pass1 1343 */ 1344 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1345 break; 1346 1347 /* 1348 * Protect ourself from insane mwait line size. 1349 * Workaround for incomplete hardware emulator(s). 1350 */ 1351 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1352 if (mwait_size < sizeof (uint32_t) || 1353 !ISP2(mwait_size)) { 1354 #if DEBUG 1355 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1356 "size %ld", 1357 cpu->cpu_id, (long)mwait_size); 1358 #endif 1359 break; 1360 } 1361 1362 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1363 cpi->cpi_mwait.mon_max = mwait_size; 1364 if (MWAIT_EXTENSION(cpi)) { 1365 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1366 if (MWAIT_INT_ENABLE(cpi)) 1367 cpi->cpi_mwait.support |= 1368 MWAIT_ECX_INT_ENABLE; 1369 } 1370 break; 1371 } 1372 default: 1373 break; 1374 } 1375 } 1376 1377 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1378 goto pass2_done; 1379 1380 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1381 nmax = NMAX_CPI_EXTD; 1382 /* 1383 * Copy the extended properties, fixing them as we go. 1384 * (We already handled n == 0 and n == 1 in pass 1) 1385 */ 1386 iptr = (void *)cpi->cpi_brandstr; 1387 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1388 cp->cp_eax = 0x80000000 + n; 1389 (void) __cpuid_insn(cp); 1390 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1391 switch (n) { 1392 case 2: 1393 case 3: 1394 case 4: 1395 /* 1396 * Extract the brand string 1397 */ 1398 *iptr++ = cp->cp_eax; 1399 *iptr++ = cp->cp_ebx; 1400 *iptr++ = cp->cp_ecx; 1401 *iptr++ = cp->cp_edx; 1402 break; 1403 case 5: 1404 switch (cpi->cpi_vendor) { 1405 case X86_VENDOR_AMD: 1406 /* 1407 * The Athlon and Duron were the first 1408 * parts to report the sizes of the 1409 * TLB for large pages. Before then, 1410 * we don't trust the data. 1411 */ 1412 if (cpi->cpi_family < 6 || 1413 (cpi->cpi_family == 6 && 1414 cpi->cpi_model < 1)) 1415 cp->cp_eax = 0; 1416 break; 1417 default: 1418 break; 1419 } 1420 break; 1421 case 6: 1422 switch (cpi->cpi_vendor) { 1423 case X86_VENDOR_AMD: 1424 /* 1425 * The Athlon and Duron were the first 1426 * AMD parts with L2 TLB's. 1427 * Before then, don't trust the data. 1428 */ 1429 if (cpi->cpi_family < 6 || 1430 cpi->cpi_family == 6 && 1431 cpi->cpi_model < 1) 1432 cp->cp_eax = cp->cp_ebx = 0; 1433 /* 1434 * AMD Duron rev A0 reports L2 1435 * cache size incorrectly as 1K 1436 * when it is really 64K 1437 */ 1438 if (cpi->cpi_family == 6 && 1439 cpi->cpi_model == 3 && 1440 cpi->cpi_step == 0) { 1441 cp->cp_ecx &= 0xffff; 1442 cp->cp_ecx |= 0x400000; 1443 } 1444 break; 1445 case X86_VENDOR_Cyrix: /* VIA C3 */ 1446 /* 1447 * VIA C3 processors are a bit messed 1448 * up w.r.t. encoding cache sizes in %ecx 1449 */ 1450 if (cpi->cpi_family != 6) 1451 break; 1452 /* 1453 * model 7 and 8 were incorrectly encoded 1454 * 1455 * xxx is model 8 really broken? 1456 */ 1457 if (cpi->cpi_model == 7 || 1458 cpi->cpi_model == 8) 1459 cp->cp_ecx = 1460 BITX(cp->cp_ecx, 31, 24) << 16 | 1461 BITX(cp->cp_ecx, 23, 16) << 12 | 1462 BITX(cp->cp_ecx, 15, 8) << 8 | 1463 BITX(cp->cp_ecx, 7, 0); 1464 /* 1465 * model 9 stepping 1 has wrong associativity 1466 */ 1467 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1468 cp->cp_ecx |= 8 << 12; 1469 break; 1470 case X86_VENDOR_Intel: 1471 /* 1472 * Extended L2 Cache features function. 1473 * First appeared on Prescott. 1474 */ 1475 default: 1476 break; 1477 } 1478 break; 1479 default: 1480 break; 1481 } 1482 } 1483 1484 pass2_done: 1485 cpi->cpi_pass = 2; 1486 } 1487 1488 static const char * 1489 intel_cpubrand(const struct cpuid_info *cpi) 1490 { 1491 int i; 1492 1493 if ((x86_feature & X86_CPUID) == 0 || 1494 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1495 return ("i486"); 1496 1497 switch (cpi->cpi_family) { 1498 case 5: 1499 return ("Intel Pentium(r)"); 1500 case 6: 1501 switch (cpi->cpi_model) { 1502 uint_t celeron, xeon; 1503 const struct cpuid_regs *cp; 1504 case 0: 1505 case 1: 1506 case 2: 1507 return ("Intel Pentium(r) Pro"); 1508 case 3: 1509 case 4: 1510 return ("Intel Pentium(r) II"); 1511 case 6: 1512 return ("Intel Celeron(r)"); 1513 case 5: 1514 case 7: 1515 celeron = xeon = 0; 1516 cp = &cpi->cpi_std[2]; /* cache info */ 1517 1518 for (i = 1; i < 3; i++) { 1519 uint_t tmp; 1520 1521 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1522 if (tmp == 0x40) 1523 celeron++; 1524 if (tmp >= 0x44 && tmp <= 0x45) 1525 xeon++; 1526 } 1527 1528 for (i = 0; i < 2; i++) { 1529 uint_t tmp; 1530 1531 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1532 if (tmp == 0x40) 1533 celeron++; 1534 else if (tmp >= 0x44 && tmp <= 0x45) 1535 xeon++; 1536 } 1537 1538 for (i = 0; i < 4; i++) { 1539 uint_t tmp; 1540 1541 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1542 if (tmp == 0x40) 1543 celeron++; 1544 else if (tmp >= 0x44 && tmp <= 0x45) 1545 xeon++; 1546 } 1547 1548 for (i = 0; i < 4; i++) { 1549 uint_t tmp; 1550 1551 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1552 if (tmp == 0x40) 1553 celeron++; 1554 else if (tmp >= 0x44 && tmp <= 0x45) 1555 xeon++; 1556 } 1557 1558 if (celeron) 1559 return ("Intel Celeron(r)"); 1560 if (xeon) 1561 return (cpi->cpi_model == 5 ? 1562 "Intel Pentium(r) II Xeon(tm)" : 1563 "Intel Pentium(r) III Xeon(tm)"); 1564 return (cpi->cpi_model == 5 ? 1565 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1566 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1567 default: 1568 break; 1569 } 1570 default: 1571 break; 1572 } 1573 1574 /* BrandID is present if the field is nonzero */ 1575 if (cpi->cpi_brandid != 0) { 1576 static const struct { 1577 uint_t bt_bid; 1578 const char *bt_str; 1579 } brand_tbl[] = { 1580 { 0x1, "Intel(r) Celeron(r)" }, 1581 { 0x2, "Intel(r) Pentium(r) III" }, 1582 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1583 { 0x4, "Intel(r) Pentium(r) III" }, 1584 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1585 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1586 { 0x8, "Intel(r) Pentium(r) 4" }, 1587 { 0x9, "Intel(r) Pentium(r) 4" }, 1588 { 0xa, "Intel(r) Celeron(r)" }, 1589 { 0xb, "Intel(r) Xeon(tm)" }, 1590 { 0xc, "Intel(r) Xeon(tm) MP" }, 1591 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1592 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1593 { 0x11, "Mobile Genuine Intel(r)" }, 1594 { 0x12, "Intel(r) Celeron(r) M" }, 1595 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1596 { 0x14, "Intel(r) Celeron(r)" }, 1597 { 0x15, "Mobile Genuine Intel(r)" }, 1598 { 0x16, "Intel(r) Pentium(r) M" }, 1599 { 0x17, "Mobile Intel(r) Celeron(r)" } 1600 }; 1601 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1602 uint_t sgn; 1603 1604 sgn = (cpi->cpi_family << 8) | 1605 (cpi->cpi_model << 4) | cpi->cpi_step; 1606 1607 for (i = 0; i < btblmax; i++) 1608 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1609 break; 1610 if (i < btblmax) { 1611 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1612 return ("Intel(r) Celeron(r)"); 1613 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1614 return ("Intel(r) Xeon(tm) MP"); 1615 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1616 return ("Intel(r) Xeon(tm)"); 1617 return (brand_tbl[i].bt_str); 1618 } 1619 } 1620 1621 return (NULL); 1622 } 1623 1624 static const char * 1625 amd_cpubrand(const struct cpuid_info *cpi) 1626 { 1627 if ((x86_feature & X86_CPUID) == 0 || 1628 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1629 return ("i486 compatible"); 1630 1631 switch (cpi->cpi_family) { 1632 case 5: 1633 switch (cpi->cpi_model) { 1634 case 0: 1635 case 1: 1636 case 2: 1637 case 3: 1638 case 4: 1639 case 5: 1640 return ("AMD-K5(r)"); 1641 case 6: 1642 case 7: 1643 return ("AMD-K6(r)"); 1644 case 8: 1645 return ("AMD-K6(r)-2"); 1646 case 9: 1647 return ("AMD-K6(r)-III"); 1648 default: 1649 return ("AMD (family 5)"); 1650 } 1651 case 6: 1652 switch (cpi->cpi_model) { 1653 case 1: 1654 return ("AMD-K7(tm)"); 1655 case 0: 1656 case 2: 1657 case 4: 1658 return ("AMD Athlon(tm)"); 1659 case 3: 1660 case 7: 1661 return ("AMD Duron(tm)"); 1662 case 6: 1663 case 8: 1664 case 10: 1665 /* 1666 * Use the L2 cache size to distinguish 1667 */ 1668 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1669 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1670 default: 1671 return ("AMD (family 6)"); 1672 } 1673 default: 1674 break; 1675 } 1676 1677 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1678 cpi->cpi_brandid != 0) { 1679 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1680 case 3: 1681 return ("AMD Opteron(tm) UP 1xx"); 1682 case 4: 1683 return ("AMD Opteron(tm) DP 2xx"); 1684 case 5: 1685 return ("AMD Opteron(tm) MP 8xx"); 1686 default: 1687 return ("AMD Opteron(tm)"); 1688 } 1689 } 1690 1691 return (NULL); 1692 } 1693 1694 static const char * 1695 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1696 { 1697 if ((x86_feature & X86_CPUID) == 0 || 1698 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1699 type == X86_TYPE_CYRIX_486) 1700 return ("i486 compatible"); 1701 1702 switch (type) { 1703 case X86_TYPE_CYRIX_6x86: 1704 return ("Cyrix 6x86"); 1705 case X86_TYPE_CYRIX_6x86L: 1706 return ("Cyrix 6x86L"); 1707 case X86_TYPE_CYRIX_6x86MX: 1708 return ("Cyrix 6x86MX"); 1709 case X86_TYPE_CYRIX_GXm: 1710 return ("Cyrix GXm"); 1711 case X86_TYPE_CYRIX_MediaGX: 1712 return ("Cyrix MediaGX"); 1713 case X86_TYPE_CYRIX_MII: 1714 return ("Cyrix M2"); 1715 case X86_TYPE_VIA_CYRIX_III: 1716 return ("VIA Cyrix M3"); 1717 default: 1718 /* 1719 * Have another wild guess .. 1720 */ 1721 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1722 return ("Cyrix 5x86"); 1723 else if (cpi->cpi_family == 5) { 1724 switch (cpi->cpi_model) { 1725 case 2: 1726 return ("Cyrix 6x86"); /* Cyrix M1 */ 1727 case 4: 1728 return ("Cyrix MediaGX"); 1729 default: 1730 break; 1731 } 1732 } else if (cpi->cpi_family == 6) { 1733 switch (cpi->cpi_model) { 1734 case 0: 1735 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1736 case 5: 1737 case 6: 1738 case 7: 1739 case 8: 1740 case 9: 1741 return ("VIA C3"); 1742 default: 1743 break; 1744 } 1745 } 1746 break; 1747 } 1748 return (NULL); 1749 } 1750 1751 /* 1752 * This only gets called in the case that the CPU extended 1753 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1754 * aren't available, or contain null bytes for some reason. 1755 */ 1756 static void 1757 fabricate_brandstr(struct cpuid_info *cpi) 1758 { 1759 const char *brand = NULL; 1760 1761 switch (cpi->cpi_vendor) { 1762 case X86_VENDOR_Intel: 1763 brand = intel_cpubrand(cpi); 1764 break; 1765 case X86_VENDOR_AMD: 1766 brand = amd_cpubrand(cpi); 1767 break; 1768 case X86_VENDOR_Cyrix: 1769 brand = cyrix_cpubrand(cpi, x86_type); 1770 break; 1771 case X86_VENDOR_NexGen: 1772 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1773 brand = "NexGen Nx586"; 1774 break; 1775 case X86_VENDOR_Centaur: 1776 if (cpi->cpi_family == 5) 1777 switch (cpi->cpi_model) { 1778 case 4: 1779 brand = "Centaur C6"; 1780 break; 1781 case 8: 1782 brand = "Centaur C2"; 1783 break; 1784 case 9: 1785 brand = "Centaur C3"; 1786 break; 1787 default: 1788 break; 1789 } 1790 break; 1791 case X86_VENDOR_Rise: 1792 if (cpi->cpi_family == 5 && 1793 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1794 brand = "Rise mP6"; 1795 break; 1796 case X86_VENDOR_SiS: 1797 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1798 brand = "SiS 55x"; 1799 break; 1800 case X86_VENDOR_TM: 1801 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1802 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1803 break; 1804 case X86_VENDOR_NSC: 1805 case X86_VENDOR_UMC: 1806 default: 1807 break; 1808 } 1809 if (brand) { 1810 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1811 return; 1812 } 1813 1814 /* 1815 * If all else fails ... 1816 */ 1817 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1818 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1819 cpi->cpi_model, cpi->cpi_step); 1820 } 1821 1822 /* 1823 * This routine is called just after kernel memory allocation 1824 * becomes available on cpu0, and as part of mp_startup() on 1825 * the other cpus. 1826 * 1827 * Fixup the brand string, and collect any information from cpuid 1828 * that requires dynamicically allocated storage to represent. 1829 */ 1830 /*ARGSUSED*/ 1831 void 1832 cpuid_pass3(cpu_t *cpu) 1833 { 1834 int i, max, shft, level, size; 1835 struct cpuid_regs regs; 1836 struct cpuid_regs *cp; 1837 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1838 1839 ASSERT(cpi->cpi_pass == 2); 1840 1841 /* 1842 * Function 4: Deterministic cache parameters 1843 * 1844 * Take this opportunity to detect the number of threads 1845 * sharing the last level cache, and construct a corresponding 1846 * cache id. The respective cpuid_info members are initialized 1847 * to the default case of "no last level cache sharing". 1848 */ 1849 cpi->cpi_ncpu_shr_last_cache = 1; 1850 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1851 1852 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1853 1854 /* 1855 * Find the # of elements (size) returned by fn 4, and along 1856 * the way detect last level cache sharing details. 1857 */ 1858 bzero(®s, sizeof (regs)); 1859 cp = ®s; 1860 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1861 cp->cp_eax = 4; 1862 cp->cp_ecx = i; 1863 1864 (void) __cpuid_insn(cp); 1865 1866 if (CPI_CACHE_TYPE(cp) == 0) 1867 break; 1868 level = CPI_CACHE_LVL(cp); 1869 if (level > max) { 1870 max = level; 1871 cpi->cpi_ncpu_shr_last_cache = 1872 CPI_NTHR_SHR_CACHE(cp) + 1; 1873 } 1874 } 1875 cpi->cpi_std_4_size = size = i; 1876 1877 /* 1878 * Allocate the cpi_std_4 array. The first element 1879 * references the regs for fn 4, %ecx == 0, which 1880 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1881 */ 1882 if (size > 0) { 1883 cpi->cpi_std_4 = 1884 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1885 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1886 1887 /* 1888 * Allocate storage to hold the additional regs 1889 * for function 4, %ecx == 1 .. cpi_std_4_size. 1890 * 1891 * The regs for fn 4, %ecx == 0 has already 1892 * been allocated as indicated above. 1893 */ 1894 for (i = 1; i < size; i++) { 1895 cp = cpi->cpi_std_4[i] = 1896 kmem_zalloc(sizeof (regs), KM_SLEEP); 1897 cp->cp_eax = 4; 1898 cp->cp_ecx = i; 1899 1900 (void) __cpuid_insn(cp); 1901 } 1902 } 1903 /* 1904 * Determine the number of bits needed to represent 1905 * the number of CPUs sharing the last level cache. 1906 * 1907 * Shift off that number of bits from the APIC id to 1908 * derive the cache id. 1909 */ 1910 shft = 0; 1911 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1912 shft++; 1913 cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft; 1914 } 1915 1916 /* 1917 * Now fixup the brand string 1918 */ 1919 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1920 fabricate_brandstr(cpi); 1921 } else { 1922 1923 /* 1924 * If we successfully extracted a brand string from the cpuid 1925 * instruction, clean it up by removing leading spaces and 1926 * similar junk. 1927 */ 1928 if (cpi->cpi_brandstr[0]) { 1929 size_t maxlen = sizeof (cpi->cpi_brandstr); 1930 char *src, *dst; 1931 1932 dst = src = (char *)cpi->cpi_brandstr; 1933 src[maxlen - 1] = '\0'; 1934 /* 1935 * strip leading spaces 1936 */ 1937 while (*src == ' ') 1938 src++; 1939 /* 1940 * Remove any 'Genuine' or "Authentic" prefixes 1941 */ 1942 if (strncmp(src, "Genuine ", 8) == 0) 1943 src += 8; 1944 if (strncmp(src, "Authentic ", 10) == 0) 1945 src += 10; 1946 1947 /* 1948 * Now do an in-place copy. 1949 * Map (R) to (r) and (TM) to (tm). 1950 * The era of teletypes is long gone, and there's 1951 * -really- no need to shout. 1952 */ 1953 while (*src != '\0') { 1954 if (src[0] == '(') { 1955 if (strncmp(src + 1, "R)", 2) == 0) { 1956 (void) strncpy(dst, "(r)", 3); 1957 src += 3; 1958 dst += 3; 1959 continue; 1960 } 1961 if (strncmp(src + 1, "TM)", 3) == 0) { 1962 (void) strncpy(dst, "(tm)", 4); 1963 src += 4; 1964 dst += 4; 1965 continue; 1966 } 1967 } 1968 *dst++ = *src++; 1969 } 1970 *dst = '\0'; 1971 1972 /* 1973 * Finally, remove any trailing spaces 1974 */ 1975 while (--dst > cpi->cpi_brandstr) 1976 if (*dst == ' ') 1977 *dst = '\0'; 1978 else 1979 break; 1980 } else 1981 fabricate_brandstr(cpi); 1982 } 1983 cpi->cpi_pass = 3; 1984 } 1985 1986 /* 1987 * This routine is called out of bind_hwcap() much later in the life 1988 * of the kernel (post_startup()). The job of this routine is to resolve 1989 * the hardware feature support and kernel support for those features into 1990 * what we're actually going to tell applications via the aux vector. 1991 */ 1992 uint_t 1993 cpuid_pass4(cpu_t *cpu) 1994 { 1995 struct cpuid_info *cpi; 1996 uint_t hwcap_flags = 0; 1997 1998 if (cpu == NULL) 1999 cpu = CPU; 2000 cpi = cpu->cpu_m.mcpu_cpi; 2001 2002 ASSERT(cpi->cpi_pass == 3); 2003 2004 if (cpi->cpi_maxeax >= 1) { 2005 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2006 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2007 2008 *edx = CPI_FEATURES_EDX(cpi); 2009 *ecx = CPI_FEATURES_ECX(cpi); 2010 2011 /* 2012 * [these require explicit kernel support] 2013 */ 2014 if ((x86_feature & X86_SEP) == 0) 2015 *edx &= ~CPUID_INTC_EDX_SEP; 2016 2017 if ((x86_feature & X86_SSE) == 0) 2018 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2019 if ((x86_feature & X86_SSE2) == 0) 2020 *edx &= ~CPUID_INTC_EDX_SSE2; 2021 2022 if ((x86_feature & X86_HTT) == 0) 2023 *edx &= ~CPUID_INTC_EDX_HTT; 2024 2025 if ((x86_feature & X86_SSE3) == 0) 2026 *ecx &= ~CPUID_INTC_ECX_SSE3; 2027 2028 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2029 if ((x86_feature & X86_SSSE3) == 0) 2030 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2031 if ((x86_feature & X86_SSE4_1) == 0) 2032 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2033 if ((x86_feature & X86_SSE4_2) == 0) 2034 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2035 } 2036 2037 /* 2038 * [no explicit support required beyond x87 fp context] 2039 */ 2040 if (!fpu_exists) 2041 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2042 2043 /* 2044 * Now map the supported feature vector to things that we 2045 * think userland will care about. 2046 */ 2047 if (*edx & CPUID_INTC_EDX_SEP) 2048 hwcap_flags |= AV_386_SEP; 2049 if (*edx & CPUID_INTC_EDX_SSE) 2050 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2051 if (*edx & CPUID_INTC_EDX_SSE2) 2052 hwcap_flags |= AV_386_SSE2; 2053 if (*ecx & CPUID_INTC_ECX_SSE3) 2054 hwcap_flags |= AV_386_SSE3; 2055 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2056 if (*ecx & CPUID_INTC_ECX_SSSE3) 2057 hwcap_flags |= AV_386_SSSE3; 2058 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2059 hwcap_flags |= AV_386_SSE4_1; 2060 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2061 hwcap_flags |= AV_386_SSE4_2; 2062 } 2063 if (*ecx & CPUID_INTC_ECX_POPCNT) 2064 hwcap_flags |= AV_386_POPCNT; 2065 if (*edx & CPUID_INTC_EDX_FPU) 2066 hwcap_flags |= AV_386_FPU; 2067 if (*edx & CPUID_INTC_EDX_MMX) 2068 hwcap_flags |= AV_386_MMX; 2069 2070 if (*edx & CPUID_INTC_EDX_TSC) 2071 hwcap_flags |= AV_386_TSC; 2072 if (*edx & CPUID_INTC_EDX_CX8) 2073 hwcap_flags |= AV_386_CX8; 2074 if (*edx & CPUID_INTC_EDX_CMOV) 2075 hwcap_flags |= AV_386_CMOV; 2076 if (*ecx & CPUID_INTC_ECX_MON) 2077 hwcap_flags |= AV_386_MON; 2078 if (*ecx & CPUID_INTC_ECX_CX16) 2079 hwcap_flags |= AV_386_CX16; 2080 } 2081 2082 if (x86_feature & X86_HTT) 2083 hwcap_flags |= AV_386_PAUSE; 2084 2085 if (cpi->cpi_xmaxeax < 0x80000001) 2086 goto pass4_done; 2087 2088 switch (cpi->cpi_vendor) { 2089 struct cpuid_regs cp; 2090 uint32_t *edx, *ecx; 2091 2092 case X86_VENDOR_Intel: 2093 /* 2094 * Seems like Intel duplicated what we necessary 2095 * here to make the initial crop of 64-bit OS's work. 2096 * Hopefully, those are the only "extended" bits 2097 * they'll add. 2098 */ 2099 /*FALLTHROUGH*/ 2100 2101 case X86_VENDOR_AMD: 2102 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2103 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2104 2105 *edx = CPI_FEATURES_XTD_EDX(cpi); 2106 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2107 2108 /* 2109 * [these features require explicit kernel support] 2110 */ 2111 switch (cpi->cpi_vendor) { 2112 case X86_VENDOR_Intel: 2113 break; 2114 2115 case X86_VENDOR_AMD: 2116 if ((x86_feature & X86_TSCP) == 0) 2117 *edx &= ~CPUID_AMD_EDX_TSCP; 2118 if ((x86_feature & X86_SSE4A) == 0) 2119 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2120 break; 2121 2122 default: 2123 break; 2124 } 2125 2126 /* 2127 * [no explicit support required beyond 2128 * x87 fp context and exception handlers] 2129 */ 2130 if (!fpu_exists) 2131 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2132 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2133 2134 if ((x86_feature & X86_NX) == 0) 2135 *edx &= ~CPUID_AMD_EDX_NX; 2136 #if !defined(__amd64) 2137 *edx &= ~CPUID_AMD_EDX_LM; 2138 #endif 2139 /* 2140 * Now map the supported feature vector to 2141 * things that we think userland will care about. 2142 */ 2143 #if defined(__amd64) 2144 if (*edx & CPUID_AMD_EDX_SYSC) 2145 hwcap_flags |= AV_386_AMD_SYSC; 2146 #endif 2147 if (*edx & CPUID_AMD_EDX_MMXamd) 2148 hwcap_flags |= AV_386_AMD_MMX; 2149 if (*edx & CPUID_AMD_EDX_3DNow) 2150 hwcap_flags |= AV_386_AMD_3DNow; 2151 if (*edx & CPUID_AMD_EDX_3DNowx) 2152 hwcap_flags |= AV_386_AMD_3DNowx; 2153 2154 switch (cpi->cpi_vendor) { 2155 case X86_VENDOR_AMD: 2156 if (*edx & CPUID_AMD_EDX_TSCP) 2157 hwcap_flags |= AV_386_TSCP; 2158 if (*ecx & CPUID_AMD_ECX_AHF64) 2159 hwcap_flags |= AV_386_AHF; 2160 if (*ecx & CPUID_AMD_ECX_SSE4A) 2161 hwcap_flags |= AV_386_AMD_SSE4A; 2162 if (*ecx & CPUID_AMD_ECX_LZCNT) 2163 hwcap_flags |= AV_386_AMD_LZCNT; 2164 break; 2165 2166 case X86_VENDOR_Intel: 2167 /* 2168 * Aarrgh. 2169 * Intel uses a different bit in the same word. 2170 */ 2171 if (*ecx & CPUID_INTC_ECX_AHF64) 2172 hwcap_flags |= AV_386_AHF; 2173 break; 2174 2175 default: 2176 break; 2177 } 2178 break; 2179 2180 case X86_VENDOR_TM: 2181 cp.cp_eax = 0x80860001; 2182 (void) __cpuid_insn(&cp); 2183 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2184 break; 2185 2186 default: 2187 break; 2188 } 2189 2190 pass4_done: 2191 cpi->cpi_pass = 4; 2192 return (hwcap_flags); 2193 } 2194 2195 2196 /* 2197 * Simulate the cpuid instruction using the data we previously 2198 * captured about this CPU. We try our best to return the truth 2199 * about the hardware, independently of kernel support. 2200 */ 2201 uint32_t 2202 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2203 { 2204 struct cpuid_info *cpi; 2205 struct cpuid_regs *xcp; 2206 2207 if (cpu == NULL) 2208 cpu = CPU; 2209 cpi = cpu->cpu_m.mcpu_cpi; 2210 2211 ASSERT(cpuid_checkpass(cpu, 3)); 2212 2213 /* 2214 * CPUID data is cached in two separate places: cpi_std for standard 2215 * CPUID functions, and cpi_extd for extended CPUID functions. 2216 */ 2217 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2218 xcp = &cpi->cpi_std[cp->cp_eax]; 2219 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2220 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2221 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2222 else 2223 /* 2224 * The caller is asking for data from an input parameter which 2225 * the kernel has not cached. In this case we go fetch from 2226 * the hardware and return the data directly to the user. 2227 */ 2228 return (__cpuid_insn(cp)); 2229 2230 cp->cp_eax = xcp->cp_eax; 2231 cp->cp_ebx = xcp->cp_ebx; 2232 cp->cp_ecx = xcp->cp_ecx; 2233 cp->cp_edx = xcp->cp_edx; 2234 return (cp->cp_eax); 2235 } 2236 2237 int 2238 cpuid_checkpass(cpu_t *cpu, int pass) 2239 { 2240 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2241 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2242 } 2243 2244 int 2245 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2246 { 2247 ASSERT(cpuid_checkpass(cpu, 3)); 2248 2249 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2250 } 2251 2252 int 2253 cpuid_is_cmt(cpu_t *cpu) 2254 { 2255 if (cpu == NULL) 2256 cpu = CPU; 2257 2258 ASSERT(cpuid_checkpass(cpu, 1)); 2259 2260 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2261 } 2262 2263 /* 2264 * AMD and Intel both implement the 64-bit variant of the syscall 2265 * instruction (syscallq), so if there's -any- support for syscall, 2266 * cpuid currently says "yes, we support this". 2267 * 2268 * However, Intel decided to -not- implement the 32-bit variant of the 2269 * syscall instruction, so we provide a predicate to allow our caller 2270 * to test that subtlety here. 2271 * 2272 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2273 * even in the case where the hardware would in fact support it. 2274 */ 2275 /*ARGSUSED*/ 2276 int 2277 cpuid_syscall32_insn(cpu_t *cpu) 2278 { 2279 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2280 2281 #if !defined(__xpv) 2282 if (cpu == NULL) 2283 cpu = CPU; 2284 2285 /*CSTYLED*/ 2286 { 2287 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2288 2289 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2290 cpi->cpi_xmaxeax >= 0x80000001 && 2291 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2292 return (1); 2293 } 2294 #endif 2295 return (0); 2296 } 2297 2298 int 2299 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2300 { 2301 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2302 2303 static const char fmt[] = 2304 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2305 static const char fmt_ht[] = 2306 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2307 2308 ASSERT(cpuid_checkpass(cpu, 1)); 2309 2310 if (cpuid_is_cmt(cpu)) 2311 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2312 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2313 cpi->cpi_family, cpi->cpi_model, 2314 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2315 return (snprintf(s, n, fmt, 2316 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2317 cpi->cpi_family, cpi->cpi_model, 2318 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2319 } 2320 2321 const char * 2322 cpuid_getvendorstr(cpu_t *cpu) 2323 { 2324 ASSERT(cpuid_checkpass(cpu, 1)); 2325 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2326 } 2327 2328 uint_t 2329 cpuid_getvendor(cpu_t *cpu) 2330 { 2331 ASSERT(cpuid_checkpass(cpu, 1)); 2332 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2333 } 2334 2335 uint_t 2336 cpuid_getfamily(cpu_t *cpu) 2337 { 2338 ASSERT(cpuid_checkpass(cpu, 1)); 2339 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2340 } 2341 2342 uint_t 2343 cpuid_getmodel(cpu_t *cpu) 2344 { 2345 ASSERT(cpuid_checkpass(cpu, 1)); 2346 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2347 } 2348 2349 uint_t 2350 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2351 { 2352 ASSERT(cpuid_checkpass(cpu, 1)); 2353 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2354 } 2355 2356 uint_t 2357 cpuid_get_ncore_per_chip(cpu_t *cpu) 2358 { 2359 ASSERT(cpuid_checkpass(cpu, 1)); 2360 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2361 } 2362 2363 uint_t 2364 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2365 { 2366 ASSERT(cpuid_checkpass(cpu, 2)); 2367 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2368 } 2369 2370 id_t 2371 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2372 { 2373 ASSERT(cpuid_checkpass(cpu, 2)); 2374 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2375 } 2376 2377 uint_t 2378 cpuid_getstep(cpu_t *cpu) 2379 { 2380 ASSERT(cpuid_checkpass(cpu, 1)); 2381 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2382 } 2383 2384 uint_t 2385 cpuid_getsig(struct cpu *cpu) 2386 { 2387 ASSERT(cpuid_checkpass(cpu, 1)); 2388 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2389 } 2390 2391 uint32_t 2392 cpuid_getchiprev(struct cpu *cpu) 2393 { 2394 ASSERT(cpuid_checkpass(cpu, 1)); 2395 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2396 } 2397 2398 const char * 2399 cpuid_getchiprevstr(struct cpu *cpu) 2400 { 2401 ASSERT(cpuid_checkpass(cpu, 1)); 2402 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2403 } 2404 2405 uint32_t 2406 cpuid_getsockettype(struct cpu *cpu) 2407 { 2408 ASSERT(cpuid_checkpass(cpu, 1)); 2409 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2410 } 2411 2412 int 2413 cpuid_get_chipid(cpu_t *cpu) 2414 { 2415 ASSERT(cpuid_checkpass(cpu, 1)); 2416 2417 if (cpuid_is_cmt(cpu)) 2418 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2419 return (cpu->cpu_id); 2420 } 2421 2422 id_t 2423 cpuid_get_coreid(cpu_t *cpu) 2424 { 2425 ASSERT(cpuid_checkpass(cpu, 1)); 2426 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2427 } 2428 2429 int 2430 cpuid_get_clogid(cpu_t *cpu) 2431 { 2432 ASSERT(cpuid_checkpass(cpu, 1)); 2433 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2434 } 2435 2436 void 2437 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2438 { 2439 struct cpuid_info *cpi; 2440 2441 if (cpu == NULL) 2442 cpu = CPU; 2443 cpi = cpu->cpu_m.mcpu_cpi; 2444 2445 ASSERT(cpuid_checkpass(cpu, 1)); 2446 2447 if (pabits) 2448 *pabits = cpi->cpi_pabits; 2449 if (vabits) 2450 *vabits = cpi->cpi_vabits; 2451 } 2452 2453 /* 2454 * Returns the number of data TLB entries for a corresponding 2455 * pagesize. If it can't be computed, or isn't known, the 2456 * routine returns zero. If you ask about an architecturally 2457 * impossible pagesize, the routine will panic (so that the 2458 * hat implementor knows that things are inconsistent.) 2459 */ 2460 uint_t 2461 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2462 { 2463 struct cpuid_info *cpi; 2464 uint_t dtlb_nent = 0; 2465 2466 if (cpu == NULL) 2467 cpu = CPU; 2468 cpi = cpu->cpu_m.mcpu_cpi; 2469 2470 ASSERT(cpuid_checkpass(cpu, 1)); 2471 2472 /* 2473 * Check the L2 TLB info 2474 */ 2475 if (cpi->cpi_xmaxeax >= 0x80000006) { 2476 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2477 2478 switch (pagesize) { 2479 2480 case 4 * 1024: 2481 /* 2482 * All zero in the top 16 bits of the register 2483 * indicates a unified TLB. Size is in low 16 bits. 2484 */ 2485 if ((cp->cp_ebx & 0xffff0000) == 0) 2486 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2487 else 2488 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2489 break; 2490 2491 case 2 * 1024 * 1024: 2492 if ((cp->cp_eax & 0xffff0000) == 0) 2493 dtlb_nent = cp->cp_eax & 0x0000ffff; 2494 else 2495 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2496 break; 2497 2498 default: 2499 panic("unknown L2 pagesize"); 2500 /*NOTREACHED*/ 2501 } 2502 } 2503 2504 if (dtlb_nent != 0) 2505 return (dtlb_nent); 2506 2507 /* 2508 * No L2 TLB support for this size, try L1. 2509 */ 2510 if (cpi->cpi_xmaxeax >= 0x80000005) { 2511 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2512 2513 switch (pagesize) { 2514 case 4 * 1024: 2515 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2516 break; 2517 case 2 * 1024 * 1024: 2518 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2519 break; 2520 default: 2521 panic("unknown L1 d-TLB pagesize"); 2522 /*NOTREACHED*/ 2523 } 2524 } 2525 2526 return (dtlb_nent); 2527 } 2528 2529 /* 2530 * Return 0 if the erratum is not present or not applicable, positive 2531 * if it is, and negative if the status of the erratum is unknown. 2532 * 2533 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2534 * Processors" #25759, Rev 3.57, August 2005 2535 */ 2536 int 2537 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2538 { 2539 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2540 uint_t eax; 2541 2542 /* 2543 * Bail out if this CPU isn't an AMD CPU, or if it's 2544 * a legacy (32-bit) AMD CPU. 2545 */ 2546 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2547 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2548 cpi->cpi_family == 6) 2549 2550 return (0); 2551 2552 eax = cpi->cpi_std[1].cp_eax; 2553 2554 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2555 #define SH_B3(eax) (eax == 0xf51) 2556 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2557 2558 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2559 2560 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2561 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2562 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2563 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2564 2565 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2566 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2567 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2568 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2569 2570 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2571 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2572 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2573 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2574 #define BH_E4(eax) (eax == 0x20fb1) 2575 #define SH_E5(eax) (eax == 0x20f42) 2576 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2577 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2578 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2579 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2580 DH_E6(eax) || JH_E6(eax)) 2581 2582 switch (erratum) { 2583 case 1: 2584 return (cpi->cpi_family < 0x10); 2585 case 51: /* what does the asterisk mean? */ 2586 return (B(eax) || SH_C0(eax) || CG(eax)); 2587 case 52: 2588 return (B(eax)); 2589 case 57: 2590 return (cpi->cpi_family <= 0x10); 2591 case 58: 2592 return (B(eax)); 2593 case 60: 2594 return (cpi->cpi_family <= 0x10); 2595 case 61: 2596 case 62: 2597 case 63: 2598 case 64: 2599 case 65: 2600 case 66: 2601 case 68: 2602 case 69: 2603 case 70: 2604 case 71: 2605 return (B(eax)); 2606 case 72: 2607 return (SH_B0(eax)); 2608 case 74: 2609 return (B(eax)); 2610 case 75: 2611 return (cpi->cpi_family < 0x10); 2612 case 76: 2613 return (B(eax)); 2614 case 77: 2615 return (cpi->cpi_family <= 0x10); 2616 case 78: 2617 return (B(eax) || SH_C0(eax)); 2618 case 79: 2619 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2620 case 80: 2621 case 81: 2622 case 82: 2623 return (B(eax)); 2624 case 83: 2625 return (B(eax) || SH_C0(eax) || CG(eax)); 2626 case 85: 2627 return (cpi->cpi_family < 0x10); 2628 case 86: 2629 return (SH_C0(eax) || CG(eax)); 2630 case 88: 2631 #if !defined(__amd64) 2632 return (0); 2633 #else 2634 return (B(eax) || SH_C0(eax)); 2635 #endif 2636 case 89: 2637 return (cpi->cpi_family < 0x10); 2638 case 90: 2639 return (B(eax) || SH_C0(eax) || CG(eax)); 2640 case 91: 2641 case 92: 2642 return (B(eax) || SH_C0(eax)); 2643 case 93: 2644 return (SH_C0(eax)); 2645 case 94: 2646 return (B(eax) || SH_C0(eax) || CG(eax)); 2647 case 95: 2648 #if !defined(__amd64) 2649 return (0); 2650 #else 2651 return (B(eax) || SH_C0(eax)); 2652 #endif 2653 case 96: 2654 return (B(eax) || SH_C0(eax) || CG(eax)); 2655 case 97: 2656 case 98: 2657 return (SH_C0(eax) || CG(eax)); 2658 case 99: 2659 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2660 case 100: 2661 return (B(eax) || SH_C0(eax)); 2662 case 101: 2663 case 103: 2664 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2665 case 104: 2666 return (SH_C0(eax) || CG(eax) || D0(eax)); 2667 case 105: 2668 case 106: 2669 case 107: 2670 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2671 case 108: 2672 return (DH_CG(eax)); 2673 case 109: 2674 return (SH_C0(eax) || CG(eax) || D0(eax)); 2675 case 110: 2676 return (D0(eax) || EX(eax)); 2677 case 111: 2678 return (CG(eax)); 2679 case 112: 2680 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2681 case 113: 2682 return (eax == 0x20fc0); 2683 case 114: 2684 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2685 case 115: 2686 return (SH_E0(eax) || JH_E1(eax)); 2687 case 116: 2688 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2689 case 117: 2690 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2691 case 118: 2692 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2693 JH_E6(eax)); 2694 case 121: 2695 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2696 case 122: 2697 return (cpi->cpi_family < 0x10); 2698 case 123: 2699 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2700 case 131: 2701 return (cpi->cpi_family < 0x10); 2702 case 6336786: 2703 /* 2704 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2705 * if this is a K8 family or newer processor 2706 */ 2707 if (CPI_FAMILY(cpi) == 0xf) { 2708 struct cpuid_regs regs; 2709 regs.cp_eax = 0x80000007; 2710 (void) __cpuid_insn(®s); 2711 return (!(regs.cp_edx & 0x100)); 2712 } 2713 return (0); 2714 case 6323525: 2715 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2716 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2717 2718 default: 2719 return (-1); 2720 } 2721 } 2722 2723 static const char assoc_str[] = "associativity"; 2724 static const char line_str[] = "line-size"; 2725 static const char size_str[] = "size"; 2726 2727 static void 2728 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2729 uint32_t val) 2730 { 2731 char buf[128]; 2732 2733 /* 2734 * ndi_prop_update_int() is used because it is desirable for 2735 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2736 */ 2737 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2738 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2739 } 2740 2741 /* 2742 * Intel-style cache/tlb description 2743 * 2744 * Standard cpuid level 2 gives a randomly ordered 2745 * selection of tags that index into a table that describes 2746 * cache and tlb properties. 2747 */ 2748 2749 static const char l1_icache_str[] = "l1-icache"; 2750 static const char l1_dcache_str[] = "l1-dcache"; 2751 static const char l2_cache_str[] = "l2-cache"; 2752 static const char l3_cache_str[] = "l3-cache"; 2753 static const char itlb4k_str[] = "itlb-4K"; 2754 static const char dtlb4k_str[] = "dtlb-4K"; 2755 static const char itlb4M_str[] = "itlb-4M"; 2756 static const char dtlb4M_str[] = "dtlb-4M"; 2757 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2758 static const char dtlb44_str[] = "dtlb-4K-4M"; 2759 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2760 static const char sl2_cache_str[] = "sectored-l2-cache"; 2761 static const char itrace_str[] = "itrace-cache"; 2762 static const char sl3_cache_str[] = "sectored-l3-cache"; 2763 2764 static const struct cachetab { 2765 uint8_t ct_code; 2766 uint8_t ct_assoc; 2767 uint16_t ct_line_size; 2768 size_t ct_size; 2769 const char *ct_label; 2770 } intel_ctab[] = { 2771 /* maintain descending order! */ 2772 { 0xb4, 4, 0, 256, dtlb4k_str }, 2773 { 0xb3, 4, 0, 128, dtlb4k_str }, 2774 { 0xb0, 4, 0, 128, itlb4k_str }, 2775 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2776 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2777 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2778 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2779 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2780 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2781 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2782 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2783 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2784 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2785 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2786 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2787 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2788 { 0x73, 8, 0, 64*1024, itrace_str}, 2789 { 0x72, 8, 0, 32*1024, itrace_str}, 2790 { 0x71, 8, 0, 16*1024, itrace_str}, 2791 { 0x70, 8, 0, 12*1024, itrace_str}, 2792 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2793 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2794 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2795 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2796 { 0x5d, 0, 0, 256, dtlb44_str}, 2797 { 0x5c, 0, 0, 128, dtlb44_str}, 2798 { 0x5b, 0, 0, 64, dtlb44_str}, 2799 { 0x52, 0, 0, 256, itlb424_str}, 2800 { 0x51, 0, 0, 128, itlb424_str}, 2801 { 0x50, 0, 0, 64, itlb424_str}, 2802 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2803 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2804 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2805 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2806 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2807 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2808 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2809 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2810 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2811 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2812 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2813 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2814 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2815 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2816 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2817 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2818 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2819 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2820 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2821 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2822 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2823 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2824 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2825 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2826 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2827 { 0x0b, 4, 0, 4, itlb4M_str}, 2828 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2829 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2830 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2831 { 0x04, 4, 0, 8, dtlb4M_str}, 2832 { 0x03, 4, 0, 64, dtlb4k_str}, 2833 { 0x02, 4, 0, 2, itlb4M_str}, 2834 { 0x01, 4, 0, 32, itlb4k_str}, 2835 { 0 } 2836 }; 2837 2838 static const struct cachetab cyrix_ctab[] = { 2839 { 0x70, 4, 0, 32, "tlb-4K" }, 2840 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2841 { 0 } 2842 }; 2843 2844 /* 2845 * Search a cache table for a matching entry 2846 */ 2847 static const struct cachetab * 2848 find_cacheent(const struct cachetab *ct, uint_t code) 2849 { 2850 if (code != 0) { 2851 for (; ct->ct_code != 0; ct++) 2852 if (ct->ct_code <= code) 2853 break; 2854 if (ct->ct_code == code) 2855 return (ct); 2856 } 2857 return (NULL); 2858 } 2859 2860 /* 2861 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2862 * The walk is terminated if the walker returns non-zero. 2863 */ 2864 static void 2865 intel_walk_cacheinfo(struct cpuid_info *cpi, 2866 void *arg, int (*func)(void *, const struct cachetab *)) 2867 { 2868 const struct cachetab *ct; 2869 uint8_t *dp; 2870 int i; 2871 2872 if ((dp = cpi->cpi_cacheinfo) == NULL) 2873 return; 2874 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2875 /* 2876 * For overloaded descriptor 0x49 we use cpuid function 4 2877 * if supported by the current processor, to update 2878 * cache information. 2879 */ 2880 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4) { 2881 intel_cpuid_4_cache_info(arg, cpi); 2882 continue; 2883 } 2884 2885 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2886 if (func(arg, ct) != 0) 2887 break; 2888 } 2889 } 2890 } 2891 2892 /* 2893 * (Like the Intel one, except for Cyrix CPUs) 2894 */ 2895 static void 2896 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2897 void *arg, int (*func)(void *, const struct cachetab *)) 2898 { 2899 const struct cachetab *ct; 2900 uint8_t *dp; 2901 int i; 2902 2903 if ((dp = cpi->cpi_cacheinfo) == NULL) 2904 return; 2905 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2906 /* 2907 * Search Cyrix-specific descriptor table first .. 2908 */ 2909 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2910 if (func(arg, ct) != 0) 2911 break; 2912 continue; 2913 } 2914 /* 2915 * .. else fall back to the Intel one 2916 */ 2917 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2918 if (func(arg, ct) != 0) 2919 break; 2920 continue; 2921 } 2922 } 2923 } 2924 2925 /* 2926 * A cacheinfo walker that adds associativity, line-size, and size properties 2927 * to the devinfo node it is passed as an argument. 2928 */ 2929 static int 2930 add_cacheent_props(void *arg, const struct cachetab *ct) 2931 { 2932 dev_info_t *devi = arg; 2933 2934 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2935 if (ct->ct_line_size != 0) 2936 add_cache_prop(devi, ct->ct_label, line_str, 2937 ct->ct_line_size); 2938 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2939 return (0); 2940 } 2941 2942 /* 2943 * Add L2 or L3 cache-information using cpuid function 4. This 2944 * function is called from intel_walk_cacheinfo() when descriptor 2945 * 0x49 is encountered. 2946 */ 2947 static void 2948 intel_cpuid_4_cache_info(void *arg, struct cpuid_info *cpi) 2949 { 2950 uint32_t level, i; 2951 2952 struct cachetab ct; 2953 2954 for (i = 0; i < cpi->cpi_std_4_size; i++) { 2955 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 2956 2957 if (level == 2 || level == 3) { 2958 ct.ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 2959 ct.ct_line_size = 2960 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 2961 ct.ct_size = ct.ct_assoc * 2962 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 2963 ct.ct_line_size * 2964 (cpi->cpi_std_4[i]->cp_ecx + 1); 2965 2966 if (level == 2) { 2967 ct.ct_label = l2_cache_str; 2968 } else if (level == 3) { 2969 ct.ct_label = l3_cache_str; 2970 } 2971 2972 (void) add_cacheent_props(arg, 2973 (const struct cachetab *) (&ct)); 2974 } 2975 } 2976 } 2977 2978 static const char fully_assoc[] = "fully-associative?"; 2979 2980 /* 2981 * AMD style cache/tlb description 2982 * 2983 * Extended functions 5 and 6 directly describe properties of 2984 * tlbs and various cache levels. 2985 */ 2986 static void 2987 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2988 { 2989 switch (assoc) { 2990 case 0: /* reserved; ignore */ 2991 break; 2992 default: 2993 add_cache_prop(devi, label, assoc_str, assoc); 2994 break; 2995 case 0xff: 2996 add_cache_prop(devi, label, fully_assoc, 1); 2997 break; 2998 } 2999 } 3000 3001 static void 3002 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3003 { 3004 if (size == 0) 3005 return; 3006 add_cache_prop(devi, label, size_str, size); 3007 add_amd_assoc(devi, label, assoc); 3008 } 3009 3010 static void 3011 add_amd_cache(dev_info_t *devi, const char *label, 3012 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3013 { 3014 if (size == 0 || line_size == 0) 3015 return; 3016 add_amd_assoc(devi, label, assoc); 3017 /* 3018 * Most AMD parts have a sectored cache. Multiple cache lines are 3019 * associated with each tag. A sector consists of all cache lines 3020 * associated with a tag. For example, the AMD K6-III has a sector 3021 * size of 2 cache lines per tag. 3022 */ 3023 if (lines_per_tag != 0) 3024 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3025 add_cache_prop(devi, label, line_str, line_size); 3026 add_cache_prop(devi, label, size_str, size * 1024); 3027 } 3028 3029 static void 3030 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3031 { 3032 switch (assoc) { 3033 case 0: /* off */ 3034 break; 3035 case 1: 3036 case 2: 3037 case 4: 3038 add_cache_prop(devi, label, assoc_str, assoc); 3039 break; 3040 case 6: 3041 add_cache_prop(devi, label, assoc_str, 8); 3042 break; 3043 case 8: 3044 add_cache_prop(devi, label, assoc_str, 16); 3045 break; 3046 case 0xf: 3047 add_cache_prop(devi, label, fully_assoc, 1); 3048 break; 3049 default: /* reserved; ignore */ 3050 break; 3051 } 3052 } 3053 3054 static void 3055 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3056 { 3057 if (size == 0 || assoc == 0) 3058 return; 3059 add_amd_l2_assoc(devi, label, assoc); 3060 add_cache_prop(devi, label, size_str, size); 3061 } 3062 3063 static void 3064 add_amd_l2_cache(dev_info_t *devi, const char *label, 3065 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3066 { 3067 if (size == 0 || assoc == 0 || line_size == 0) 3068 return; 3069 add_amd_l2_assoc(devi, label, assoc); 3070 if (lines_per_tag != 0) 3071 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3072 add_cache_prop(devi, label, line_str, line_size); 3073 add_cache_prop(devi, label, size_str, size * 1024); 3074 } 3075 3076 static void 3077 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3078 { 3079 struct cpuid_regs *cp; 3080 3081 if (cpi->cpi_xmaxeax < 0x80000005) 3082 return; 3083 cp = &cpi->cpi_extd[5]; 3084 3085 /* 3086 * 4M/2M L1 TLB configuration 3087 * 3088 * We report the size for 2M pages because AMD uses two 3089 * TLB entries for one 4M page. 3090 */ 3091 add_amd_tlb(devi, "dtlb-2M", 3092 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3093 add_amd_tlb(devi, "itlb-2M", 3094 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3095 3096 /* 3097 * 4K L1 TLB configuration 3098 */ 3099 3100 switch (cpi->cpi_vendor) { 3101 uint_t nentries; 3102 case X86_VENDOR_TM: 3103 if (cpi->cpi_family >= 5) { 3104 /* 3105 * Crusoe processors have 256 TLB entries, but 3106 * cpuid data format constrains them to only 3107 * reporting 255 of them. 3108 */ 3109 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3110 nentries = 256; 3111 /* 3112 * Crusoe processors also have a unified TLB 3113 */ 3114 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3115 nentries); 3116 break; 3117 } 3118 /*FALLTHROUGH*/ 3119 default: 3120 add_amd_tlb(devi, itlb4k_str, 3121 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3122 add_amd_tlb(devi, dtlb4k_str, 3123 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3124 break; 3125 } 3126 3127 /* 3128 * data L1 cache configuration 3129 */ 3130 3131 add_amd_cache(devi, l1_dcache_str, 3132 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3133 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3134 3135 /* 3136 * code L1 cache configuration 3137 */ 3138 3139 add_amd_cache(devi, l1_icache_str, 3140 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3141 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3142 3143 if (cpi->cpi_xmaxeax < 0x80000006) 3144 return; 3145 cp = &cpi->cpi_extd[6]; 3146 3147 /* Check for a unified L2 TLB for large pages */ 3148 3149 if (BITX(cp->cp_eax, 31, 16) == 0) 3150 add_amd_l2_tlb(devi, "l2-tlb-2M", 3151 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3152 else { 3153 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3154 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3155 add_amd_l2_tlb(devi, "l2-itlb-2M", 3156 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3157 } 3158 3159 /* Check for a unified L2 TLB for 4K pages */ 3160 3161 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3162 add_amd_l2_tlb(devi, "l2-tlb-4K", 3163 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3164 } else { 3165 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3166 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3167 add_amd_l2_tlb(devi, "l2-itlb-4K", 3168 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3169 } 3170 3171 add_amd_l2_cache(devi, l2_cache_str, 3172 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3173 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3174 } 3175 3176 /* 3177 * There are two basic ways that the x86 world describes it cache 3178 * and tlb architecture - Intel's way and AMD's way. 3179 * 3180 * Return which flavor of cache architecture we should use 3181 */ 3182 static int 3183 x86_which_cacheinfo(struct cpuid_info *cpi) 3184 { 3185 switch (cpi->cpi_vendor) { 3186 case X86_VENDOR_Intel: 3187 if (cpi->cpi_maxeax >= 2) 3188 return (X86_VENDOR_Intel); 3189 break; 3190 case X86_VENDOR_AMD: 3191 /* 3192 * The K5 model 1 was the first part from AMD that reported 3193 * cache sizes via extended cpuid functions. 3194 */ 3195 if (cpi->cpi_family > 5 || 3196 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3197 return (X86_VENDOR_AMD); 3198 break; 3199 case X86_VENDOR_TM: 3200 if (cpi->cpi_family >= 5) 3201 return (X86_VENDOR_AMD); 3202 /*FALLTHROUGH*/ 3203 default: 3204 /* 3205 * If they have extended CPU data for 0x80000005 3206 * then we assume they have AMD-format cache 3207 * information. 3208 * 3209 * If not, and the vendor happens to be Cyrix, 3210 * then try our-Cyrix specific handler. 3211 * 3212 * If we're not Cyrix, then assume we're using Intel's 3213 * table-driven format instead. 3214 */ 3215 if (cpi->cpi_xmaxeax >= 0x80000005) 3216 return (X86_VENDOR_AMD); 3217 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3218 return (X86_VENDOR_Cyrix); 3219 else if (cpi->cpi_maxeax >= 2) 3220 return (X86_VENDOR_Intel); 3221 break; 3222 } 3223 return (-1); 3224 } 3225 3226 /* 3227 * create a node for the given cpu under the prom root node. 3228 * Also, create a cpu node in the device tree. 3229 */ 3230 static dev_info_t *cpu_nex_devi = NULL; 3231 static kmutex_t cpu_node_lock; 3232 3233 /* 3234 * Called from post_startup() and mp_startup() 3235 */ 3236 void 3237 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3238 { 3239 dev_info_t *cpu_devi; 3240 int create; 3241 3242 mutex_enter(&cpu_node_lock); 3243 3244 /* 3245 * create a nexus node for all cpus identified as 'cpu_id' under 3246 * the root node. 3247 */ 3248 if (cpu_nex_devi == NULL) { 3249 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3250 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3251 mutex_exit(&cpu_node_lock); 3252 return; 3253 } 3254 (void) ndi_devi_online(cpu_nex_devi, 0); 3255 } 3256 3257 /* 3258 * create a child node for cpu identified as 'cpu_id' 3259 */ 3260 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3261 cpu_id); 3262 if (cpu_devi == NULL) { 3263 mutex_exit(&cpu_node_lock); 3264 return; 3265 } 3266 3267 /* device_type */ 3268 3269 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3270 "device_type", "cpu"); 3271 3272 /* reg */ 3273 3274 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3275 "reg", cpu_id); 3276 3277 /* cpu-mhz, and clock-frequency */ 3278 3279 if (cpu_freq > 0) { 3280 long long mul; 3281 3282 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3283 "cpu-mhz", cpu_freq); 3284 3285 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3286 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3287 "clock-frequency", (int)mul); 3288 } 3289 3290 (void) ndi_devi_online(cpu_devi, 0); 3291 3292 if ((x86_feature & X86_CPUID) == 0) { 3293 mutex_exit(&cpu_node_lock); 3294 return; 3295 } 3296 3297 /* vendor-id */ 3298 3299 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3300 "vendor-id", cpi->cpi_vendorstr); 3301 3302 if (cpi->cpi_maxeax == 0) { 3303 mutex_exit(&cpu_node_lock); 3304 return; 3305 } 3306 3307 /* 3308 * family, model, and step 3309 */ 3310 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3311 "family", CPI_FAMILY(cpi)); 3312 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3313 "cpu-model", CPI_MODEL(cpi)); 3314 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3315 "stepping-id", CPI_STEP(cpi)); 3316 3317 /* type */ 3318 3319 switch (cpi->cpi_vendor) { 3320 case X86_VENDOR_Intel: 3321 create = 1; 3322 break; 3323 default: 3324 create = 0; 3325 break; 3326 } 3327 if (create) 3328 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3329 "type", CPI_TYPE(cpi)); 3330 3331 /* ext-family */ 3332 3333 switch (cpi->cpi_vendor) { 3334 case X86_VENDOR_Intel: 3335 case X86_VENDOR_AMD: 3336 create = cpi->cpi_family >= 0xf; 3337 break; 3338 default: 3339 create = 0; 3340 break; 3341 } 3342 if (create) 3343 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3344 "ext-family", CPI_FAMILY_XTD(cpi)); 3345 3346 /* ext-model */ 3347 3348 switch (cpi->cpi_vendor) { 3349 case X86_VENDOR_Intel: 3350 create = CPI_MODEL(cpi) == 0xf; 3351 break; 3352 case X86_VENDOR_AMD: 3353 create = CPI_FAMILY(cpi) == 0xf; 3354 break; 3355 default: 3356 create = 0; 3357 break; 3358 } 3359 if (create) 3360 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3361 "ext-model", CPI_MODEL_XTD(cpi)); 3362 3363 /* generation */ 3364 3365 switch (cpi->cpi_vendor) { 3366 case X86_VENDOR_AMD: 3367 /* 3368 * AMD K5 model 1 was the first part to support this 3369 */ 3370 create = cpi->cpi_xmaxeax >= 0x80000001; 3371 break; 3372 default: 3373 create = 0; 3374 break; 3375 } 3376 if (create) 3377 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3378 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3379 3380 /* brand-id */ 3381 3382 switch (cpi->cpi_vendor) { 3383 case X86_VENDOR_Intel: 3384 /* 3385 * brand id first appeared on Pentium III Xeon model 8, 3386 * and Celeron model 8 processors and Opteron 3387 */ 3388 create = cpi->cpi_family > 6 || 3389 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3390 break; 3391 case X86_VENDOR_AMD: 3392 create = cpi->cpi_family >= 0xf; 3393 break; 3394 default: 3395 create = 0; 3396 break; 3397 } 3398 if (create && cpi->cpi_brandid != 0) { 3399 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3400 "brand-id", cpi->cpi_brandid); 3401 } 3402 3403 /* chunks, and apic-id */ 3404 3405 switch (cpi->cpi_vendor) { 3406 /* 3407 * first available on Pentium IV and Opteron (K8) 3408 */ 3409 case X86_VENDOR_Intel: 3410 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3411 break; 3412 case X86_VENDOR_AMD: 3413 create = cpi->cpi_family >= 0xf; 3414 break; 3415 default: 3416 create = 0; 3417 break; 3418 } 3419 if (create) { 3420 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3421 "chunks", CPI_CHUNKS(cpi)); 3422 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3423 "apic-id", CPI_APIC_ID(cpi)); 3424 if (cpi->cpi_chipid >= 0) { 3425 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3426 "chip#", cpi->cpi_chipid); 3427 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3428 "clog#", cpi->cpi_clogid); 3429 } 3430 } 3431 3432 /* cpuid-features */ 3433 3434 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3435 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3436 3437 3438 /* cpuid-features-ecx */ 3439 3440 switch (cpi->cpi_vendor) { 3441 case X86_VENDOR_Intel: 3442 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3443 break; 3444 default: 3445 create = 0; 3446 break; 3447 } 3448 if (create) 3449 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3450 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3451 3452 /* ext-cpuid-features */ 3453 3454 switch (cpi->cpi_vendor) { 3455 case X86_VENDOR_Intel: 3456 case X86_VENDOR_AMD: 3457 case X86_VENDOR_Cyrix: 3458 case X86_VENDOR_TM: 3459 case X86_VENDOR_Centaur: 3460 create = cpi->cpi_xmaxeax >= 0x80000001; 3461 break; 3462 default: 3463 create = 0; 3464 break; 3465 } 3466 if (create) { 3467 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3468 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3469 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3470 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3471 } 3472 3473 /* 3474 * Brand String first appeared in Intel Pentium IV, AMD K5 3475 * model 1, and Cyrix GXm. On earlier models we try and 3476 * simulate something similar .. so this string should always 3477 * same -something- about the processor, however lame. 3478 */ 3479 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3480 "brand-string", cpi->cpi_brandstr); 3481 3482 /* 3483 * Finally, cache and tlb information 3484 */ 3485 switch (x86_which_cacheinfo(cpi)) { 3486 case X86_VENDOR_Intel: 3487 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3488 break; 3489 case X86_VENDOR_Cyrix: 3490 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3491 break; 3492 case X86_VENDOR_AMD: 3493 amd_cache_info(cpi, cpu_devi); 3494 break; 3495 default: 3496 break; 3497 } 3498 3499 mutex_exit(&cpu_node_lock); 3500 } 3501 3502 struct l2info { 3503 int *l2i_csz; 3504 int *l2i_lsz; 3505 int *l2i_assoc; 3506 int l2i_ret; 3507 }; 3508 3509 /* 3510 * A cacheinfo walker that fetches the size, line-size and associativity 3511 * of the L2 cache 3512 */ 3513 static int 3514 intel_l2cinfo(void *arg, const struct cachetab *ct) 3515 { 3516 struct l2info *l2i = arg; 3517 int *ip; 3518 3519 if (ct->ct_label != l2_cache_str && 3520 ct->ct_label != sl2_cache_str) 3521 return (0); /* not an L2 -- keep walking */ 3522 3523 if ((ip = l2i->l2i_csz) != NULL) 3524 *ip = ct->ct_size; 3525 if ((ip = l2i->l2i_lsz) != NULL) 3526 *ip = ct->ct_line_size; 3527 if ((ip = l2i->l2i_assoc) != NULL) 3528 *ip = ct->ct_assoc; 3529 l2i->l2i_ret = ct->ct_size; 3530 return (1); /* was an L2 -- terminate walk */ 3531 } 3532 3533 /* 3534 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3535 * 3536 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3537 * value is the associativity, the associativity for the L2 cache and 3538 * tlb is encoded in the following table. The 4 bit L2 value serves as 3539 * an index into the amd_afd[] array to determine the associativity. 3540 * -1 is undefined. 0 is fully associative. 3541 */ 3542 3543 static int amd_afd[] = 3544 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3545 3546 static void 3547 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3548 { 3549 struct cpuid_regs *cp; 3550 uint_t size, assoc; 3551 int i; 3552 int *ip; 3553 3554 if (cpi->cpi_xmaxeax < 0x80000006) 3555 return; 3556 cp = &cpi->cpi_extd[6]; 3557 3558 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3559 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3560 uint_t cachesz = size * 1024; 3561 assoc = amd_afd[i]; 3562 3563 ASSERT(assoc != -1); 3564 3565 if ((ip = l2i->l2i_csz) != NULL) 3566 *ip = cachesz; 3567 if ((ip = l2i->l2i_lsz) != NULL) 3568 *ip = BITX(cp->cp_ecx, 7, 0); 3569 if ((ip = l2i->l2i_assoc) != NULL) 3570 *ip = assoc; 3571 l2i->l2i_ret = cachesz; 3572 } 3573 } 3574 3575 int 3576 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3577 { 3578 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3579 struct l2info __l2info, *l2i = &__l2info; 3580 3581 l2i->l2i_csz = csz; 3582 l2i->l2i_lsz = lsz; 3583 l2i->l2i_assoc = assoc; 3584 l2i->l2i_ret = -1; 3585 3586 switch (x86_which_cacheinfo(cpi)) { 3587 case X86_VENDOR_Intel: 3588 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3589 break; 3590 case X86_VENDOR_Cyrix: 3591 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3592 break; 3593 case X86_VENDOR_AMD: 3594 amd_l2cacheinfo(cpi, l2i); 3595 break; 3596 default: 3597 break; 3598 } 3599 return (l2i->l2i_ret); 3600 } 3601 3602 #if !defined(__xpv) 3603 3604 uint32_t * 3605 cpuid_mwait_alloc(cpu_t *cpu) 3606 { 3607 uint32_t *ret; 3608 size_t mwait_size; 3609 3610 ASSERT(cpuid_checkpass(cpu, 2)); 3611 3612 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3613 if (mwait_size == 0) 3614 return (NULL); 3615 3616 /* 3617 * kmem_alloc() returns cache line size aligned data for mwait_size 3618 * allocations. mwait_size is currently cache line sized. Neither 3619 * of these implementation details are guarantied to be true in the 3620 * future. 3621 * 3622 * First try allocating mwait_size as kmem_alloc() currently returns 3623 * correctly aligned memory. If kmem_alloc() does not return 3624 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3625 * 3626 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3627 * decide to free this memory. 3628 */ 3629 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3630 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3631 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3632 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3633 *ret = MWAIT_RUNNING; 3634 return (ret); 3635 } else { 3636 kmem_free(ret, mwait_size); 3637 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3638 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3639 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3640 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3641 *ret = MWAIT_RUNNING; 3642 return (ret); 3643 } 3644 } 3645 3646 void 3647 cpuid_mwait_free(cpu_t *cpu) 3648 { 3649 ASSERT(cpuid_checkpass(cpu, 2)); 3650 3651 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3652 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3653 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3654 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3655 } 3656 3657 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3658 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3659 } 3660 3661 #endif /* !__xpv */ 3662