1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/sysmacros.h> 44 #include <sys/pg.h> 45 #include <sys/fp.h> 46 #include <sys/controlregs.h> 47 #include <sys/auxv_386.h> 48 #include <sys/bitmap.h> 49 #include <sys/memnode.h> 50 51 /* 52 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 53 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 54 * them accordingly. For most modern processors, feature detection occurs here 55 * in pass 1. 56 * 57 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 58 * for the boot CPU and does the basic analysis that the early kernel needs. 59 * x86_feature is set based on the return value of cpuid_pass1() of the boot 60 * CPU. 61 * 62 * Pass 1 includes: 63 * 64 * o Determining vendor/model/family/stepping and setting x86_type and 65 * x86_vendor accordingly. 66 * o Processing the feature flags returned by the cpuid instruction while 67 * applying any workarounds or tricks for the specific processor. 68 * o Mapping the feature flags into Solaris feature bits (X86_*). 69 * o Processing extended feature flags if supported by the processor, 70 * again while applying specific processor knowledge. 71 * o Determining the CMT characteristics of the system. 72 * 73 * Pass 1 is done on non-boot CPUs during their initialization and the results 74 * are used only as a meager attempt at ensuring that all processors within the 75 * system support the same features. 76 * 77 * Pass 2 of cpuid feature analysis happens just at the beginning 78 * of startup(). It just copies in and corrects the remainder 79 * of the cpuid data we depend on: standard cpuid functions that we didn't 80 * need for pass1 feature analysis, and extended cpuid functions beyond the 81 * simple feature processing done in pass1. 82 * 83 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 84 * particular kernel memory allocation has been made available. It creates a 85 * readable brand string based on the data collected in the first two passes. 86 * 87 * Pass 4 of cpuid analysis is invoked after post_startup() when all 88 * the support infrastructure for various hardware features has been 89 * initialized. It determines which processor features will be reported 90 * to userland via the aux vector. 91 * 92 * All passes are executed on all CPUs, but only the boot CPU determines what 93 * features the kernel will use. 94 * 95 * Much of the worst junk in this file is for the support of processors 96 * that didn't really implement the cpuid instruction properly. 97 * 98 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 99 * the pass numbers. Accordingly, changes to the pass code may require changes 100 * to the accessor code. 101 */ 102 103 uint_t x86_feature = 0; 104 uint_t x86_vendor = X86_VENDOR_IntelClone; 105 uint_t x86_type = X86_TYPE_OTHER; 106 107 uint_t pentiumpro_bug4046376; 108 uint_t pentiumpro_bug4064495; 109 110 uint_t enable486; 111 112 /* 113 * This set of strings are for processors rumored to support the cpuid 114 * instruction, and is used by locore.s to figure out how to set x86_vendor 115 */ 116 const char CyrixInstead[] = "CyrixInstead"; 117 118 /* 119 * monitor/mwait info. 120 * 121 * size_actual and buf_actual are the real address and size allocated to get 122 * proper mwait_buf alignement. buf_actual and size_actual should be passed 123 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 124 * processor cache-line alignment, but this is not guarantied in the furture. 125 */ 126 struct mwait_info { 127 size_t mon_min; /* min size to avoid missed wakeups */ 128 size_t mon_max; /* size to avoid false wakeups */ 129 size_t size_actual; /* size actually allocated */ 130 void *buf_actual; /* memory actually allocated */ 131 uint32_t support; /* processor support of monitor/mwait */ 132 }; 133 134 /* 135 * These constants determine how many of the elements of the 136 * cpuid we cache in the cpuid_info data structure; the 137 * remaining elements are accessible via the cpuid instruction. 138 */ 139 140 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 141 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 142 143 struct cpuid_info { 144 uint_t cpi_pass; /* last pass completed */ 145 /* 146 * standard function information 147 */ 148 uint_t cpi_maxeax; /* fn 0: %eax */ 149 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 150 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 151 152 uint_t cpi_family; /* fn 1: extended family */ 153 uint_t cpi_model; /* fn 1: extended model */ 154 uint_t cpi_step; /* fn 1: stepping */ 155 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 156 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 157 int cpi_clogid; /* fn 1: %ebx: thread # */ 158 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 159 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 160 uint_t cpi_ncache; /* fn 2: number of elements */ 161 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 162 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 163 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 164 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 165 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 166 /* 167 * extended function information 168 */ 169 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 170 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 171 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 172 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 173 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 174 id_t cpi_coreid; 175 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 176 /* Intel: fn 4: %eax[31-26] */ 177 /* 178 * supported feature information 179 */ 180 uint32_t cpi_support[5]; 181 #define STD_EDX_FEATURES 0 182 #define AMD_EDX_FEATURES 1 183 #define TM_EDX_FEATURES 2 184 #define STD_ECX_FEATURES 3 185 #define AMD_ECX_FEATURES 4 186 /* 187 * Synthesized information, where known. 188 */ 189 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 190 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 191 uint32_t cpi_socket; /* Chip package/socket type */ 192 193 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 194 }; 195 196 197 static struct cpuid_info cpuid_info0; 198 199 /* 200 * These bit fields are defined by the Intel Application Note AP-485 201 * "Intel Processor Identification and the CPUID Instruction" 202 */ 203 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 204 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 205 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 206 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 207 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 208 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 209 210 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 211 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 212 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 213 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 214 215 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 216 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 217 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 218 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 219 220 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 221 #define CPI_XMAXEAX_MAX 0x80000100 222 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 223 224 /* 225 * Function 4 (Deterministic Cache Parameters) macros 226 * Defined by Intel Application Note AP-485 227 */ 228 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 229 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 230 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 231 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 232 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 233 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 234 235 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 236 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 237 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 238 239 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 240 241 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 242 243 244 /* 245 * A couple of shorthand macros to identify "later" P6-family chips 246 * like the Pentium M and Core. First, the "older" P6-based stuff 247 * (loosely defined as "pre-Pentium-4"): 248 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 249 */ 250 251 #define IS_LEGACY_P6(cpi) ( \ 252 cpi->cpi_family == 6 && \ 253 (cpi->cpi_model == 1 || \ 254 cpi->cpi_model == 3 || \ 255 cpi->cpi_model == 5 || \ 256 cpi->cpi_model == 6 || \ 257 cpi->cpi_model == 7 || \ 258 cpi->cpi_model == 8 || \ 259 cpi->cpi_model == 0xA || \ 260 cpi->cpi_model == 0xB) \ 261 ) 262 263 /* A "new F6" is everything with family 6 that's not the above */ 264 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 265 266 /* Extended family/model support */ 267 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 268 cpi->cpi_family >= 0xf) 269 270 /* 271 * AMD family 0xf and family 0x10 socket types. 272 * First index : 273 * 0 for family 0xf, revs B thru E 274 * 1 for family 0xf, revs F and G 275 * 2 for family 0x10, rev B 276 * Second index by (model & 0x3) 277 */ 278 static uint32_t amd_skts[3][4] = { 279 /* 280 * Family 0xf revisions B through E 281 */ 282 #define A_SKTS_0 0 283 { 284 X86_SOCKET_754, /* 0b00 */ 285 X86_SOCKET_940, /* 0b01 */ 286 X86_SOCKET_754, /* 0b10 */ 287 X86_SOCKET_939 /* 0b11 */ 288 }, 289 /* 290 * Family 0xf revisions F and G 291 */ 292 #define A_SKTS_1 1 293 { 294 X86_SOCKET_S1g1, /* 0b00 */ 295 X86_SOCKET_F1207, /* 0b01 */ 296 X86_SOCKET_UNKNOWN, /* 0b10 */ 297 X86_SOCKET_AM2 /* 0b11 */ 298 }, 299 /* 300 * Family 0x10 revisions A and B 301 * It is not clear whether, as new sockets release, that 302 * model & 0x3 will id socket for this family 303 */ 304 #define A_SKTS_2 2 305 { 306 X86_SOCKET_F1207, /* 0b00 */ 307 X86_SOCKET_F1207, /* 0b01 */ 308 X86_SOCKET_F1207, /* 0b10 */ 309 X86_SOCKET_F1207, /* 0b11 */ 310 } 311 }; 312 313 /* 314 * Table for mapping AMD Family 0xf and AMD Family 0x10 model/stepping 315 * combination to chip "revision" and socket type. 316 * 317 * The first member of this array that matches a given family, extended model 318 * plus model range, and stepping range will be considered a match. 319 */ 320 static const struct amd_rev_mapent { 321 uint_t rm_family; 322 uint_t rm_modello; 323 uint_t rm_modelhi; 324 uint_t rm_steplo; 325 uint_t rm_stephi; 326 uint32_t rm_chiprev; 327 const char *rm_chiprevstr; 328 int rm_sktidx; 329 } amd_revmap[] = { 330 /* 331 * =============== AuthenticAMD Family 0xf =============== 332 */ 333 334 /* 335 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 336 */ 337 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 338 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 339 /* 340 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 341 */ 342 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", A_SKTS_0 }, 343 /* 344 * Rev CG is the rest of extended model 0x0 - i.e., everything 345 * but the rev B and C0 combinations covered above. 346 */ 347 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", A_SKTS_0 }, 348 /* 349 * Rev D has extended model 0x1. 350 */ 351 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", A_SKTS_0 }, 352 /* 353 * Rev E has extended model 0x2. 354 * Extended model 0x3 is unused but available to grow into. 355 */ 356 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", A_SKTS_0 }, 357 /* 358 * Rev F has extended models 0x4 and 0x5. 359 */ 360 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", A_SKTS_1 }, 361 /* 362 * Rev G has extended model 0x6. 363 */ 364 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", A_SKTS_1 }, 365 366 /* 367 * =============== AuthenticAMD Family 0x10 =============== 368 */ 369 370 /* 371 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}. 372 * Give all of model 0 stepping range to rev A. 373 */ 374 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_A, "A", A_SKTS_2 }, 375 376 /* 377 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}. 378 * Give all of model 2 stepping range to rev B. 379 */ 380 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_B, "B", A_SKTS_2 }, 381 }; 382 383 /* 384 * Info for monitor/mwait idle loop. 385 * 386 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 387 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 388 * 2006. 389 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 390 * Documentation Updates" #33633, Rev 2.05, December 2006. 391 */ 392 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 393 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 394 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 395 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 396 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 397 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 398 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 399 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 400 /* 401 * Number of sub-cstates for a given c-state. 402 */ 403 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 404 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 405 406 static void intel_cpuid_4_cache_info(void *, struct cpuid_info *); 407 408 static void 409 synth_amd_info(struct cpuid_info *cpi) 410 { 411 const struct amd_rev_mapent *rmp; 412 uint_t family, model, step; 413 int i; 414 415 /* 416 * Currently only AMD family 0xf and family 0x10 use these fields. 417 */ 418 if (cpi->cpi_family != 0xf && cpi->cpi_family != 0x10) 419 return; 420 421 family = cpi->cpi_family; 422 model = cpi->cpi_model; 423 step = cpi->cpi_step; 424 425 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); 426 i++, rmp++) { 427 if (family == rmp->rm_family && 428 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 429 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 430 cpi->cpi_chiprev = rmp->rm_chiprev; 431 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; 432 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; 433 return; 434 } 435 } 436 } 437 438 static void 439 synth_info(struct cpuid_info *cpi) 440 { 441 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; 442 cpi->cpi_chiprevstr = "Unknown"; 443 cpi->cpi_socket = X86_SOCKET_UNKNOWN; 444 445 switch (cpi->cpi_vendor) { 446 case X86_VENDOR_AMD: 447 synth_amd_info(cpi); 448 break; 449 450 default: 451 break; 452 453 } 454 } 455 456 /* 457 * Apply up various platform-dependent restrictions where the 458 * underlying platform restrictions mean the CPU can be marked 459 * as less capable than its cpuid instruction would imply. 460 */ 461 #if defined(__xpv) 462 static void 463 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 464 { 465 switch (eax) { 466 case 1: 467 cp->cp_edx &= 468 ~(CPUID_INTC_EDX_PSE | 469 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 470 CPUID_INTC_EDX_MCA | /* XXPV true on dom0? */ 471 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 472 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 473 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 474 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 475 break; 476 477 case 0x80000001: 478 cp->cp_edx &= 479 ~(CPUID_AMD_EDX_PSE | 480 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 481 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 482 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 483 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 484 CPUID_AMD_EDX_TSCP); 485 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 486 break; 487 default: 488 break; 489 } 490 491 switch (vendor) { 492 case X86_VENDOR_Intel: 493 switch (eax) { 494 case 4: 495 /* 496 * Zero out the (ncores-per-chip - 1) field 497 */ 498 cp->cp_eax &= 0x03fffffff; 499 break; 500 default: 501 break; 502 } 503 break; 504 case X86_VENDOR_AMD: 505 switch (eax) { 506 case 0x80000008: 507 /* 508 * Zero out the (ncores-per-chip - 1) field 509 */ 510 cp->cp_ecx &= 0xffffff00; 511 break; 512 default: 513 break; 514 } 515 break; 516 default: 517 break; 518 } 519 } 520 #else 521 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 522 #endif 523 524 /* 525 * Some undocumented ways of patching the results of the cpuid 526 * instruction to permit running Solaris 10 on future cpus that 527 * we don't currently support. Could be set to non-zero values 528 * via settings in eeprom. 529 */ 530 531 uint32_t cpuid_feature_ecx_include; 532 uint32_t cpuid_feature_ecx_exclude; 533 uint32_t cpuid_feature_edx_include; 534 uint32_t cpuid_feature_edx_exclude; 535 536 void 537 cpuid_alloc_space(cpu_t *cpu) 538 { 539 /* 540 * By convention, cpu0 is the boot cpu, which is set up 541 * before memory allocation is available. All other cpus get 542 * their cpuid_info struct allocated here. 543 */ 544 ASSERT(cpu->cpu_id != 0); 545 cpu->cpu_m.mcpu_cpi = 546 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 547 } 548 549 void 550 cpuid_free_space(cpu_t *cpu) 551 { 552 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 553 int i; 554 555 ASSERT(cpu->cpu_id != 0); 556 557 /* 558 * Free up any function 4 related dynamic storage 559 */ 560 for (i = 1; i < cpi->cpi_std_4_size; i++) 561 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 562 if (cpi->cpi_std_4_size > 0) 563 kmem_free(cpi->cpi_std_4, 564 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 565 566 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 567 } 568 569 uint_t 570 cpuid_pass1(cpu_t *cpu) 571 { 572 uint32_t mask_ecx, mask_edx; 573 uint_t feature = X86_CPUID; 574 struct cpuid_info *cpi; 575 struct cpuid_regs *cp; 576 int xcpuid; 577 #if !defined(__xpv) 578 extern int idle_cpu_prefer_mwait; 579 #endif 580 581 /* 582 * Space statically allocated for cpu0, ensure pointer is set 583 */ 584 if (cpu->cpu_id == 0) 585 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 586 cpi = cpu->cpu_m.mcpu_cpi; 587 ASSERT(cpi != NULL); 588 cp = &cpi->cpi_std[0]; 589 cp->cp_eax = 0; 590 cpi->cpi_maxeax = __cpuid_insn(cp); 591 { 592 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 593 *iptr++ = cp->cp_ebx; 594 *iptr++ = cp->cp_edx; 595 *iptr++ = cp->cp_ecx; 596 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 597 } 598 599 /* 600 * Map the vendor string to a type code 601 */ 602 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 603 cpi->cpi_vendor = X86_VENDOR_Intel; 604 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 605 cpi->cpi_vendor = X86_VENDOR_AMD; 606 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 607 cpi->cpi_vendor = X86_VENDOR_TM; 608 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 609 /* 610 * CyrixInstead is a variable used by the Cyrix detection code 611 * in locore. 612 */ 613 cpi->cpi_vendor = X86_VENDOR_Cyrix; 614 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 615 cpi->cpi_vendor = X86_VENDOR_UMC; 616 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 617 cpi->cpi_vendor = X86_VENDOR_NexGen; 618 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 619 cpi->cpi_vendor = X86_VENDOR_Centaur; 620 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 621 cpi->cpi_vendor = X86_VENDOR_Rise; 622 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 623 cpi->cpi_vendor = X86_VENDOR_SiS; 624 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 625 cpi->cpi_vendor = X86_VENDOR_NSC; 626 else 627 cpi->cpi_vendor = X86_VENDOR_IntelClone; 628 629 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 630 631 /* 632 * Limit the range in case of weird hardware 633 */ 634 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 635 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 636 if (cpi->cpi_maxeax < 1) 637 goto pass1_done; 638 639 cp = &cpi->cpi_std[1]; 640 cp->cp_eax = 1; 641 (void) __cpuid_insn(cp); 642 643 /* 644 * Extract identifying constants for easy access. 645 */ 646 cpi->cpi_model = CPI_MODEL(cpi); 647 cpi->cpi_family = CPI_FAMILY(cpi); 648 649 if (cpi->cpi_family == 0xf) 650 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 651 652 /* 653 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 654 * Intel, and presumably everyone else, uses model == 0xf, as 655 * one would expect (max value means possible overflow). Sigh. 656 */ 657 658 switch (cpi->cpi_vendor) { 659 case X86_VENDOR_Intel: 660 if (IS_EXTENDED_MODEL_INTEL(cpi)) 661 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 662 break; 663 case X86_VENDOR_AMD: 664 if (CPI_FAMILY(cpi) == 0xf) 665 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 666 break; 667 default: 668 if (cpi->cpi_model == 0xf) 669 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 670 break; 671 } 672 673 cpi->cpi_step = CPI_STEP(cpi); 674 cpi->cpi_brandid = CPI_BRANDID(cpi); 675 676 /* 677 * *default* assumptions: 678 * - believe %edx feature word 679 * - ignore %ecx feature word 680 * - 32-bit virtual and physical addressing 681 */ 682 mask_edx = 0xffffffff; 683 mask_ecx = 0; 684 685 cpi->cpi_pabits = cpi->cpi_vabits = 32; 686 687 switch (cpi->cpi_vendor) { 688 case X86_VENDOR_Intel: 689 if (cpi->cpi_family == 5) 690 x86_type = X86_TYPE_P5; 691 else if (IS_LEGACY_P6(cpi)) { 692 x86_type = X86_TYPE_P6; 693 pentiumpro_bug4046376 = 1; 694 pentiumpro_bug4064495 = 1; 695 /* 696 * Clear the SEP bit when it was set erroneously 697 */ 698 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 699 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 700 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 701 x86_type = X86_TYPE_P4; 702 /* 703 * We don't currently depend on any of the %ecx 704 * features until Prescott, so we'll only check 705 * this from P4 onwards. We might want to revisit 706 * that idea later. 707 */ 708 mask_ecx = 0xffffffff; 709 } else if (cpi->cpi_family > 0xf) 710 mask_ecx = 0xffffffff; 711 /* 712 * We don't support MONITOR/MWAIT if leaf 5 is not available 713 * to obtain the monitor linesize. 714 */ 715 if (cpi->cpi_maxeax < 5) 716 mask_ecx &= ~CPUID_INTC_ECX_MON; 717 break; 718 case X86_VENDOR_IntelClone: 719 default: 720 break; 721 case X86_VENDOR_AMD: 722 #if defined(OPTERON_ERRATUM_108) 723 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 724 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 725 cpi->cpi_model = 0xc; 726 } else 727 #endif 728 if (cpi->cpi_family == 5) { 729 /* 730 * AMD K5 and K6 731 * 732 * These CPUs have an incomplete implementation 733 * of MCA/MCE which we mask away. 734 */ 735 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 736 737 /* 738 * Model 0 uses the wrong (APIC) bit 739 * to indicate PGE. Fix it here. 740 */ 741 if (cpi->cpi_model == 0) { 742 if (cp->cp_edx & 0x200) { 743 cp->cp_edx &= ~0x200; 744 cp->cp_edx |= CPUID_INTC_EDX_PGE; 745 } 746 } 747 748 /* 749 * Early models had problems w/ MMX; disable. 750 */ 751 if (cpi->cpi_model < 6) 752 mask_edx &= ~CPUID_INTC_EDX_MMX; 753 } 754 755 /* 756 * For newer families, SSE3 and CX16, at least, are valid; 757 * enable all 758 */ 759 if (cpi->cpi_family >= 0xf) 760 mask_ecx = 0xffffffff; 761 /* 762 * We don't support MONITOR/MWAIT if leaf 5 is not available 763 * to obtain the monitor linesize. 764 */ 765 if (cpi->cpi_maxeax < 5) 766 mask_ecx &= ~CPUID_INTC_ECX_MON; 767 768 #if !defined(__xpv) 769 /* 770 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 771 * processors. AMD does not intend MWAIT to be used in the cpu 772 * idle loop on current and future processors. 10h and future 773 * AMD processors use more power in MWAIT than HLT. 774 * Pre-family-10h Opterons do not have the MWAIT instruction. 775 */ 776 idle_cpu_prefer_mwait = 0; 777 #endif 778 779 break; 780 case X86_VENDOR_TM: 781 /* 782 * workaround the NT workaround in CMS 4.1 783 */ 784 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 785 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 786 cp->cp_edx |= CPUID_INTC_EDX_CX8; 787 break; 788 case X86_VENDOR_Centaur: 789 /* 790 * workaround the NT workarounds again 791 */ 792 if (cpi->cpi_family == 6) 793 cp->cp_edx |= CPUID_INTC_EDX_CX8; 794 break; 795 case X86_VENDOR_Cyrix: 796 /* 797 * We rely heavily on the probing in locore 798 * to actually figure out what parts, if any, 799 * of the Cyrix cpuid instruction to believe. 800 */ 801 switch (x86_type) { 802 case X86_TYPE_CYRIX_486: 803 mask_edx = 0; 804 break; 805 case X86_TYPE_CYRIX_6x86: 806 mask_edx = 0; 807 break; 808 case X86_TYPE_CYRIX_6x86L: 809 mask_edx = 810 CPUID_INTC_EDX_DE | 811 CPUID_INTC_EDX_CX8; 812 break; 813 case X86_TYPE_CYRIX_6x86MX: 814 mask_edx = 815 CPUID_INTC_EDX_DE | 816 CPUID_INTC_EDX_MSR | 817 CPUID_INTC_EDX_CX8 | 818 CPUID_INTC_EDX_PGE | 819 CPUID_INTC_EDX_CMOV | 820 CPUID_INTC_EDX_MMX; 821 break; 822 case X86_TYPE_CYRIX_GXm: 823 mask_edx = 824 CPUID_INTC_EDX_MSR | 825 CPUID_INTC_EDX_CX8 | 826 CPUID_INTC_EDX_CMOV | 827 CPUID_INTC_EDX_MMX; 828 break; 829 case X86_TYPE_CYRIX_MediaGX: 830 break; 831 case X86_TYPE_CYRIX_MII: 832 case X86_TYPE_VIA_CYRIX_III: 833 mask_edx = 834 CPUID_INTC_EDX_DE | 835 CPUID_INTC_EDX_TSC | 836 CPUID_INTC_EDX_MSR | 837 CPUID_INTC_EDX_CX8 | 838 CPUID_INTC_EDX_PGE | 839 CPUID_INTC_EDX_CMOV | 840 CPUID_INTC_EDX_MMX; 841 break; 842 default: 843 break; 844 } 845 break; 846 } 847 848 #if defined(__xpv) 849 /* 850 * Do not support MONITOR/MWAIT under a hypervisor 851 */ 852 mask_ecx &= ~CPUID_INTC_ECX_MON; 853 #endif /* __xpv */ 854 855 /* 856 * Now we've figured out the masks that determine 857 * which bits we choose to believe, apply the masks 858 * to the feature words, then map the kernel's view 859 * of these feature words into its feature word. 860 */ 861 cp->cp_edx &= mask_edx; 862 cp->cp_ecx &= mask_ecx; 863 864 /* 865 * apply any platform restrictions (we don't call this 866 * immediately after __cpuid_insn here, because we need the 867 * workarounds applied above first) 868 */ 869 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 870 871 /* 872 * fold in overrides from the "eeprom" mechanism 873 */ 874 cp->cp_edx |= cpuid_feature_edx_include; 875 cp->cp_edx &= ~cpuid_feature_edx_exclude; 876 877 cp->cp_ecx |= cpuid_feature_ecx_include; 878 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 879 880 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 881 feature |= X86_LARGEPAGE; 882 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 883 feature |= X86_TSC; 884 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 885 feature |= X86_MSR; 886 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 887 feature |= X86_MTRR; 888 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 889 feature |= X86_PGE; 890 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 891 feature |= X86_CMOV; 892 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 893 feature |= X86_MMX; 894 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 895 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 896 feature |= X86_MCA; 897 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 898 feature |= X86_PAE; 899 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 900 feature |= X86_CX8; 901 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 902 feature |= X86_CX16; 903 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 904 feature |= X86_PAT; 905 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 906 feature |= X86_SEP; 907 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 908 /* 909 * In our implementation, fxsave/fxrstor 910 * are prerequisites before we'll even 911 * try and do SSE things. 912 */ 913 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 914 feature |= X86_SSE; 915 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 916 feature |= X86_SSE2; 917 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 918 feature |= X86_SSE3; 919 } 920 if (cp->cp_edx & CPUID_INTC_EDX_DE) 921 feature |= X86_DE; 922 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 923 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 924 feature |= X86_MWAIT; 925 } 926 927 if (feature & X86_PAE) 928 cpi->cpi_pabits = 36; 929 930 /* 931 * Hyperthreading configuration is slightly tricky on Intel 932 * and pure clones, and even trickier on AMD. 933 * 934 * (AMD chose to set the HTT bit on their CMP processors, 935 * even though they're not actually hyperthreaded. Thus it 936 * takes a bit more work to figure out what's really going 937 * on ... see the handling of the CMP_LGCY bit below) 938 */ 939 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 940 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 941 if (cpi->cpi_ncpu_per_chip > 1) 942 feature |= X86_HTT; 943 } else { 944 cpi->cpi_ncpu_per_chip = 1; 945 } 946 947 /* 948 * Work on the "extended" feature information, doing 949 * some basic initialization for cpuid_pass2() 950 */ 951 xcpuid = 0; 952 switch (cpi->cpi_vendor) { 953 case X86_VENDOR_Intel: 954 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 955 xcpuid++; 956 break; 957 case X86_VENDOR_AMD: 958 if (cpi->cpi_family > 5 || 959 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 960 xcpuid++; 961 break; 962 case X86_VENDOR_Cyrix: 963 /* 964 * Only these Cyrix CPUs are -known- to support 965 * extended cpuid operations. 966 */ 967 if (x86_type == X86_TYPE_VIA_CYRIX_III || 968 x86_type == X86_TYPE_CYRIX_GXm) 969 xcpuid++; 970 break; 971 case X86_VENDOR_Centaur: 972 case X86_VENDOR_TM: 973 default: 974 xcpuid++; 975 break; 976 } 977 978 if (xcpuid) { 979 cp = &cpi->cpi_extd[0]; 980 cp->cp_eax = 0x80000000; 981 cpi->cpi_xmaxeax = __cpuid_insn(cp); 982 } 983 984 if (cpi->cpi_xmaxeax & 0x80000000) { 985 986 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 987 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 988 989 switch (cpi->cpi_vendor) { 990 case X86_VENDOR_Intel: 991 case X86_VENDOR_AMD: 992 if (cpi->cpi_xmaxeax < 0x80000001) 993 break; 994 cp = &cpi->cpi_extd[1]; 995 cp->cp_eax = 0x80000001; 996 (void) __cpuid_insn(cp); 997 998 if (cpi->cpi_vendor == X86_VENDOR_AMD && 999 cpi->cpi_family == 5 && 1000 cpi->cpi_model == 6 && 1001 cpi->cpi_step == 6) { 1002 /* 1003 * K6 model 6 uses bit 10 to indicate SYSC 1004 * Later models use bit 11. Fix it here. 1005 */ 1006 if (cp->cp_edx & 0x400) { 1007 cp->cp_edx &= ~0x400; 1008 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 1009 } 1010 } 1011 1012 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 1013 1014 /* 1015 * Compute the additions to the kernel's feature word. 1016 */ 1017 if (cp->cp_edx & CPUID_AMD_EDX_NX) 1018 feature |= X86_NX; 1019 1020 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 1021 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 1022 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 1023 feature |= X86_SSE4A; 1024 1025 /* 1026 * If both the HTT and CMP_LGCY bits are set, 1027 * then we're not actually HyperThreaded. Read 1028 * "AMD CPUID Specification" for more details. 1029 */ 1030 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1031 (feature & X86_HTT) && 1032 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 1033 feature &= ~X86_HTT; 1034 feature |= X86_CMP; 1035 } 1036 #if defined(__amd64) 1037 /* 1038 * It's really tricky to support syscall/sysret in 1039 * the i386 kernel; we rely on sysenter/sysexit 1040 * instead. In the amd64 kernel, things are -way- 1041 * better. 1042 */ 1043 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 1044 feature |= X86_ASYSC; 1045 1046 /* 1047 * While we're thinking about system calls, note 1048 * that AMD processors don't support sysenter 1049 * in long mode at all, so don't try to program them. 1050 */ 1051 if (x86_vendor == X86_VENDOR_AMD) 1052 feature &= ~X86_SEP; 1053 #endif 1054 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 1055 feature |= X86_TSCP; 1056 break; 1057 default: 1058 break; 1059 } 1060 1061 /* 1062 * Get CPUID data about processor cores and hyperthreads. 1063 */ 1064 switch (cpi->cpi_vendor) { 1065 case X86_VENDOR_Intel: 1066 if (cpi->cpi_maxeax >= 4) { 1067 cp = &cpi->cpi_std[4]; 1068 cp->cp_eax = 4; 1069 cp->cp_ecx = 0; 1070 (void) __cpuid_insn(cp); 1071 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 1072 } 1073 /*FALLTHROUGH*/ 1074 case X86_VENDOR_AMD: 1075 if (cpi->cpi_xmaxeax < 0x80000008) 1076 break; 1077 cp = &cpi->cpi_extd[8]; 1078 cp->cp_eax = 0x80000008; 1079 (void) __cpuid_insn(cp); 1080 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1081 1082 /* 1083 * Virtual and physical address limits from 1084 * cpuid override previously guessed values. 1085 */ 1086 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1087 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1088 break; 1089 default: 1090 break; 1091 } 1092 1093 /* 1094 * Derive the number of cores per chip 1095 */ 1096 switch (cpi->cpi_vendor) { 1097 case X86_VENDOR_Intel: 1098 if (cpi->cpi_maxeax < 4) { 1099 cpi->cpi_ncore_per_chip = 1; 1100 break; 1101 } else { 1102 cpi->cpi_ncore_per_chip = 1103 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1104 } 1105 break; 1106 case X86_VENDOR_AMD: 1107 if (cpi->cpi_xmaxeax < 0x80000008) { 1108 cpi->cpi_ncore_per_chip = 1; 1109 break; 1110 } else { 1111 cpi->cpi_ncore_per_chip = 1112 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1113 } 1114 break; 1115 default: 1116 cpi->cpi_ncore_per_chip = 1; 1117 break; 1118 } 1119 } 1120 1121 /* 1122 * If more than one core, then this processor is CMP. 1123 */ 1124 if (cpi->cpi_ncore_per_chip > 1) 1125 feature |= X86_CMP; 1126 1127 /* 1128 * If the number of cores is the same as the number 1129 * of CPUs, then we cannot have HyperThreading. 1130 */ 1131 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1132 feature &= ~X86_HTT; 1133 1134 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1135 /* 1136 * Single-core single-threaded processors. 1137 */ 1138 cpi->cpi_chipid = -1; 1139 cpi->cpi_clogid = 0; 1140 cpi->cpi_coreid = cpu->cpu_id; 1141 } else if (cpi->cpi_ncpu_per_chip > 1) { 1142 uint_t i; 1143 uint_t chipid_shift = 0; 1144 uint_t coreid_shift = 0; 1145 uint_t apic_id = CPI_APIC_ID(cpi); 1146 1147 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1148 chipid_shift++; 1149 cpi->cpi_chipid = apic_id >> chipid_shift; 1150 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1151 1152 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1153 if (feature & X86_CMP) { 1154 /* 1155 * Multi-core (and possibly multi-threaded) 1156 * processors. 1157 */ 1158 uint_t ncpu_per_core; 1159 if (cpi->cpi_ncore_per_chip == 1) 1160 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1161 else if (cpi->cpi_ncore_per_chip > 1) 1162 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1163 cpi->cpi_ncore_per_chip; 1164 /* 1165 * 8bit APIC IDs on dual core Pentiums 1166 * look like this: 1167 * 1168 * +-----------------------+------+------+ 1169 * | Physical Package ID | MC | HT | 1170 * +-----------------------+------+------+ 1171 * <------- chipid --------> 1172 * <------- coreid ---------------> 1173 * <--- clogid --> 1174 * 1175 * Where the number of bits necessary to 1176 * represent MC and HT fields together equals 1177 * to the minimum number of bits necessary to 1178 * store the value of cpi->cpi_ncpu_per_chip. 1179 * Of those bits, the MC part uses the number 1180 * of bits necessary to store the value of 1181 * cpi->cpi_ncore_per_chip. 1182 */ 1183 for (i = 1; i < ncpu_per_core; i <<= 1) 1184 coreid_shift++; 1185 cpi->cpi_coreid = apic_id >> coreid_shift; 1186 } else if (feature & X86_HTT) { 1187 /* 1188 * Single-core multi-threaded processors. 1189 */ 1190 cpi->cpi_coreid = cpi->cpi_chipid; 1191 } 1192 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1193 /* 1194 * AMD currently only has dual-core processors with 1195 * single-threaded cores. If they ever release 1196 * multi-threaded processors, then this code 1197 * will have to be updated. 1198 */ 1199 cpi->cpi_coreid = cpu->cpu_id; 1200 } else { 1201 /* 1202 * All other processors are currently 1203 * assumed to have single cores. 1204 */ 1205 cpi->cpi_coreid = cpi->cpi_chipid; 1206 } 1207 } 1208 1209 /* 1210 * Synthesize chip "revision" and socket type 1211 */ 1212 synth_info(cpi); 1213 1214 pass1_done: 1215 cpi->cpi_pass = 1; 1216 return (feature); 1217 } 1218 1219 /* 1220 * Make copies of the cpuid table entries we depend on, in 1221 * part for ease of parsing now, in part so that we have only 1222 * one place to correct any of it, in part for ease of 1223 * later export to userland, and in part so we can look at 1224 * this stuff in a crash dump. 1225 */ 1226 1227 /*ARGSUSED*/ 1228 void 1229 cpuid_pass2(cpu_t *cpu) 1230 { 1231 uint_t n, nmax; 1232 int i; 1233 struct cpuid_regs *cp; 1234 uint8_t *dp; 1235 uint32_t *iptr; 1236 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1237 1238 ASSERT(cpi->cpi_pass == 1); 1239 1240 if (cpi->cpi_maxeax < 1) 1241 goto pass2_done; 1242 1243 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1244 nmax = NMAX_CPI_STD; 1245 /* 1246 * (We already handled n == 0 and n == 1 in pass 1) 1247 */ 1248 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1249 cp->cp_eax = n; 1250 1251 /* 1252 * CPUID function 4 expects %ecx to be initialized 1253 * with an index which indicates which cache to return 1254 * information about. The OS is expected to call function 4 1255 * with %ecx set to 0, 1, 2, ... until it returns with 1256 * EAX[4:0] set to 0, which indicates there are no more 1257 * caches. 1258 * 1259 * Here, populate cpi_std[4] with the information returned by 1260 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1261 * when dynamic memory allocation becomes available. 1262 * 1263 * Note: we need to explicitly initialize %ecx here, since 1264 * function 4 may have been previously invoked. 1265 */ 1266 if (n == 4) 1267 cp->cp_ecx = 0; 1268 1269 (void) __cpuid_insn(cp); 1270 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1271 switch (n) { 1272 case 2: 1273 /* 1274 * "the lower 8 bits of the %eax register 1275 * contain a value that identifies the number 1276 * of times the cpuid [instruction] has to be 1277 * executed to obtain a complete image of the 1278 * processor's caching systems." 1279 * 1280 * How *do* they make this stuff up? 1281 */ 1282 cpi->cpi_ncache = sizeof (*cp) * 1283 BITX(cp->cp_eax, 7, 0); 1284 if (cpi->cpi_ncache == 0) 1285 break; 1286 cpi->cpi_ncache--; /* skip count byte */ 1287 1288 /* 1289 * Well, for now, rather than attempt to implement 1290 * this slightly dubious algorithm, we just look 1291 * at the first 15 .. 1292 */ 1293 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1294 cpi->cpi_ncache = sizeof (*cp) - 1; 1295 1296 dp = cpi->cpi_cacheinfo; 1297 if (BITX(cp->cp_eax, 31, 31) == 0) { 1298 uint8_t *p = (void *)&cp->cp_eax; 1299 for (i = 1; i < 3; i++) 1300 if (p[i] != 0) 1301 *dp++ = p[i]; 1302 } 1303 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1304 uint8_t *p = (void *)&cp->cp_ebx; 1305 for (i = 0; i < 4; i++) 1306 if (p[i] != 0) 1307 *dp++ = p[i]; 1308 } 1309 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1310 uint8_t *p = (void *)&cp->cp_ecx; 1311 for (i = 0; i < 4; i++) 1312 if (p[i] != 0) 1313 *dp++ = p[i]; 1314 } 1315 if (BITX(cp->cp_edx, 31, 31) == 0) { 1316 uint8_t *p = (void *)&cp->cp_edx; 1317 for (i = 0; i < 4; i++) 1318 if (p[i] != 0) 1319 *dp++ = p[i]; 1320 } 1321 break; 1322 1323 case 3: /* Processor serial number, if PSN supported */ 1324 break; 1325 1326 case 4: /* Deterministic cache parameters */ 1327 break; 1328 1329 case 5: /* Monitor/Mwait parameters */ 1330 { 1331 size_t mwait_size; 1332 1333 /* 1334 * check cpi_mwait.support which was set in cpuid_pass1 1335 */ 1336 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1337 break; 1338 1339 /* 1340 * Protect ourself from insane mwait line size. 1341 * Workaround for incomplete hardware emulator(s). 1342 */ 1343 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1344 if (mwait_size < sizeof (uint32_t) || 1345 !ISP2(mwait_size)) { 1346 #if DEBUG 1347 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1348 "size %ld", 1349 cpu->cpu_id, (long)mwait_size); 1350 #endif 1351 break; 1352 } 1353 1354 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1355 cpi->cpi_mwait.mon_max = mwait_size; 1356 if (MWAIT_EXTENSION(cpi)) { 1357 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1358 if (MWAIT_INT_ENABLE(cpi)) 1359 cpi->cpi_mwait.support |= 1360 MWAIT_ECX_INT_ENABLE; 1361 } 1362 break; 1363 } 1364 default: 1365 break; 1366 } 1367 } 1368 1369 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1370 goto pass2_done; 1371 1372 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1373 nmax = NMAX_CPI_EXTD; 1374 /* 1375 * Copy the extended properties, fixing them as we go. 1376 * (We already handled n == 0 and n == 1 in pass 1) 1377 */ 1378 iptr = (void *)cpi->cpi_brandstr; 1379 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1380 cp->cp_eax = 0x80000000 + n; 1381 (void) __cpuid_insn(cp); 1382 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1383 switch (n) { 1384 case 2: 1385 case 3: 1386 case 4: 1387 /* 1388 * Extract the brand string 1389 */ 1390 *iptr++ = cp->cp_eax; 1391 *iptr++ = cp->cp_ebx; 1392 *iptr++ = cp->cp_ecx; 1393 *iptr++ = cp->cp_edx; 1394 break; 1395 case 5: 1396 switch (cpi->cpi_vendor) { 1397 case X86_VENDOR_AMD: 1398 /* 1399 * The Athlon and Duron were the first 1400 * parts to report the sizes of the 1401 * TLB for large pages. Before then, 1402 * we don't trust the data. 1403 */ 1404 if (cpi->cpi_family < 6 || 1405 (cpi->cpi_family == 6 && 1406 cpi->cpi_model < 1)) 1407 cp->cp_eax = 0; 1408 break; 1409 default: 1410 break; 1411 } 1412 break; 1413 case 6: 1414 switch (cpi->cpi_vendor) { 1415 case X86_VENDOR_AMD: 1416 /* 1417 * The Athlon and Duron were the first 1418 * AMD parts with L2 TLB's. 1419 * Before then, don't trust the data. 1420 */ 1421 if (cpi->cpi_family < 6 || 1422 cpi->cpi_family == 6 && 1423 cpi->cpi_model < 1) 1424 cp->cp_eax = cp->cp_ebx = 0; 1425 /* 1426 * AMD Duron rev A0 reports L2 1427 * cache size incorrectly as 1K 1428 * when it is really 64K 1429 */ 1430 if (cpi->cpi_family == 6 && 1431 cpi->cpi_model == 3 && 1432 cpi->cpi_step == 0) { 1433 cp->cp_ecx &= 0xffff; 1434 cp->cp_ecx |= 0x400000; 1435 } 1436 break; 1437 case X86_VENDOR_Cyrix: /* VIA C3 */ 1438 /* 1439 * VIA C3 processors are a bit messed 1440 * up w.r.t. encoding cache sizes in %ecx 1441 */ 1442 if (cpi->cpi_family != 6) 1443 break; 1444 /* 1445 * model 7 and 8 were incorrectly encoded 1446 * 1447 * xxx is model 8 really broken? 1448 */ 1449 if (cpi->cpi_model == 7 || 1450 cpi->cpi_model == 8) 1451 cp->cp_ecx = 1452 BITX(cp->cp_ecx, 31, 24) << 16 | 1453 BITX(cp->cp_ecx, 23, 16) << 12 | 1454 BITX(cp->cp_ecx, 15, 8) << 8 | 1455 BITX(cp->cp_ecx, 7, 0); 1456 /* 1457 * model 9 stepping 1 has wrong associativity 1458 */ 1459 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1460 cp->cp_ecx |= 8 << 12; 1461 break; 1462 case X86_VENDOR_Intel: 1463 /* 1464 * Extended L2 Cache features function. 1465 * First appeared on Prescott. 1466 */ 1467 default: 1468 break; 1469 } 1470 break; 1471 default: 1472 break; 1473 } 1474 } 1475 1476 pass2_done: 1477 cpi->cpi_pass = 2; 1478 } 1479 1480 static const char * 1481 intel_cpubrand(const struct cpuid_info *cpi) 1482 { 1483 int i; 1484 1485 if ((x86_feature & X86_CPUID) == 0 || 1486 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1487 return ("i486"); 1488 1489 switch (cpi->cpi_family) { 1490 case 5: 1491 return ("Intel Pentium(r)"); 1492 case 6: 1493 switch (cpi->cpi_model) { 1494 uint_t celeron, xeon; 1495 const struct cpuid_regs *cp; 1496 case 0: 1497 case 1: 1498 case 2: 1499 return ("Intel Pentium(r) Pro"); 1500 case 3: 1501 case 4: 1502 return ("Intel Pentium(r) II"); 1503 case 6: 1504 return ("Intel Celeron(r)"); 1505 case 5: 1506 case 7: 1507 celeron = xeon = 0; 1508 cp = &cpi->cpi_std[2]; /* cache info */ 1509 1510 for (i = 1; i < 3; i++) { 1511 uint_t tmp; 1512 1513 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1514 if (tmp == 0x40) 1515 celeron++; 1516 if (tmp >= 0x44 && tmp <= 0x45) 1517 xeon++; 1518 } 1519 1520 for (i = 0; i < 2; i++) { 1521 uint_t tmp; 1522 1523 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1524 if (tmp == 0x40) 1525 celeron++; 1526 else if (tmp >= 0x44 && tmp <= 0x45) 1527 xeon++; 1528 } 1529 1530 for (i = 0; i < 4; i++) { 1531 uint_t tmp; 1532 1533 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1534 if (tmp == 0x40) 1535 celeron++; 1536 else if (tmp >= 0x44 && tmp <= 0x45) 1537 xeon++; 1538 } 1539 1540 for (i = 0; i < 4; i++) { 1541 uint_t tmp; 1542 1543 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1544 if (tmp == 0x40) 1545 celeron++; 1546 else if (tmp >= 0x44 && tmp <= 0x45) 1547 xeon++; 1548 } 1549 1550 if (celeron) 1551 return ("Intel Celeron(r)"); 1552 if (xeon) 1553 return (cpi->cpi_model == 5 ? 1554 "Intel Pentium(r) II Xeon(tm)" : 1555 "Intel Pentium(r) III Xeon(tm)"); 1556 return (cpi->cpi_model == 5 ? 1557 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1558 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1559 default: 1560 break; 1561 } 1562 default: 1563 break; 1564 } 1565 1566 /* BrandID is present if the field is nonzero */ 1567 if (cpi->cpi_brandid != 0) { 1568 static const struct { 1569 uint_t bt_bid; 1570 const char *bt_str; 1571 } brand_tbl[] = { 1572 { 0x1, "Intel(r) Celeron(r)" }, 1573 { 0x2, "Intel(r) Pentium(r) III" }, 1574 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1575 { 0x4, "Intel(r) Pentium(r) III" }, 1576 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1577 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1578 { 0x8, "Intel(r) Pentium(r) 4" }, 1579 { 0x9, "Intel(r) Pentium(r) 4" }, 1580 { 0xa, "Intel(r) Celeron(r)" }, 1581 { 0xb, "Intel(r) Xeon(tm)" }, 1582 { 0xc, "Intel(r) Xeon(tm) MP" }, 1583 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1584 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1585 { 0x11, "Mobile Genuine Intel(r)" }, 1586 { 0x12, "Intel(r) Celeron(r) M" }, 1587 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1588 { 0x14, "Intel(r) Celeron(r)" }, 1589 { 0x15, "Mobile Genuine Intel(r)" }, 1590 { 0x16, "Intel(r) Pentium(r) M" }, 1591 { 0x17, "Mobile Intel(r) Celeron(r)" } 1592 }; 1593 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1594 uint_t sgn; 1595 1596 sgn = (cpi->cpi_family << 8) | 1597 (cpi->cpi_model << 4) | cpi->cpi_step; 1598 1599 for (i = 0; i < btblmax; i++) 1600 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1601 break; 1602 if (i < btblmax) { 1603 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1604 return ("Intel(r) Celeron(r)"); 1605 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1606 return ("Intel(r) Xeon(tm) MP"); 1607 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1608 return ("Intel(r) Xeon(tm)"); 1609 return (brand_tbl[i].bt_str); 1610 } 1611 } 1612 1613 return (NULL); 1614 } 1615 1616 static const char * 1617 amd_cpubrand(const struct cpuid_info *cpi) 1618 { 1619 if ((x86_feature & X86_CPUID) == 0 || 1620 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1621 return ("i486 compatible"); 1622 1623 switch (cpi->cpi_family) { 1624 case 5: 1625 switch (cpi->cpi_model) { 1626 case 0: 1627 case 1: 1628 case 2: 1629 case 3: 1630 case 4: 1631 case 5: 1632 return ("AMD-K5(r)"); 1633 case 6: 1634 case 7: 1635 return ("AMD-K6(r)"); 1636 case 8: 1637 return ("AMD-K6(r)-2"); 1638 case 9: 1639 return ("AMD-K6(r)-III"); 1640 default: 1641 return ("AMD (family 5)"); 1642 } 1643 case 6: 1644 switch (cpi->cpi_model) { 1645 case 1: 1646 return ("AMD-K7(tm)"); 1647 case 0: 1648 case 2: 1649 case 4: 1650 return ("AMD Athlon(tm)"); 1651 case 3: 1652 case 7: 1653 return ("AMD Duron(tm)"); 1654 case 6: 1655 case 8: 1656 case 10: 1657 /* 1658 * Use the L2 cache size to distinguish 1659 */ 1660 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1661 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1662 default: 1663 return ("AMD (family 6)"); 1664 } 1665 default: 1666 break; 1667 } 1668 1669 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1670 cpi->cpi_brandid != 0) { 1671 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1672 case 3: 1673 return ("AMD Opteron(tm) UP 1xx"); 1674 case 4: 1675 return ("AMD Opteron(tm) DP 2xx"); 1676 case 5: 1677 return ("AMD Opteron(tm) MP 8xx"); 1678 default: 1679 return ("AMD Opteron(tm)"); 1680 } 1681 } 1682 1683 return (NULL); 1684 } 1685 1686 static const char * 1687 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1688 { 1689 if ((x86_feature & X86_CPUID) == 0 || 1690 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1691 type == X86_TYPE_CYRIX_486) 1692 return ("i486 compatible"); 1693 1694 switch (type) { 1695 case X86_TYPE_CYRIX_6x86: 1696 return ("Cyrix 6x86"); 1697 case X86_TYPE_CYRIX_6x86L: 1698 return ("Cyrix 6x86L"); 1699 case X86_TYPE_CYRIX_6x86MX: 1700 return ("Cyrix 6x86MX"); 1701 case X86_TYPE_CYRIX_GXm: 1702 return ("Cyrix GXm"); 1703 case X86_TYPE_CYRIX_MediaGX: 1704 return ("Cyrix MediaGX"); 1705 case X86_TYPE_CYRIX_MII: 1706 return ("Cyrix M2"); 1707 case X86_TYPE_VIA_CYRIX_III: 1708 return ("VIA Cyrix M3"); 1709 default: 1710 /* 1711 * Have another wild guess .. 1712 */ 1713 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1714 return ("Cyrix 5x86"); 1715 else if (cpi->cpi_family == 5) { 1716 switch (cpi->cpi_model) { 1717 case 2: 1718 return ("Cyrix 6x86"); /* Cyrix M1 */ 1719 case 4: 1720 return ("Cyrix MediaGX"); 1721 default: 1722 break; 1723 } 1724 } else if (cpi->cpi_family == 6) { 1725 switch (cpi->cpi_model) { 1726 case 0: 1727 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1728 case 5: 1729 case 6: 1730 case 7: 1731 case 8: 1732 case 9: 1733 return ("VIA C3"); 1734 default: 1735 break; 1736 } 1737 } 1738 break; 1739 } 1740 return (NULL); 1741 } 1742 1743 /* 1744 * This only gets called in the case that the CPU extended 1745 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1746 * aren't available, or contain null bytes for some reason. 1747 */ 1748 static void 1749 fabricate_brandstr(struct cpuid_info *cpi) 1750 { 1751 const char *brand = NULL; 1752 1753 switch (cpi->cpi_vendor) { 1754 case X86_VENDOR_Intel: 1755 brand = intel_cpubrand(cpi); 1756 break; 1757 case X86_VENDOR_AMD: 1758 brand = amd_cpubrand(cpi); 1759 break; 1760 case X86_VENDOR_Cyrix: 1761 brand = cyrix_cpubrand(cpi, x86_type); 1762 break; 1763 case X86_VENDOR_NexGen: 1764 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1765 brand = "NexGen Nx586"; 1766 break; 1767 case X86_VENDOR_Centaur: 1768 if (cpi->cpi_family == 5) 1769 switch (cpi->cpi_model) { 1770 case 4: 1771 brand = "Centaur C6"; 1772 break; 1773 case 8: 1774 brand = "Centaur C2"; 1775 break; 1776 case 9: 1777 brand = "Centaur C3"; 1778 break; 1779 default: 1780 break; 1781 } 1782 break; 1783 case X86_VENDOR_Rise: 1784 if (cpi->cpi_family == 5 && 1785 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1786 brand = "Rise mP6"; 1787 break; 1788 case X86_VENDOR_SiS: 1789 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1790 brand = "SiS 55x"; 1791 break; 1792 case X86_VENDOR_TM: 1793 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1794 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1795 break; 1796 case X86_VENDOR_NSC: 1797 case X86_VENDOR_UMC: 1798 default: 1799 break; 1800 } 1801 if (brand) { 1802 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1803 return; 1804 } 1805 1806 /* 1807 * If all else fails ... 1808 */ 1809 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1810 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1811 cpi->cpi_model, cpi->cpi_step); 1812 } 1813 1814 /* 1815 * This routine is called just after kernel memory allocation 1816 * becomes available on cpu0, and as part of mp_startup() on 1817 * the other cpus. 1818 * 1819 * Fixup the brand string, and collect any information from cpuid 1820 * that requires dynamicically allocated storage to represent. 1821 */ 1822 /*ARGSUSED*/ 1823 void 1824 cpuid_pass3(cpu_t *cpu) 1825 { 1826 int i, max, shft, level, size; 1827 struct cpuid_regs regs; 1828 struct cpuid_regs *cp; 1829 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1830 1831 ASSERT(cpi->cpi_pass == 2); 1832 1833 /* 1834 * Function 4: Deterministic cache parameters 1835 * 1836 * Take this opportunity to detect the number of threads 1837 * sharing the last level cache, and construct a corresponding 1838 * cache id. The respective cpuid_info members are initialized 1839 * to the default case of "no last level cache sharing". 1840 */ 1841 cpi->cpi_ncpu_shr_last_cache = 1; 1842 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1843 1844 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1845 1846 /* 1847 * Find the # of elements (size) returned by fn 4, and along 1848 * the way detect last level cache sharing details. 1849 */ 1850 bzero(®s, sizeof (regs)); 1851 cp = ®s; 1852 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1853 cp->cp_eax = 4; 1854 cp->cp_ecx = i; 1855 1856 (void) __cpuid_insn(cp); 1857 1858 if (CPI_CACHE_TYPE(cp) == 0) 1859 break; 1860 level = CPI_CACHE_LVL(cp); 1861 if (level > max) { 1862 max = level; 1863 cpi->cpi_ncpu_shr_last_cache = 1864 CPI_NTHR_SHR_CACHE(cp) + 1; 1865 } 1866 } 1867 cpi->cpi_std_4_size = size = i; 1868 1869 /* 1870 * Allocate the cpi_std_4 array. The first element 1871 * references the regs for fn 4, %ecx == 0, which 1872 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1873 */ 1874 if (size > 0) { 1875 cpi->cpi_std_4 = 1876 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1877 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1878 1879 /* 1880 * Allocate storage to hold the additional regs 1881 * for function 4, %ecx == 1 .. cpi_std_4_size. 1882 * 1883 * The regs for fn 4, %ecx == 0 has already 1884 * been allocated as indicated above. 1885 */ 1886 for (i = 1; i < size; i++) { 1887 cp = cpi->cpi_std_4[i] = 1888 kmem_zalloc(sizeof (regs), KM_SLEEP); 1889 cp->cp_eax = 4; 1890 cp->cp_ecx = i; 1891 1892 (void) __cpuid_insn(cp); 1893 } 1894 } 1895 /* 1896 * Determine the number of bits needed to represent 1897 * the number of CPUs sharing the last level cache. 1898 * 1899 * Shift off that number of bits from the APIC id to 1900 * derive the cache id. 1901 */ 1902 shft = 0; 1903 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1904 shft++; 1905 cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft; 1906 } 1907 1908 /* 1909 * Now fixup the brand string 1910 */ 1911 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1912 fabricate_brandstr(cpi); 1913 } else { 1914 1915 /* 1916 * If we successfully extracted a brand string from the cpuid 1917 * instruction, clean it up by removing leading spaces and 1918 * similar junk. 1919 */ 1920 if (cpi->cpi_brandstr[0]) { 1921 size_t maxlen = sizeof (cpi->cpi_brandstr); 1922 char *src, *dst; 1923 1924 dst = src = (char *)cpi->cpi_brandstr; 1925 src[maxlen - 1] = '\0'; 1926 /* 1927 * strip leading spaces 1928 */ 1929 while (*src == ' ') 1930 src++; 1931 /* 1932 * Remove any 'Genuine' or "Authentic" prefixes 1933 */ 1934 if (strncmp(src, "Genuine ", 8) == 0) 1935 src += 8; 1936 if (strncmp(src, "Authentic ", 10) == 0) 1937 src += 10; 1938 1939 /* 1940 * Now do an in-place copy. 1941 * Map (R) to (r) and (TM) to (tm). 1942 * The era of teletypes is long gone, and there's 1943 * -really- no need to shout. 1944 */ 1945 while (*src != '\0') { 1946 if (src[0] == '(') { 1947 if (strncmp(src + 1, "R)", 2) == 0) { 1948 (void) strncpy(dst, "(r)", 3); 1949 src += 3; 1950 dst += 3; 1951 continue; 1952 } 1953 if (strncmp(src + 1, "TM)", 3) == 0) { 1954 (void) strncpy(dst, "(tm)", 4); 1955 src += 4; 1956 dst += 4; 1957 continue; 1958 } 1959 } 1960 *dst++ = *src++; 1961 } 1962 *dst = '\0'; 1963 1964 /* 1965 * Finally, remove any trailing spaces 1966 */ 1967 while (--dst > cpi->cpi_brandstr) 1968 if (*dst == ' ') 1969 *dst = '\0'; 1970 else 1971 break; 1972 } else 1973 fabricate_brandstr(cpi); 1974 } 1975 cpi->cpi_pass = 3; 1976 } 1977 1978 /* 1979 * This routine is called out of bind_hwcap() much later in the life 1980 * of the kernel (post_startup()). The job of this routine is to resolve 1981 * the hardware feature support and kernel support for those features into 1982 * what we're actually going to tell applications via the aux vector. 1983 */ 1984 uint_t 1985 cpuid_pass4(cpu_t *cpu) 1986 { 1987 struct cpuid_info *cpi; 1988 uint_t hwcap_flags = 0; 1989 1990 if (cpu == NULL) 1991 cpu = CPU; 1992 cpi = cpu->cpu_m.mcpu_cpi; 1993 1994 ASSERT(cpi->cpi_pass == 3); 1995 1996 if (cpi->cpi_maxeax >= 1) { 1997 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1998 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1999 2000 *edx = CPI_FEATURES_EDX(cpi); 2001 *ecx = CPI_FEATURES_ECX(cpi); 2002 2003 /* 2004 * [these require explicit kernel support] 2005 */ 2006 if ((x86_feature & X86_SEP) == 0) 2007 *edx &= ~CPUID_INTC_EDX_SEP; 2008 2009 if ((x86_feature & X86_SSE) == 0) 2010 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2011 if ((x86_feature & X86_SSE2) == 0) 2012 *edx &= ~CPUID_INTC_EDX_SSE2; 2013 2014 if ((x86_feature & X86_HTT) == 0) 2015 *edx &= ~CPUID_INTC_EDX_HTT; 2016 2017 if ((x86_feature & X86_SSE3) == 0) 2018 *ecx &= ~CPUID_INTC_ECX_SSE3; 2019 2020 /* 2021 * [no explicit support required beyond x87 fp context] 2022 */ 2023 if (!fpu_exists) 2024 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2025 2026 /* 2027 * Now map the supported feature vector to things that we 2028 * think userland will care about. 2029 */ 2030 if (*edx & CPUID_INTC_EDX_SEP) 2031 hwcap_flags |= AV_386_SEP; 2032 if (*edx & CPUID_INTC_EDX_SSE) 2033 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2034 if (*edx & CPUID_INTC_EDX_SSE2) 2035 hwcap_flags |= AV_386_SSE2; 2036 if (*ecx & CPUID_INTC_ECX_SSE3) 2037 hwcap_flags |= AV_386_SSE3; 2038 if (*ecx & CPUID_INTC_ECX_POPCNT) 2039 hwcap_flags |= AV_386_POPCNT; 2040 if (*edx & CPUID_INTC_EDX_FPU) 2041 hwcap_flags |= AV_386_FPU; 2042 if (*edx & CPUID_INTC_EDX_MMX) 2043 hwcap_flags |= AV_386_MMX; 2044 2045 if (*edx & CPUID_INTC_EDX_TSC) 2046 hwcap_flags |= AV_386_TSC; 2047 if (*edx & CPUID_INTC_EDX_CX8) 2048 hwcap_flags |= AV_386_CX8; 2049 if (*edx & CPUID_INTC_EDX_CMOV) 2050 hwcap_flags |= AV_386_CMOV; 2051 if (*ecx & CPUID_INTC_ECX_MON) 2052 hwcap_flags |= AV_386_MON; 2053 if (*ecx & CPUID_INTC_ECX_CX16) 2054 hwcap_flags |= AV_386_CX16; 2055 } 2056 2057 if (x86_feature & X86_HTT) 2058 hwcap_flags |= AV_386_PAUSE; 2059 2060 if (cpi->cpi_xmaxeax < 0x80000001) 2061 goto pass4_done; 2062 2063 switch (cpi->cpi_vendor) { 2064 struct cpuid_regs cp; 2065 uint32_t *edx, *ecx; 2066 2067 case X86_VENDOR_Intel: 2068 /* 2069 * Seems like Intel duplicated what we necessary 2070 * here to make the initial crop of 64-bit OS's work. 2071 * Hopefully, those are the only "extended" bits 2072 * they'll add. 2073 */ 2074 /*FALLTHROUGH*/ 2075 2076 case X86_VENDOR_AMD: 2077 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2078 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2079 2080 *edx = CPI_FEATURES_XTD_EDX(cpi); 2081 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2082 2083 /* 2084 * [these features require explicit kernel support] 2085 */ 2086 switch (cpi->cpi_vendor) { 2087 case X86_VENDOR_Intel: 2088 break; 2089 2090 case X86_VENDOR_AMD: 2091 if ((x86_feature & X86_TSCP) == 0) 2092 *edx &= ~CPUID_AMD_EDX_TSCP; 2093 if ((x86_feature & X86_SSE4A) == 0) 2094 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2095 break; 2096 2097 default: 2098 break; 2099 } 2100 2101 /* 2102 * [no explicit support required beyond 2103 * x87 fp context and exception handlers] 2104 */ 2105 if (!fpu_exists) 2106 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2107 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2108 2109 if ((x86_feature & X86_NX) == 0) 2110 *edx &= ~CPUID_AMD_EDX_NX; 2111 #if !defined(__amd64) 2112 *edx &= ~CPUID_AMD_EDX_LM; 2113 #endif 2114 /* 2115 * Now map the supported feature vector to 2116 * things that we think userland will care about. 2117 */ 2118 #if defined(__amd64) 2119 if (*edx & CPUID_AMD_EDX_SYSC) 2120 hwcap_flags |= AV_386_AMD_SYSC; 2121 #endif 2122 if (*edx & CPUID_AMD_EDX_MMXamd) 2123 hwcap_flags |= AV_386_AMD_MMX; 2124 if (*edx & CPUID_AMD_EDX_3DNow) 2125 hwcap_flags |= AV_386_AMD_3DNow; 2126 if (*edx & CPUID_AMD_EDX_3DNowx) 2127 hwcap_flags |= AV_386_AMD_3DNowx; 2128 2129 switch (cpi->cpi_vendor) { 2130 case X86_VENDOR_AMD: 2131 if (*edx & CPUID_AMD_EDX_TSCP) 2132 hwcap_flags |= AV_386_TSCP; 2133 if (*ecx & CPUID_AMD_ECX_AHF64) 2134 hwcap_flags |= AV_386_AHF; 2135 if (*ecx & CPUID_AMD_ECX_SSE4A) 2136 hwcap_flags |= AV_386_AMD_SSE4A; 2137 if (*ecx & CPUID_AMD_ECX_LZCNT) 2138 hwcap_flags |= AV_386_AMD_LZCNT; 2139 break; 2140 2141 case X86_VENDOR_Intel: 2142 /* 2143 * Aarrgh. 2144 * Intel uses a different bit in the same word. 2145 */ 2146 if (*ecx & CPUID_INTC_ECX_AHF64) 2147 hwcap_flags |= AV_386_AHF; 2148 break; 2149 2150 default: 2151 break; 2152 } 2153 break; 2154 2155 case X86_VENDOR_TM: 2156 cp.cp_eax = 0x80860001; 2157 (void) __cpuid_insn(&cp); 2158 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2159 break; 2160 2161 default: 2162 break; 2163 } 2164 2165 pass4_done: 2166 cpi->cpi_pass = 4; 2167 return (hwcap_flags); 2168 } 2169 2170 2171 /* 2172 * Simulate the cpuid instruction using the data we previously 2173 * captured about this CPU. We try our best to return the truth 2174 * about the hardware, independently of kernel support. 2175 */ 2176 uint32_t 2177 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2178 { 2179 struct cpuid_info *cpi; 2180 struct cpuid_regs *xcp; 2181 2182 if (cpu == NULL) 2183 cpu = CPU; 2184 cpi = cpu->cpu_m.mcpu_cpi; 2185 2186 ASSERT(cpuid_checkpass(cpu, 3)); 2187 2188 /* 2189 * CPUID data is cached in two separate places: cpi_std for standard 2190 * CPUID functions, and cpi_extd for extended CPUID functions. 2191 */ 2192 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2193 xcp = &cpi->cpi_std[cp->cp_eax]; 2194 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2195 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2196 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2197 else 2198 /* 2199 * The caller is asking for data from an input parameter which 2200 * the kernel has not cached. In this case we go fetch from 2201 * the hardware and return the data directly to the user. 2202 */ 2203 return (__cpuid_insn(cp)); 2204 2205 cp->cp_eax = xcp->cp_eax; 2206 cp->cp_ebx = xcp->cp_ebx; 2207 cp->cp_ecx = xcp->cp_ecx; 2208 cp->cp_edx = xcp->cp_edx; 2209 return (cp->cp_eax); 2210 } 2211 2212 int 2213 cpuid_checkpass(cpu_t *cpu, int pass) 2214 { 2215 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2216 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2217 } 2218 2219 int 2220 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2221 { 2222 ASSERT(cpuid_checkpass(cpu, 3)); 2223 2224 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2225 } 2226 2227 int 2228 cpuid_is_cmt(cpu_t *cpu) 2229 { 2230 if (cpu == NULL) 2231 cpu = CPU; 2232 2233 ASSERT(cpuid_checkpass(cpu, 1)); 2234 2235 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2236 } 2237 2238 /* 2239 * AMD and Intel both implement the 64-bit variant of the syscall 2240 * instruction (syscallq), so if there's -any- support for syscall, 2241 * cpuid currently says "yes, we support this". 2242 * 2243 * However, Intel decided to -not- implement the 32-bit variant of the 2244 * syscall instruction, so we provide a predicate to allow our caller 2245 * to test that subtlety here. 2246 * 2247 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2248 * even in the case where the hardware would in fact support it. 2249 */ 2250 /*ARGSUSED*/ 2251 int 2252 cpuid_syscall32_insn(cpu_t *cpu) 2253 { 2254 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2255 2256 #if !defined(__xpv) 2257 if (cpu == NULL) 2258 cpu = CPU; 2259 2260 /*CSTYLED*/ 2261 { 2262 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2263 2264 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2265 cpi->cpi_xmaxeax >= 0x80000001 && 2266 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2267 return (1); 2268 } 2269 #endif 2270 return (0); 2271 } 2272 2273 int 2274 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2275 { 2276 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2277 2278 static const char fmt[] = 2279 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2280 static const char fmt_ht[] = 2281 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2282 2283 ASSERT(cpuid_checkpass(cpu, 1)); 2284 2285 if (cpuid_is_cmt(cpu)) 2286 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2287 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2288 cpi->cpi_family, cpi->cpi_model, 2289 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2290 return (snprintf(s, n, fmt, 2291 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2292 cpi->cpi_family, cpi->cpi_model, 2293 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2294 } 2295 2296 const char * 2297 cpuid_getvendorstr(cpu_t *cpu) 2298 { 2299 ASSERT(cpuid_checkpass(cpu, 1)); 2300 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2301 } 2302 2303 uint_t 2304 cpuid_getvendor(cpu_t *cpu) 2305 { 2306 ASSERT(cpuid_checkpass(cpu, 1)); 2307 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2308 } 2309 2310 uint_t 2311 cpuid_getfamily(cpu_t *cpu) 2312 { 2313 ASSERT(cpuid_checkpass(cpu, 1)); 2314 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2315 } 2316 2317 uint_t 2318 cpuid_getmodel(cpu_t *cpu) 2319 { 2320 ASSERT(cpuid_checkpass(cpu, 1)); 2321 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2322 } 2323 2324 uint_t 2325 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2326 { 2327 ASSERT(cpuid_checkpass(cpu, 1)); 2328 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2329 } 2330 2331 uint_t 2332 cpuid_get_ncore_per_chip(cpu_t *cpu) 2333 { 2334 ASSERT(cpuid_checkpass(cpu, 1)); 2335 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2336 } 2337 2338 uint_t 2339 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2340 { 2341 ASSERT(cpuid_checkpass(cpu, 2)); 2342 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2343 } 2344 2345 id_t 2346 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2347 { 2348 ASSERT(cpuid_checkpass(cpu, 2)); 2349 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2350 } 2351 2352 uint_t 2353 cpuid_getstep(cpu_t *cpu) 2354 { 2355 ASSERT(cpuid_checkpass(cpu, 1)); 2356 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2357 } 2358 2359 uint_t 2360 cpuid_getsig(struct cpu *cpu) 2361 { 2362 ASSERT(cpuid_checkpass(cpu, 1)); 2363 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2364 } 2365 2366 uint32_t 2367 cpuid_getchiprev(struct cpu *cpu) 2368 { 2369 ASSERT(cpuid_checkpass(cpu, 1)); 2370 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2371 } 2372 2373 const char * 2374 cpuid_getchiprevstr(struct cpu *cpu) 2375 { 2376 ASSERT(cpuid_checkpass(cpu, 1)); 2377 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2378 } 2379 2380 uint32_t 2381 cpuid_getsockettype(struct cpu *cpu) 2382 { 2383 ASSERT(cpuid_checkpass(cpu, 1)); 2384 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2385 } 2386 2387 int 2388 cpuid_get_chipid(cpu_t *cpu) 2389 { 2390 ASSERT(cpuid_checkpass(cpu, 1)); 2391 2392 if (cpuid_is_cmt(cpu)) 2393 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2394 return (cpu->cpu_id); 2395 } 2396 2397 id_t 2398 cpuid_get_coreid(cpu_t *cpu) 2399 { 2400 ASSERT(cpuid_checkpass(cpu, 1)); 2401 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2402 } 2403 2404 int 2405 cpuid_get_clogid(cpu_t *cpu) 2406 { 2407 ASSERT(cpuid_checkpass(cpu, 1)); 2408 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2409 } 2410 2411 void 2412 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2413 { 2414 struct cpuid_info *cpi; 2415 2416 if (cpu == NULL) 2417 cpu = CPU; 2418 cpi = cpu->cpu_m.mcpu_cpi; 2419 2420 ASSERT(cpuid_checkpass(cpu, 1)); 2421 2422 if (pabits) 2423 *pabits = cpi->cpi_pabits; 2424 if (vabits) 2425 *vabits = cpi->cpi_vabits; 2426 } 2427 2428 /* 2429 * Returns the number of data TLB entries for a corresponding 2430 * pagesize. If it can't be computed, or isn't known, the 2431 * routine returns zero. If you ask about an architecturally 2432 * impossible pagesize, the routine will panic (so that the 2433 * hat implementor knows that things are inconsistent.) 2434 */ 2435 uint_t 2436 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2437 { 2438 struct cpuid_info *cpi; 2439 uint_t dtlb_nent = 0; 2440 2441 if (cpu == NULL) 2442 cpu = CPU; 2443 cpi = cpu->cpu_m.mcpu_cpi; 2444 2445 ASSERT(cpuid_checkpass(cpu, 1)); 2446 2447 /* 2448 * Check the L2 TLB info 2449 */ 2450 if (cpi->cpi_xmaxeax >= 0x80000006) { 2451 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2452 2453 switch (pagesize) { 2454 2455 case 4 * 1024: 2456 /* 2457 * All zero in the top 16 bits of the register 2458 * indicates a unified TLB. Size is in low 16 bits. 2459 */ 2460 if ((cp->cp_ebx & 0xffff0000) == 0) 2461 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2462 else 2463 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2464 break; 2465 2466 case 2 * 1024 * 1024: 2467 if ((cp->cp_eax & 0xffff0000) == 0) 2468 dtlb_nent = cp->cp_eax & 0x0000ffff; 2469 else 2470 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2471 break; 2472 2473 default: 2474 panic("unknown L2 pagesize"); 2475 /*NOTREACHED*/ 2476 } 2477 } 2478 2479 if (dtlb_nent != 0) 2480 return (dtlb_nent); 2481 2482 /* 2483 * No L2 TLB support for this size, try L1. 2484 */ 2485 if (cpi->cpi_xmaxeax >= 0x80000005) { 2486 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2487 2488 switch (pagesize) { 2489 case 4 * 1024: 2490 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2491 break; 2492 case 2 * 1024 * 1024: 2493 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2494 break; 2495 default: 2496 panic("unknown L1 d-TLB pagesize"); 2497 /*NOTREACHED*/ 2498 } 2499 } 2500 2501 return (dtlb_nent); 2502 } 2503 2504 /* 2505 * Return 0 if the erratum is not present or not applicable, positive 2506 * if it is, and negative if the status of the erratum is unknown. 2507 * 2508 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2509 * Processors" #25759, Rev 3.57, August 2005 2510 */ 2511 int 2512 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2513 { 2514 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2515 uint_t eax; 2516 2517 /* 2518 * Bail out if this CPU isn't an AMD CPU, or if it's 2519 * a legacy (32-bit) AMD CPU. 2520 */ 2521 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2522 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2523 cpi->cpi_family == 6) 2524 2525 return (0); 2526 2527 eax = cpi->cpi_std[1].cp_eax; 2528 2529 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2530 #define SH_B3(eax) (eax == 0xf51) 2531 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2532 2533 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2534 2535 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2536 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2537 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2538 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2539 2540 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2541 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2542 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2543 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2544 2545 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2546 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2547 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2548 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2549 #define BH_E4(eax) (eax == 0x20fb1) 2550 #define SH_E5(eax) (eax == 0x20f42) 2551 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2552 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2553 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2554 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2555 DH_E6(eax) || JH_E6(eax)) 2556 2557 switch (erratum) { 2558 case 1: 2559 return (cpi->cpi_family < 0x10); 2560 case 51: /* what does the asterisk mean? */ 2561 return (B(eax) || SH_C0(eax) || CG(eax)); 2562 case 52: 2563 return (B(eax)); 2564 case 57: 2565 return (cpi->cpi_family <= 0x10); 2566 case 58: 2567 return (B(eax)); 2568 case 60: 2569 return (cpi->cpi_family <= 0x10); 2570 case 61: 2571 case 62: 2572 case 63: 2573 case 64: 2574 case 65: 2575 case 66: 2576 case 68: 2577 case 69: 2578 case 70: 2579 case 71: 2580 return (B(eax)); 2581 case 72: 2582 return (SH_B0(eax)); 2583 case 74: 2584 return (B(eax)); 2585 case 75: 2586 return (cpi->cpi_family < 0x10); 2587 case 76: 2588 return (B(eax)); 2589 case 77: 2590 return (cpi->cpi_family <= 0x10); 2591 case 78: 2592 return (B(eax) || SH_C0(eax)); 2593 case 79: 2594 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2595 case 80: 2596 case 81: 2597 case 82: 2598 return (B(eax)); 2599 case 83: 2600 return (B(eax) || SH_C0(eax) || CG(eax)); 2601 case 85: 2602 return (cpi->cpi_family < 0x10); 2603 case 86: 2604 return (SH_C0(eax) || CG(eax)); 2605 case 88: 2606 #if !defined(__amd64) 2607 return (0); 2608 #else 2609 return (B(eax) || SH_C0(eax)); 2610 #endif 2611 case 89: 2612 return (cpi->cpi_family < 0x10); 2613 case 90: 2614 return (B(eax) || SH_C0(eax) || CG(eax)); 2615 case 91: 2616 case 92: 2617 return (B(eax) || SH_C0(eax)); 2618 case 93: 2619 return (SH_C0(eax)); 2620 case 94: 2621 return (B(eax) || SH_C0(eax) || CG(eax)); 2622 case 95: 2623 #if !defined(__amd64) 2624 return (0); 2625 #else 2626 return (B(eax) || SH_C0(eax)); 2627 #endif 2628 case 96: 2629 return (B(eax) || SH_C0(eax) || CG(eax)); 2630 case 97: 2631 case 98: 2632 return (SH_C0(eax) || CG(eax)); 2633 case 99: 2634 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2635 case 100: 2636 return (B(eax) || SH_C0(eax)); 2637 case 101: 2638 case 103: 2639 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2640 case 104: 2641 return (SH_C0(eax) || CG(eax) || D0(eax)); 2642 case 105: 2643 case 106: 2644 case 107: 2645 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2646 case 108: 2647 return (DH_CG(eax)); 2648 case 109: 2649 return (SH_C0(eax) || CG(eax) || D0(eax)); 2650 case 110: 2651 return (D0(eax) || EX(eax)); 2652 case 111: 2653 return (CG(eax)); 2654 case 112: 2655 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2656 case 113: 2657 return (eax == 0x20fc0); 2658 case 114: 2659 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2660 case 115: 2661 return (SH_E0(eax) || JH_E1(eax)); 2662 case 116: 2663 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2664 case 117: 2665 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2666 case 118: 2667 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2668 JH_E6(eax)); 2669 case 121: 2670 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2671 case 122: 2672 return (cpi->cpi_family < 0x10); 2673 case 123: 2674 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2675 case 131: 2676 return (cpi->cpi_family < 0x10); 2677 case 6336786: 2678 /* 2679 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2680 * if this is a K8 family or newer processor 2681 */ 2682 if (CPI_FAMILY(cpi) == 0xf) { 2683 struct cpuid_regs regs; 2684 regs.cp_eax = 0x80000007; 2685 (void) __cpuid_insn(®s); 2686 return (!(regs.cp_edx & 0x100)); 2687 } 2688 return (0); 2689 case 6323525: 2690 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2691 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2692 2693 default: 2694 return (-1); 2695 } 2696 } 2697 2698 static const char assoc_str[] = "associativity"; 2699 static const char line_str[] = "line-size"; 2700 static const char size_str[] = "size"; 2701 2702 static void 2703 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2704 uint32_t val) 2705 { 2706 char buf[128]; 2707 2708 /* 2709 * ndi_prop_update_int() is used because it is desirable for 2710 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2711 */ 2712 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2713 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2714 } 2715 2716 /* 2717 * Intel-style cache/tlb description 2718 * 2719 * Standard cpuid level 2 gives a randomly ordered 2720 * selection of tags that index into a table that describes 2721 * cache and tlb properties. 2722 */ 2723 2724 static const char l1_icache_str[] = "l1-icache"; 2725 static const char l1_dcache_str[] = "l1-dcache"; 2726 static const char l2_cache_str[] = "l2-cache"; 2727 static const char l3_cache_str[] = "l3-cache"; 2728 static const char itlb4k_str[] = "itlb-4K"; 2729 static const char dtlb4k_str[] = "dtlb-4K"; 2730 static const char itlb4M_str[] = "itlb-4M"; 2731 static const char dtlb4M_str[] = "dtlb-4M"; 2732 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2733 static const char dtlb44_str[] = "dtlb-4K-4M"; 2734 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2735 static const char sl2_cache_str[] = "sectored-l2-cache"; 2736 static const char itrace_str[] = "itrace-cache"; 2737 static const char sl3_cache_str[] = "sectored-l3-cache"; 2738 2739 static const struct cachetab { 2740 uint8_t ct_code; 2741 uint8_t ct_assoc; 2742 uint16_t ct_line_size; 2743 size_t ct_size; 2744 const char *ct_label; 2745 } intel_ctab[] = { 2746 /* maintain descending order! */ 2747 { 0xb4, 4, 0, 256, dtlb4k_str }, 2748 { 0xb3, 4, 0, 128, dtlb4k_str }, 2749 { 0xb0, 4, 0, 128, itlb4k_str }, 2750 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2751 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2752 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2753 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2754 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2755 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2756 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2757 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2758 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2759 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2760 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2761 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2762 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2763 { 0x73, 8, 0, 64*1024, itrace_str}, 2764 { 0x72, 8, 0, 32*1024, itrace_str}, 2765 { 0x71, 8, 0, 16*1024, itrace_str}, 2766 { 0x70, 8, 0, 12*1024, itrace_str}, 2767 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2768 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2769 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2770 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2771 { 0x5d, 0, 0, 256, dtlb44_str}, 2772 { 0x5c, 0, 0, 128, dtlb44_str}, 2773 { 0x5b, 0, 0, 64, dtlb44_str}, 2774 { 0x52, 0, 0, 256, itlb424_str}, 2775 { 0x51, 0, 0, 128, itlb424_str}, 2776 { 0x50, 0, 0, 64, itlb424_str}, 2777 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2778 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2779 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2780 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2781 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2782 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2783 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2784 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2785 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2786 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2787 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2788 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2789 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2790 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2791 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2792 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2793 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2794 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2795 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2796 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2797 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2798 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2799 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2800 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2801 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2802 { 0x0b, 4, 0, 4, itlb4M_str}, 2803 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2804 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2805 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2806 { 0x04, 4, 0, 8, dtlb4M_str}, 2807 { 0x03, 4, 0, 64, dtlb4k_str}, 2808 { 0x02, 4, 0, 2, itlb4M_str}, 2809 { 0x01, 4, 0, 32, itlb4k_str}, 2810 { 0 } 2811 }; 2812 2813 static const struct cachetab cyrix_ctab[] = { 2814 { 0x70, 4, 0, 32, "tlb-4K" }, 2815 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2816 { 0 } 2817 }; 2818 2819 /* 2820 * Search a cache table for a matching entry 2821 */ 2822 static const struct cachetab * 2823 find_cacheent(const struct cachetab *ct, uint_t code) 2824 { 2825 if (code != 0) { 2826 for (; ct->ct_code != 0; ct++) 2827 if (ct->ct_code <= code) 2828 break; 2829 if (ct->ct_code == code) 2830 return (ct); 2831 } 2832 return (NULL); 2833 } 2834 2835 /* 2836 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2837 * The walk is terminated if the walker returns non-zero. 2838 */ 2839 static void 2840 intel_walk_cacheinfo(struct cpuid_info *cpi, 2841 void *arg, int (*func)(void *, const struct cachetab *)) 2842 { 2843 const struct cachetab *ct; 2844 uint8_t *dp; 2845 int i; 2846 2847 if ((dp = cpi->cpi_cacheinfo) == NULL) 2848 return; 2849 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2850 /* 2851 * For overloaded descriptor 0x49 we use cpuid function 4 2852 * if supported by the current processor, to update 2853 * cache information. 2854 */ 2855 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4) { 2856 intel_cpuid_4_cache_info(arg, cpi); 2857 continue; 2858 } 2859 2860 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2861 if (func(arg, ct) != 0) 2862 break; 2863 } 2864 } 2865 } 2866 2867 /* 2868 * (Like the Intel one, except for Cyrix CPUs) 2869 */ 2870 static void 2871 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2872 void *arg, int (*func)(void *, const struct cachetab *)) 2873 { 2874 const struct cachetab *ct; 2875 uint8_t *dp; 2876 int i; 2877 2878 if ((dp = cpi->cpi_cacheinfo) == NULL) 2879 return; 2880 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2881 /* 2882 * Search Cyrix-specific descriptor table first .. 2883 */ 2884 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2885 if (func(arg, ct) != 0) 2886 break; 2887 continue; 2888 } 2889 /* 2890 * .. else fall back to the Intel one 2891 */ 2892 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2893 if (func(arg, ct) != 0) 2894 break; 2895 continue; 2896 } 2897 } 2898 } 2899 2900 /* 2901 * A cacheinfo walker that adds associativity, line-size, and size properties 2902 * to the devinfo node it is passed as an argument. 2903 */ 2904 static int 2905 add_cacheent_props(void *arg, const struct cachetab *ct) 2906 { 2907 dev_info_t *devi = arg; 2908 2909 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2910 if (ct->ct_line_size != 0) 2911 add_cache_prop(devi, ct->ct_label, line_str, 2912 ct->ct_line_size); 2913 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2914 return (0); 2915 } 2916 2917 /* 2918 * Add L2 or L3 cache-information using cpuid function 4. This 2919 * function is called from intel_walk_cacheinfo() when descriptor 2920 * 0x49 is encountered. 2921 */ 2922 static void 2923 intel_cpuid_4_cache_info(void *arg, struct cpuid_info *cpi) 2924 { 2925 uint32_t level, i; 2926 2927 struct cachetab ct; 2928 2929 for (i = 0; i < cpi->cpi_std_4_size; i++) { 2930 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 2931 2932 if (level == 2 || level == 3) { 2933 ct.ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 2934 ct.ct_line_size = 2935 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 2936 ct.ct_size = ct.ct_assoc * 2937 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 2938 ct.ct_line_size * 2939 (cpi->cpi_std_4[i]->cp_ecx + 1); 2940 2941 if (level == 2) { 2942 ct.ct_label = l2_cache_str; 2943 } else if (level == 3) { 2944 ct.ct_label = l3_cache_str; 2945 } 2946 2947 (void) add_cacheent_props(arg, 2948 (const struct cachetab *) (&ct)); 2949 } 2950 } 2951 } 2952 2953 static const char fully_assoc[] = "fully-associative?"; 2954 2955 /* 2956 * AMD style cache/tlb description 2957 * 2958 * Extended functions 5 and 6 directly describe properties of 2959 * tlbs and various cache levels. 2960 */ 2961 static void 2962 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2963 { 2964 switch (assoc) { 2965 case 0: /* reserved; ignore */ 2966 break; 2967 default: 2968 add_cache_prop(devi, label, assoc_str, assoc); 2969 break; 2970 case 0xff: 2971 add_cache_prop(devi, label, fully_assoc, 1); 2972 break; 2973 } 2974 } 2975 2976 static void 2977 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2978 { 2979 if (size == 0) 2980 return; 2981 add_cache_prop(devi, label, size_str, size); 2982 add_amd_assoc(devi, label, assoc); 2983 } 2984 2985 static void 2986 add_amd_cache(dev_info_t *devi, const char *label, 2987 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2988 { 2989 if (size == 0 || line_size == 0) 2990 return; 2991 add_amd_assoc(devi, label, assoc); 2992 /* 2993 * Most AMD parts have a sectored cache. Multiple cache lines are 2994 * associated with each tag. A sector consists of all cache lines 2995 * associated with a tag. For example, the AMD K6-III has a sector 2996 * size of 2 cache lines per tag. 2997 */ 2998 if (lines_per_tag != 0) 2999 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3000 add_cache_prop(devi, label, line_str, line_size); 3001 add_cache_prop(devi, label, size_str, size * 1024); 3002 } 3003 3004 static void 3005 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3006 { 3007 switch (assoc) { 3008 case 0: /* off */ 3009 break; 3010 case 1: 3011 case 2: 3012 case 4: 3013 add_cache_prop(devi, label, assoc_str, assoc); 3014 break; 3015 case 6: 3016 add_cache_prop(devi, label, assoc_str, 8); 3017 break; 3018 case 8: 3019 add_cache_prop(devi, label, assoc_str, 16); 3020 break; 3021 case 0xf: 3022 add_cache_prop(devi, label, fully_assoc, 1); 3023 break; 3024 default: /* reserved; ignore */ 3025 break; 3026 } 3027 } 3028 3029 static void 3030 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3031 { 3032 if (size == 0 || assoc == 0) 3033 return; 3034 add_amd_l2_assoc(devi, label, assoc); 3035 add_cache_prop(devi, label, size_str, size); 3036 } 3037 3038 static void 3039 add_amd_l2_cache(dev_info_t *devi, const char *label, 3040 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3041 { 3042 if (size == 0 || assoc == 0 || line_size == 0) 3043 return; 3044 add_amd_l2_assoc(devi, label, assoc); 3045 if (lines_per_tag != 0) 3046 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3047 add_cache_prop(devi, label, line_str, line_size); 3048 add_cache_prop(devi, label, size_str, size * 1024); 3049 } 3050 3051 static void 3052 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3053 { 3054 struct cpuid_regs *cp; 3055 3056 if (cpi->cpi_xmaxeax < 0x80000005) 3057 return; 3058 cp = &cpi->cpi_extd[5]; 3059 3060 /* 3061 * 4M/2M L1 TLB configuration 3062 * 3063 * We report the size for 2M pages because AMD uses two 3064 * TLB entries for one 4M page. 3065 */ 3066 add_amd_tlb(devi, "dtlb-2M", 3067 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3068 add_amd_tlb(devi, "itlb-2M", 3069 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3070 3071 /* 3072 * 4K L1 TLB configuration 3073 */ 3074 3075 switch (cpi->cpi_vendor) { 3076 uint_t nentries; 3077 case X86_VENDOR_TM: 3078 if (cpi->cpi_family >= 5) { 3079 /* 3080 * Crusoe processors have 256 TLB entries, but 3081 * cpuid data format constrains them to only 3082 * reporting 255 of them. 3083 */ 3084 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3085 nentries = 256; 3086 /* 3087 * Crusoe processors also have a unified TLB 3088 */ 3089 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3090 nentries); 3091 break; 3092 } 3093 /*FALLTHROUGH*/ 3094 default: 3095 add_amd_tlb(devi, itlb4k_str, 3096 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3097 add_amd_tlb(devi, dtlb4k_str, 3098 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3099 break; 3100 } 3101 3102 /* 3103 * data L1 cache configuration 3104 */ 3105 3106 add_amd_cache(devi, l1_dcache_str, 3107 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3108 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3109 3110 /* 3111 * code L1 cache configuration 3112 */ 3113 3114 add_amd_cache(devi, l1_icache_str, 3115 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3116 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3117 3118 if (cpi->cpi_xmaxeax < 0x80000006) 3119 return; 3120 cp = &cpi->cpi_extd[6]; 3121 3122 /* Check for a unified L2 TLB for large pages */ 3123 3124 if (BITX(cp->cp_eax, 31, 16) == 0) 3125 add_amd_l2_tlb(devi, "l2-tlb-2M", 3126 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3127 else { 3128 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3129 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3130 add_amd_l2_tlb(devi, "l2-itlb-2M", 3131 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3132 } 3133 3134 /* Check for a unified L2 TLB for 4K pages */ 3135 3136 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3137 add_amd_l2_tlb(devi, "l2-tlb-4K", 3138 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3139 } else { 3140 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3141 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3142 add_amd_l2_tlb(devi, "l2-itlb-4K", 3143 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3144 } 3145 3146 add_amd_l2_cache(devi, l2_cache_str, 3147 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3148 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3149 } 3150 3151 /* 3152 * There are two basic ways that the x86 world describes it cache 3153 * and tlb architecture - Intel's way and AMD's way. 3154 * 3155 * Return which flavor of cache architecture we should use 3156 */ 3157 static int 3158 x86_which_cacheinfo(struct cpuid_info *cpi) 3159 { 3160 switch (cpi->cpi_vendor) { 3161 case X86_VENDOR_Intel: 3162 if (cpi->cpi_maxeax >= 2) 3163 return (X86_VENDOR_Intel); 3164 break; 3165 case X86_VENDOR_AMD: 3166 /* 3167 * The K5 model 1 was the first part from AMD that reported 3168 * cache sizes via extended cpuid functions. 3169 */ 3170 if (cpi->cpi_family > 5 || 3171 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3172 return (X86_VENDOR_AMD); 3173 break; 3174 case X86_VENDOR_TM: 3175 if (cpi->cpi_family >= 5) 3176 return (X86_VENDOR_AMD); 3177 /*FALLTHROUGH*/ 3178 default: 3179 /* 3180 * If they have extended CPU data for 0x80000005 3181 * then we assume they have AMD-format cache 3182 * information. 3183 * 3184 * If not, and the vendor happens to be Cyrix, 3185 * then try our-Cyrix specific handler. 3186 * 3187 * If we're not Cyrix, then assume we're using Intel's 3188 * table-driven format instead. 3189 */ 3190 if (cpi->cpi_xmaxeax >= 0x80000005) 3191 return (X86_VENDOR_AMD); 3192 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3193 return (X86_VENDOR_Cyrix); 3194 else if (cpi->cpi_maxeax >= 2) 3195 return (X86_VENDOR_Intel); 3196 break; 3197 } 3198 return (-1); 3199 } 3200 3201 /* 3202 * create a node for the given cpu under the prom root node. 3203 * Also, create a cpu node in the device tree. 3204 */ 3205 static dev_info_t *cpu_nex_devi = NULL; 3206 static kmutex_t cpu_node_lock; 3207 3208 /* 3209 * Called from post_startup() and mp_startup() 3210 */ 3211 void 3212 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3213 { 3214 dev_info_t *cpu_devi; 3215 int create; 3216 3217 mutex_enter(&cpu_node_lock); 3218 3219 /* 3220 * create a nexus node for all cpus identified as 'cpu_id' under 3221 * the root node. 3222 */ 3223 if (cpu_nex_devi == NULL) { 3224 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3225 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3226 mutex_exit(&cpu_node_lock); 3227 return; 3228 } 3229 (void) ndi_devi_online(cpu_nex_devi, 0); 3230 } 3231 3232 /* 3233 * create a child node for cpu identified as 'cpu_id' 3234 */ 3235 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3236 cpu_id); 3237 if (cpu_devi == NULL) { 3238 mutex_exit(&cpu_node_lock); 3239 return; 3240 } 3241 3242 /* device_type */ 3243 3244 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3245 "device_type", "cpu"); 3246 3247 /* reg */ 3248 3249 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3250 "reg", cpu_id); 3251 3252 /* cpu-mhz, and clock-frequency */ 3253 3254 if (cpu_freq > 0) { 3255 long long mul; 3256 3257 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3258 "cpu-mhz", cpu_freq); 3259 3260 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3261 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3262 "clock-frequency", (int)mul); 3263 } 3264 3265 (void) ndi_devi_online(cpu_devi, 0); 3266 3267 if ((x86_feature & X86_CPUID) == 0) { 3268 mutex_exit(&cpu_node_lock); 3269 return; 3270 } 3271 3272 /* vendor-id */ 3273 3274 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3275 "vendor-id", cpi->cpi_vendorstr); 3276 3277 if (cpi->cpi_maxeax == 0) { 3278 mutex_exit(&cpu_node_lock); 3279 return; 3280 } 3281 3282 /* 3283 * family, model, and step 3284 */ 3285 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3286 "family", CPI_FAMILY(cpi)); 3287 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3288 "cpu-model", CPI_MODEL(cpi)); 3289 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3290 "stepping-id", CPI_STEP(cpi)); 3291 3292 /* type */ 3293 3294 switch (cpi->cpi_vendor) { 3295 case X86_VENDOR_Intel: 3296 create = 1; 3297 break; 3298 default: 3299 create = 0; 3300 break; 3301 } 3302 if (create) 3303 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3304 "type", CPI_TYPE(cpi)); 3305 3306 /* ext-family */ 3307 3308 switch (cpi->cpi_vendor) { 3309 case X86_VENDOR_Intel: 3310 case X86_VENDOR_AMD: 3311 create = cpi->cpi_family >= 0xf; 3312 break; 3313 default: 3314 create = 0; 3315 break; 3316 } 3317 if (create) 3318 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3319 "ext-family", CPI_FAMILY_XTD(cpi)); 3320 3321 /* ext-model */ 3322 3323 switch (cpi->cpi_vendor) { 3324 case X86_VENDOR_Intel: 3325 create = CPI_MODEL(cpi) == 0xf; 3326 break; 3327 case X86_VENDOR_AMD: 3328 create = CPI_FAMILY(cpi) == 0xf; 3329 break; 3330 default: 3331 create = 0; 3332 break; 3333 } 3334 if (create) 3335 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3336 "ext-model", CPI_MODEL_XTD(cpi)); 3337 3338 /* generation */ 3339 3340 switch (cpi->cpi_vendor) { 3341 case X86_VENDOR_AMD: 3342 /* 3343 * AMD K5 model 1 was the first part to support this 3344 */ 3345 create = cpi->cpi_xmaxeax >= 0x80000001; 3346 break; 3347 default: 3348 create = 0; 3349 break; 3350 } 3351 if (create) 3352 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3353 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3354 3355 /* brand-id */ 3356 3357 switch (cpi->cpi_vendor) { 3358 case X86_VENDOR_Intel: 3359 /* 3360 * brand id first appeared on Pentium III Xeon model 8, 3361 * and Celeron model 8 processors and Opteron 3362 */ 3363 create = cpi->cpi_family > 6 || 3364 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3365 break; 3366 case X86_VENDOR_AMD: 3367 create = cpi->cpi_family >= 0xf; 3368 break; 3369 default: 3370 create = 0; 3371 break; 3372 } 3373 if (create && cpi->cpi_brandid != 0) { 3374 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3375 "brand-id", cpi->cpi_brandid); 3376 } 3377 3378 /* chunks, and apic-id */ 3379 3380 switch (cpi->cpi_vendor) { 3381 /* 3382 * first available on Pentium IV and Opteron (K8) 3383 */ 3384 case X86_VENDOR_Intel: 3385 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3386 break; 3387 case X86_VENDOR_AMD: 3388 create = cpi->cpi_family >= 0xf; 3389 break; 3390 default: 3391 create = 0; 3392 break; 3393 } 3394 if (create) { 3395 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3396 "chunks", CPI_CHUNKS(cpi)); 3397 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3398 "apic-id", CPI_APIC_ID(cpi)); 3399 if (cpi->cpi_chipid >= 0) { 3400 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3401 "chip#", cpi->cpi_chipid); 3402 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3403 "clog#", cpi->cpi_clogid); 3404 } 3405 } 3406 3407 /* cpuid-features */ 3408 3409 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3410 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3411 3412 3413 /* cpuid-features-ecx */ 3414 3415 switch (cpi->cpi_vendor) { 3416 case X86_VENDOR_Intel: 3417 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3418 break; 3419 default: 3420 create = 0; 3421 break; 3422 } 3423 if (create) 3424 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3425 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3426 3427 /* ext-cpuid-features */ 3428 3429 switch (cpi->cpi_vendor) { 3430 case X86_VENDOR_Intel: 3431 case X86_VENDOR_AMD: 3432 case X86_VENDOR_Cyrix: 3433 case X86_VENDOR_TM: 3434 case X86_VENDOR_Centaur: 3435 create = cpi->cpi_xmaxeax >= 0x80000001; 3436 break; 3437 default: 3438 create = 0; 3439 break; 3440 } 3441 if (create) { 3442 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3443 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3444 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3445 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3446 } 3447 3448 /* 3449 * Brand String first appeared in Intel Pentium IV, AMD K5 3450 * model 1, and Cyrix GXm. On earlier models we try and 3451 * simulate something similar .. so this string should always 3452 * same -something- about the processor, however lame. 3453 */ 3454 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3455 "brand-string", cpi->cpi_brandstr); 3456 3457 /* 3458 * Finally, cache and tlb information 3459 */ 3460 switch (x86_which_cacheinfo(cpi)) { 3461 case X86_VENDOR_Intel: 3462 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3463 break; 3464 case X86_VENDOR_Cyrix: 3465 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3466 break; 3467 case X86_VENDOR_AMD: 3468 amd_cache_info(cpi, cpu_devi); 3469 break; 3470 default: 3471 break; 3472 } 3473 3474 mutex_exit(&cpu_node_lock); 3475 } 3476 3477 struct l2info { 3478 int *l2i_csz; 3479 int *l2i_lsz; 3480 int *l2i_assoc; 3481 int l2i_ret; 3482 }; 3483 3484 /* 3485 * A cacheinfo walker that fetches the size, line-size and associativity 3486 * of the L2 cache 3487 */ 3488 static int 3489 intel_l2cinfo(void *arg, const struct cachetab *ct) 3490 { 3491 struct l2info *l2i = arg; 3492 int *ip; 3493 3494 if (ct->ct_label != l2_cache_str && 3495 ct->ct_label != sl2_cache_str) 3496 return (0); /* not an L2 -- keep walking */ 3497 3498 if ((ip = l2i->l2i_csz) != NULL) 3499 *ip = ct->ct_size; 3500 if ((ip = l2i->l2i_lsz) != NULL) 3501 *ip = ct->ct_line_size; 3502 if ((ip = l2i->l2i_assoc) != NULL) 3503 *ip = ct->ct_assoc; 3504 l2i->l2i_ret = ct->ct_size; 3505 return (1); /* was an L2 -- terminate walk */ 3506 } 3507 3508 /* 3509 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3510 * 3511 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3512 * value is the associativity, the associativity for the L2 cache and 3513 * tlb is encoded in the following table. The 4 bit L2 value serves as 3514 * an index into the amd_afd[] array to determine the associativity. 3515 * -1 is undefined. 0 is fully associative. 3516 */ 3517 3518 static int amd_afd[] = 3519 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3520 3521 static void 3522 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3523 { 3524 struct cpuid_regs *cp; 3525 uint_t size, assoc; 3526 int i; 3527 int *ip; 3528 3529 if (cpi->cpi_xmaxeax < 0x80000006) 3530 return; 3531 cp = &cpi->cpi_extd[6]; 3532 3533 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3534 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3535 uint_t cachesz = size * 1024; 3536 assoc = amd_afd[i]; 3537 3538 ASSERT(assoc != -1); 3539 3540 if ((ip = l2i->l2i_csz) != NULL) 3541 *ip = cachesz; 3542 if ((ip = l2i->l2i_lsz) != NULL) 3543 *ip = BITX(cp->cp_ecx, 7, 0); 3544 if ((ip = l2i->l2i_assoc) != NULL) 3545 *ip = assoc; 3546 l2i->l2i_ret = cachesz; 3547 } 3548 } 3549 3550 int 3551 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3552 { 3553 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3554 struct l2info __l2info, *l2i = &__l2info; 3555 3556 l2i->l2i_csz = csz; 3557 l2i->l2i_lsz = lsz; 3558 l2i->l2i_assoc = assoc; 3559 l2i->l2i_ret = -1; 3560 3561 switch (x86_which_cacheinfo(cpi)) { 3562 case X86_VENDOR_Intel: 3563 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3564 break; 3565 case X86_VENDOR_Cyrix: 3566 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3567 break; 3568 case X86_VENDOR_AMD: 3569 amd_l2cacheinfo(cpi, l2i); 3570 break; 3571 default: 3572 break; 3573 } 3574 return (l2i->l2i_ret); 3575 } 3576 3577 #if !defined(__xpv) 3578 3579 uint32_t * 3580 cpuid_mwait_alloc(cpu_t *cpu) 3581 { 3582 uint32_t *ret; 3583 size_t mwait_size; 3584 3585 ASSERT(cpuid_checkpass(cpu, 2)); 3586 3587 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3588 if (mwait_size == 0) 3589 return (NULL); 3590 3591 /* 3592 * kmem_alloc() returns cache line size aligned data for mwait_size 3593 * allocations. mwait_size is currently cache line sized. Neither 3594 * of these implementation details are guarantied to be true in the 3595 * future. 3596 * 3597 * First try allocating mwait_size as kmem_alloc() currently returns 3598 * correctly aligned memory. If kmem_alloc() does not return 3599 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3600 * 3601 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3602 * decide to free this memory. 3603 */ 3604 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3605 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3606 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3607 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3608 *ret = MWAIT_RUNNING; 3609 return (ret); 3610 } else { 3611 kmem_free(ret, mwait_size); 3612 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3613 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3614 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3615 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3616 *ret = MWAIT_RUNNING; 3617 return (ret); 3618 } 3619 } 3620 3621 void 3622 cpuid_mwait_free(cpu_t *cpu) 3623 { 3624 ASSERT(cpuid_checkpass(cpu, 2)); 3625 3626 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3627 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3628 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3629 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3630 } 3631 3632 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3633 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3634 } 3635 3636 #endif /* !__xpv */ 3637