1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/chip.h> 44 #include <sys/fp.h> 45 #include <sys/controlregs.h> 46 #include <sys/auxv_386.h> 47 #include <sys/bitmap.h> 48 #include <sys/controlregs.h> 49 #include <sys/memnode.h> 50 51 /* 52 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 53 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 54 * them accordingly. For most modern processors, feature detection occurs here 55 * in pass 1. 56 * 57 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 58 * for the boot CPU and does the basic analysis that the early kernel needs. 59 * x86_feature is set based on the return value of cpuid_pass1() of the boot 60 * CPU. 61 * 62 * Pass 1 includes: 63 * 64 * o Determining vendor/model/family/stepping and setting x86_type and 65 * x86_vendor accordingly. 66 * o Processing the feature flags returned by the cpuid instruction while 67 * applying any workarounds or tricks for the specific processor. 68 * o Mapping the feature flags into Solaris feature bits (X86_*). 69 * o Processing extended feature flags if supported by the processor, 70 * again while applying specific processor knowledge. 71 * o Determining the CMT characteristics of the system. 72 * 73 * Pass 1 is done on non-boot CPUs during their initialization and the results 74 * are used only as a meager attempt at ensuring that all processors within the 75 * system support the same features. 76 * 77 * Pass 2 of cpuid feature analysis happens just at the beginning 78 * of startup(). It just copies in and corrects the remainder 79 * of the cpuid data we depend on: standard cpuid functions that we didn't 80 * need for pass1 feature analysis, and extended cpuid functions beyond the 81 * simple feature processing done in pass1. 82 * 83 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 84 * particular kernel memory allocation has been made available. It creates a 85 * readable brand string based on the data collected in the first two passes. 86 * 87 * Pass 4 of cpuid analysis is invoked after post_startup() when all 88 * the support infrastructure for various hardware features has been 89 * initialized. It determines which processor features will be reported 90 * to userland via the aux vector. 91 * 92 * All passes are executed on all CPUs, but only the boot CPU determines what 93 * features the kernel will use. 94 * 95 * Much of the worst junk in this file is for the support of processors 96 * that didn't really implement the cpuid instruction properly. 97 * 98 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 99 * the pass numbers. Accordingly, changes to the pass code may require changes 100 * to the accessor code. 101 */ 102 103 uint_t x86_feature = 0; 104 uint_t x86_vendor = X86_VENDOR_IntelClone; 105 uint_t x86_type = X86_TYPE_OTHER; 106 107 ulong_t cr4_value; 108 uint_t pentiumpro_bug4046376; 109 uint_t pentiumpro_bug4064495; 110 111 uint_t enable486; 112 113 /* 114 * This set of strings are for processors rumored to support the cpuid 115 * instruction, and is used by locore.s to figure out how to set x86_vendor 116 */ 117 const char CyrixInstead[] = "CyrixInstead"; 118 119 /* 120 * These constants determine how many of the elements of the 121 * cpuid we cache in the cpuid_info data structure; the 122 * remaining elements are accessible via the cpuid instruction. 123 */ 124 125 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 126 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 127 128 struct cpuid_info { 129 uint_t cpi_pass; /* last pass completed */ 130 /* 131 * standard function information 132 */ 133 uint_t cpi_maxeax; /* fn 0: %eax */ 134 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 135 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 136 137 uint_t cpi_family; /* fn 1: extended family */ 138 uint_t cpi_model; /* fn 1: extended model */ 139 uint_t cpi_step; /* fn 1: stepping */ 140 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 141 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 142 int cpi_clogid; /* fn 1: %ebx: thread # */ 143 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 144 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 145 uint_t cpi_ncache; /* fn 2: number of elements */ 146 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 147 /* 148 * extended function information 149 */ 150 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 151 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 152 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 153 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 154 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 155 id_t cpi_coreid; 156 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 157 /* Intel: fn 4: %eax[31-26] */ 158 /* 159 * supported feature information 160 */ 161 uint32_t cpi_support[4]; 162 #define STD_EDX_FEATURES 0 163 #define AMD_EDX_FEATURES 1 164 #define TM_EDX_FEATURES 2 165 #define STD_ECX_FEATURES 3 166 167 }; 168 169 170 static struct cpuid_info cpuid_info0; 171 172 /* 173 * These bit fields are defined by the Intel Application Note AP-485 174 * "Intel Processor Identification and the CPUID Instruction" 175 */ 176 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 177 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 178 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 179 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 180 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 181 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 182 183 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 184 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 185 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 186 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 187 188 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 189 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 190 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 191 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 192 193 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 194 #define CPI_XMAXEAX_MAX 0x80000100 195 196 /* 197 * A couple of shorthand macros to identify "later" P6-family chips 198 * like the Pentium M and Core. First, the "older" P6-based stuff 199 * (loosely defined as "pre-Pentium-4"): 200 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 201 */ 202 203 #define IS_LEGACY_P6(cpi) ( \ 204 cpi->cpi_family == 6 && \ 205 (cpi->cpi_model == 1 || \ 206 cpi->cpi_model == 3 || \ 207 cpi->cpi_model == 5 || \ 208 cpi->cpi_model == 6 || \ 209 cpi->cpi_model == 7 || \ 210 cpi->cpi_model == 8 || \ 211 cpi->cpi_model == 0xA || \ 212 cpi->cpi_model == 0xB) \ 213 ) 214 215 /* A "new F6" is everything with family 6 that's not the above */ 216 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 217 218 /* 219 * Some undocumented ways of patching the results of the cpuid 220 * instruction to permit running Solaris 10 on future cpus that 221 * we don't currently support. Could be set to non-zero values 222 * via settings in eeprom. 223 */ 224 225 uint32_t cpuid_feature_ecx_include; 226 uint32_t cpuid_feature_ecx_exclude; 227 uint32_t cpuid_feature_edx_include; 228 uint32_t cpuid_feature_edx_exclude; 229 230 uint_t 231 cpuid_pass1(cpu_t *cpu) 232 { 233 uint32_t mask_ecx, mask_edx; 234 uint_t feature = X86_CPUID; 235 struct cpuid_info *cpi; 236 struct cpuid_regs *cp; 237 int xcpuid; 238 239 /* 240 * By convention, cpu0 is the boot cpu, which is called 241 * before memory allocation is available. Other cpus are 242 * initialized when memory becomes available. 243 */ 244 if (cpu->cpu_id == 0) 245 cpu->cpu_m.mcpu_cpi = cpi = &cpuid_info0; 246 else 247 cpu->cpu_m.mcpu_cpi = cpi = 248 kmem_zalloc(sizeof (*cpi), KM_SLEEP); 249 250 cp = &cpi->cpi_std[0]; 251 cp->cp_eax = 0; 252 cpi->cpi_maxeax = __cpuid_insn(cp); 253 { 254 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 255 *iptr++ = cp->cp_ebx; 256 *iptr++ = cp->cp_edx; 257 *iptr++ = cp->cp_ecx; 258 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 259 } 260 261 /* 262 * Map the vendor string to a type code 263 */ 264 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 265 cpi->cpi_vendor = X86_VENDOR_Intel; 266 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 267 cpi->cpi_vendor = X86_VENDOR_AMD; 268 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 269 cpi->cpi_vendor = X86_VENDOR_TM; 270 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 271 /* 272 * CyrixInstead is a variable used by the Cyrix detection code 273 * in locore. 274 */ 275 cpi->cpi_vendor = X86_VENDOR_Cyrix; 276 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 277 cpi->cpi_vendor = X86_VENDOR_UMC; 278 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 279 cpi->cpi_vendor = X86_VENDOR_NexGen; 280 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 281 cpi->cpi_vendor = X86_VENDOR_Centaur; 282 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 283 cpi->cpi_vendor = X86_VENDOR_Rise; 284 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 285 cpi->cpi_vendor = X86_VENDOR_SiS; 286 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 287 cpi->cpi_vendor = X86_VENDOR_NSC; 288 else 289 cpi->cpi_vendor = X86_VENDOR_IntelClone; 290 291 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 292 293 /* 294 * Limit the range in case of weird hardware 295 */ 296 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 297 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 298 if (cpi->cpi_maxeax < 1) 299 goto pass1_done; 300 301 cp = &cpi->cpi_std[1]; 302 cp->cp_eax = 1; 303 (void) __cpuid_insn(cp); 304 305 /* 306 * Extract identifying constants for easy access. 307 */ 308 cpi->cpi_model = CPI_MODEL(cpi); 309 cpi->cpi_family = CPI_FAMILY(cpi); 310 311 if (cpi->cpi_family == 0xf) 312 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 313 314 /* 315 * Beware: AMD uses "extended model" iff *FAMILY* == 0xf. 316 * Intel, and presumably everyone else, uses model == 0xf, as 317 * one would expect (max value means possible overflow). Sigh. 318 */ 319 320 switch (cpi->cpi_vendor) { 321 case X86_VENDOR_AMD: 322 if (cpi->cpi_family == 0xf) 323 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 324 break; 325 default: 326 if (cpi->cpi_model == 0xf) 327 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 328 break; 329 } 330 331 cpi->cpi_step = CPI_STEP(cpi); 332 cpi->cpi_brandid = CPI_BRANDID(cpi); 333 334 /* 335 * *default* assumptions: 336 * - believe %edx feature word 337 * - ignore %ecx feature word 338 * - 32-bit virtual and physical addressing 339 */ 340 mask_edx = 0xffffffff; 341 mask_ecx = 0; 342 343 cpi->cpi_pabits = cpi->cpi_vabits = 32; 344 345 switch (cpi->cpi_vendor) { 346 case X86_VENDOR_Intel: 347 if (cpi->cpi_family == 5) 348 x86_type = X86_TYPE_P5; 349 else if (IS_LEGACY_P6(cpi)) { 350 x86_type = X86_TYPE_P6; 351 pentiumpro_bug4046376 = 1; 352 pentiumpro_bug4064495 = 1; 353 /* 354 * Clear the SEP bit when it was set erroneously 355 */ 356 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 357 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 358 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 359 x86_type = X86_TYPE_P4; 360 /* 361 * We don't currently depend on any of the %ecx 362 * features until Prescott, so we'll only check 363 * this from P4 onwards. We might want to revisit 364 * that idea later. 365 */ 366 mask_ecx = 0xffffffff; 367 } else if (cpi->cpi_family > 0xf) 368 mask_ecx = 0xffffffff; 369 break; 370 case X86_VENDOR_IntelClone: 371 default: 372 break; 373 case X86_VENDOR_AMD: 374 #if defined(OPTERON_ERRATUM_108) 375 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 376 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 377 cpi->cpi_model = 0xc; 378 } else 379 #endif 380 if (cpi->cpi_family == 5) { 381 /* 382 * AMD K5 and K6 383 * 384 * These CPUs have an incomplete implementation 385 * of MCA/MCE which we mask away. 386 */ 387 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 388 389 /* 390 * Model 0 uses the wrong (APIC) bit 391 * to indicate PGE. Fix it here. 392 */ 393 if (cpi->cpi_model == 0) { 394 if (cp->cp_edx & 0x200) { 395 cp->cp_edx &= ~0x200; 396 cp->cp_edx |= CPUID_INTC_EDX_PGE; 397 } 398 } 399 400 /* 401 * Early models had problems w/ MMX; disable. 402 */ 403 if (cpi->cpi_model < 6) 404 mask_edx &= ~CPUID_INTC_EDX_MMX; 405 } 406 407 /* 408 * For newer families, SSE3 and CX16, at least, are valid; 409 * enable all 410 */ 411 if (cpi->cpi_family >= 0xf) 412 mask_ecx = 0xffffffff; 413 break; 414 case X86_VENDOR_TM: 415 /* 416 * workaround the NT workaround in CMS 4.1 417 */ 418 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 419 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 420 cp->cp_edx |= CPUID_INTC_EDX_CX8; 421 break; 422 case X86_VENDOR_Centaur: 423 /* 424 * workaround the NT workarounds again 425 */ 426 if (cpi->cpi_family == 6) 427 cp->cp_edx |= CPUID_INTC_EDX_CX8; 428 break; 429 case X86_VENDOR_Cyrix: 430 /* 431 * We rely heavily on the probing in locore 432 * to actually figure out what parts, if any, 433 * of the Cyrix cpuid instruction to believe. 434 */ 435 switch (x86_type) { 436 case X86_TYPE_CYRIX_486: 437 mask_edx = 0; 438 break; 439 case X86_TYPE_CYRIX_6x86: 440 mask_edx = 0; 441 break; 442 case X86_TYPE_CYRIX_6x86L: 443 mask_edx = 444 CPUID_INTC_EDX_DE | 445 CPUID_INTC_EDX_CX8; 446 break; 447 case X86_TYPE_CYRIX_6x86MX: 448 mask_edx = 449 CPUID_INTC_EDX_DE | 450 CPUID_INTC_EDX_MSR | 451 CPUID_INTC_EDX_CX8 | 452 CPUID_INTC_EDX_PGE | 453 CPUID_INTC_EDX_CMOV | 454 CPUID_INTC_EDX_MMX; 455 break; 456 case X86_TYPE_CYRIX_GXm: 457 mask_edx = 458 CPUID_INTC_EDX_MSR | 459 CPUID_INTC_EDX_CX8 | 460 CPUID_INTC_EDX_CMOV | 461 CPUID_INTC_EDX_MMX; 462 break; 463 case X86_TYPE_CYRIX_MediaGX: 464 break; 465 case X86_TYPE_CYRIX_MII: 466 case X86_TYPE_VIA_CYRIX_III: 467 mask_edx = 468 CPUID_INTC_EDX_DE | 469 CPUID_INTC_EDX_TSC | 470 CPUID_INTC_EDX_MSR | 471 CPUID_INTC_EDX_CX8 | 472 CPUID_INTC_EDX_PGE | 473 CPUID_INTC_EDX_CMOV | 474 CPUID_INTC_EDX_MMX; 475 break; 476 default: 477 break; 478 } 479 break; 480 } 481 482 /* 483 * Now we've figured out the masks that determine 484 * which bits we choose to believe, apply the masks 485 * to the feature words, then map the kernel's view 486 * of these feature words into its feature word. 487 */ 488 cp->cp_edx &= mask_edx; 489 cp->cp_ecx &= mask_ecx; 490 491 /* 492 * fold in fix ups 493 */ 494 495 cp->cp_edx |= cpuid_feature_edx_include; 496 cp->cp_edx &= ~cpuid_feature_edx_exclude; 497 498 499 cp->cp_ecx |= cpuid_feature_ecx_include; 500 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 501 502 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 503 feature |= X86_LARGEPAGE; 504 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 505 feature |= X86_TSC; 506 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 507 feature |= X86_MSR; 508 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 509 feature |= X86_MTRR; 510 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 511 feature |= X86_PGE; 512 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 513 feature |= X86_CMOV; 514 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 515 feature |= X86_MMX; 516 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 517 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 518 feature |= X86_MCA; 519 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 520 feature |= X86_PAE; 521 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 522 feature |= X86_CX8; 523 /* 524 * Once this bit was thought questionable, but it looks like it's 525 * back, as of Application Note 485 March 2005 (24161829.pdf) 526 */ 527 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 528 feature |= X86_CX16; 529 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 530 feature |= X86_PAT; 531 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 532 feature |= X86_SEP; 533 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 534 /* 535 * In our implementation, fxsave/fxrstor 536 * are prerequisites before we'll even 537 * try and do SSE things. 538 */ 539 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 540 feature |= X86_SSE; 541 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 542 feature |= X86_SSE2; 543 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 544 feature |= X86_SSE3; 545 } 546 if (cp->cp_edx & CPUID_INTC_EDX_DE) 547 cr4_value |= CR4_DE; 548 549 if (feature & X86_PAE) 550 cpi->cpi_pabits = 36; 551 552 /* 553 * Hyperthreading configuration is slightly tricky on Intel 554 * and pure clones, and even trickier on AMD. 555 * 556 * (AMD chose to set the HTT bit on their CMP processors, 557 * even though they're not actually hyperthreaded. Thus it 558 * takes a bit more work to figure out what's really going 559 * on ... see the handling of the CMP_LEGACY bit below) 560 */ 561 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 562 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 563 if (cpi->cpi_ncpu_per_chip > 1) 564 feature |= X86_HTT; 565 } else { 566 cpi->cpi_ncpu_per_chip = 1; 567 } 568 569 /* 570 * Work on the "extended" feature information, doing 571 * some basic initialization for cpuid_pass2() 572 */ 573 xcpuid = 0; 574 switch (cpi->cpi_vendor) { 575 case X86_VENDOR_Intel: 576 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 577 xcpuid++; 578 break; 579 case X86_VENDOR_AMD: 580 if (cpi->cpi_family > 5 || 581 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 582 xcpuid++; 583 break; 584 case X86_VENDOR_Cyrix: 585 /* 586 * Only these Cyrix CPUs are -known- to support 587 * extended cpuid operations. 588 */ 589 if (x86_type == X86_TYPE_VIA_CYRIX_III || 590 x86_type == X86_TYPE_CYRIX_GXm) 591 xcpuid++; 592 break; 593 case X86_VENDOR_Centaur: 594 case X86_VENDOR_TM: 595 default: 596 xcpuid++; 597 break; 598 } 599 600 if (xcpuid) { 601 cp = &cpi->cpi_extd[0]; 602 cp->cp_eax = 0x80000000; 603 cpi->cpi_xmaxeax = __cpuid_insn(cp); 604 } 605 606 if (cpi->cpi_xmaxeax & 0x80000000) { 607 608 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 609 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 610 611 switch (cpi->cpi_vendor) { 612 case X86_VENDOR_Intel: 613 case X86_VENDOR_AMD: 614 if (cpi->cpi_xmaxeax < 0x80000001) 615 break; 616 cp = &cpi->cpi_extd[1]; 617 cp->cp_eax = 0x80000001; 618 (void) __cpuid_insn(cp); 619 if (cpi->cpi_vendor == X86_VENDOR_AMD && 620 cpi->cpi_family == 5 && 621 cpi->cpi_model == 6 && 622 cpi->cpi_step == 6) { 623 /* 624 * K6 model 6 uses bit 10 to indicate SYSC 625 * Later models use bit 11. Fix it here. 626 */ 627 if (cp->cp_edx & 0x400) { 628 cp->cp_edx &= ~0x400; 629 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 630 } 631 } 632 633 /* 634 * Compute the additions to the kernel's feature word. 635 */ 636 if (cp->cp_edx & CPUID_AMD_EDX_NX) 637 feature |= X86_NX; 638 639 /* 640 * If both the HTT and CMP_LEGACY bits are set, 641 * then we're not actually HyperThreaded. Read 642 * "AMD CPUID Specification" for more details. 643 */ 644 if (cpi->cpi_vendor == X86_VENDOR_AMD && 645 (feature & X86_HTT) && 646 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LEGACY)) { 647 feature &= ~X86_HTT; 648 feature |= X86_CMP; 649 } 650 #if defined(_LP64) 651 /* 652 * It's really tricky to support syscall/sysret in 653 * the i386 kernel; we rely on sysenter/sysexit 654 * instead. In the amd64 kernel, things are -way- 655 * better. 656 */ 657 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 658 feature |= X86_ASYSC; 659 660 /* 661 * While we're thinking about system calls, note 662 * that AMD processors don't support sysenter 663 * in long mode at all, so don't try to program them. 664 */ 665 if (x86_vendor == X86_VENDOR_AMD) 666 feature &= ~X86_SEP; 667 #endif 668 break; 669 default: 670 break; 671 } 672 673 /* 674 * Get CPUID data about processor cores and hyperthreads. 675 */ 676 switch (cpi->cpi_vendor) { 677 case X86_VENDOR_Intel: 678 if (cpi->cpi_maxeax >= 4) { 679 cp = &cpi->cpi_std[4]; 680 cp->cp_eax = 4; 681 cp->cp_ecx = 0; 682 (void) __cpuid_insn(cp); 683 } 684 /*FALLTHROUGH*/ 685 case X86_VENDOR_AMD: 686 if (cpi->cpi_xmaxeax < 0x80000008) 687 break; 688 cp = &cpi->cpi_extd[8]; 689 cp->cp_eax = 0x80000008; 690 (void) __cpuid_insn(cp); 691 /* 692 * Virtual and physical address limits from 693 * cpuid override previously guessed values. 694 */ 695 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 696 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 697 break; 698 default: 699 break; 700 } 701 702 switch (cpi->cpi_vendor) { 703 case X86_VENDOR_Intel: 704 if (cpi->cpi_maxeax < 4) { 705 cpi->cpi_ncore_per_chip = 1; 706 break; 707 } else { 708 cpi->cpi_ncore_per_chip = 709 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 710 } 711 break; 712 case X86_VENDOR_AMD: 713 if (cpi->cpi_xmaxeax < 0x80000008) { 714 cpi->cpi_ncore_per_chip = 1; 715 break; 716 } else { 717 cpi->cpi_ncore_per_chip = 718 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 719 } 720 break; 721 default: 722 cpi->cpi_ncore_per_chip = 1; 723 break; 724 } 725 726 } 727 728 /* 729 * If more than one core, then this processor is CMP. 730 */ 731 if (cpi->cpi_ncore_per_chip > 1) 732 feature |= X86_CMP; 733 /* 734 * If the number of cores is the same as the number 735 * of CPUs, then we cannot have HyperThreading. 736 */ 737 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 738 feature &= ~X86_HTT; 739 740 if ((feature & (X86_HTT | X86_CMP)) == 0) { 741 /* 742 * Single-core single-threaded processors. 743 */ 744 cpi->cpi_chipid = -1; 745 cpi->cpi_clogid = 0; 746 cpi->cpi_coreid = cpu->cpu_id; 747 } else if (cpi->cpi_ncpu_per_chip > 1) { 748 uint_t i; 749 uint_t chipid_shift = 0; 750 uint_t coreid_shift = 0; 751 uint_t apic_id = CPI_APIC_ID(cpi); 752 753 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 754 chipid_shift++; 755 cpi->cpi_chipid = apic_id >> chipid_shift; 756 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 757 758 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 759 if (feature & X86_CMP) { 760 /* 761 * Multi-core (and possibly multi-threaded) 762 * processors. 763 */ 764 uint_t ncpu_per_core; 765 if (cpi->cpi_ncore_per_chip == 1) 766 ncpu_per_core = cpi->cpi_ncpu_per_chip; 767 else if (cpi->cpi_ncore_per_chip > 1) 768 ncpu_per_core = cpi->cpi_ncpu_per_chip / 769 cpi->cpi_ncore_per_chip; 770 /* 771 * 8bit APIC IDs on dual core Pentiums 772 * look like this: 773 * 774 * +-----------------------+------+------+ 775 * | Physical Package ID | MC | HT | 776 * +-----------------------+------+------+ 777 * <------- chipid --------> 778 * <------- coreid ---------------> 779 * <--- clogid --> 780 * 781 * Where the number of bits necessary to 782 * represent MC and HT fields together equals 783 * to the minimum number of bits necessary to 784 * store the value of cpi->cpi_ncpu_per_chip. 785 * Of those bits, the MC part uses the number 786 * of bits necessary to store the value of 787 * cpi->cpi_ncore_per_chip. 788 */ 789 for (i = 1; i < ncpu_per_core; i <<= 1) 790 coreid_shift++; 791 cpi->cpi_coreid = apic_id >> coreid_shift; 792 } else if (feature & X86_HTT) { 793 /* 794 * Single-core multi-threaded processors. 795 */ 796 cpi->cpi_coreid = cpi->cpi_chipid; 797 } 798 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 799 /* 800 * AMD currently only has dual-core processors with 801 * single-threaded cores. If they ever release 802 * multi-threaded processors, then this code 803 * will have to be updated. 804 */ 805 cpi->cpi_coreid = cpu->cpu_id; 806 } else { 807 /* 808 * All other processors are currently 809 * assumed to have single cores. 810 */ 811 cpi->cpi_coreid = cpi->cpi_chipid; 812 } 813 } 814 815 pass1_done: 816 cpi->cpi_pass = 1; 817 return (feature); 818 } 819 820 /* 821 * Make copies of the cpuid table entries we depend on, in 822 * part for ease of parsing now, in part so that we have only 823 * one place to correct any of it, in part for ease of 824 * later export to userland, and in part so we can look at 825 * this stuff in a crash dump. 826 */ 827 828 /*ARGSUSED*/ 829 void 830 cpuid_pass2(cpu_t *cpu) 831 { 832 uint_t n, nmax; 833 int i; 834 struct cpuid_regs *cp; 835 uint8_t *dp; 836 uint32_t *iptr; 837 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 838 839 ASSERT(cpi->cpi_pass == 1); 840 841 if (cpi->cpi_maxeax < 1) 842 goto pass2_done; 843 844 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 845 nmax = NMAX_CPI_STD; 846 /* 847 * (We already handled n == 0 and n == 1 in pass 1) 848 */ 849 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 850 cp->cp_eax = n; 851 (void) __cpuid_insn(cp); 852 switch (n) { 853 case 2: 854 /* 855 * "the lower 8 bits of the %eax register 856 * contain a value that identifies the number 857 * of times the cpuid [instruction] has to be 858 * executed to obtain a complete image of the 859 * processor's caching systems." 860 * 861 * How *do* they make this stuff up? 862 */ 863 cpi->cpi_ncache = sizeof (*cp) * 864 BITX(cp->cp_eax, 7, 0); 865 if (cpi->cpi_ncache == 0) 866 break; 867 cpi->cpi_ncache--; /* skip count byte */ 868 869 /* 870 * Well, for now, rather than attempt to implement 871 * this slightly dubious algorithm, we just look 872 * at the first 15 .. 873 */ 874 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 875 cpi->cpi_ncache = sizeof (*cp) - 1; 876 877 dp = cpi->cpi_cacheinfo; 878 if (BITX(cp->cp_eax, 31, 31) == 0) { 879 uint8_t *p = (void *)&cp->cp_eax; 880 for (i = 1; i < 3; i++) 881 if (p[i] != 0) 882 *dp++ = p[i]; 883 } 884 if (BITX(cp->cp_ebx, 31, 31) == 0) { 885 uint8_t *p = (void *)&cp->cp_ebx; 886 for (i = 0; i < 4; i++) 887 if (p[i] != 0) 888 *dp++ = p[i]; 889 } 890 if (BITX(cp->cp_ecx, 31, 31) == 0) { 891 uint8_t *p = (void *)&cp->cp_ecx; 892 for (i = 0; i < 4; i++) 893 if (p[i] != 0) 894 *dp++ = p[i]; 895 } 896 if (BITX(cp->cp_edx, 31, 31) == 0) { 897 uint8_t *p = (void *)&cp->cp_edx; 898 for (i = 0; i < 4; i++) 899 if (p[i] != 0) 900 *dp++ = p[i]; 901 } 902 break; 903 case 3: /* Processor serial number, if PSN supported */ 904 case 4: /* Deterministic cache parameters */ 905 case 5: /* Monitor/Mwait parameters */ 906 default: 907 break; 908 } 909 } 910 911 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 912 goto pass2_done; 913 914 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 915 nmax = NMAX_CPI_EXTD; 916 /* 917 * Copy the extended properties, fixing them as we go. 918 * (We already handled n == 0 and n == 1 in pass 1) 919 */ 920 iptr = (void *)cpi->cpi_brandstr; 921 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 922 cp->cp_eax = 0x80000000 + n; 923 (void) __cpuid_insn(cp); 924 switch (n) { 925 case 2: 926 case 3: 927 case 4: 928 /* 929 * Extract the brand string 930 */ 931 *iptr++ = cp->cp_eax; 932 *iptr++ = cp->cp_ebx; 933 *iptr++ = cp->cp_ecx; 934 *iptr++ = cp->cp_edx; 935 break; 936 case 5: 937 switch (cpi->cpi_vendor) { 938 case X86_VENDOR_AMD: 939 /* 940 * The Athlon and Duron were the first 941 * parts to report the sizes of the 942 * TLB for large pages. Before then, 943 * we don't trust the data. 944 */ 945 if (cpi->cpi_family < 6 || 946 (cpi->cpi_family == 6 && 947 cpi->cpi_model < 1)) 948 cp->cp_eax = 0; 949 break; 950 default: 951 break; 952 } 953 break; 954 case 6: 955 switch (cpi->cpi_vendor) { 956 case X86_VENDOR_AMD: 957 /* 958 * The Athlon and Duron were the first 959 * AMD parts with L2 TLB's. 960 * Before then, don't trust the data. 961 */ 962 if (cpi->cpi_family < 6 || 963 cpi->cpi_family == 6 && 964 cpi->cpi_model < 1) 965 cp->cp_eax = cp->cp_ebx = 0; 966 /* 967 * AMD Duron rev A0 reports L2 968 * cache size incorrectly as 1K 969 * when it is really 64K 970 */ 971 if (cpi->cpi_family == 6 && 972 cpi->cpi_model == 3 && 973 cpi->cpi_step == 0) { 974 cp->cp_ecx &= 0xffff; 975 cp->cp_ecx |= 0x400000; 976 } 977 break; 978 case X86_VENDOR_Cyrix: /* VIA C3 */ 979 /* 980 * VIA C3 processors are a bit messed 981 * up w.r.t. encoding cache sizes in %ecx 982 */ 983 if (cpi->cpi_family != 6) 984 break; 985 /* 986 * model 7 and 8 were incorrectly encoded 987 * 988 * xxx is model 8 really broken? 989 */ 990 if (cpi->cpi_model == 7 || 991 cpi->cpi_model == 8) 992 cp->cp_ecx = 993 BITX(cp->cp_ecx, 31, 24) << 16 | 994 BITX(cp->cp_ecx, 23, 16) << 12 | 995 BITX(cp->cp_ecx, 15, 8) << 8 | 996 BITX(cp->cp_ecx, 7, 0); 997 /* 998 * model 9 stepping 1 has wrong associativity 999 */ 1000 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1001 cp->cp_ecx |= 8 << 12; 1002 break; 1003 case X86_VENDOR_Intel: 1004 /* 1005 * Extended L2 Cache features function. 1006 * First appeared on Prescott. 1007 */ 1008 default: 1009 break; 1010 } 1011 break; 1012 default: 1013 break; 1014 } 1015 } 1016 1017 pass2_done: 1018 cpi->cpi_pass = 2; 1019 } 1020 1021 static const char * 1022 intel_cpubrand(const struct cpuid_info *cpi) 1023 { 1024 int i; 1025 1026 if ((x86_feature & X86_CPUID) == 0 || 1027 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1028 return ("i486"); 1029 1030 switch (cpi->cpi_family) { 1031 case 5: 1032 return ("Intel Pentium(r)"); 1033 case 6: 1034 switch (cpi->cpi_model) { 1035 uint_t celeron, xeon; 1036 const struct cpuid_regs *cp; 1037 case 0: 1038 case 1: 1039 case 2: 1040 return ("Intel Pentium(r) Pro"); 1041 case 3: 1042 case 4: 1043 return ("Intel Pentium(r) II"); 1044 case 6: 1045 return ("Intel Celeron(r)"); 1046 case 5: 1047 case 7: 1048 celeron = xeon = 0; 1049 cp = &cpi->cpi_std[2]; /* cache info */ 1050 1051 for (i = 1; i < 3; i++) { 1052 uint_t tmp; 1053 1054 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1055 if (tmp == 0x40) 1056 celeron++; 1057 if (tmp >= 0x44 && tmp <= 0x45) 1058 xeon++; 1059 } 1060 1061 for (i = 0; i < 2; i++) { 1062 uint_t tmp; 1063 1064 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1065 if (tmp == 0x40) 1066 celeron++; 1067 else if (tmp >= 0x44 && tmp <= 0x45) 1068 xeon++; 1069 } 1070 1071 for (i = 0; i < 4; i++) { 1072 uint_t tmp; 1073 1074 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1075 if (tmp == 0x40) 1076 celeron++; 1077 else if (tmp >= 0x44 && tmp <= 0x45) 1078 xeon++; 1079 } 1080 1081 for (i = 0; i < 4; i++) { 1082 uint_t tmp; 1083 1084 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1085 if (tmp == 0x40) 1086 celeron++; 1087 else if (tmp >= 0x44 && tmp <= 0x45) 1088 xeon++; 1089 } 1090 1091 if (celeron) 1092 return ("Intel Celeron(r)"); 1093 if (xeon) 1094 return (cpi->cpi_model == 5 ? 1095 "Intel Pentium(r) II Xeon(tm)" : 1096 "Intel Pentium(r) III Xeon(tm)"); 1097 return (cpi->cpi_model == 5 ? 1098 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1099 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1100 default: 1101 break; 1102 } 1103 default: 1104 break; 1105 } 1106 1107 /* BrandID is present if the field is nonzero */ 1108 if (cpi->cpi_brandid != 0) { 1109 static const struct { 1110 uint_t bt_bid; 1111 const char *bt_str; 1112 } brand_tbl[] = { 1113 { 0x1, "Intel(r) Celeron(r)" }, 1114 { 0x2, "Intel(r) Pentium(r) III" }, 1115 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1116 { 0x4, "Intel(r) Pentium(r) III" }, 1117 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1118 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1119 { 0x8, "Intel(r) Pentium(r) 4" }, 1120 { 0x9, "Intel(r) Pentium(r) 4" }, 1121 { 0xa, "Intel(r) Celeron(r)" }, 1122 { 0xb, "Intel(r) Xeon(tm)" }, 1123 { 0xc, "Intel(r) Xeon(tm) MP" }, 1124 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1125 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1126 { 0x11, "Mobile Genuine Intel(r)" }, 1127 { 0x12, "Intel(r) Celeron(r) M" }, 1128 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1129 { 0x14, "Intel(r) Celeron(r)" }, 1130 { 0x15, "Mobile Genuine Intel(r)" }, 1131 { 0x16, "Intel(r) Pentium(r) M" }, 1132 { 0x17, "Mobile Intel(r) Celeron(r)" } 1133 }; 1134 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1135 uint_t sgn; 1136 1137 sgn = (cpi->cpi_family << 8) | 1138 (cpi->cpi_model << 4) | cpi->cpi_step; 1139 1140 for (i = 0; i < btblmax; i++) 1141 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1142 break; 1143 if (i < btblmax) { 1144 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1145 return ("Intel(r) Celeron(r)"); 1146 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1147 return ("Intel(r) Xeon(tm) MP"); 1148 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1149 return ("Intel(r) Xeon(tm)"); 1150 return (brand_tbl[i].bt_str); 1151 } 1152 } 1153 1154 return (NULL); 1155 } 1156 1157 static const char * 1158 amd_cpubrand(const struct cpuid_info *cpi) 1159 { 1160 if ((x86_feature & X86_CPUID) == 0 || 1161 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1162 return ("i486 compatible"); 1163 1164 switch (cpi->cpi_family) { 1165 case 5: 1166 switch (cpi->cpi_model) { 1167 case 0: 1168 case 1: 1169 case 2: 1170 case 3: 1171 case 4: 1172 case 5: 1173 return ("AMD-K5(r)"); 1174 case 6: 1175 case 7: 1176 return ("AMD-K6(r)"); 1177 case 8: 1178 return ("AMD-K6(r)-2"); 1179 case 9: 1180 return ("AMD-K6(r)-III"); 1181 default: 1182 return ("AMD (family 5)"); 1183 } 1184 case 6: 1185 switch (cpi->cpi_model) { 1186 case 1: 1187 return ("AMD-K7(tm)"); 1188 case 0: 1189 case 2: 1190 case 4: 1191 return ("AMD Athlon(tm)"); 1192 case 3: 1193 case 7: 1194 return ("AMD Duron(tm)"); 1195 case 6: 1196 case 8: 1197 case 10: 1198 /* 1199 * Use the L2 cache size to distinguish 1200 */ 1201 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1202 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1203 default: 1204 return ("AMD (family 6)"); 1205 } 1206 default: 1207 break; 1208 } 1209 1210 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1211 cpi->cpi_brandid != 0) { 1212 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1213 case 3: 1214 return ("AMD Opteron(tm) UP 1xx"); 1215 case 4: 1216 return ("AMD Opteron(tm) DP 2xx"); 1217 case 5: 1218 return ("AMD Opteron(tm) MP 8xx"); 1219 default: 1220 return ("AMD Opteron(tm)"); 1221 } 1222 } 1223 1224 return (NULL); 1225 } 1226 1227 static const char * 1228 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1229 { 1230 if ((x86_feature & X86_CPUID) == 0 || 1231 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1232 type == X86_TYPE_CYRIX_486) 1233 return ("i486 compatible"); 1234 1235 switch (type) { 1236 case X86_TYPE_CYRIX_6x86: 1237 return ("Cyrix 6x86"); 1238 case X86_TYPE_CYRIX_6x86L: 1239 return ("Cyrix 6x86L"); 1240 case X86_TYPE_CYRIX_6x86MX: 1241 return ("Cyrix 6x86MX"); 1242 case X86_TYPE_CYRIX_GXm: 1243 return ("Cyrix GXm"); 1244 case X86_TYPE_CYRIX_MediaGX: 1245 return ("Cyrix MediaGX"); 1246 case X86_TYPE_CYRIX_MII: 1247 return ("Cyrix M2"); 1248 case X86_TYPE_VIA_CYRIX_III: 1249 return ("VIA Cyrix M3"); 1250 default: 1251 /* 1252 * Have another wild guess .. 1253 */ 1254 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1255 return ("Cyrix 5x86"); 1256 else if (cpi->cpi_family == 5) { 1257 switch (cpi->cpi_model) { 1258 case 2: 1259 return ("Cyrix 6x86"); /* Cyrix M1 */ 1260 case 4: 1261 return ("Cyrix MediaGX"); 1262 default: 1263 break; 1264 } 1265 } else if (cpi->cpi_family == 6) { 1266 switch (cpi->cpi_model) { 1267 case 0: 1268 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1269 case 5: 1270 case 6: 1271 case 7: 1272 case 8: 1273 case 9: 1274 return ("VIA C3"); 1275 default: 1276 break; 1277 } 1278 } 1279 break; 1280 } 1281 return (NULL); 1282 } 1283 1284 /* 1285 * This only gets called in the case that the CPU extended 1286 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1287 * aren't available, or contain null bytes for some reason. 1288 */ 1289 static void 1290 fabricate_brandstr(struct cpuid_info *cpi) 1291 { 1292 const char *brand = NULL; 1293 1294 switch (cpi->cpi_vendor) { 1295 case X86_VENDOR_Intel: 1296 brand = intel_cpubrand(cpi); 1297 break; 1298 case X86_VENDOR_AMD: 1299 brand = amd_cpubrand(cpi); 1300 break; 1301 case X86_VENDOR_Cyrix: 1302 brand = cyrix_cpubrand(cpi, x86_type); 1303 break; 1304 case X86_VENDOR_NexGen: 1305 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1306 brand = "NexGen Nx586"; 1307 break; 1308 case X86_VENDOR_Centaur: 1309 if (cpi->cpi_family == 5) 1310 switch (cpi->cpi_model) { 1311 case 4: 1312 brand = "Centaur C6"; 1313 break; 1314 case 8: 1315 brand = "Centaur C2"; 1316 break; 1317 case 9: 1318 brand = "Centaur C3"; 1319 break; 1320 default: 1321 break; 1322 } 1323 break; 1324 case X86_VENDOR_Rise: 1325 if (cpi->cpi_family == 5 && 1326 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1327 brand = "Rise mP6"; 1328 break; 1329 case X86_VENDOR_SiS: 1330 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1331 brand = "SiS 55x"; 1332 break; 1333 case X86_VENDOR_TM: 1334 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1335 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1336 break; 1337 case X86_VENDOR_NSC: 1338 case X86_VENDOR_UMC: 1339 default: 1340 break; 1341 } 1342 if (brand) { 1343 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1344 return; 1345 } 1346 1347 /* 1348 * If all else fails ... 1349 */ 1350 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1351 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1352 cpi->cpi_model, cpi->cpi_step); 1353 } 1354 1355 /* 1356 * This routine is called just after kernel memory allocation 1357 * becomes available on cpu0, and as part of mp_startup() on 1358 * the other cpus. 1359 * 1360 * Fixup the brand string. 1361 */ 1362 /*ARGSUSED*/ 1363 void 1364 cpuid_pass3(cpu_t *cpu) 1365 { 1366 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1367 1368 ASSERT(cpi->cpi_pass == 2); 1369 1370 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1371 fabricate_brandstr(cpi); 1372 goto pass3_done; 1373 } 1374 1375 /* 1376 * If we successfully extracted a brand string from the cpuid 1377 * instruction, clean it up by removing leading spaces and 1378 * similar junk. 1379 */ 1380 if (cpi->cpi_brandstr[0]) { 1381 size_t maxlen = sizeof (cpi->cpi_brandstr); 1382 char *src, *dst; 1383 1384 dst = src = (char *)cpi->cpi_brandstr; 1385 src[maxlen - 1] = '\0'; 1386 /* 1387 * strip leading spaces 1388 */ 1389 while (*src == ' ') 1390 src++; 1391 /* 1392 * Remove any 'Genuine' or "Authentic" prefixes 1393 */ 1394 if (strncmp(src, "Genuine ", 8) == 0) 1395 src += 8; 1396 if (strncmp(src, "Authentic ", 10) == 0) 1397 src += 10; 1398 1399 /* 1400 * Now do an in-place copy. 1401 * Map (R) to (r) and (TM) to (tm). 1402 * The era of teletypes is long gone, and there's 1403 * -really- no need to shout. 1404 */ 1405 while (*src != '\0') { 1406 if (src[0] == '(') { 1407 if (strncmp(src + 1, "R)", 2) == 0) { 1408 (void) strncpy(dst, "(r)", 3); 1409 src += 3; 1410 dst += 3; 1411 continue; 1412 } 1413 if (strncmp(src + 1, "TM)", 3) == 0) { 1414 (void) strncpy(dst, "(tm)", 4); 1415 src += 4; 1416 dst += 4; 1417 continue; 1418 } 1419 } 1420 *dst++ = *src++; 1421 } 1422 *dst = '\0'; 1423 1424 /* 1425 * Finally, remove any trailing spaces 1426 */ 1427 while (--dst > cpi->cpi_brandstr) 1428 if (*dst == ' ') 1429 *dst = '\0'; 1430 else 1431 break; 1432 } else 1433 fabricate_brandstr(cpi); 1434 1435 pass3_done: 1436 cpi->cpi_pass = 3; 1437 } 1438 1439 /* 1440 * This routine is called out of bind_hwcap() much later in the life 1441 * of the kernel (post_startup()). The job of this routine is to resolve 1442 * the hardware feature support and kernel support for those features into 1443 * what we're actually going to tell applications via the aux vector. 1444 */ 1445 uint_t 1446 cpuid_pass4(cpu_t *cpu) 1447 { 1448 struct cpuid_info *cpi; 1449 uint_t hwcap_flags = 0; 1450 1451 if (cpu == NULL) 1452 cpu = CPU; 1453 cpi = cpu->cpu_m.mcpu_cpi; 1454 1455 ASSERT(cpi->cpi_pass == 3); 1456 1457 if (cpi->cpi_maxeax >= 1) { 1458 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1459 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1460 1461 *edx = CPI_FEATURES_EDX(cpi); 1462 *ecx = CPI_FEATURES_ECX(cpi); 1463 1464 /* 1465 * [these require explicit kernel support] 1466 */ 1467 if ((x86_feature & X86_SEP) == 0) 1468 *edx &= ~CPUID_INTC_EDX_SEP; 1469 1470 if ((x86_feature & X86_SSE) == 0) 1471 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 1472 if ((x86_feature & X86_SSE2) == 0) 1473 *edx &= ~CPUID_INTC_EDX_SSE2; 1474 1475 if ((x86_feature & X86_HTT) == 0) 1476 *edx &= ~CPUID_INTC_EDX_HTT; 1477 1478 if ((x86_feature & X86_SSE3) == 0) 1479 *ecx &= ~CPUID_INTC_ECX_SSE3; 1480 1481 /* 1482 * [no explicit support required beyond x87 fp context] 1483 */ 1484 if (!fpu_exists) 1485 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 1486 1487 /* 1488 * Now map the supported feature vector to things that we 1489 * think userland will care about. 1490 */ 1491 if (*edx & CPUID_INTC_EDX_SEP) 1492 hwcap_flags |= AV_386_SEP; 1493 if (*edx & CPUID_INTC_EDX_SSE) 1494 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 1495 if (*edx & CPUID_INTC_EDX_SSE2) 1496 hwcap_flags |= AV_386_SSE2; 1497 if (*ecx & CPUID_INTC_ECX_SSE3) 1498 hwcap_flags |= AV_386_SSE3; 1499 1500 if (*edx & CPUID_INTC_EDX_FPU) 1501 hwcap_flags |= AV_386_FPU; 1502 if (*edx & CPUID_INTC_EDX_MMX) 1503 hwcap_flags |= AV_386_MMX; 1504 1505 if (*edx & CPUID_INTC_EDX_TSC) 1506 hwcap_flags |= AV_386_TSC; 1507 if (*edx & CPUID_INTC_EDX_CX8) 1508 hwcap_flags |= AV_386_CX8; 1509 if (*edx & CPUID_INTC_EDX_CMOV) 1510 hwcap_flags |= AV_386_CMOV; 1511 if (*ecx & CPUID_INTC_ECX_MON) 1512 hwcap_flags |= AV_386_MON; 1513 #if defined(CPUID_INTC_ECX_CX16) 1514 if (*ecx & CPUID_INTC_ECX_CX16) 1515 hwcap_flags |= AV_386_CX16; 1516 #endif 1517 } 1518 1519 if (x86_feature & X86_HTT) 1520 hwcap_flags |= AV_386_PAUSE; 1521 1522 if (cpi->cpi_xmaxeax < 0x80000001) 1523 goto pass4_done; 1524 1525 switch (cpi->cpi_vendor) { 1526 struct cpuid_regs cp; 1527 uint32_t *edx; 1528 1529 case X86_VENDOR_Intel: /* sigh */ 1530 case X86_VENDOR_AMD: 1531 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 1532 1533 *edx = CPI_FEATURES_XTD_EDX(cpi); 1534 1535 /* 1536 * [no explicit support required beyond 1537 * x87 fp context and exception handlers] 1538 */ 1539 if (!fpu_exists) 1540 *edx &= ~(CPUID_AMD_EDX_MMXamd | 1541 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 1542 1543 if ((x86_feature & X86_ASYSC) == 0) 1544 *edx &= ~CPUID_AMD_EDX_SYSC; 1545 if ((x86_feature & X86_NX) == 0) 1546 *edx &= ~CPUID_AMD_EDX_NX; 1547 #if !defined(_LP64) 1548 *edx &= ~CPUID_AMD_EDX_LM; 1549 #endif 1550 /* 1551 * Now map the supported feature vector to 1552 * things that we think userland will care about. 1553 */ 1554 if (*edx & CPUID_AMD_EDX_SYSC) 1555 hwcap_flags |= AV_386_AMD_SYSC; 1556 if (*edx & CPUID_AMD_EDX_MMXamd) 1557 hwcap_flags |= AV_386_AMD_MMX; 1558 if (*edx & CPUID_AMD_EDX_3DNow) 1559 hwcap_flags |= AV_386_AMD_3DNow; 1560 if (*edx & CPUID_AMD_EDX_3DNowx) 1561 hwcap_flags |= AV_386_AMD_3DNowx; 1562 break; 1563 1564 case X86_VENDOR_TM: 1565 cp.cp_eax = 0x80860001; 1566 (void) __cpuid_insn(&cp); 1567 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 1568 break; 1569 1570 default: 1571 break; 1572 } 1573 1574 pass4_done: 1575 cpi->cpi_pass = 4; 1576 return (hwcap_flags); 1577 } 1578 1579 1580 /* 1581 * Simulate the cpuid instruction using the data we previously 1582 * captured about this CPU. We try our best to return the truth 1583 * about the hardware, independently of kernel support. 1584 */ 1585 uint32_t 1586 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 1587 { 1588 struct cpuid_info *cpi; 1589 struct cpuid_regs *xcp; 1590 1591 if (cpu == NULL) 1592 cpu = CPU; 1593 cpi = cpu->cpu_m.mcpu_cpi; 1594 1595 ASSERT(cpuid_checkpass(cpu, 3)); 1596 1597 /* 1598 * CPUID data is cached in two separate places: cpi_std for standard 1599 * CPUID functions, and cpi_extd for extended CPUID functions. 1600 */ 1601 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 1602 xcp = &cpi->cpi_std[cp->cp_eax]; 1603 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 1604 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 1605 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 1606 else 1607 /* 1608 * The caller is asking for data from an input parameter which 1609 * the kernel has not cached. In this case we go fetch from 1610 * the hardware and return the data directly to the user. 1611 */ 1612 return (__cpuid_insn(cp)); 1613 1614 cp->cp_eax = xcp->cp_eax; 1615 cp->cp_ebx = xcp->cp_ebx; 1616 cp->cp_ecx = xcp->cp_ecx; 1617 cp->cp_edx = xcp->cp_edx; 1618 return (cp->cp_eax); 1619 } 1620 1621 int 1622 cpuid_checkpass(cpu_t *cpu, int pass) 1623 { 1624 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 1625 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 1626 } 1627 1628 int 1629 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 1630 { 1631 ASSERT(cpuid_checkpass(cpu, 3)); 1632 1633 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 1634 } 1635 1636 int 1637 cpuid_is_cmt(cpu_t *cpu) 1638 { 1639 if (cpu == NULL) 1640 cpu = CPU; 1641 1642 ASSERT(cpuid_checkpass(cpu, 1)); 1643 1644 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 1645 } 1646 1647 /* 1648 * AMD and Intel both implement the 64-bit variant of the syscall 1649 * instruction (syscallq), so if there's -any- support for syscall, 1650 * cpuid currently says "yes, we support this". 1651 * 1652 * However, Intel decided to -not- implement the 32-bit variant of the 1653 * syscall instruction, so we provide a predicate to allow our caller 1654 * to test that subtlety here. 1655 */ 1656 /*ARGSUSED*/ 1657 int 1658 cpuid_syscall32_insn(cpu_t *cpu) 1659 { 1660 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 1661 1662 if (x86_feature & X86_ASYSC) 1663 return (x86_vendor != X86_VENDOR_Intel); 1664 return (0); 1665 } 1666 1667 int 1668 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 1669 { 1670 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1671 1672 static const char fmt[] = 1673 "x86 (%s family %d model %d step %d clock %d MHz)"; 1674 static const char fmt_ht[] = 1675 "x86 (chipid 0x%x %s family %d model %d step %d clock %d MHz)"; 1676 1677 ASSERT(cpuid_checkpass(cpu, 1)); 1678 1679 if (cpuid_is_cmt(cpu)) 1680 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 1681 cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model, 1682 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1683 return (snprintf(s, n, fmt, 1684 cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model, 1685 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1686 } 1687 1688 const char * 1689 cpuid_getvendorstr(cpu_t *cpu) 1690 { 1691 ASSERT(cpuid_checkpass(cpu, 1)); 1692 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 1693 } 1694 1695 uint_t 1696 cpuid_getvendor(cpu_t *cpu) 1697 { 1698 ASSERT(cpuid_checkpass(cpu, 1)); 1699 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 1700 } 1701 1702 uint_t 1703 cpuid_getfamily(cpu_t *cpu) 1704 { 1705 ASSERT(cpuid_checkpass(cpu, 1)); 1706 return (cpu->cpu_m.mcpu_cpi->cpi_family); 1707 } 1708 1709 uint_t 1710 cpuid_getmodel(cpu_t *cpu) 1711 { 1712 ASSERT(cpuid_checkpass(cpu, 1)); 1713 return (cpu->cpu_m.mcpu_cpi->cpi_model); 1714 } 1715 1716 uint_t 1717 cpuid_get_ncpu_per_chip(cpu_t *cpu) 1718 { 1719 ASSERT(cpuid_checkpass(cpu, 1)); 1720 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 1721 } 1722 1723 uint_t 1724 cpuid_get_ncore_per_chip(cpu_t *cpu) 1725 { 1726 ASSERT(cpuid_checkpass(cpu, 1)); 1727 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 1728 } 1729 1730 uint_t 1731 cpuid_getstep(cpu_t *cpu) 1732 { 1733 ASSERT(cpuid_checkpass(cpu, 1)); 1734 return (cpu->cpu_m.mcpu_cpi->cpi_step); 1735 } 1736 1737 chipid_t 1738 chip_plat_get_chipid(cpu_t *cpu) 1739 { 1740 ASSERT(cpuid_checkpass(cpu, 1)); 1741 1742 if (cpuid_is_cmt(cpu)) 1743 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 1744 return (cpu->cpu_id); 1745 } 1746 1747 id_t 1748 chip_plat_get_coreid(cpu_t *cpu) 1749 { 1750 ASSERT(cpuid_checkpass(cpu, 1)); 1751 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 1752 } 1753 1754 int 1755 chip_plat_get_clogid(cpu_t *cpu) 1756 { 1757 ASSERT(cpuid_checkpass(cpu, 1)); 1758 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 1759 } 1760 1761 void 1762 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 1763 { 1764 struct cpuid_info *cpi; 1765 1766 if (cpu == NULL) 1767 cpu = CPU; 1768 cpi = cpu->cpu_m.mcpu_cpi; 1769 1770 ASSERT(cpuid_checkpass(cpu, 1)); 1771 1772 if (pabits) 1773 *pabits = cpi->cpi_pabits; 1774 if (vabits) 1775 *vabits = cpi->cpi_vabits; 1776 } 1777 1778 /* 1779 * Returns the number of data TLB entries for a corresponding 1780 * pagesize. If it can't be computed, or isn't known, the 1781 * routine returns zero. If you ask about an architecturally 1782 * impossible pagesize, the routine will panic (so that the 1783 * hat implementor knows that things are inconsistent.) 1784 */ 1785 uint_t 1786 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 1787 { 1788 struct cpuid_info *cpi; 1789 uint_t dtlb_nent = 0; 1790 1791 if (cpu == NULL) 1792 cpu = CPU; 1793 cpi = cpu->cpu_m.mcpu_cpi; 1794 1795 ASSERT(cpuid_checkpass(cpu, 1)); 1796 1797 /* 1798 * Check the L2 TLB info 1799 */ 1800 if (cpi->cpi_xmaxeax >= 0x80000006) { 1801 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 1802 1803 switch (pagesize) { 1804 1805 case 4 * 1024: 1806 /* 1807 * All zero in the top 16 bits of the register 1808 * indicates a unified TLB. Size is in low 16 bits. 1809 */ 1810 if ((cp->cp_ebx & 0xffff0000) == 0) 1811 dtlb_nent = cp->cp_ebx & 0x0000ffff; 1812 else 1813 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 1814 break; 1815 1816 case 2 * 1024 * 1024: 1817 if ((cp->cp_eax & 0xffff0000) == 0) 1818 dtlb_nent = cp->cp_eax & 0x0000ffff; 1819 else 1820 dtlb_nent = BITX(cp->cp_eax, 27, 16); 1821 break; 1822 1823 default: 1824 panic("unknown L2 pagesize"); 1825 /*NOTREACHED*/ 1826 } 1827 } 1828 1829 if (dtlb_nent != 0) 1830 return (dtlb_nent); 1831 1832 /* 1833 * No L2 TLB support for this size, try L1. 1834 */ 1835 if (cpi->cpi_xmaxeax >= 0x80000005) { 1836 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 1837 1838 switch (pagesize) { 1839 case 4 * 1024: 1840 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 1841 break; 1842 case 2 * 1024 * 1024: 1843 dtlb_nent = BITX(cp->cp_eax, 23, 16); 1844 break; 1845 default: 1846 panic("unknown L1 d-TLB pagesize"); 1847 /*NOTREACHED*/ 1848 } 1849 } 1850 1851 return (dtlb_nent); 1852 } 1853 1854 /* 1855 * Return 0 if the erratum is not present or not applicable, positive 1856 * if it is, and negative if the status of the erratum is unknown. 1857 * 1858 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 1859 * Processors" #25759, Rev 3.57, August 2005 1860 */ 1861 int 1862 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 1863 { 1864 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1865 uint_t eax; 1866 1867 if (cpi->cpi_vendor != X86_VENDOR_AMD) 1868 return (0); 1869 1870 eax = cpi->cpi_std[1].cp_eax; 1871 1872 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 1873 #define SH_B3(eax) (eax == 0xf51) 1874 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 1875 1876 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 1877 1878 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 1879 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 1880 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 1881 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 1882 1883 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 1884 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 1885 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 1886 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 1887 1888 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 1889 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 1890 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 1891 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 1892 #define BH_E4(eax) (eax == 0x20fb1) 1893 #define SH_E5(eax) (eax == 0x20f42) 1894 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 1895 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 1896 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 1897 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 1898 DH_E6(eax) || JH_E6(eax)) 1899 1900 switch (erratum) { 1901 case 1: 1902 return (1); 1903 case 51: /* what does the asterisk mean? */ 1904 return (B(eax) || SH_C0(eax) || CG(eax)); 1905 case 52: 1906 return (B(eax)); 1907 case 57: 1908 return (1); 1909 case 58: 1910 return (B(eax)); 1911 case 60: 1912 return (1); 1913 case 61: 1914 case 62: 1915 case 63: 1916 case 64: 1917 case 65: 1918 case 66: 1919 case 68: 1920 case 69: 1921 case 70: 1922 case 71: 1923 return (B(eax)); 1924 case 72: 1925 return (SH_B0(eax)); 1926 case 74: 1927 return (B(eax)); 1928 case 75: 1929 return (1); 1930 case 76: 1931 return (B(eax)); 1932 case 77: 1933 return (1); 1934 case 78: 1935 return (B(eax) || SH_C0(eax)); 1936 case 79: 1937 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1938 case 80: 1939 case 81: 1940 case 82: 1941 return (B(eax)); 1942 case 83: 1943 return (B(eax) || SH_C0(eax) || CG(eax)); 1944 case 85: 1945 return (1); 1946 case 86: 1947 return (SH_C0(eax) || CG(eax)); 1948 case 88: 1949 #if !defined(__amd64) 1950 return (0); 1951 #else 1952 return (B(eax) || SH_C0(eax)); 1953 #endif 1954 case 89: 1955 return (1); 1956 case 90: 1957 return (B(eax) || SH_C0(eax) || CG(eax)); 1958 case 91: 1959 case 92: 1960 return (B(eax) || SH_C0(eax)); 1961 case 93: 1962 return (SH_C0(eax)); 1963 case 94: 1964 return (B(eax) || SH_C0(eax) || CG(eax)); 1965 case 95: 1966 #if !defined(__amd64) 1967 return (0); 1968 #else 1969 return (B(eax) || SH_C0(eax)); 1970 #endif 1971 case 96: 1972 return (B(eax) || SH_C0(eax) || CG(eax)); 1973 case 97: 1974 case 98: 1975 return (SH_C0(eax) || CG(eax)); 1976 case 99: 1977 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1978 case 100: 1979 return (B(eax) || SH_C0(eax)); 1980 case 101: 1981 case 103: 1982 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1983 case 104: 1984 return (SH_C0(eax) || CG(eax) || D0(eax)); 1985 case 105: 1986 case 106: 1987 case 107: 1988 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1989 case 108: 1990 return (DH_CG(eax)); 1991 case 109: 1992 return (SH_C0(eax) || CG(eax) || D0(eax)); 1993 case 110: 1994 return (D0(eax) || EX(eax)); 1995 case 111: 1996 return (CG(eax)); 1997 case 112: 1998 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1999 case 113: 2000 return (eax == 0x20fc0); 2001 case 114: 2002 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2003 case 115: 2004 return (SH_E0(eax) || JH_E1(eax)); 2005 case 116: 2006 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2007 case 117: 2008 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2009 case 118: 2010 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2011 JH_E6(eax)); 2012 case 121: 2013 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2014 case 122: 2015 return (SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2016 case 123: 2017 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2018 case 131: 2019 return (1); 2020 case 6336786: 2021 /* 2022 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2023 * if this is a K8 family processor 2024 */ 2025 if (CPI_FAMILY(cpi) == 0xf) { 2026 struct cpuid_regs regs; 2027 regs.cp_eax = 0x80000007; 2028 (void) __cpuid_insn(®s); 2029 return (!(regs.cp_edx & 0x100)); 2030 } 2031 return (0); 2032 case 6323525: 2033 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2034 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2035 2036 default: 2037 return (-1); 2038 } 2039 } 2040 2041 static const char assoc_str[] = "associativity"; 2042 static const char line_str[] = "line-size"; 2043 static const char size_str[] = "size"; 2044 2045 static void 2046 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2047 uint32_t val) 2048 { 2049 char buf[128]; 2050 2051 /* 2052 * ndi_prop_update_int() is used because it is desirable for 2053 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2054 */ 2055 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2056 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2057 } 2058 2059 /* 2060 * Intel-style cache/tlb description 2061 * 2062 * Standard cpuid level 2 gives a randomly ordered 2063 * selection of tags that index into a table that describes 2064 * cache and tlb properties. 2065 */ 2066 2067 static const char l1_icache_str[] = "l1-icache"; 2068 static const char l1_dcache_str[] = "l1-dcache"; 2069 static const char l2_cache_str[] = "l2-cache"; 2070 static const char itlb4k_str[] = "itlb-4K"; 2071 static const char dtlb4k_str[] = "dtlb-4K"; 2072 static const char itlb4M_str[] = "itlb-4M"; 2073 static const char dtlb4M_str[] = "dtlb-4M"; 2074 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2075 static const char dtlb44_str[] = "dtlb-4K-4M"; 2076 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2077 static const char sl2_cache_str[] = "sectored-l2-cache"; 2078 static const char itrace_str[] = "itrace-cache"; 2079 static const char sl3_cache_str[] = "sectored-l3-cache"; 2080 2081 static const struct cachetab { 2082 uint8_t ct_code; 2083 uint8_t ct_assoc; 2084 uint16_t ct_line_size; 2085 size_t ct_size; 2086 const char *ct_label; 2087 } intel_ctab[] = { 2088 /* maintain descending order! */ 2089 { 0xb3, 4, 0, 128, dtlb4k_str }, 2090 { 0xb0, 4, 0, 128, itlb4k_str }, 2091 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2092 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2093 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2094 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2095 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2096 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2097 { 0x81, 8, 32, 128*1024, l2_cache_str}, /* suspect! */ 2098 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2099 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2100 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2101 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2102 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2103 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2104 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2105 { 0x72, 8, 0, 32*1024, itrace_str}, 2106 { 0x71, 8, 0, 16*1024, itrace_str}, 2107 { 0x70, 8, 0, 12*1024, itrace_str}, 2108 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2109 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2110 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2111 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2112 { 0x5d, 0, 0, 256, dtlb44_str}, 2113 { 0x5c, 0, 0, 128, dtlb44_str}, 2114 { 0x5b, 0, 0, 64, dtlb44_str}, 2115 { 0x52, 0, 0, 256, itlb424_str}, 2116 { 0x51, 0, 0, 128, itlb424_str}, 2117 { 0x50, 0, 0, 64, itlb424_str}, 2118 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2119 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2120 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2121 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2122 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2123 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2124 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2125 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2126 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2127 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2128 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2129 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2130 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2131 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2132 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2133 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2134 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2135 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2136 { 0x04, 4, 0, 8, dtlb4M_str}, 2137 { 0x03, 4, 0, 64, dtlb4k_str}, 2138 { 0x02, 4, 0, 2, itlb4M_str}, 2139 { 0x01, 4, 0, 32, itlb4k_str}, 2140 { 0 } 2141 }; 2142 2143 static const struct cachetab cyrix_ctab[] = { 2144 { 0x70, 4, 0, 32, "tlb-4K" }, 2145 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2146 { 0 } 2147 }; 2148 2149 /* 2150 * Search a cache table for a matching entry 2151 */ 2152 static const struct cachetab * 2153 find_cacheent(const struct cachetab *ct, uint_t code) 2154 { 2155 if (code != 0) { 2156 for (; ct->ct_code != 0; ct++) 2157 if (ct->ct_code <= code) 2158 break; 2159 if (ct->ct_code == code) 2160 return (ct); 2161 } 2162 return (NULL); 2163 } 2164 2165 /* 2166 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2167 * The walk is terminated if the walker returns non-zero. 2168 */ 2169 static void 2170 intel_walk_cacheinfo(struct cpuid_info *cpi, 2171 void *arg, int (*func)(void *, const struct cachetab *)) 2172 { 2173 const struct cachetab *ct; 2174 uint8_t *dp; 2175 int i; 2176 2177 if ((dp = cpi->cpi_cacheinfo) == NULL) 2178 return; 2179 for (i = 0; i < cpi->cpi_ncache; i++, dp++) 2180 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2181 if (func(arg, ct) != 0) 2182 break; 2183 } 2184 } 2185 2186 /* 2187 * (Like the Intel one, except for Cyrix CPUs) 2188 */ 2189 static void 2190 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2191 void *arg, int (*func)(void *, const struct cachetab *)) 2192 { 2193 const struct cachetab *ct; 2194 uint8_t *dp; 2195 int i; 2196 2197 if ((dp = cpi->cpi_cacheinfo) == NULL) 2198 return; 2199 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2200 /* 2201 * Search Cyrix-specific descriptor table first .. 2202 */ 2203 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2204 if (func(arg, ct) != 0) 2205 break; 2206 continue; 2207 } 2208 /* 2209 * .. else fall back to the Intel one 2210 */ 2211 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2212 if (func(arg, ct) != 0) 2213 break; 2214 continue; 2215 } 2216 } 2217 } 2218 2219 /* 2220 * A cacheinfo walker that adds associativity, line-size, and size properties 2221 * to the devinfo node it is passed as an argument. 2222 */ 2223 static int 2224 add_cacheent_props(void *arg, const struct cachetab *ct) 2225 { 2226 dev_info_t *devi = arg; 2227 2228 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2229 if (ct->ct_line_size != 0) 2230 add_cache_prop(devi, ct->ct_label, line_str, 2231 ct->ct_line_size); 2232 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2233 return (0); 2234 } 2235 2236 static const char fully_assoc[] = "fully-associative?"; 2237 2238 /* 2239 * AMD style cache/tlb description 2240 * 2241 * Extended functions 5 and 6 directly describe properties of 2242 * tlbs and various cache levels. 2243 */ 2244 static void 2245 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2246 { 2247 switch (assoc) { 2248 case 0: /* reserved; ignore */ 2249 break; 2250 default: 2251 add_cache_prop(devi, label, assoc_str, assoc); 2252 break; 2253 case 0xff: 2254 add_cache_prop(devi, label, fully_assoc, 1); 2255 break; 2256 } 2257 } 2258 2259 static void 2260 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2261 { 2262 if (size == 0) 2263 return; 2264 add_cache_prop(devi, label, size_str, size); 2265 add_amd_assoc(devi, label, assoc); 2266 } 2267 2268 static void 2269 add_amd_cache(dev_info_t *devi, const char *label, 2270 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2271 { 2272 if (size == 0 || line_size == 0) 2273 return; 2274 add_amd_assoc(devi, label, assoc); 2275 /* 2276 * Most AMD parts have a sectored cache. Multiple cache lines are 2277 * associated with each tag. A sector consists of all cache lines 2278 * associated with a tag. For example, the AMD K6-III has a sector 2279 * size of 2 cache lines per tag. 2280 */ 2281 if (lines_per_tag != 0) 2282 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2283 add_cache_prop(devi, label, line_str, line_size); 2284 add_cache_prop(devi, label, size_str, size * 1024); 2285 } 2286 2287 static void 2288 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2289 { 2290 switch (assoc) { 2291 case 0: /* off */ 2292 break; 2293 case 1: 2294 case 2: 2295 case 4: 2296 add_cache_prop(devi, label, assoc_str, assoc); 2297 break; 2298 case 6: 2299 add_cache_prop(devi, label, assoc_str, 8); 2300 break; 2301 case 8: 2302 add_cache_prop(devi, label, assoc_str, 16); 2303 break; 2304 case 0xf: 2305 add_cache_prop(devi, label, fully_assoc, 1); 2306 break; 2307 default: /* reserved; ignore */ 2308 break; 2309 } 2310 } 2311 2312 static void 2313 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2314 { 2315 if (size == 0 || assoc == 0) 2316 return; 2317 add_amd_l2_assoc(devi, label, assoc); 2318 add_cache_prop(devi, label, size_str, size); 2319 } 2320 2321 static void 2322 add_amd_l2_cache(dev_info_t *devi, const char *label, 2323 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2324 { 2325 if (size == 0 || assoc == 0 || line_size == 0) 2326 return; 2327 add_amd_l2_assoc(devi, label, assoc); 2328 if (lines_per_tag != 0) 2329 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2330 add_cache_prop(devi, label, line_str, line_size); 2331 add_cache_prop(devi, label, size_str, size * 1024); 2332 } 2333 2334 static void 2335 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 2336 { 2337 struct cpuid_regs *cp; 2338 2339 if (cpi->cpi_xmaxeax < 0x80000005) 2340 return; 2341 cp = &cpi->cpi_extd[5]; 2342 2343 /* 2344 * 4M/2M L1 TLB configuration 2345 * 2346 * We report the size for 2M pages because AMD uses two 2347 * TLB entries for one 4M page. 2348 */ 2349 add_amd_tlb(devi, "dtlb-2M", 2350 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 2351 add_amd_tlb(devi, "itlb-2M", 2352 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 2353 2354 /* 2355 * 4K L1 TLB configuration 2356 */ 2357 2358 switch (cpi->cpi_vendor) { 2359 uint_t nentries; 2360 case X86_VENDOR_TM: 2361 if (cpi->cpi_family >= 5) { 2362 /* 2363 * Crusoe processors have 256 TLB entries, but 2364 * cpuid data format constrains them to only 2365 * reporting 255 of them. 2366 */ 2367 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 2368 nentries = 256; 2369 /* 2370 * Crusoe processors also have a unified TLB 2371 */ 2372 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 2373 nentries); 2374 break; 2375 } 2376 /*FALLTHROUGH*/ 2377 default: 2378 add_amd_tlb(devi, itlb4k_str, 2379 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 2380 add_amd_tlb(devi, dtlb4k_str, 2381 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 2382 break; 2383 } 2384 2385 /* 2386 * data L1 cache configuration 2387 */ 2388 2389 add_amd_cache(devi, l1_dcache_str, 2390 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 2391 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 2392 2393 /* 2394 * code L1 cache configuration 2395 */ 2396 2397 add_amd_cache(devi, l1_icache_str, 2398 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 2399 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 2400 2401 if (cpi->cpi_xmaxeax < 0x80000006) 2402 return; 2403 cp = &cpi->cpi_extd[6]; 2404 2405 /* Check for a unified L2 TLB for large pages */ 2406 2407 if (BITX(cp->cp_eax, 31, 16) == 0) 2408 add_amd_l2_tlb(devi, "l2-tlb-2M", 2409 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2410 else { 2411 add_amd_l2_tlb(devi, "l2-dtlb-2M", 2412 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2413 add_amd_l2_tlb(devi, "l2-itlb-2M", 2414 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2415 } 2416 2417 /* Check for a unified L2 TLB for 4K pages */ 2418 2419 if (BITX(cp->cp_ebx, 31, 16) == 0) { 2420 add_amd_l2_tlb(devi, "l2-tlb-4K", 2421 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2422 } else { 2423 add_amd_l2_tlb(devi, "l2-dtlb-4K", 2424 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2425 add_amd_l2_tlb(devi, "l2-itlb-4K", 2426 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2427 } 2428 2429 add_amd_l2_cache(devi, l2_cache_str, 2430 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 2431 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 2432 } 2433 2434 /* 2435 * There are two basic ways that the x86 world describes it cache 2436 * and tlb architecture - Intel's way and AMD's way. 2437 * 2438 * Return which flavor of cache architecture we should use 2439 */ 2440 static int 2441 x86_which_cacheinfo(struct cpuid_info *cpi) 2442 { 2443 switch (cpi->cpi_vendor) { 2444 case X86_VENDOR_Intel: 2445 if (cpi->cpi_maxeax >= 2) 2446 return (X86_VENDOR_Intel); 2447 break; 2448 case X86_VENDOR_AMD: 2449 /* 2450 * The K5 model 1 was the first part from AMD that reported 2451 * cache sizes via extended cpuid functions. 2452 */ 2453 if (cpi->cpi_family > 5 || 2454 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 2455 return (X86_VENDOR_AMD); 2456 break; 2457 case X86_VENDOR_TM: 2458 if (cpi->cpi_family >= 5) 2459 return (X86_VENDOR_AMD); 2460 /*FALLTHROUGH*/ 2461 default: 2462 /* 2463 * If they have extended CPU data for 0x80000005 2464 * then we assume they have AMD-format cache 2465 * information. 2466 * 2467 * If not, and the vendor happens to be Cyrix, 2468 * then try our-Cyrix specific handler. 2469 * 2470 * If we're not Cyrix, then assume we're using Intel's 2471 * table-driven format instead. 2472 */ 2473 if (cpi->cpi_xmaxeax >= 0x80000005) 2474 return (X86_VENDOR_AMD); 2475 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 2476 return (X86_VENDOR_Cyrix); 2477 else if (cpi->cpi_maxeax >= 2) 2478 return (X86_VENDOR_Intel); 2479 break; 2480 } 2481 return (-1); 2482 } 2483 2484 /* 2485 * create a node for the given cpu under the prom root node. 2486 * Also, create a cpu node in the device tree. 2487 */ 2488 static dev_info_t *cpu_nex_devi = NULL; 2489 static kmutex_t cpu_node_lock; 2490 2491 /* 2492 * Called from post_startup() and mp_startup() 2493 */ 2494 void 2495 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 2496 { 2497 dev_info_t *cpu_devi; 2498 int create; 2499 2500 mutex_enter(&cpu_node_lock); 2501 2502 /* 2503 * create a nexus node for all cpus identified as 'cpu_id' under 2504 * the root node. 2505 */ 2506 if (cpu_nex_devi == NULL) { 2507 if (ndi_devi_alloc(ddi_root_node(), "cpus", 2508 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 2509 mutex_exit(&cpu_node_lock); 2510 return; 2511 } 2512 (void) ndi_devi_online(cpu_nex_devi, 0); 2513 } 2514 2515 /* 2516 * create a child node for cpu identified as 'cpu_id' 2517 */ 2518 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 2519 cpu_id); 2520 if (cpu_devi == NULL) { 2521 mutex_exit(&cpu_node_lock); 2522 return; 2523 } 2524 2525 /* device_type */ 2526 2527 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2528 "device_type", "cpu"); 2529 2530 /* reg */ 2531 2532 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2533 "reg", cpu_id); 2534 2535 /* cpu-mhz, and clock-frequency */ 2536 2537 if (cpu_freq > 0) { 2538 long long mul; 2539 2540 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2541 "cpu-mhz", cpu_freq); 2542 2543 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 2544 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2545 "clock-frequency", (int)mul); 2546 } 2547 2548 (void) ndi_devi_online(cpu_devi, 0); 2549 2550 if ((x86_feature & X86_CPUID) == 0) { 2551 mutex_exit(&cpu_node_lock); 2552 return; 2553 } 2554 2555 /* vendor-id */ 2556 2557 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2558 "vendor-id", cpi->cpi_vendorstr); 2559 2560 if (cpi->cpi_maxeax == 0) { 2561 mutex_exit(&cpu_node_lock); 2562 return; 2563 } 2564 2565 /* 2566 * family, model, and step 2567 */ 2568 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2569 "family", CPI_FAMILY(cpi)); 2570 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2571 "cpu-model", CPI_MODEL(cpi)); 2572 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2573 "stepping-id", CPI_STEP(cpi)); 2574 2575 /* type */ 2576 2577 switch (cpi->cpi_vendor) { 2578 case X86_VENDOR_Intel: 2579 create = 1; 2580 break; 2581 default: 2582 create = 0; 2583 break; 2584 } 2585 if (create) 2586 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2587 "type", CPI_TYPE(cpi)); 2588 2589 /* ext-family */ 2590 2591 switch (cpi->cpi_vendor) { 2592 case X86_VENDOR_Intel: 2593 case X86_VENDOR_AMD: 2594 create = cpi->cpi_family >= 0xf; 2595 break; 2596 default: 2597 create = 0; 2598 break; 2599 } 2600 if (create) 2601 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2602 "ext-family", CPI_FAMILY_XTD(cpi)); 2603 2604 /* ext-model */ 2605 2606 switch (cpi->cpi_vendor) { 2607 case X86_VENDOR_Intel: 2608 create = CPI_MODEL(cpi) == 0xf; 2609 break; 2610 case X86_VENDOR_AMD: 2611 create = CPI_FAMILY(cpi) == 0xf; 2612 break; 2613 default: 2614 create = 0; 2615 break; 2616 } 2617 if (create) 2618 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2619 "ext-model", CPI_MODEL_XTD(cpi)); 2620 2621 /* generation */ 2622 2623 switch (cpi->cpi_vendor) { 2624 case X86_VENDOR_AMD: 2625 /* 2626 * AMD K5 model 1 was the first part to support this 2627 */ 2628 create = cpi->cpi_xmaxeax >= 0x80000001; 2629 break; 2630 default: 2631 create = 0; 2632 break; 2633 } 2634 if (create) 2635 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2636 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 2637 2638 /* brand-id */ 2639 2640 switch (cpi->cpi_vendor) { 2641 case X86_VENDOR_Intel: 2642 /* 2643 * brand id first appeared on Pentium III Xeon model 8, 2644 * and Celeron model 8 processors and Opteron 2645 */ 2646 create = cpi->cpi_family > 6 || 2647 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 2648 break; 2649 case X86_VENDOR_AMD: 2650 create = cpi->cpi_family >= 0xf; 2651 break; 2652 default: 2653 create = 0; 2654 break; 2655 } 2656 if (create && cpi->cpi_brandid != 0) { 2657 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2658 "brand-id", cpi->cpi_brandid); 2659 } 2660 2661 /* chunks, and apic-id */ 2662 2663 switch (cpi->cpi_vendor) { 2664 /* 2665 * first available on Pentium IV and Opteron (K8) 2666 */ 2667 case X86_VENDOR_Intel: 2668 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 2669 break; 2670 case X86_VENDOR_AMD: 2671 create = cpi->cpi_family >= 0xf; 2672 break; 2673 default: 2674 create = 0; 2675 break; 2676 } 2677 if (create) { 2678 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2679 "chunks", CPI_CHUNKS(cpi)); 2680 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2681 "apic-id", CPI_APIC_ID(cpi)); 2682 if (cpi->cpi_chipid >= 0) { 2683 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2684 "chip#", cpi->cpi_chipid); 2685 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2686 "clog#", cpi->cpi_clogid); 2687 } 2688 } 2689 2690 /* cpuid-features */ 2691 2692 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2693 "cpuid-features", CPI_FEATURES_EDX(cpi)); 2694 2695 2696 /* cpuid-features-ecx */ 2697 2698 switch (cpi->cpi_vendor) { 2699 case X86_VENDOR_Intel: 2700 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 2701 break; 2702 default: 2703 create = 0; 2704 break; 2705 } 2706 if (create) 2707 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2708 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 2709 2710 /* ext-cpuid-features */ 2711 2712 switch (cpi->cpi_vendor) { 2713 case X86_VENDOR_Intel: 2714 case X86_VENDOR_AMD: 2715 case X86_VENDOR_Cyrix: 2716 case X86_VENDOR_TM: 2717 case X86_VENDOR_Centaur: 2718 create = cpi->cpi_xmaxeax >= 0x80000001; 2719 break; 2720 default: 2721 create = 0; 2722 break; 2723 } 2724 if (create) { 2725 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2726 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 2727 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2728 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 2729 } 2730 2731 /* 2732 * Brand String first appeared in Intel Pentium IV, AMD K5 2733 * model 1, and Cyrix GXm. On earlier models we try and 2734 * simulate something similar .. so this string should always 2735 * same -something- about the processor, however lame. 2736 */ 2737 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2738 "brand-string", cpi->cpi_brandstr); 2739 2740 /* 2741 * Finally, cache and tlb information 2742 */ 2743 switch (x86_which_cacheinfo(cpi)) { 2744 case X86_VENDOR_Intel: 2745 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 2746 break; 2747 case X86_VENDOR_Cyrix: 2748 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 2749 break; 2750 case X86_VENDOR_AMD: 2751 amd_cache_info(cpi, cpu_devi); 2752 break; 2753 default: 2754 break; 2755 } 2756 2757 mutex_exit(&cpu_node_lock); 2758 } 2759 2760 struct l2info { 2761 int *l2i_csz; 2762 int *l2i_lsz; 2763 int *l2i_assoc; 2764 int l2i_ret; 2765 }; 2766 2767 /* 2768 * A cacheinfo walker that fetches the size, line-size and associativity 2769 * of the L2 cache 2770 */ 2771 static int 2772 intel_l2cinfo(void *arg, const struct cachetab *ct) 2773 { 2774 struct l2info *l2i = arg; 2775 int *ip; 2776 2777 if (ct->ct_label != l2_cache_str && 2778 ct->ct_label != sl2_cache_str) 2779 return (0); /* not an L2 -- keep walking */ 2780 2781 if ((ip = l2i->l2i_csz) != NULL) 2782 *ip = ct->ct_size; 2783 if ((ip = l2i->l2i_lsz) != NULL) 2784 *ip = ct->ct_line_size; 2785 if ((ip = l2i->l2i_assoc) != NULL) 2786 *ip = ct->ct_assoc; 2787 l2i->l2i_ret = ct->ct_size; 2788 return (1); /* was an L2 -- terminate walk */ 2789 } 2790 2791 static void 2792 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 2793 { 2794 struct cpuid_regs *cp; 2795 uint_t size, assoc; 2796 int *ip; 2797 2798 if (cpi->cpi_xmaxeax < 0x80000006) 2799 return; 2800 cp = &cpi->cpi_extd[6]; 2801 2802 if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && 2803 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 2804 uint_t cachesz = size * 1024; 2805 2806 2807 if ((ip = l2i->l2i_csz) != NULL) 2808 *ip = cachesz; 2809 if ((ip = l2i->l2i_lsz) != NULL) 2810 *ip = BITX(cp->cp_ecx, 7, 0); 2811 if ((ip = l2i->l2i_assoc) != NULL) 2812 *ip = assoc; 2813 l2i->l2i_ret = cachesz; 2814 } 2815 } 2816 2817 int 2818 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 2819 { 2820 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2821 struct l2info __l2info, *l2i = &__l2info; 2822 2823 l2i->l2i_csz = csz; 2824 l2i->l2i_lsz = lsz; 2825 l2i->l2i_assoc = assoc; 2826 l2i->l2i_ret = -1; 2827 2828 switch (x86_which_cacheinfo(cpi)) { 2829 case X86_VENDOR_Intel: 2830 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 2831 break; 2832 case X86_VENDOR_Cyrix: 2833 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 2834 break; 2835 case X86_VENDOR_AMD: 2836 amd_l2cacheinfo(cpi, l2i); 2837 break; 2838 default: 2839 break; 2840 } 2841 return (l2i->l2i_ret); 2842 } 2843