1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Various routines to handle identification 28 * and classification of x86 processors. 29 */ 30 31 #include <sys/types.h> 32 #include <sys/archsystm.h> 33 #include <sys/x86_archext.h> 34 #include <sys/kmem.h> 35 #include <sys/systm.h> 36 #include <sys/cmn_err.h> 37 #include <sys/sunddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/cpuvar.h> 40 #include <sys/processor.h> 41 #include <sys/sysmacros.h> 42 #include <sys/pg.h> 43 #include <sys/fp.h> 44 #include <sys/controlregs.h> 45 #include <sys/auxv_386.h> 46 #include <sys/bitmap.h> 47 #include <sys/memnode.h> 48 49 #ifdef __xpv 50 #include <sys/hypervisor.h> 51 #endif 52 53 /* 54 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 55 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 56 * them accordingly. For most modern processors, feature detection occurs here 57 * in pass 1. 58 * 59 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 60 * for the boot CPU and does the basic analysis that the early kernel needs. 61 * x86_feature is set based on the return value of cpuid_pass1() of the boot 62 * CPU. 63 * 64 * Pass 1 includes: 65 * 66 * o Determining vendor/model/family/stepping and setting x86_type and 67 * x86_vendor accordingly. 68 * o Processing the feature flags returned by the cpuid instruction while 69 * applying any workarounds or tricks for the specific processor. 70 * o Mapping the feature flags into Solaris feature bits (X86_*). 71 * o Processing extended feature flags if supported by the processor, 72 * again while applying specific processor knowledge. 73 * o Determining the CMT characteristics of the system. 74 * 75 * Pass 1 is done on non-boot CPUs during their initialization and the results 76 * are used only as a meager attempt at ensuring that all processors within the 77 * system support the same features. 78 * 79 * Pass 2 of cpuid feature analysis happens just at the beginning 80 * of startup(). It just copies in and corrects the remainder 81 * of the cpuid data we depend on: standard cpuid functions that we didn't 82 * need for pass1 feature analysis, and extended cpuid functions beyond the 83 * simple feature processing done in pass1. 84 * 85 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 86 * particular kernel memory allocation has been made available. It creates a 87 * readable brand string based on the data collected in the first two passes. 88 * 89 * Pass 4 of cpuid analysis is invoked after post_startup() when all 90 * the support infrastructure for various hardware features has been 91 * initialized. It determines which processor features will be reported 92 * to userland via the aux vector. 93 * 94 * All passes are executed on all CPUs, but only the boot CPU determines what 95 * features the kernel will use. 96 * 97 * Much of the worst junk in this file is for the support of processors 98 * that didn't really implement the cpuid instruction properly. 99 * 100 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 101 * the pass numbers. Accordingly, changes to the pass code may require changes 102 * to the accessor code. 103 */ 104 105 uint_t x86_feature = 0; 106 uint_t x86_vendor = X86_VENDOR_IntelClone; 107 uint_t x86_type = X86_TYPE_OTHER; 108 uint_t x86_clflush_size = 0; 109 110 uint_t pentiumpro_bug4046376; 111 uint_t pentiumpro_bug4064495; 112 113 uint_t enable486; 114 115 /* 116 * monitor/mwait info. 117 * 118 * size_actual and buf_actual are the real address and size allocated to get 119 * proper mwait_buf alignement. buf_actual and size_actual should be passed 120 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 121 * processor cache-line alignment, but this is not guarantied in the furture. 122 */ 123 struct mwait_info { 124 size_t mon_min; /* min size to avoid missed wakeups */ 125 size_t mon_max; /* size to avoid false wakeups */ 126 size_t size_actual; /* size actually allocated */ 127 void *buf_actual; /* memory actually allocated */ 128 uint32_t support; /* processor support of monitor/mwait */ 129 }; 130 131 /* 132 * These constants determine how many of the elements of the 133 * cpuid we cache in the cpuid_info data structure; the 134 * remaining elements are accessible via the cpuid instruction. 135 */ 136 137 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 138 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 139 140 struct cpuid_info { 141 uint_t cpi_pass; /* last pass completed */ 142 /* 143 * standard function information 144 */ 145 uint_t cpi_maxeax; /* fn 0: %eax */ 146 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 147 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 148 149 uint_t cpi_family; /* fn 1: extended family */ 150 uint_t cpi_model; /* fn 1: extended model */ 151 uint_t cpi_step; /* fn 1: stepping */ 152 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 153 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 154 int cpi_clogid; /* fn 1: %ebx: thread # */ 155 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 156 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 157 uint_t cpi_ncache; /* fn 2: number of elements */ 158 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 159 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 160 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 161 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 162 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 163 /* 164 * extended function information 165 */ 166 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 167 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 168 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 169 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 170 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 171 id_t cpi_coreid; /* same coreid => strands share core */ 172 int cpi_pkgcoreid; /* core number within single package */ 173 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 174 /* Intel: fn 4: %eax[31-26] */ 175 /* 176 * supported feature information 177 */ 178 uint32_t cpi_support[5]; 179 #define STD_EDX_FEATURES 0 180 #define AMD_EDX_FEATURES 1 181 #define TM_EDX_FEATURES 2 182 #define STD_ECX_FEATURES 3 183 #define AMD_ECX_FEATURES 4 184 /* 185 * Synthesized information, where known. 186 */ 187 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 188 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 189 uint32_t cpi_socket; /* Chip package/socket type */ 190 191 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 192 uint32_t cpi_apicid; 193 }; 194 195 196 static struct cpuid_info cpuid_info0; 197 198 /* 199 * These bit fields are defined by the Intel Application Note AP-485 200 * "Intel Processor Identification and the CPUID Instruction" 201 */ 202 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 203 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 204 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 205 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 206 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 207 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 208 209 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 210 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 211 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 212 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 213 214 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 215 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 216 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 217 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 218 219 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 220 #define CPI_XMAXEAX_MAX 0x80000100 221 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 222 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 223 224 /* 225 * Function 4 (Deterministic Cache Parameters) macros 226 * Defined by Intel Application Note AP-485 227 */ 228 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 229 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 230 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 231 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 232 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 233 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 234 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 235 236 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 237 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 238 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 239 240 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 241 242 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 243 244 245 /* 246 * A couple of shorthand macros to identify "later" P6-family chips 247 * like the Pentium M and Core. First, the "older" P6-based stuff 248 * (loosely defined as "pre-Pentium-4"): 249 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 250 */ 251 252 #define IS_LEGACY_P6(cpi) ( \ 253 cpi->cpi_family == 6 && \ 254 (cpi->cpi_model == 1 || \ 255 cpi->cpi_model == 3 || \ 256 cpi->cpi_model == 5 || \ 257 cpi->cpi_model == 6 || \ 258 cpi->cpi_model == 7 || \ 259 cpi->cpi_model == 8 || \ 260 cpi->cpi_model == 0xA || \ 261 cpi->cpi_model == 0xB) \ 262 ) 263 264 /* A "new F6" is everything with family 6 that's not the above */ 265 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 266 267 /* Extended family/model support */ 268 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 269 cpi->cpi_family >= 0xf) 270 271 /* 272 * Info for monitor/mwait idle loop. 273 * 274 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 275 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 276 * 2006. 277 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 278 * Documentation Updates" #33633, Rev 2.05, December 2006. 279 */ 280 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 281 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 282 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 283 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 284 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 285 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 286 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 287 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 288 /* 289 * Number of sub-cstates for a given c-state. 290 */ 291 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 292 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 293 294 /* 295 * Functions we consune from cpuid_subr.c; don't publish these in a header 296 * file to try and keep people using the expected cpuid_* interfaces. 297 */ 298 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 299 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 300 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 301 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 302 303 /* 304 * Apply up various platform-dependent restrictions where the 305 * underlying platform restrictions mean the CPU can be marked 306 * as less capable than its cpuid instruction would imply. 307 */ 308 #if defined(__xpv) 309 static void 310 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 311 { 312 switch (eax) { 313 case 1: { 314 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 315 0 : CPUID_INTC_EDX_MCA; 316 cp->cp_edx &= 317 ~(mcamask | 318 CPUID_INTC_EDX_PSE | 319 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 320 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 321 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 322 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 323 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 324 break; 325 } 326 327 case 0x80000001: 328 cp->cp_edx &= 329 ~(CPUID_AMD_EDX_PSE | 330 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 331 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 332 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 333 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 334 CPUID_AMD_EDX_TSCP); 335 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 336 break; 337 default: 338 break; 339 } 340 341 switch (vendor) { 342 case X86_VENDOR_Intel: 343 switch (eax) { 344 case 4: 345 /* 346 * Zero out the (ncores-per-chip - 1) field 347 */ 348 cp->cp_eax &= 0x03fffffff; 349 break; 350 default: 351 break; 352 } 353 break; 354 case X86_VENDOR_AMD: 355 switch (eax) { 356 case 0x80000008: 357 /* 358 * Zero out the (ncores-per-chip - 1) field 359 */ 360 cp->cp_ecx &= 0xffffff00; 361 break; 362 default: 363 break; 364 } 365 break; 366 default: 367 break; 368 } 369 } 370 #else 371 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 372 #endif 373 374 /* 375 * Some undocumented ways of patching the results of the cpuid 376 * instruction to permit running Solaris 10 on future cpus that 377 * we don't currently support. Could be set to non-zero values 378 * via settings in eeprom. 379 */ 380 381 uint32_t cpuid_feature_ecx_include; 382 uint32_t cpuid_feature_ecx_exclude; 383 uint32_t cpuid_feature_edx_include; 384 uint32_t cpuid_feature_edx_exclude; 385 386 void 387 cpuid_alloc_space(cpu_t *cpu) 388 { 389 /* 390 * By convention, cpu0 is the boot cpu, which is set up 391 * before memory allocation is available. All other cpus get 392 * their cpuid_info struct allocated here. 393 */ 394 ASSERT(cpu->cpu_id != 0); 395 cpu->cpu_m.mcpu_cpi = 396 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 397 } 398 399 void 400 cpuid_free_space(cpu_t *cpu) 401 { 402 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 403 int i; 404 405 ASSERT(cpu->cpu_id != 0); 406 407 /* 408 * Free up any function 4 related dynamic storage 409 */ 410 for (i = 1; i < cpi->cpi_std_4_size; i++) 411 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 412 if (cpi->cpi_std_4_size > 0) 413 kmem_free(cpi->cpi_std_4, 414 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 415 416 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 417 } 418 419 #if !defined(__xpv) 420 421 static void 422 check_for_hvm() 423 { 424 struct cpuid_regs cp; 425 char *xen_str; 426 uint32_t xen_signature[4]; 427 extern int xpv_is_hvm; 428 429 /* 430 * In a fully virtualized domain, Xen's pseudo-cpuid function 431 * 0x40000000 returns a string representing the Xen signature in 432 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid 433 * function. 434 */ 435 cp.cp_eax = 0x40000000; 436 (void) __cpuid_insn(&cp); 437 xen_signature[0] = cp.cp_ebx; 438 xen_signature[1] = cp.cp_ecx; 439 xen_signature[2] = cp.cp_edx; 440 xen_signature[3] = 0; 441 xen_str = (char *)xen_signature; 442 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) 443 xpv_is_hvm = 1; 444 } 445 #endif /* __xpv */ 446 447 uint_t 448 cpuid_pass1(cpu_t *cpu) 449 { 450 uint32_t mask_ecx, mask_edx; 451 uint_t feature = X86_CPUID; 452 struct cpuid_info *cpi; 453 struct cpuid_regs *cp; 454 int xcpuid; 455 #if !defined(__xpv) 456 extern int idle_cpu_prefer_mwait; 457 #endif 458 459 /* 460 * Space statically allocated for cpu0, ensure pointer is set 461 */ 462 if (cpu->cpu_id == 0) 463 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 464 cpi = cpu->cpu_m.mcpu_cpi; 465 ASSERT(cpi != NULL); 466 cp = &cpi->cpi_std[0]; 467 cp->cp_eax = 0; 468 cpi->cpi_maxeax = __cpuid_insn(cp); 469 { 470 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 471 *iptr++ = cp->cp_ebx; 472 *iptr++ = cp->cp_edx; 473 *iptr++ = cp->cp_ecx; 474 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 475 } 476 477 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 478 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 479 480 /* 481 * Limit the range in case of weird hardware 482 */ 483 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 484 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 485 if (cpi->cpi_maxeax < 1) 486 goto pass1_done; 487 488 cp = &cpi->cpi_std[1]; 489 cp->cp_eax = 1; 490 (void) __cpuid_insn(cp); 491 492 /* 493 * Extract identifying constants for easy access. 494 */ 495 cpi->cpi_model = CPI_MODEL(cpi); 496 cpi->cpi_family = CPI_FAMILY(cpi); 497 498 if (cpi->cpi_family == 0xf) 499 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 500 501 /* 502 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 503 * Intel, and presumably everyone else, uses model == 0xf, as 504 * one would expect (max value means possible overflow). Sigh. 505 */ 506 507 switch (cpi->cpi_vendor) { 508 case X86_VENDOR_Intel: 509 if (IS_EXTENDED_MODEL_INTEL(cpi)) 510 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 511 break; 512 case X86_VENDOR_AMD: 513 if (CPI_FAMILY(cpi) == 0xf) 514 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 515 break; 516 default: 517 if (cpi->cpi_model == 0xf) 518 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 519 break; 520 } 521 522 cpi->cpi_step = CPI_STEP(cpi); 523 cpi->cpi_brandid = CPI_BRANDID(cpi); 524 525 /* 526 * *default* assumptions: 527 * - believe %edx feature word 528 * - ignore %ecx feature word 529 * - 32-bit virtual and physical addressing 530 */ 531 mask_edx = 0xffffffff; 532 mask_ecx = 0; 533 534 cpi->cpi_pabits = cpi->cpi_vabits = 32; 535 536 switch (cpi->cpi_vendor) { 537 case X86_VENDOR_Intel: 538 if (cpi->cpi_family == 5) 539 x86_type = X86_TYPE_P5; 540 else if (IS_LEGACY_P6(cpi)) { 541 x86_type = X86_TYPE_P6; 542 pentiumpro_bug4046376 = 1; 543 pentiumpro_bug4064495 = 1; 544 /* 545 * Clear the SEP bit when it was set erroneously 546 */ 547 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 548 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 549 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 550 x86_type = X86_TYPE_P4; 551 /* 552 * We don't currently depend on any of the %ecx 553 * features until Prescott, so we'll only check 554 * this from P4 onwards. We might want to revisit 555 * that idea later. 556 */ 557 mask_ecx = 0xffffffff; 558 } else if (cpi->cpi_family > 0xf) 559 mask_ecx = 0xffffffff; 560 /* 561 * We don't support MONITOR/MWAIT if leaf 5 is not available 562 * to obtain the monitor linesize. 563 */ 564 if (cpi->cpi_maxeax < 5) 565 mask_ecx &= ~CPUID_INTC_ECX_MON; 566 break; 567 case X86_VENDOR_IntelClone: 568 default: 569 break; 570 case X86_VENDOR_AMD: 571 #if defined(OPTERON_ERRATUM_108) 572 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 573 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 574 cpi->cpi_model = 0xc; 575 } else 576 #endif 577 if (cpi->cpi_family == 5) { 578 /* 579 * AMD K5 and K6 580 * 581 * These CPUs have an incomplete implementation 582 * of MCA/MCE which we mask away. 583 */ 584 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 585 586 /* 587 * Model 0 uses the wrong (APIC) bit 588 * to indicate PGE. Fix it here. 589 */ 590 if (cpi->cpi_model == 0) { 591 if (cp->cp_edx & 0x200) { 592 cp->cp_edx &= ~0x200; 593 cp->cp_edx |= CPUID_INTC_EDX_PGE; 594 } 595 } 596 597 /* 598 * Early models had problems w/ MMX; disable. 599 */ 600 if (cpi->cpi_model < 6) 601 mask_edx &= ~CPUID_INTC_EDX_MMX; 602 } 603 604 /* 605 * For newer families, SSE3 and CX16, at least, are valid; 606 * enable all 607 */ 608 if (cpi->cpi_family >= 0xf) 609 mask_ecx = 0xffffffff; 610 /* 611 * We don't support MONITOR/MWAIT if leaf 5 is not available 612 * to obtain the monitor linesize. 613 */ 614 if (cpi->cpi_maxeax < 5) 615 mask_ecx &= ~CPUID_INTC_ECX_MON; 616 617 #if !defined(__xpv) 618 /* 619 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 620 * processors. AMD does not intend MWAIT to be used in the cpu 621 * idle loop on current and future processors. 10h and future 622 * AMD processors use more power in MWAIT than HLT. 623 * Pre-family-10h Opterons do not have the MWAIT instruction. 624 */ 625 idle_cpu_prefer_mwait = 0; 626 #endif 627 628 break; 629 case X86_VENDOR_TM: 630 /* 631 * workaround the NT workaround in CMS 4.1 632 */ 633 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 634 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 635 cp->cp_edx |= CPUID_INTC_EDX_CX8; 636 break; 637 case X86_VENDOR_Centaur: 638 /* 639 * workaround the NT workarounds again 640 */ 641 if (cpi->cpi_family == 6) 642 cp->cp_edx |= CPUID_INTC_EDX_CX8; 643 break; 644 case X86_VENDOR_Cyrix: 645 /* 646 * We rely heavily on the probing in locore 647 * to actually figure out what parts, if any, 648 * of the Cyrix cpuid instruction to believe. 649 */ 650 switch (x86_type) { 651 case X86_TYPE_CYRIX_486: 652 mask_edx = 0; 653 break; 654 case X86_TYPE_CYRIX_6x86: 655 mask_edx = 0; 656 break; 657 case X86_TYPE_CYRIX_6x86L: 658 mask_edx = 659 CPUID_INTC_EDX_DE | 660 CPUID_INTC_EDX_CX8; 661 break; 662 case X86_TYPE_CYRIX_6x86MX: 663 mask_edx = 664 CPUID_INTC_EDX_DE | 665 CPUID_INTC_EDX_MSR | 666 CPUID_INTC_EDX_CX8 | 667 CPUID_INTC_EDX_PGE | 668 CPUID_INTC_EDX_CMOV | 669 CPUID_INTC_EDX_MMX; 670 break; 671 case X86_TYPE_CYRIX_GXm: 672 mask_edx = 673 CPUID_INTC_EDX_MSR | 674 CPUID_INTC_EDX_CX8 | 675 CPUID_INTC_EDX_CMOV | 676 CPUID_INTC_EDX_MMX; 677 break; 678 case X86_TYPE_CYRIX_MediaGX: 679 break; 680 case X86_TYPE_CYRIX_MII: 681 case X86_TYPE_VIA_CYRIX_III: 682 mask_edx = 683 CPUID_INTC_EDX_DE | 684 CPUID_INTC_EDX_TSC | 685 CPUID_INTC_EDX_MSR | 686 CPUID_INTC_EDX_CX8 | 687 CPUID_INTC_EDX_PGE | 688 CPUID_INTC_EDX_CMOV | 689 CPUID_INTC_EDX_MMX; 690 break; 691 default: 692 break; 693 } 694 break; 695 } 696 697 #if defined(__xpv) 698 /* 699 * Do not support MONITOR/MWAIT under a hypervisor 700 */ 701 mask_ecx &= ~CPUID_INTC_ECX_MON; 702 #endif /* __xpv */ 703 704 /* 705 * Now we've figured out the masks that determine 706 * which bits we choose to believe, apply the masks 707 * to the feature words, then map the kernel's view 708 * of these feature words into its feature word. 709 */ 710 cp->cp_edx &= mask_edx; 711 cp->cp_ecx &= mask_ecx; 712 713 /* 714 * apply any platform restrictions (we don't call this 715 * immediately after __cpuid_insn here, because we need the 716 * workarounds applied above first) 717 */ 718 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 719 720 /* 721 * fold in overrides from the "eeprom" mechanism 722 */ 723 cp->cp_edx |= cpuid_feature_edx_include; 724 cp->cp_edx &= ~cpuid_feature_edx_exclude; 725 726 cp->cp_ecx |= cpuid_feature_ecx_include; 727 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 728 729 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 730 feature |= X86_LARGEPAGE; 731 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 732 feature |= X86_TSC; 733 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 734 feature |= X86_MSR; 735 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 736 feature |= X86_MTRR; 737 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 738 feature |= X86_PGE; 739 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 740 feature |= X86_CMOV; 741 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 742 feature |= X86_MMX; 743 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 744 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 745 feature |= X86_MCA; 746 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 747 feature |= X86_PAE; 748 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 749 feature |= X86_CX8; 750 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 751 feature |= X86_CX16; 752 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 753 feature |= X86_PAT; 754 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 755 feature |= X86_SEP; 756 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 757 /* 758 * In our implementation, fxsave/fxrstor 759 * are prerequisites before we'll even 760 * try and do SSE things. 761 */ 762 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 763 feature |= X86_SSE; 764 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 765 feature |= X86_SSE2; 766 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 767 feature |= X86_SSE3; 768 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 769 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 770 feature |= X86_SSSE3; 771 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 772 feature |= X86_SSE4_1; 773 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 774 feature |= X86_SSE4_2; 775 } 776 } 777 if (cp->cp_edx & CPUID_INTC_EDX_DE) 778 feature |= X86_DE; 779 #if !defined(__xpv) 780 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 781 782 /* 783 * We require the CLFLUSH instruction for erratum workaround 784 * to use MONITOR/MWAIT. 785 */ 786 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 787 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 788 feature |= X86_MWAIT; 789 } else { 790 extern int idle_cpu_assert_cflush_monitor; 791 792 /* 793 * All processors we are aware of which have 794 * MONITOR/MWAIT also have CLFLUSH. 795 */ 796 if (idle_cpu_assert_cflush_monitor) { 797 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && 798 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); 799 } 800 } 801 } 802 #endif /* __xpv */ 803 804 /* 805 * Only need it first time, rest of the cpus would follow suite. 806 * we only capture this for the bootcpu. 807 */ 808 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 809 feature |= X86_CLFSH; 810 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 811 } 812 813 if (feature & X86_PAE) 814 cpi->cpi_pabits = 36; 815 816 /* 817 * Hyperthreading configuration is slightly tricky on Intel 818 * and pure clones, and even trickier on AMD. 819 * 820 * (AMD chose to set the HTT bit on their CMP processors, 821 * even though they're not actually hyperthreaded. Thus it 822 * takes a bit more work to figure out what's really going 823 * on ... see the handling of the CMP_LGCY bit below) 824 */ 825 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 826 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 827 if (cpi->cpi_ncpu_per_chip > 1) 828 feature |= X86_HTT; 829 } else { 830 cpi->cpi_ncpu_per_chip = 1; 831 } 832 833 /* 834 * Work on the "extended" feature information, doing 835 * some basic initialization for cpuid_pass2() 836 */ 837 xcpuid = 0; 838 switch (cpi->cpi_vendor) { 839 case X86_VENDOR_Intel: 840 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 841 xcpuid++; 842 break; 843 case X86_VENDOR_AMD: 844 if (cpi->cpi_family > 5 || 845 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 846 xcpuid++; 847 break; 848 case X86_VENDOR_Cyrix: 849 /* 850 * Only these Cyrix CPUs are -known- to support 851 * extended cpuid operations. 852 */ 853 if (x86_type == X86_TYPE_VIA_CYRIX_III || 854 x86_type == X86_TYPE_CYRIX_GXm) 855 xcpuid++; 856 break; 857 case X86_VENDOR_Centaur: 858 case X86_VENDOR_TM: 859 default: 860 xcpuid++; 861 break; 862 } 863 864 if (xcpuid) { 865 cp = &cpi->cpi_extd[0]; 866 cp->cp_eax = 0x80000000; 867 cpi->cpi_xmaxeax = __cpuid_insn(cp); 868 } 869 870 if (cpi->cpi_xmaxeax & 0x80000000) { 871 872 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 873 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 874 875 switch (cpi->cpi_vendor) { 876 case X86_VENDOR_Intel: 877 case X86_VENDOR_AMD: 878 if (cpi->cpi_xmaxeax < 0x80000001) 879 break; 880 cp = &cpi->cpi_extd[1]; 881 cp->cp_eax = 0x80000001; 882 (void) __cpuid_insn(cp); 883 884 if (cpi->cpi_vendor == X86_VENDOR_AMD && 885 cpi->cpi_family == 5 && 886 cpi->cpi_model == 6 && 887 cpi->cpi_step == 6) { 888 /* 889 * K6 model 6 uses bit 10 to indicate SYSC 890 * Later models use bit 11. Fix it here. 891 */ 892 if (cp->cp_edx & 0x400) { 893 cp->cp_edx &= ~0x400; 894 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 895 } 896 } 897 898 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 899 900 /* 901 * Compute the additions to the kernel's feature word. 902 */ 903 if (cp->cp_edx & CPUID_AMD_EDX_NX) 904 feature |= X86_NX; 905 906 /* 907 * Regardless whether or not we boot 64-bit, 908 * we should have a way to identify whether 909 * the CPU is capable of running 64-bit. 910 */ 911 if (cp->cp_edx & CPUID_AMD_EDX_LM) 912 feature |= X86_64; 913 914 #if defined(__amd64) 915 /* 1 GB large page - enable only for 64 bit kernel */ 916 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) 917 feature |= X86_1GPG; 918 #endif 919 920 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 921 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 922 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 923 feature |= X86_SSE4A; 924 925 /* 926 * If both the HTT and CMP_LGCY bits are set, 927 * then we're not actually HyperThreaded. Read 928 * "AMD CPUID Specification" for more details. 929 */ 930 if (cpi->cpi_vendor == X86_VENDOR_AMD && 931 (feature & X86_HTT) && 932 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 933 feature &= ~X86_HTT; 934 feature |= X86_CMP; 935 } 936 #if defined(__amd64) 937 /* 938 * It's really tricky to support syscall/sysret in 939 * the i386 kernel; we rely on sysenter/sysexit 940 * instead. In the amd64 kernel, things are -way- 941 * better. 942 */ 943 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 944 feature |= X86_ASYSC; 945 946 /* 947 * While we're thinking about system calls, note 948 * that AMD processors don't support sysenter 949 * in long mode at all, so don't try to program them. 950 */ 951 if (x86_vendor == X86_VENDOR_AMD) 952 feature &= ~X86_SEP; 953 #endif 954 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 955 feature |= X86_TSCP; 956 break; 957 default: 958 break; 959 } 960 961 /* 962 * Get CPUID data about processor cores and hyperthreads. 963 */ 964 switch (cpi->cpi_vendor) { 965 case X86_VENDOR_Intel: 966 if (cpi->cpi_maxeax >= 4) { 967 cp = &cpi->cpi_std[4]; 968 cp->cp_eax = 4; 969 cp->cp_ecx = 0; 970 (void) __cpuid_insn(cp); 971 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 972 } 973 /*FALLTHROUGH*/ 974 case X86_VENDOR_AMD: 975 if (cpi->cpi_xmaxeax < 0x80000008) 976 break; 977 cp = &cpi->cpi_extd[8]; 978 cp->cp_eax = 0x80000008; 979 (void) __cpuid_insn(cp); 980 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 981 982 /* 983 * Virtual and physical address limits from 984 * cpuid override previously guessed values. 985 */ 986 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 987 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 988 break; 989 default: 990 break; 991 } 992 993 /* 994 * Derive the number of cores per chip 995 */ 996 switch (cpi->cpi_vendor) { 997 case X86_VENDOR_Intel: 998 if (cpi->cpi_maxeax < 4) { 999 cpi->cpi_ncore_per_chip = 1; 1000 break; 1001 } else { 1002 cpi->cpi_ncore_per_chip = 1003 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1004 } 1005 break; 1006 case X86_VENDOR_AMD: 1007 if (cpi->cpi_xmaxeax < 0x80000008) { 1008 cpi->cpi_ncore_per_chip = 1; 1009 break; 1010 } else { 1011 /* 1012 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 1013 * 1 less than the number of physical cores on 1014 * the chip. In family 0x10 this value can 1015 * be affected by "downcoring" - it reflects 1016 * 1 less than the number of cores actually 1017 * enabled on this node. 1018 */ 1019 cpi->cpi_ncore_per_chip = 1020 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1021 } 1022 break; 1023 default: 1024 cpi->cpi_ncore_per_chip = 1; 1025 break; 1026 } 1027 } else { 1028 cpi->cpi_ncore_per_chip = 1; 1029 } 1030 1031 /* 1032 * If more than one core, then this processor is CMP. 1033 */ 1034 if (cpi->cpi_ncore_per_chip > 1) 1035 feature |= X86_CMP; 1036 1037 /* 1038 * If the number of cores is the same as the number 1039 * of CPUs, then we cannot have HyperThreading. 1040 */ 1041 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1042 feature &= ~X86_HTT; 1043 1044 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1045 /* 1046 * Single-core single-threaded processors. 1047 */ 1048 cpi->cpi_chipid = -1; 1049 cpi->cpi_clogid = 0; 1050 cpi->cpi_coreid = cpu->cpu_id; 1051 cpi->cpi_pkgcoreid = 0; 1052 } else if (cpi->cpi_ncpu_per_chip > 1) { 1053 uint_t i; 1054 uint_t chipid_shift = 0; 1055 uint_t coreid_shift = 0; 1056 uint_t apic_id = CPI_APIC_ID(cpi); 1057 1058 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1059 chipid_shift++; 1060 cpi->cpi_chipid = apic_id >> chipid_shift; 1061 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1062 1063 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1064 if (feature & X86_CMP) { 1065 /* 1066 * Multi-core (and possibly multi-threaded) 1067 * processors. 1068 */ 1069 uint_t ncpu_per_core; 1070 if (cpi->cpi_ncore_per_chip == 1) 1071 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1072 else if (cpi->cpi_ncore_per_chip > 1) 1073 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1074 cpi->cpi_ncore_per_chip; 1075 /* 1076 * 8bit APIC IDs on dual core Pentiums 1077 * look like this: 1078 * 1079 * +-----------------------+------+------+ 1080 * | Physical Package ID | MC | HT | 1081 * +-----------------------+------+------+ 1082 * <------- chipid --------> 1083 * <------- coreid ---------------> 1084 * <--- clogid --> 1085 * <------> 1086 * pkgcoreid 1087 * 1088 * Where the number of bits necessary to 1089 * represent MC and HT fields together equals 1090 * to the minimum number of bits necessary to 1091 * store the value of cpi->cpi_ncpu_per_chip. 1092 * Of those bits, the MC part uses the number 1093 * of bits necessary to store the value of 1094 * cpi->cpi_ncore_per_chip. 1095 */ 1096 for (i = 1; i < ncpu_per_core; i <<= 1) 1097 coreid_shift++; 1098 cpi->cpi_coreid = apic_id >> coreid_shift; 1099 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> 1100 coreid_shift; 1101 } else if (feature & X86_HTT) { 1102 /* 1103 * Single-core multi-threaded processors. 1104 */ 1105 cpi->cpi_coreid = cpi->cpi_chipid; 1106 cpi->cpi_pkgcoreid = 0; 1107 } 1108 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1109 /* 1110 * AMD CMP chips currently have a single thread per 1111 * core, with 2 cores on family 0xf and 2, 3 or 4 1112 * cores on family 0x10. 1113 * 1114 * Since no two cpus share a core we must assign a 1115 * distinct coreid per cpu, and we do this by using 1116 * the cpu_id. This scheme does not, however, 1117 * guarantee that sibling cores of a chip will have 1118 * sequential coreids starting at a multiple of the 1119 * number of cores per chip - that is usually the 1120 * case, but if the ACPI MADT table is presented 1121 * in a different order then we need to perform a 1122 * few more gymnastics for the pkgcoreid. 1123 * 1124 * In family 0xf CMPs there are 2 cores on all nodes 1125 * present - no mixing of single and dual core parts. 1126 * 1127 * In family 0x10 CMPs cpuid fn 2 ECX[15:12] 1128 * "ApicIdCoreIdSize[3:0]" tells us how 1129 * many least-significant bits in the ApicId 1130 * are used to represent the core number 1131 * within the node. Cores are always 1132 * numbered sequentially from 0 regardless 1133 * of how many or which are disabled, and 1134 * there seems to be no way to discover the 1135 * real core id when some are disabled. 1136 */ 1137 cpi->cpi_coreid = cpu->cpu_id; 1138 1139 if (cpi->cpi_family == 0x10 && 1140 cpi->cpi_xmaxeax >= 0x80000008) { 1141 int coreidsz = 1142 BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 1143 1144 cpi->cpi_pkgcoreid = 1145 apic_id & ((1 << coreidsz) - 1); 1146 } else { 1147 cpi->cpi_pkgcoreid = cpi->cpi_clogid; 1148 } 1149 } else { 1150 /* 1151 * All other processors are currently 1152 * assumed to have single cores. 1153 */ 1154 cpi->cpi_coreid = cpi->cpi_chipid; 1155 cpi->cpi_pkgcoreid = 0; 1156 } 1157 } 1158 1159 cpi->cpi_apicid = CPI_APIC_ID(cpi); 1160 1161 /* 1162 * Synthesize chip "revision" and socket type 1163 */ 1164 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1165 cpi->cpi_model, cpi->cpi_step); 1166 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1167 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1168 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1169 cpi->cpi_model, cpi->cpi_step); 1170 1171 pass1_done: 1172 #if !defined(__xpv) 1173 check_for_hvm(); 1174 #endif 1175 cpi->cpi_pass = 1; 1176 return (feature); 1177 } 1178 1179 /* 1180 * Make copies of the cpuid table entries we depend on, in 1181 * part for ease of parsing now, in part so that we have only 1182 * one place to correct any of it, in part for ease of 1183 * later export to userland, and in part so we can look at 1184 * this stuff in a crash dump. 1185 */ 1186 1187 /*ARGSUSED*/ 1188 void 1189 cpuid_pass2(cpu_t *cpu) 1190 { 1191 uint_t n, nmax; 1192 int i; 1193 struct cpuid_regs *cp; 1194 uint8_t *dp; 1195 uint32_t *iptr; 1196 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1197 1198 ASSERT(cpi->cpi_pass == 1); 1199 1200 if (cpi->cpi_maxeax < 1) 1201 goto pass2_done; 1202 1203 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1204 nmax = NMAX_CPI_STD; 1205 /* 1206 * (We already handled n == 0 and n == 1 in pass 1) 1207 */ 1208 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1209 cp->cp_eax = n; 1210 1211 /* 1212 * CPUID function 4 expects %ecx to be initialized 1213 * with an index which indicates which cache to return 1214 * information about. The OS is expected to call function 4 1215 * with %ecx set to 0, 1, 2, ... until it returns with 1216 * EAX[4:0] set to 0, which indicates there are no more 1217 * caches. 1218 * 1219 * Here, populate cpi_std[4] with the information returned by 1220 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1221 * when dynamic memory allocation becomes available. 1222 * 1223 * Note: we need to explicitly initialize %ecx here, since 1224 * function 4 may have been previously invoked. 1225 */ 1226 if (n == 4) 1227 cp->cp_ecx = 0; 1228 1229 (void) __cpuid_insn(cp); 1230 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1231 switch (n) { 1232 case 2: 1233 /* 1234 * "the lower 8 bits of the %eax register 1235 * contain a value that identifies the number 1236 * of times the cpuid [instruction] has to be 1237 * executed to obtain a complete image of the 1238 * processor's caching systems." 1239 * 1240 * How *do* they make this stuff up? 1241 */ 1242 cpi->cpi_ncache = sizeof (*cp) * 1243 BITX(cp->cp_eax, 7, 0); 1244 if (cpi->cpi_ncache == 0) 1245 break; 1246 cpi->cpi_ncache--; /* skip count byte */ 1247 1248 /* 1249 * Well, for now, rather than attempt to implement 1250 * this slightly dubious algorithm, we just look 1251 * at the first 15 .. 1252 */ 1253 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1254 cpi->cpi_ncache = sizeof (*cp) - 1; 1255 1256 dp = cpi->cpi_cacheinfo; 1257 if (BITX(cp->cp_eax, 31, 31) == 0) { 1258 uint8_t *p = (void *)&cp->cp_eax; 1259 for (i = 1; i < 4; i++) 1260 if (p[i] != 0) 1261 *dp++ = p[i]; 1262 } 1263 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1264 uint8_t *p = (void *)&cp->cp_ebx; 1265 for (i = 0; i < 4; i++) 1266 if (p[i] != 0) 1267 *dp++ = p[i]; 1268 } 1269 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1270 uint8_t *p = (void *)&cp->cp_ecx; 1271 for (i = 0; i < 4; i++) 1272 if (p[i] != 0) 1273 *dp++ = p[i]; 1274 } 1275 if (BITX(cp->cp_edx, 31, 31) == 0) { 1276 uint8_t *p = (void *)&cp->cp_edx; 1277 for (i = 0; i < 4; i++) 1278 if (p[i] != 0) 1279 *dp++ = p[i]; 1280 } 1281 break; 1282 1283 case 3: /* Processor serial number, if PSN supported */ 1284 break; 1285 1286 case 4: /* Deterministic cache parameters */ 1287 break; 1288 1289 case 5: /* Monitor/Mwait parameters */ 1290 { 1291 size_t mwait_size; 1292 1293 /* 1294 * check cpi_mwait.support which was set in cpuid_pass1 1295 */ 1296 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1297 break; 1298 1299 /* 1300 * Protect ourself from insane mwait line size. 1301 * Workaround for incomplete hardware emulator(s). 1302 */ 1303 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1304 if (mwait_size < sizeof (uint32_t) || 1305 !ISP2(mwait_size)) { 1306 #if DEBUG 1307 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1308 "size %ld", cpu->cpu_id, (long)mwait_size); 1309 #endif 1310 break; 1311 } 1312 1313 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1314 cpi->cpi_mwait.mon_max = mwait_size; 1315 if (MWAIT_EXTENSION(cpi)) { 1316 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1317 if (MWAIT_INT_ENABLE(cpi)) 1318 cpi->cpi_mwait.support |= 1319 MWAIT_ECX_INT_ENABLE; 1320 } 1321 break; 1322 } 1323 default: 1324 break; 1325 } 1326 } 1327 1328 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 1329 struct cpuid_regs regs; 1330 1331 cp = ®s; 1332 cp->cp_eax = 0xB; 1333 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1334 1335 (void) __cpuid_insn(cp); 1336 1337 /* 1338 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1339 * indicates that the extended topology enumeration leaf is 1340 * available. 1341 */ 1342 if (cp->cp_ebx) { 1343 uint32_t x2apic_id; 1344 uint_t coreid_shift = 0; 1345 uint_t ncpu_per_core = 1; 1346 uint_t chipid_shift = 0; 1347 uint_t ncpu_per_chip = 1; 1348 uint_t i; 1349 uint_t level; 1350 1351 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1352 cp->cp_eax = 0xB; 1353 cp->cp_ecx = i; 1354 1355 (void) __cpuid_insn(cp); 1356 level = CPI_CPU_LEVEL_TYPE(cp); 1357 1358 if (level == 1) { 1359 x2apic_id = cp->cp_edx; 1360 coreid_shift = BITX(cp->cp_eax, 4, 0); 1361 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1362 } else if (level == 2) { 1363 x2apic_id = cp->cp_edx; 1364 chipid_shift = BITX(cp->cp_eax, 4, 0); 1365 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1366 } 1367 } 1368 1369 cpi->cpi_apicid = x2apic_id; 1370 cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1371 cpi->cpi_ncore_per_chip = ncpu_per_chip / 1372 ncpu_per_core; 1373 cpi->cpi_chipid = x2apic_id >> chipid_shift; 1374 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1375 cpi->cpi_coreid = x2apic_id >> coreid_shift; 1376 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1377 } 1378 1379 /* Make cp NULL so that we don't stumble on others */ 1380 cp = NULL; 1381 } 1382 1383 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1384 goto pass2_done; 1385 1386 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1387 nmax = NMAX_CPI_EXTD; 1388 /* 1389 * Copy the extended properties, fixing them as we go. 1390 * (We already handled n == 0 and n == 1 in pass 1) 1391 */ 1392 iptr = (void *)cpi->cpi_brandstr; 1393 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1394 cp->cp_eax = 0x80000000 + n; 1395 (void) __cpuid_insn(cp); 1396 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1397 switch (n) { 1398 case 2: 1399 case 3: 1400 case 4: 1401 /* 1402 * Extract the brand string 1403 */ 1404 *iptr++ = cp->cp_eax; 1405 *iptr++ = cp->cp_ebx; 1406 *iptr++ = cp->cp_ecx; 1407 *iptr++ = cp->cp_edx; 1408 break; 1409 case 5: 1410 switch (cpi->cpi_vendor) { 1411 case X86_VENDOR_AMD: 1412 /* 1413 * The Athlon and Duron were the first 1414 * parts to report the sizes of the 1415 * TLB for large pages. Before then, 1416 * we don't trust the data. 1417 */ 1418 if (cpi->cpi_family < 6 || 1419 (cpi->cpi_family == 6 && 1420 cpi->cpi_model < 1)) 1421 cp->cp_eax = 0; 1422 break; 1423 default: 1424 break; 1425 } 1426 break; 1427 case 6: 1428 switch (cpi->cpi_vendor) { 1429 case X86_VENDOR_AMD: 1430 /* 1431 * The Athlon and Duron were the first 1432 * AMD parts with L2 TLB's. 1433 * Before then, don't trust the data. 1434 */ 1435 if (cpi->cpi_family < 6 || 1436 cpi->cpi_family == 6 && 1437 cpi->cpi_model < 1) 1438 cp->cp_eax = cp->cp_ebx = 0; 1439 /* 1440 * AMD Duron rev A0 reports L2 1441 * cache size incorrectly as 1K 1442 * when it is really 64K 1443 */ 1444 if (cpi->cpi_family == 6 && 1445 cpi->cpi_model == 3 && 1446 cpi->cpi_step == 0) { 1447 cp->cp_ecx &= 0xffff; 1448 cp->cp_ecx |= 0x400000; 1449 } 1450 break; 1451 case X86_VENDOR_Cyrix: /* VIA C3 */ 1452 /* 1453 * VIA C3 processors are a bit messed 1454 * up w.r.t. encoding cache sizes in %ecx 1455 */ 1456 if (cpi->cpi_family != 6) 1457 break; 1458 /* 1459 * model 7 and 8 were incorrectly encoded 1460 * 1461 * xxx is model 8 really broken? 1462 */ 1463 if (cpi->cpi_model == 7 || 1464 cpi->cpi_model == 8) 1465 cp->cp_ecx = 1466 BITX(cp->cp_ecx, 31, 24) << 16 | 1467 BITX(cp->cp_ecx, 23, 16) << 12 | 1468 BITX(cp->cp_ecx, 15, 8) << 8 | 1469 BITX(cp->cp_ecx, 7, 0); 1470 /* 1471 * model 9 stepping 1 has wrong associativity 1472 */ 1473 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1474 cp->cp_ecx |= 8 << 12; 1475 break; 1476 case X86_VENDOR_Intel: 1477 /* 1478 * Extended L2 Cache features function. 1479 * First appeared on Prescott. 1480 */ 1481 default: 1482 break; 1483 } 1484 break; 1485 default: 1486 break; 1487 } 1488 } 1489 1490 pass2_done: 1491 cpi->cpi_pass = 2; 1492 } 1493 1494 static const char * 1495 intel_cpubrand(const struct cpuid_info *cpi) 1496 { 1497 int i; 1498 1499 if ((x86_feature & X86_CPUID) == 0 || 1500 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1501 return ("i486"); 1502 1503 switch (cpi->cpi_family) { 1504 case 5: 1505 return ("Intel Pentium(r)"); 1506 case 6: 1507 switch (cpi->cpi_model) { 1508 uint_t celeron, xeon; 1509 const struct cpuid_regs *cp; 1510 case 0: 1511 case 1: 1512 case 2: 1513 return ("Intel Pentium(r) Pro"); 1514 case 3: 1515 case 4: 1516 return ("Intel Pentium(r) II"); 1517 case 6: 1518 return ("Intel Celeron(r)"); 1519 case 5: 1520 case 7: 1521 celeron = xeon = 0; 1522 cp = &cpi->cpi_std[2]; /* cache info */ 1523 1524 for (i = 1; i < 4; i++) { 1525 uint_t tmp; 1526 1527 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1528 if (tmp == 0x40) 1529 celeron++; 1530 if (tmp >= 0x44 && tmp <= 0x45) 1531 xeon++; 1532 } 1533 1534 for (i = 0; i < 2; i++) { 1535 uint_t tmp; 1536 1537 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1538 if (tmp == 0x40) 1539 celeron++; 1540 else if (tmp >= 0x44 && tmp <= 0x45) 1541 xeon++; 1542 } 1543 1544 for (i = 0; i < 4; i++) { 1545 uint_t tmp; 1546 1547 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1548 if (tmp == 0x40) 1549 celeron++; 1550 else if (tmp >= 0x44 && tmp <= 0x45) 1551 xeon++; 1552 } 1553 1554 for (i = 0; i < 4; i++) { 1555 uint_t tmp; 1556 1557 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1558 if (tmp == 0x40) 1559 celeron++; 1560 else if (tmp >= 0x44 && tmp <= 0x45) 1561 xeon++; 1562 } 1563 1564 if (celeron) 1565 return ("Intel Celeron(r)"); 1566 if (xeon) 1567 return (cpi->cpi_model == 5 ? 1568 "Intel Pentium(r) II Xeon(tm)" : 1569 "Intel Pentium(r) III Xeon(tm)"); 1570 return (cpi->cpi_model == 5 ? 1571 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1572 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1573 default: 1574 break; 1575 } 1576 default: 1577 break; 1578 } 1579 1580 /* BrandID is present if the field is nonzero */ 1581 if (cpi->cpi_brandid != 0) { 1582 static const struct { 1583 uint_t bt_bid; 1584 const char *bt_str; 1585 } brand_tbl[] = { 1586 { 0x1, "Intel(r) Celeron(r)" }, 1587 { 0x2, "Intel(r) Pentium(r) III" }, 1588 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1589 { 0x4, "Intel(r) Pentium(r) III" }, 1590 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1591 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1592 { 0x8, "Intel(r) Pentium(r) 4" }, 1593 { 0x9, "Intel(r) Pentium(r) 4" }, 1594 { 0xa, "Intel(r) Celeron(r)" }, 1595 { 0xb, "Intel(r) Xeon(tm)" }, 1596 { 0xc, "Intel(r) Xeon(tm) MP" }, 1597 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1598 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1599 { 0x11, "Mobile Genuine Intel(r)" }, 1600 { 0x12, "Intel(r) Celeron(r) M" }, 1601 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1602 { 0x14, "Intel(r) Celeron(r)" }, 1603 { 0x15, "Mobile Genuine Intel(r)" }, 1604 { 0x16, "Intel(r) Pentium(r) M" }, 1605 { 0x17, "Mobile Intel(r) Celeron(r)" } 1606 }; 1607 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1608 uint_t sgn; 1609 1610 sgn = (cpi->cpi_family << 8) | 1611 (cpi->cpi_model << 4) | cpi->cpi_step; 1612 1613 for (i = 0; i < btblmax; i++) 1614 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1615 break; 1616 if (i < btblmax) { 1617 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1618 return ("Intel(r) Celeron(r)"); 1619 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1620 return ("Intel(r) Xeon(tm) MP"); 1621 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1622 return ("Intel(r) Xeon(tm)"); 1623 return (brand_tbl[i].bt_str); 1624 } 1625 } 1626 1627 return (NULL); 1628 } 1629 1630 static const char * 1631 amd_cpubrand(const struct cpuid_info *cpi) 1632 { 1633 if ((x86_feature & X86_CPUID) == 0 || 1634 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1635 return ("i486 compatible"); 1636 1637 switch (cpi->cpi_family) { 1638 case 5: 1639 switch (cpi->cpi_model) { 1640 case 0: 1641 case 1: 1642 case 2: 1643 case 3: 1644 case 4: 1645 case 5: 1646 return ("AMD-K5(r)"); 1647 case 6: 1648 case 7: 1649 return ("AMD-K6(r)"); 1650 case 8: 1651 return ("AMD-K6(r)-2"); 1652 case 9: 1653 return ("AMD-K6(r)-III"); 1654 default: 1655 return ("AMD (family 5)"); 1656 } 1657 case 6: 1658 switch (cpi->cpi_model) { 1659 case 1: 1660 return ("AMD-K7(tm)"); 1661 case 0: 1662 case 2: 1663 case 4: 1664 return ("AMD Athlon(tm)"); 1665 case 3: 1666 case 7: 1667 return ("AMD Duron(tm)"); 1668 case 6: 1669 case 8: 1670 case 10: 1671 /* 1672 * Use the L2 cache size to distinguish 1673 */ 1674 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1675 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1676 default: 1677 return ("AMD (family 6)"); 1678 } 1679 default: 1680 break; 1681 } 1682 1683 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1684 cpi->cpi_brandid != 0) { 1685 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1686 case 3: 1687 return ("AMD Opteron(tm) UP 1xx"); 1688 case 4: 1689 return ("AMD Opteron(tm) DP 2xx"); 1690 case 5: 1691 return ("AMD Opteron(tm) MP 8xx"); 1692 default: 1693 return ("AMD Opteron(tm)"); 1694 } 1695 } 1696 1697 return (NULL); 1698 } 1699 1700 static const char * 1701 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1702 { 1703 if ((x86_feature & X86_CPUID) == 0 || 1704 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1705 type == X86_TYPE_CYRIX_486) 1706 return ("i486 compatible"); 1707 1708 switch (type) { 1709 case X86_TYPE_CYRIX_6x86: 1710 return ("Cyrix 6x86"); 1711 case X86_TYPE_CYRIX_6x86L: 1712 return ("Cyrix 6x86L"); 1713 case X86_TYPE_CYRIX_6x86MX: 1714 return ("Cyrix 6x86MX"); 1715 case X86_TYPE_CYRIX_GXm: 1716 return ("Cyrix GXm"); 1717 case X86_TYPE_CYRIX_MediaGX: 1718 return ("Cyrix MediaGX"); 1719 case X86_TYPE_CYRIX_MII: 1720 return ("Cyrix M2"); 1721 case X86_TYPE_VIA_CYRIX_III: 1722 return ("VIA Cyrix M3"); 1723 default: 1724 /* 1725 * Have another wild guess .. 1726 */ 1727 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1728 return ("Cyrix 5x86"); 1729 else if (cpi->cpi_family == 5) { 1730 switch (cpi->cpi_model) { 1731 case 2: 1732 return ("Cyrix 6x86"); /* Cyrix M1 */ 1733 case 4: 1734 return ("Cyrix MediaGX"); 1735 default: 1736 break; 1737 } 1738 } else if (cpi->cpi_family == 6) { 1739 switch (cpi->cpi_model) { 1740 case 0: 1741 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1742 case 5: 1743 case 6: 1744 case 7: 1745 case 8: 1746 case 9: 1747 return ("VIA C3"); 1748 default: 1749 break; 1750 } 1751 } 1752 break; 1753 } 1754 return (NULL); 1755 } 1756 1757 /* 1758 * This only gets called in the case that the CPU extended 1759 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1760 * aren't available, or contain null bytes for some reason. 1761 */ 1762 static void 1763 fabricate_brandstr(struct cpuid_info *cpi) 1764 { 1765 const char *brand = NULL; 1766 1767 switch (cpi->cpi_vendor) { 1768 case X86_VENDOR_Intel: 1769 brand = intel_cpubrand(cpi); 1770 break; 1771 case X86_VENDOR_AMD: 1772 brand = amd_cpubrand(cpi); 1773 break; 1774 case X86_VENDOR_Cyrix: 1775 brand = cyrix_cpubrand(cpi, x86_type); 1776 break; 1777 case X86_VENDOR_NexGen: 1778 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1779 brand = "NexGen Nx586"; 1780 break; 1781 case X86_VENDOR_Centaur: 1782 if (cpi->cpi_family == 5) 1783 switch (cpi->cpi_model) { 1784 case 4: 1785 brand = "Centaur C6"; 1786 break; 1787 case 8: 1788 brand = "Centaur C2"; 1789 break; 1790 case 9: 1791 brand = "Centaur C3"; 1792 break; 1793 default: 1794 break; 1795 } 1796 break; 1797 case X86_VENDOR_Rise: 1798 if (cpi->cpi_family == 5 && 1799 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1800 brand = "Rise mP6"; 1801 break; 1802 case X86_VENDOR_SiS: 1803 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1804 brand = "SiS 55x"; 1805 break; 1806 case X86_VENDOR_TM: 1807 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1808 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1809 break; 1810 case X86_VENDOR_NSC: 1811 case X86_VENDOR_UMC: 1812 default: 1813 break; 1814 } 1815 if (brand) { 1816 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1817 return; 1818 } 1819 1820 /* 1821 * If all else fails ... 1822 */ 1823 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1824 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1825 cpi->cpi_model, cpi->cpi_step); 1826 } 1827 1828 /* 1829 * This routine is called just after kernel memory allocation 1830 * becomes available on cpu0, and as part of mp_startup() on 1831 * the other cpus. 1832 * 1833 * Fixup the brand string, and collect any information from cpuid 1834 * that requires dynamicically allocated storage to represent. 1835 */ 1836 /*ARGSUSED*/ 1837 void 1838 cpuid_pass3(cpu_t *cpu) 1839 { 1840 int i, max, shft, level, size; 1841 struct cpuid_regs regs; 1842 struct cpuid_regs *cp; 1843 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1844 1845 ASSERT(cpi->cpi_pass == 2); 1846 1847 /* 1848 * Function 4: Deterministic cache parameters 1849 * 1850 * Take this opportunity to detect the number of threads 1851 * sharing the last level cache, and construct a corresponding 1852 * cache id. The respective cpuid_info members are initialized 1853 * to the default case of "no last level cache sharing". 1854 */ 1855 cpi->cpi_ncpu_shr_last_cache = 1; 1856 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1857 1858 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1859 1860 /* 1861 * Find the # of elements (size) returned by fn 4, and along 1862 * the way detect last level cache sharing details. 1863 */ 1864 bzero(®s, sizeof (regs)); 1865 cp = ®s; 1866 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1867 cp->cp_eax = 4; 1868 cp->cp_ecx = i; 1869 1870 (void) __cpuid_insn(cp); 1871 1872 if (CPI_CACHE_TYPE(cp) == 0) 1873 break; 1874 level = CPI_CACHE_LVL(cp); 1875 if (level > max) { 1876 max = level; 1877 cpi->cpi_ncpu_shr_last_cache = 1878 CPI_NTHR_SHR_CACHE(cp) + 1; 1879 } 1880 } 1881 cpi->cpi_std_4_size = size = i; 1882 1883 /* 1884 * Allocate the cpi_std_4 array. The first element 1885 * references the regs for fn 4, %ecx == 0, which 1886 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1887 */ 1888 if (size > 0) { 1889 cpi->cpi_std_4 = 1890 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1891 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1892 1893 /* 1894 * Allocate storage to hold the additional regs 1895 * for function 4, %ecx == 1 .. cpi_std_4_size. 1896 * 1897 * The regs for fn 4, %ecx == 0 has already 1898 * been allocated as indicated above. 1899 */ 1900 for (i = 1; i < size; i++) { 1901 cp = cpi->cpi_std_4[i] = 1902 kmem_zalloc(sizeof (regs), KM_SLEEP); 1903 cp->cp_eax = 4; 1904 cp->cp_ecx = i; 1905 1906 (void) __cpuid_insn(cp); 1907 } 1908 } 1909 /* 1910 * Determine the number of bits needed to represent 1911 * the number of CPUs sharing the last level cache. 1912 * 1913 * Shift off that number of bits from the APIC id to 1914 * derive the cache id. 1915 */ 1916 shft = 0; 1917 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1918 shft++; 1919 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 1920 } 1921 1922 /* 1923 * Now fixup the brand string 1924 */ 1925 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1926 fabricate_brandstr(cpi); 1927 } else { 1928 1929 /* 1930 * If we successfully extracted a brand string from the cpuid 1931 * instruction, clean it up by removing leading spaces and 1932 * similar junk. 1933 */ 1934 if (cpi->cpi_brandstr[0]) { 1935 size_t maxlen = sizeof (cpi->cpi_brandstr); 1936 char *src, *dst; 1937 1938 dst = src = (char *)cpi->cpi_brandstr; 1939 src[maxlen - 1] = '\0'; 1940 /* 1941 * strip leading spaces 1942 */ 1943 while (*src == ' ') 1944 src++; 1945 /* 1946 * Remove any 'Genuine' or "Authentic" prefixes 1947 */ 1948 if (strncmp(src, "Genuine ", 8) == 0) 1949 src += 8; 1950 if (strncmp(src, "Authentic ", 10) == 0) 1951 src += 10; 1952 1953 /* 1954 * Now do an in-place copy. 1955 * Map (R) to (r) and (TM) to (tm). 1956 * The era of teletypes is long gone, and there's 1957 * -really- no need to shout. 1958 */ 1959 while (*src != '\0') { 1960 if (src[0] == '(') { 1961 if (strncmp(src + 1, "R)", 2) == 0) { 1962 (void) strncpy(dst, "(r)", 3); 1963 src += 3; 1964 dst += 3; 1965 continue; 1966 } 1967 if (strncmp(src + 1, "TM)", 3) == 0) { 1968 (void) strncpy(dst, "(tm)", 4); 1969 src += 4; 1970 dst += 4; 1971 continue; 1972 } 1973 } 1974 *dst++ = *src++; 1975 } 1976 *dst = '\0'; 1977 1978 /* 1979 * Finally, remove any trailing spaces 1980 */ 1981 while (--dst > cpi->cpi_brandstr) 1982 if (*dst == ' ') 1983 *dst = '\0'; 1984 else 1985 break; 1986 } else 1987 fabricate_brandstr(cpi); 1988 } 1989 cpi->cpi_pass = 3; 1990 } 1991 1992 /* 1993 * This routine is called out of bind_hwcap() much later in the life 1994 * of the kernel (post_startup()). The job of this routine is to resolve 1995 * the hardware feature support and kernel support for those features into 1996 * what we're actually going to tell applications via the aux vector. 1997 */ 1998 uint_t 1999 cpuid_pass4(cpu_t *cpu) 2000 { 2001 struct cpuid_info *cpi; 2002 uint_t hwcap_flags = 0; 2003 2004 if (cpu == NULL) 2005 cpu = CPU; 2006 cpi = cpu->cpu_m.mcpu_cpi; 2007 2008 ASSERT(cpi->cpi_pass == 3); 2009 2010 if (cpi->cpi_maxeax >= 1) { 2011 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2012 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2013 2014 *edx = CPI_FEATURES_EDX(cpi); 2015 *ecx = CPI_FEATURES_ECX(cpi); 2016 2017 /* 2018 * [these require explicit kernel support] 2019 */ 2020 if ((x86_feature & X86_SEP) == 0) 2021 *edx &= ~CPUID_INTC_EDX_SEP; 2022 2023 if ((x86_feature & X86_SSE) == 0) 2024 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2025 if ((x86_feature & X86_SSE2) == 0) 2026 *edx &= ~CPUID_INTC_EDX_SSE2; 2027 2028 if ((x86_feature & X86_HTT) == 0) 2029 *edx &= ~CPUID_INTC_EDX_HTT; 2030 2031 if ((x86_feature & X86_SSE3) == 0) 2032 *ecx &= ~CPUID_INTC_ECX_SSE3; 2033 2034 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2035 if ((x86_feature & X86_SSSE3) == 0) 2036 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2037 if ((x86_feature & X86_SSE4_1) == 0) 2038 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2039 if ((x86_feature & X86_SSE4_2) == 0) 2040 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2041 } 2042 2043 /* 2044 * [no explicit support required beyond x87 fp context] 2045 */ 2046 if (!fpu_exists) 2047 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2048 2049 /* 2050 * Now map the supported feature vector to things that we 2051 * think userland will care about. 2052 */ 2053 if (*edx & CPUID_INTC_EDX_SEP) 2054 hwcap_flags |= AV_386_SEP; 2055 if (*edx & CPUID_INTC_EDX_SSE) 2056 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2057 if (*edx & CPUID_INTC_EDX_SSE2) 2058 hwcap_flags |= AV_386_SSE2; 2059 if (*ecx & CPUID_INTC_ECX_SSE3) 2060 hwcap_flags |= AV_386_SSE3; 2061 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2062 if (*ecx & CPUID_INTC_ECX_SSSE3) 2063 hwcap_flags |= AV_386_SSSE3; 2064 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2065 hwcap_flags |= AV_386_SSE4_1; 2066 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2067 hwcap_flags |= AV_386_SSE4_2; 2068 } 2069 if (*ecx & CPUID_INTC_ECX_POPCNT) 2070 hwcap_flags |= AV_386_POPCNT; 2071 if (*edx & CPUID_INTC_EDX_FPU) 2072 hwcap_flags |= AV_386_FPU; 2073 if (*edx & CPUID_INTC_EDX_MMX) 2074 hwcap_flags |= AV_386_MMX; 2075 2076 if (*edx & CPUID_INTC_EDX_TSC) 2077 hwcap_flags |= AV_386_TSC; 2078 if (*edx & CPUID_INTC_EDX_CX8) 2079 hwcap_flags |= AV_386_CX8; 2080 if (*edx & CPUID_INTC_EDX_CMOV) 2081 hwcap_flags |= AV_386_CMOV; 2082 if (*ecx & CPUID_INTC_ECX_MON) 2083 hwcap_flags |= AV_386_MON; 2084 if (*ecx & CPUID_INTC_ECX_CX16) 2085 hwcap_flags |= AV_386_CX16; 2086 } 2087 2088 if (x86_feature & X86_HTT) 2089 hwcap_flags |= AV_386_PAUSE; 2090 2091 if (cpi->cpi_xmaxeax < 0x80000001) 2092 goto pass4_done; 2093 2094 switch (cpi->cpi_vendor) { 2095 struct cpuid_regs cp; 2096 uint32_t *edx, *ecx; 2097 2098 case X86_VENDOR_Intel: 2099 /* 2100 * Seems like Intel duplicated what we necessary 2101 * here to make the initial crop of 64-bit OS's work. 2102 * Hopefully, those are the only "extended" bits 2103 * they'll add. 2104 */ 2105 /*FALLTHROUGH*/ 2106 2107 case X86_VENDOR_AMD: 2108 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2109 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2110 2111 *edx = CPI_FEATURES_XTD_EDX(cpi); 2112 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2113 2114 /* 2115 * [these features require explicit kernel support] 2116 */ 2117 switch (cpi->cpi_vendor) { 2118 case X86_VENDOR_Intel: 2119 if ((x86_feature & X86_TSCP) == 0) 2120 *edx &= ~CPUID_AMD_EDX_TSCP; 2121 break; 2122 2123 case X86_VENDOR_AMD: 2124 if ((x86_feature & X86_TSCP) == 0) 2125 *edx &= ~CPUID_AMD_EDX_TSCP; 2126 if ((x86_feature & X86_SSE4A) == 0) 2127 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2128 break; 2129 2130 default: 2131 break; 2132 } 2133 2134 /* 2135 * [no explicit support required beyond 2136 * x87 fp context and exception handlers] 2137 */ 2138 if (!fpu_exists) 2139 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2140 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2141 2142 if ((x86_feature & X86_NX) == 0) 2143 *edx &= ~CPUID_AMD_EDX_NX; 2144 #if !defined(__amd64) 2145 *edx &= ~CPUID_AMD_EDX_LM; 2146 #endif 2147 /* 2148 * Now map the supported feature vector to 2149 * things that we think userland will care about. 2150 */ 2151 #if defined(__amd64) 2152 if (*edx & CPUID_AMD_EDX_SYSC) 2153 hwcap_flags |= AV_386_AMD_SYSC; 2154 #endif 2155 if (*edx & CPUID_AMD_EDX_MMXamd) 2156 hwcap_flags |= AV_386_AMD_MMX; 2157 if (*edx & CPUID_AMD_EDX_3DNow) 2158 hwcap_flags |= AV_386_AMD_3DNow; 2159 if (*edx & CPUID_AMD_EDX_3DNowx) 2160 hwcap_flags |= AV_386_AMD_3DNowx; 2161 2162 switch (cpi->cpi_vendor) { 2163 case X86_VENDOR_AMD: 2164 if (*edx & CPUID_AMD_EDX_TSCP) 2165 hwcap_flags |= AV_386_TSCP; 2166 if (*ecx & CPUID_AMD_ECX_AHF64) 2167 hwcap_flags |= AV_386_AHF; 2168 if (*ecx & CPUID_AMD_ECX_SSE4A) 2169 hwcap_flags |= AV_386_AMD_SSE4A; 2170 if (*ecx & CPUID_AMD_ECX_LZCNT) 2171 hwcap_flags |= AV_386_AMD_LZCNT; 2172 break; 2173 2174 case X86_VENDOR_Intel: 2175 if (*edx & CPUID_AMD_EDX_TSCP) 2176 hwcap_flags |= AV_386_TSCP; 2177 /* 2178 * Aarrgh. 2179 * Intel uses a different bit in the same word. 2180 */ 2181 if (*ecx & CPUID_INTC_ECX_AHF64) 2182 hwcap_flags |= AV_386_AHF; 2183 break; 2184 2185 default: 2186 break; 2187 } 2188 break; 2189 2190 case X86_VENDOR_TM: 2191 cp.cp_eax = 0x80860001; 2192 (void) __cpuid_insn(&cp); 2193 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2194 break; 2195 2196 default: 2197 break; 2198 } 2199 2200 pass4_done: 2201 cpi->cpi_pass = 4; 2202 return (hwcap_flags); 2203 } 2204 2205 2206 /* 2207 * Simulate the cpuid instruction using the data we previously 2208 * captured about this CPU. We try our best to return the truth 2209 * about the hardware, independently of kernel support. 2210 */ 2211 uint32_t 2212 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2213 { 2214 struct cpuid_info *cpi; 2215 struct cpuid_regs *xcp; 2216 2217 if (cpu == NULL) 2218 cpu = CPU; 2219 cpi = cpu->cpu_m.mcpu_cpi; 2220 2221 ASSERT(cpuid_checkpass(cpu, 3)); 2222 2223 /* 2224 * CPUID data is cached in two separate places: cpi_std for standard 2225 * CPUID functions, and cpi_extd for extended CPUID functions. 2226 */ 2227 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2228 xcp = &cpi->cpi_std[cp->cp_eax]; 2229 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2230 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2231 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2232 else 2233 /* 2234 * The caller is asking for data from an input parameter which 2235 * the kernel has not cached. In this case we go fetch from 2236 * the hardware and return the data directly to the user. 2237 */ 2238 return (__cpuid_insn(cp)); 2239 2240 cp->cp_eax = xcp->cp_eax; 2241 cp->cp_ebx = xcp->cp_ebx; 2242 cp->cp_ecx = xcp->cp_ecx; 2243 cp->cp_edx = xcp->cp_edx; 2244 return (cp->cp_eax); 2245 } 2246 2247 int 2248 cpuid_checkpass(cpu_t *cpu, int pass) 2249 { 2250 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2251 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2252 } 2253 2254 int 2255 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2256 { 2257 ASSERT(cpuid_checkpass(cpu, 3)); 2258 2259 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2260 } 2261 2262 int 2263 cpuid_is_cmt(cpu_t *cpu) 2264 { 2265 if (cpu == NULL) 2266 cpu = CPU; 2267 2268 ASSERT(cpuid_checkpass(cpu, 1)); 2269 2270 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2271 } 2272 2273 /* 2274 * AMD and Intel both implement the 64-bit variant of the syscall 2275 * instruction (syscallq), so if there's -any- support for syscall, 2276 * cpuid currently says "yes, we support this". 2277 * 2278 * However, Intel decided to -not- implement the 32-bit variant of the 2279 * syscall instruction, so we provide a predicate to allow our caller 2280 * to test that subtlety here. 2281 * 2282 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2283 * even in the case where the hardware would in fact support it. 2284 */ 2285 /*ARGSUSED*/ 2286 int 2287 cpuid_syscall32_insn(cpu_t *cpu) 2288 { 2289 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2290 2291 #if !defined(__xpv) 2292 if (cpu == NULL) 2293 cpu = CPU; 2294 2295 /*CSTYLED*/ 2296 { 2297 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2298 2299 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2300 cpi->cpi_xmaxeax >= 0x80000001 && 2301 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2302 return (1); 2303 } 2304 #endif 2305 return (0); 2306 } 2307 2308 int 2309 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2310 { 2311 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2312 2313 static const char fmt[] = 2314 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2315 static const char fmt_ht[] = 2316 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2317 2318 ASSERT(cpuid_checkpass(cpu, 1)); 2319 2320 if (cpuid_is_cmt(cpu)) 2321 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2322 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2323 cpi->cpi_family, cpi->cpi_model, 2324 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2325 return (snprintf(s, n, fmt, 2326 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2327 cpi->cpi_family, cpi->cpi_model, 2328 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2329 } 2330 2331 const char * 2332 cpuid_getvendorstr(cpu_t *cpu) 2333 { 2334 ASSERT(cpuid_checkpass(cpu, 1)); 2335 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2336 } 2337 2338 uint_t 2339 cpuid_getvendor(cpu_t *cpu) 2340 { 2341 ASSERT(cpuid_checkpass(cpu, 1)); 2342 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2343 } 2344 2345 uint_t 2346 cpuid_getfamily(cpu_t *cpu) 2347 { 2348 ASSERT(cpuid_checkpass(cpu, 1)); 2349 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2350 } 2351 2352 uint_t 2353 cpuid_getmodel(cpu_t *cpu) 2354 { 2355 ASSERT(cpuid_checkpass(cpu, 1)); 2356 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2357 } 2358 2359 uint_t 2360 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2361 { 2362 ASSERT(cpuid_checkpass(cpu, 1)); 2363 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2364 } 2365 2366 uint_t 2367 cpuid_get_ncore_per_chip(cpu_t *cpu) 2368 { 2369 ASSERT(cpuid_checkpass(cpu, 1)); 2370 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2371 } 2372 2373 uint_t 2374 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2375 { 2376 ASSERT(cpuid_checkpass(cpu, 2)); 2377 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2378 } 2379 2380 id_t 2381 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2382 { 2383 ASSERT(cpuid_checkpass(cpu, 2)); 2384 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2385 } 2386 2387 uint_t 2388 cpuid_getstep(cpu_t *cpu) 2389 { 2390 ASSERT(cpuid_checkpass(cpu, 1)); 2391 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2392 } 2393 2394 uint_t 2395 cpuid_getsig(struct cpu *cpu) 2396 { 2397 ASSERT(cpuid_checkpass(cpu, 1)); 2398 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2399 } 2400 2401 uint32_t 2402 cpuid_getchiprev(struct cpu *cpu) 2403 { 2404 ASSERT(cpuid_checkpass(cpu, 1)); 2405 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2406 } 2407 2408 const char * 2409 cpuid_getchiprevstr(struct cpu *cpu) 2410 { 2411 ASSERT(cpuid_checkpass(cpu, 1)); 2412 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2413 } 2414 2415 uint32_t 2416 cpuid_getsockettype(struct cpu *cpu) 2417 { 2418 ASSERT(cpuid_checkpass(cpu, 1)); 2419 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2420 } 2421 2422 int 2423 cpuid_get_chipid(cpu_t *cpu) 2424 { 2425 ASSERT(cpuid_checkpass(cpu, 1)); 2426 2427 if (cpuid_is_cmt(cpu)) 2428 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2429 return (cpu->cpu_id); 2430 } 2431 2432 id_t 2433 cpuid_get_coreid(cpu_t *cpu) 2434 { 2435 ASSERT(cpuid_checkpass(cpu, 1)); 2436 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2437 } 2438 2439 int 2440 cpuid_get_pkgcoreid(cpu_t *cpu) 2441 { 2442 ASSERT(cpuid_checkpass(cpu, 1)); 2443 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 2444 } 2445 2446 int 2447 cpuid_get_clogid(cpu_t *cpu) 2448 { 2449 ASSERT(cpuid_checkpass(cpu, 1)); 2450 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2451 } 2452 2453 void 2454 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2455 { 2456 struct cpuid_info *cpi; 2457 2458 if (cpu == NULL) 2459 cpu = CPU; 2460 cpi = cpu->cpu_m.mcpu_cpi; 2461 2462 ASSERT(cpuid_checkpass(cpu, 1)); 2463 2464 if (pabits) 2465 *pabits = cpi->cpi_pabits; 2466 if (vabits) 2467 *vabits = cpi->cpi_vabits; 2468 } 2469 2470 /* 2471 * Returns the number of data TLB entries for a corresponding 2472 * pagesize. If it can't be computed, or isn't known, the 2473 * routine returns zero. If you ask about an architecturally 2474 * impossible pagesize, the routine will panic (so that the 2475 * hat implementor knows that things are inconsistent.) 2476 */ 2477 uint_t 2478 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2479 { 2480 struct cpuid_info *cpi; 2481 uint_t dtlb_nent = 0; 2482 2483 if (cpu == NULL) 2484 cpu = CPU; 2485 cpi = cpu->cpu_m.mcpu_cpi; 2486 2487 ASSERT(cpuid_checkpass(cpu, 1)); 2488 2489 /* 2490 * Check the L2 TLB info 2491 */ 2492 if (cpi->cpi_xmaxeax >= 0x80000006) { 2493 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2494 2495 switch (pagesize) { 2496 2497 case 4 * 1024: 2498 /* 2499 * All zero in the top 16 bits of the register 2500 * indicates a unified TLB. Size is in low 16 bits. 2501 */ 2502 if ((cp->cp_ebx & 0xffff0000) == 0) 2503 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2504 else 2505 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2506 break; 2507 2508 case 2 * 1024 * 1024: 2509 if ((cp->cp_eax & 0xffff0000) == 0) 2510 dtlb_nent = cp->cp_eax & 0x0000ffff; 2511 else 2512 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2513 break; 2514 2515 default: 2516 panic("unknown L2 pagesize"); 2517 /*NOTREACHED*/ 2518 } 2519 } 2520 2521 if (dtlb_nent != 0) 2522 return (dtlb_nent); 2523 2524 /* 2525 * No L2 TLB support for this size, try L1. 2526 */ 2527 if (cpi->cpi_xmaxeax >= 0x80000005) { 2528 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2529 2530 switch (pagesize) { 2531 case 4 * 1024: 2532 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2533 break; 2534 case 2 * 1024 * 1024: 2535 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2536 break; 2537 default: 2538 panic("unknown L1 d-TLB pagesize"); 2539 /*NOTREACHED*/ 2540 } 2541 } 2542 2543 return (dtlb_nent); 2544 } 2545 2546 /* 2547 * Return 0 if the erratum is not present or not applicable, positive 2548 * if it is, and negative if the status of the erratum is unknown. 2549 * 2550 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2551 * Processors" #25759, Rev 3.57, August 2005 2552 */ 2553 int 2554 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2555 { 2556 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2557 uint_t eax; 2558 2559 /* 2560 * Bail out if this CPU isn't an AMD CPU, or if it's 2561 * a legacy (32-bit) AMD CPU. 2562 */ 2563 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2564 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2565 cpi->cpi_family == 6) 2566 2567 return (0); 2568 2569 eax = cpi->cpi_std[1].cp_eax; 2570 2571 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2572 #define SH_B3(eax) (eax == 0xf51) 2573 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2574 2575 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2576 2577 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2578 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2579 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2580 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2581 2582 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2583 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2584 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2585 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2586 2587 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2588 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2589 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2590 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2591 #define BH_E4(eax) (eax == 0x20fb1) 2592 #define SH_E5(eax) (eax == 0x20f42) 2593 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2594 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2595 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2596 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2597 DH_E6(eax) || JH_E6(eax)) 2598 2599 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 2600 #define DR_B0(eax) (eax == 0x100f20) 2601 #define DR_B1(eax) (eax == 0x100f21) 2602 #define DR_BA(eax) (eax == 0x100f2a) 2603 #define DR_B2(eax) (eax == 0x100f22) 2604 #define DR_B3(eax) (eax == 0x100f23) 2605 #define RB_C0(eax) (eax == 0x100f40) 2606 2607 switch (erratum) { 2608 case 1: 2609 return (cpi->cpi_family < 0x10); 2610 case 51: /* what does the asterisk mean? */ 2611 return (B(eax) || SH_C0(eax) || CG(eax)); 2612 case 52: 2613 return (B(eax)); 2614 case 57: 2615 return (cpi->cpi_family <= 0x11); 2616 case 58: 2617 return (B(eax)); 2618 case 60: 2619 return (cpi->cpi_family <= 0x11); 2620 case 61: 2621 case 62: 2622 case 63: 2623 case 64: 2624 case 65: 2625 case 66: 2626 case 68: 2627 case 69: 2628 case 70: 2629 case 71: 2630 return (B(eax)); 2631 case 72: 2632 return (SH_B0(eax)); 2633 case 74: 2634 return (B(eax)); 2635 case 75: 2636 return (cpi->cpi_family < 0x10); 2637 case 76: 2638 return (B(eax)); 2639 case 77: 2640 return (cpi->cpi_family <= 0x11); 2641 case 78: 2642 return (B(eax) || SH_C0(eax)); 2643 case 79: 2644 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2645 case 80: 2646 case 81: 2647 case 82: 2648 return (B(eax)); 2649 case 83: 2650 return (B(eax) || SH_C0(eax) || CG(eax)); 2651 case 85: 2652 return (cpi->cpi_family < 0x10); 2653 case 86: 2654 return (SH_C0(eax) || CG(eax)); 2655 case 88: 2656 #if !defined(__amd64) 2657 return (0); 2658 #else 2659 return (B(eax) || SH_C0(eax)); 2660 #endif 2661 case 89: 2662 return (cpi->cpi_family < 0x10); 2663 case 90: 2664 return (B(eax) || SH_C0(eax) || CG(eax)); 2665 case 91: 2666 case 92: 2667 return (B(eax) || SH_C0(eax)); 2668 case 93: 2669 return (SH_C0(eax)); 2670 case 94: 2671 return (B(eax) || SH_C0(eax) || CG(eax)); 2672 case 95: 2673 #if !defined(__amd64) 2674 return (0); 2675 #else 2676 return (B(eax) || SH_C0(eax)); 2677 #endif 2678 case 96: 2679 return (B(eax) || SH_C0(eax) || CG(eax)); 2680 case 97: 2681 case 98: 2682 return (SH_C0(eax) || CG(eax)); 2683 case 99: 2684 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2685 case 100: 2686 return (B(eax) || SH_C0(eax)); 2687 case 101: 2688 case 103: 2689 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2690 case 104: 2691 return (SH_C0(eax) || CG(eax) || D0(eax)); 2692 case 105: 2693 case 106: 2694 case 107: 2695 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2696 case 108: 2697 return (DH_CG(eax)); 2698 case 109: 2699 return (SH_C0(eax) || CG(eax) || D0(eax)); 2700 case 110: 2701 return (D0(eax) || EX(eax)); 2702 case 111: 2703 return (CG(eax)); 2704 case 112: 2705 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2706 case 113: 2707 return (eax == 0x20fc0); 2708 case 114: 2709 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2710 case 115: 2711 return (SH_E0(eax) || JH_E1(eax)); 2712 case 116: 2713 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2714 case 117: 2715 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2716 case 118: 2717 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2718 JH_E6(eax)); 2719 case 121: 2720 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2721 case 122: 2722 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 2723 case 123: 2724 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2725 case 131: 2726 return (cpi->cpi_family < 0x10); 2727 case 6336786: 2728 /* 2729 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2730 * if this is a K8 family or newer processor 2731 */ 2732 if (CPI_FAMILY(cpi) == 0xf) { 2733 struct cpuid_regs regs; 2734 regs.cp_eax = 0x80000007; 2735 (void) __cpuid_insn(®s); 2736 return (!(regs.cp_edx & 0x100)); 2737 } 2738 return (0); 2739 case 6323525: 2740 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2741 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2742 2743 case 6671130: 2744 /* 2745 * check for processors (pre-Shanghai) that do not provide 2746 * optimal management of 1gb ptes in its tlb. 2747 */ 2748 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 2749 2750 case 298: 2751 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 2752 DR_B2(eax) || RB_C0(eax)); 2753 2754 default: 2755 return (-1); 2756 2757 } 2758 } 2759 2760 /* 2761 * Determine if specified erratum is present via OSVW (OS Visible Workaround). 2762 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 2763 */ 2764 int 2765 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 2766 { 2767 struct cpuid_info *cpi; 2768 uint_t osvwid; 2769 static int osvwfeature = -1; 2770 uint64_t osvwlength; 2771 2772 2773 cpi = cpu->cpu_m.mcpu_cpi; 2774 2775 /* confirm OSVW supported */ 2776 if (osvwfeature == -1) { 2777 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 2778 } else { 2779 /* assert that osvw feature setting is consistent on all cpus */ 2780 ASSERT(osvwfeature == 2781 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 2782 } 2783 if (!osvwfeature) 2784 return (-1); 2785 2786 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 2787 2788 switch (erratum) { 2789 case 298: /* osvwid is 0 */ 2790 osvwid = 0; 2791 if (osvwlength <= (uint64_t)osvwid) { 2792 /* osvwid 0 is unknown */ 2793 return (-1); 2794 } 2795 2796 /* 2797 * Check the OSVW STATUS MSR to determine the state 2798 * of the erratum where: 2799 * 0 - fixed by HW 2800 * 1 - BIOS has applied the workaround when BIOS 2801 * workaround is available. (Or for other errata, 2802 * OS workaround is required.) 2803 * For a value of 1, caller will confirm that the 2804 * erratum 298 workaround has indeed been applied by BIOS. 2805 * 2806 * A 1 may be set in cpus that have a HW fix 2807 * in a mixed cpu system. Regarding erratum 298: 2808 * In a multiprocessor platform, the workaround above 2809 * should be applied to all processors regardless of 2810 * silicon revision when an affected processor is 2811 * present. 2812 */ 2813 2814 return (rdmsr(MSR_AMD_OSVW_STATUS + 2815 (osvwid / OSVW_ID_CNT_PER_MSR)) & 2816 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 2817 2818 default: 2819 return (-1); 2820 } 2821 } 2822 2823 static const char assoc_str[] = "associativity"; 2824 static const char line_str[] = "line-size"; 2825 static const char size_str[] = "size"; 2826 2827 static void 2828 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2829 uint32_t val) 2830 { 2831 char buf[128]; 2832 2833 /* 2834 * ndi_prop_update_int() is used because it is desirable for 2835 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2836 */ 2837 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2838 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2839 } 2840 2841 /* 2842 * Intel-style cache/tlb description 2843 * 2844 * Standard cpuid level 2 gives a randomly ordered 2845 * selection of tags that index into a table that describes 2846 * cache and tlb properties. 2847 */ 2848 2849 static const char l1_icache_str[] = "l1-icache"; 2850 static const char l1_dcache_str[] = "l1-dcache"; 2851 static const char l2_cache_str[] = "l2-cache"; 2852 static const char l3_cache_str[] = "l3-cache"; 2853 static const char itlb4k_str[] = "itlb-4K"; 2854 static const char dtlb4k_str[] = "dtlb-4K"; 2855 static const char itlb2M_str[] = "itlb-2M"; 2856 static const char itlb4M_str[] = "itlb-4M"; 2857 static const char dtlb4M_str[] = "dtlb-4M"; 2858 static const char dtlb24_str[] = "dtlb0-2M-4M"; 2859 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2860 static const char itlb24_str[] = "itlb-2M-4M"; 2861 static const char dtlb44_str[] = "dtlb-4K-4M"; 2862 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2863 static const char sl2_cache_str[] = "sectored-l2-cache"; 2864 static const char itrace_str[] = "itrace-cache"; 2865 static const char sl3_cache_str[] = "sectored-l3-cache"; 2866 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 2867 2868 static const struct cachetab { 2869 uint8_t ct_code; 2870 uint8_t ct_assoc; 2871 uint16_t ct_line_size; 2872 size_t ct_size; 2873 const char *ct_label; 2874 } intel_ctab[] = { 2875 /* 2876 * maintain descending order! 2877 * 2878 * Codes ignored - Reason 2879 * ---------------------- 2880 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 2881 * f0H/f1H - Currently we do not interpret prefetch size by design 2882 */ 2883 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 2884 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 2885 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 2886 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 2887 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 2888 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 2889 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 2890 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 2891 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 2892 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 2893 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 2894 { 0xd0, 4, 64, 512*1024, l3_cache_str}, 2895 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 2896 { 0xc0, 4, 0, 8, dtlb44_str }, 2897 { 0xba, 4, 0, 64, dtlb4k_str }, 2898 { 0xb4, 4, 0, 256, dtlb4k_str }, 2899 { 0xb3, 4, 0, 128, dtlb4k_str }, 2900 { 0xb2, 4, 0, 64, itlb4k_str }, 2901 { 0xb0, 4, 0, 128, itlb4k_str }, 2902 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2903 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2904 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2905 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2906 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2907 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2908 { 0x80, 8, 64, 512*1024, l2_cache_str}, 2909 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2910 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2911 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2912 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2913 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2914 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2915 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2916 { 0x73, 8, 0, 64*1024, itrace_str}, 2917 { 0x72, 8, 0, 32*1024, itrace_str}, 2918 { 0x71, 8, 0, 16*1024, itrace_str}, 2919 { 0x70, 8, 0, 12*1024, itrace_str}, 2920 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2921 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2922 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2923 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2924 { 0x5d, 0, 0, 256, dtlb44_str}, 2925 { 0x5c, 0, 0, 128, dtlb44_str}, 2926 { 0x5b, 0, 0, 64, dtlb44_str}, 2927 { 0x5a, 4, 0, 32, dtlb24_str}, 2928 { 0x59, 0, 0, 16, dtlb4k_str}, 2929 { 0x57, 4, 0, 16, dtlb4k_str}, 2930 { 0x56, 4, 0, 16, dtlb4M_str}, 2931 { 0x55, 0, 0, 7, itlb24_str}, 2932 { 0x52, 0, 0, 256, itlb424_str}, 2933 { 0x51, 0, 0, 128, itlb424_str}, 2934 { 0x50, 0, 0, 64, itlb424_str}, 2935 { 0x4f, 0, 0, 32, itlb4k_str}, 2936 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 2937 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2938 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2939 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2940 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2941 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2942 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 2943 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2944 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2945 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2946 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2947 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2948 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2949 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2950 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2951 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2952 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2953 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2954 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2955 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2956 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2957 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2958 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2959 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2960 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2961 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2962 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 2963 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 2964 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2965 { 0x0b, 4, 0, 4, itlb4M_str}, 2966 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2967 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2968 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2969 { 0x05, 4, 0, 32, dtlb4M_str}, 2970 { 0x04, 4, 0, 8, dtlb4M_str}, 2971 { 0x03, 4, 0, 64, dtlb4k_str}, 2972 { 0x02, 4, 0, 2, itlb4M_str}, 2973 { 0x01, 4, 0, 32, itlb4k_str}, 2974 { 0 } 2975 }; 2976 2977 static const struct cachetab cyrix_ctab[] = { 2978 { 0x70, 4, 0, 32, "tlb-4K" }, 2979 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2980 { 0 } 2981 }; 2982 2983 /* 2984 * Search a cache table for a matching entry 2985 */ 2986 static const struct cachetab * 2987 find_cacheent(const struct cachetab *ct, uint_t code) 2988 { 2989 if (code != 0) { 2990 for (; ct->ct_code != 0; ct++) 2991 if (ct->ct_code <= code) 2992 break; 2993 if (ct->ct_code == code) 2994 return (ct); 2995 } 2996 return (NULL); 2997 } 2998 2999 /* 3000 * Populate cachetab entry with L2 or L3 cache-information using 3001 * cpuid function 4. This function is called from intel_walk_cacheinfo() 3002 * when descriptor 0x49 is encountered. It returns 0 if no such cache 3003 * information is found. 3004 */ 3005 static int 3006 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 3007 { 3008 uint32_t level, i; 3009 int ret = 0; 3010 3011 for (i = 0; i < cpi->cpi_std_4_size; i++) { 3012 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 3013 3014 if (level == 2 || level == 3) { 3015 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 3016 ct->ct_line_size = 3017 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 3018 ct->ct_size = ct->ct_assoc * 3019 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 3020 ct->ct_line_size * 3021 (cpi->cpi_std_4[i]->cp_ecx + 1); 3022 3023 if (level == 2) { 3024 ct->ct_label = l2_cache_str; 3025 } else if (level == 3) { 3026 ct->ct_label = l3_cache_str; 3027 } 3028 ret = 1; 3029 } 3030 } 3031 3032 return (ret); 3033 } 3034 3035 /* 3036 * Walk the cacheinfo descriptor, applying 'func' to every valid element 3037 * The walk is terminated if the walker returns non-zero. 3038 */ 3039 static void 3040 intel_walk_cacheinfo(struct cpuid_info *cpi, 3041 void *arg, int (*func)(void *, const struct cachetab *)) 3042 { 3043 const struct cachetab *ct; 3044 struct cachetab des_49_ct, des_b1_ct; 3045 uint8_t *dp; 3046 int i; 3047 3048 if ((dp = cpi->cpi_cacheinfo) == NULL) 3049 return; 3050 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3051 /* 3052 * For overloaded descriptor 0x49 we use cpuid function 4 3053 * if supported by the current processor, to create 3054 * cache information. 3055 * For overloaded descriptor 0xb1 we use X86_PAE flag 3056 * to disambiguate the cache information. 3057 */ 3058 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 3059 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 3060 ct = &des_49_ct; 3061 } else if (*dp == 0xb1) { 3062 des_b1_ct.ct_code = 0xb1; 3063 des_b1_ct.ct_assoc = 4; 3064 des_b1_ct.ct_line_size = 0; 3065 if (x86_feature & X86_PAE) { 3066 des_b1_ct.ct_size = 8; 3067 des_b1_ct.ct_label = itlb2M_str; 3068 } else { 3069 des_b1_ct.ct_size = 4; 3070 des_b1_ct.ct_label = itlb4M_str; 3071 } 3072 ct = &des_b1_ct; 3073 } else { 3074 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3075 continue; 3076 } 3077 } 3078 3079 if (func(arg, ct) != 0) { 3080 break; 3081 } 3082 } 3083 } 3084 3085 /* 3086 * (Like the Intel one, except for Cyrix CPUs) 3087 */ 3088 static void 3089 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 3090 void *arg, int (*func)(void *, const struct cachetab *)) 3091 { 3092 const struct cachetab *ct; 3093 uint8_t *dp; 3094 int i; 3095 3096 if ((dp = cpi->cpi_cacheinfo) == NULL) 3097 return; 3098 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3099 /* 3100 * Search Cyrix-specific descriptor table first .. 3101 */ 3102 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 3103 if (func(arg, ct) != 0) 3104 break; 3105 continue; 3106 } 3107 /* 3108 * .. else fall back to the Intel one 3109 */ 3110 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 3111 if (func(arg, ct) != 0) 3112 break; 3113 continue; 3114 } 3115 } 3116 } 3117 3118 /* 3119 * A cacheinfo walker that adds associativity, line-size, and size properties 3120 * to the devinfo node it is passed as an argument. 3121 */ 3122 static int 3123 add_cacheent_props(void *arg, const struct cachetab *ct) 3124 { 3125 dev_info_t *devi = arg; 3126 3127 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 3128 if (ct->ct_line_size != 0) 3129 add_cache_prop(devi, ct->ct_label, line_str, 3130 ct->ct_line_size); 3131 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 3132 return (0); 3133 } 3134 3135 3136 static const char fully_assoc[] = "fully-associative?"; 3137 3138 /* 3139 * AMD style cache/tlb description 3140 * 3141 * Extended functions 5 and 6 directly describe properties of 3142 * tlbs and various cache levels. 3143 */ 3144 static void 3145 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3146 { 3147 switch (assoc) { 3148 case 0: /* reserved; ignore */ 3149 break; 3150 default: 3151 add_cache_prop(devi, label, assoc_str, assoc); 3152 break; 3153 case 0xff: 3154 add_cache_prop(devi, label, fully_assoc, 1); 3155 break; 3156 } 3157 } 3158 3159 static void 3160 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3161 { 3162 if (size == 0) 3163 return; 3164 add_cache_prop(devi, label, size_str, size); 3165 add_amd_assoc(devi, label, assoc); 3166 } 3167 3168 static void 3169 add_amd_cache(dev_info_t *devi, const char *label, 3170 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3171 { 3172 if (size == 0 || line_size == 0) 3173 return; 3174 add_amd_assoc(devi, label, assoc); 3175 /* 3176 * Most AMD parts have a sectored cache. Multiple cache lines are 3177 * associated with each tag. A sector consists of all cache lines 3178 * associated with a tag. For example, the AMD K6-III has a sector 3179 * size of 2 cache lines per tag. 3180 */ 3181 if (lines_per_tag != 0) 3182 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3183 add_cache_prop(devi, label, line_str, line_size); 3184 add_cache_prop(devi, label, size_str, size * 1024); 3185 } 3186 3187 static void 3188 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3189 { 3190 switch (assoc) { 3191 case 0: /* off */ 3192 break; 3193 case 1: 3194 case 2: 3195 case 4: 3196 add_cache_prop(devi, label, assoc_str, assoc); 3197 break; 3198 case 6: 3199 add_cache_prop(devi, label, assoc_str, 8); 3200 break; 3201 case 8: 3202 add_cache_prop(devi, label, assoc_str, 16); 3203 break; 3204 case 0xf: 3205 add_cache_prop(devi, label, fully_assoc, 1); 3206 break; 3207 default: /* reserved; ignore */ 3208 break; 3209 } 3210 } 3211 3212 static void 3213 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3214 { 3215 if (size == 0 || assoc == 0) 3216 return; 3217 add_amd_l2_assoc(devi, label, assoc); 3218 add_cache_prop(devi, label, size_str, size); 3219 } 3220 3221 static void 3222 add_amd_l2_cache(dev_info_t *devi, const char *label, 3223 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3224 { 3225 if (size == 0 || assoc == 0 || line_size == 0) 3226 return; 3227 add_amd_l2_assoc(devi, label, assoc); 3228 if (lines_per_tag != 0) 3229 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3230 add_cache_prop(devi, label, line_str, line_size); 3231 add_cache_prop(devi, label, size_str, size * 1024); 3232 } 3233 3234 static void 3235 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3236 { 3237 struct cpuid_regs *cp; 3238 3239 if (cpi->cpi_xmaxeax < 0x80000005) 3240 return; 3241 cp = &cpi->cpi_extd[5]; 3242 3243 /* 3244 * 4M/2M L1 TLB configuration 3245 * 3246 * We report the size for 2M pages because AMD uses two 3247 * TLB entries for one 4M page. 3248 */ 3249 add_amd_tlb(devi, "dtlb-2M", 3250 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3251 add_amd_tlb(devi, "itlb-2M", 3252 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3253 3254 /* 3255 * 4K L1 TLB configuration 3256 */ 3257 3258 switch (cpi->cpi_vendor) { 3259 uint_t nentries; 3260 case X86_VENDOR_TM: 3261 if (cpi->cpi_family >= 5) { 3262 /* 3263 * Crusoe processors have 256 TLB entries, but 3264 * cpuid data format constrains them to only 3265 * reporting 255 of them. 3266 */ 3267 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3268 nentries = 256; 3269 /* 3270 * Crusoe processors also have a unified TLB 3271 */ 3272 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3273 nentries); 3274 break; 3275 } 3276 /*FALLTHROUGH*/ 3277 default: 3278 add_amd_tlb(devi, itlb4k_str, 3279 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3280 add_amd_tlb(devi, dtlb4k_str, 3281 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3282 break; 3283 } 3284 3285 /* 3286 * data L1 cache configuration 3287 */ 3288 3289 add_amd_cache(devi, l1_dcache_str, 3290 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3291 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3292 3293 /* 3294 * code L1 cache configuration 3295 */ 3296 3297 add_amd_cache(devi, l1_icache_str, 3298 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3299 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3300 3301 if (cpi->cpi_xmaxeax < 0x80000006) 3302 return; 3303 cp = &cpi->cpi_extd[6]; 3304 3305 /* Check for a unified L2 TLB for large pages */ 3306 3307 if (BITX(cp->cp_eax, 31, 16) == 0) 3308 add_amd_l2_tlb(devi, "l2-tlb-2M", 3309 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3310 else { 3311 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3312 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3313 add_amd_l2_tlb(devi, "l2-itlb-2M", 3314 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3315 } 3316 3317 /* Check for a unified L2 TLB for 4K pages */ 3318 3319 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3320 add_amd_l2_tlb(devi, "l2-tlb-4K", 3321 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3322 } else { 3323 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3324 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3325 add_amd_l2_tlb(devi, "l2-itlb-4K", 3326 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3327 } 3328 3329 add_amd_l2_cache(devi, l2_cache_str, 3330 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3331 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3332 } 3333 3334 /* 3335 * There are two basic ways that the x86 world describes it cache 3336 * and tlb architecture - Intel's way and AMD's way. 3337 * 3338 * Return which flavor of cache architecture we should use 3339 */ 3340 static int 3341 x86_which_cacheinfo(struct cpuid_info *cpi) 3342 { 3343 switch (cpi->cpi_vendor) { 3344 case X86_VENDOR_Intel: 3345 if (cpi->cpi_maxeax >= 2) 3346 return (X86_VENDOR_Intel); 3347 break; 3348 case X86_VENDOR_AMD: 3349 /* 3350 * The K5 model 1 was the first part from AMD that reported 3351 * cache sizes via extended cpuid functions. 3352 */ 3353 if (cpi->cpi_family > 5 || 3354 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3355 return (X86_VENDOR_AMD); 3356 break; 3357 case X86_VENDOR_TM: 3358 if (cpi->cpi_family >= 5) 3359 return (X86_VENDOR_AMD); 3360 /*FALLTHROUGH*/ 3361 default: 3362 /* 3363 * If they have extended CPU data for 0x80000005 3364 * then we assume they have AMD-format cache 3365 * information. 3366 * 3367 * If not, and the vendor happens to be Cyrix, 3368 * then try our-Cyrix specific handler. 3369 * 3370 * If we're not Cyrix, then assume we're using Intel's 3371 * table-driven format instead. 3372 */ 3373 if (cpi->cpi_xmaxeax >= 0x80000005) 3374 return (X86_VENDOR_AMD); 3375 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3376 return (X86_VENDOR_Cyrix); 3377 else if (cpi->cpi_maxeax >= 2) 3378 return (X86_VENDOR_Intel); 3379 break; 3380 } 3381 return (-1); 3382 } 3383 3384 /* 3385 * create a node for the given cpu under the prom root node. 3386 * Also, create a cpu node in the device tree. 3387 */ 3388 static dev_info_t *cpu_nex_devi = NULL; 3389 static kmutex_t cpu_node_lock; 3390 3391 /* 3392 * Called from post_startup() and mp_startup() 3393 */ 3394 void 3395 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3396 { 3397 dev_info_t *cpu_devi; 3398 int create; 3399 3400 mutex_enter(&cpu_node_lock); 3401 3402 /* 3403 * create a nexus node for all cpus identified as 'cpu_id' under 3404 * the root node. 3405 */ 3406 if (cpu_nex_devi == NULL) { 3407 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3408 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3409 mutex_exit(&cpu_node_lock); 3410 return; 3411 } 3412 (void) ndi_devi_online(cpu_nex_devi, 0); 3413 } 3414 3415 /* 3416 * create a child node for cpu identified as 'cpu_id' 3417 */ 3418 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3419 cpu_id); 3420 if (cpu_devi == NULL) { 3421 mutex_exit(&cpu_node_lock); 3422 return; 3423 } 3424 3425 /* device_type */ 3426 3427 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3428 "device_type", "cpu"); 3429 3430 /* reg */ 3431 3432 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3433 "reg", cpu_id); 3434 3435 /* cpu-mhz, and clock-frequency */ 3436 3437 if (cpu_freq > 0) { 3438 long long mul; 3439 3440 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3441 "cpu-mhz", cpu_freq); 3442 3443 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3444 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3445 "clock-frequency", (int)mul); 3446 } 3447 3448 (void) ndi_devi_online(cpu_devi, 0); 3449 3450 if ((x86_feature & X86_CPUID) == 0) { 3451 mutex_exit(&cpu_node_lock); 3452 return; 3453 } 3454 3455 /* vendor-id */ 3456 3457 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3458 "vendor-id", cpi->cpi_vendorstr); 3459 3460 if (cpi->cpi_maxeax == 0) { 3461 mutex_exit(&cpu_node_lock); 3462 return; 3463 } 3464 3465 /* 3466 * family, model, and step 3467 */ 3468 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3469 "family", CPI_FAMILY(cpi)); 3470 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3471 "cpu-model", CPI_MODEL(cpi)); 3472 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3473 "stepping-id", CPI_STEP(cpi)); 3474 3475 /* type */ 3476 3477 switch (cpi->cpi_vendor) { 3478 case X86_VENDOR_Intel: 3479 create = 1; 3480 break; 3481 default: 3482 create = 0; 3483 break; 3484 } 3485 if (create) 3486 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3487 "type", CPI_TYPE(cpi)); 3488 3489 /* ext-family */ 3490 3491 switch (cpi->cpi_vendor) { 3492 case X86_VENDOR_Intel: 3493 case X86_VENDOR_AMD: 3494 create = cpi->cpi_family >= 0xf; 3495 break; 3496 default: 3497 create = 0; 3498 break; 3499 } 3500 if (create) 3501 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3502 "ext-family", CPI_FAMILY_XTD(cpi)); 3503 3504 /* ext-model */ 3505 3506 switch (cpi->cpi_vendor) { 3507 case X86_VENDOR_Intel: 3508 create = IS_EXTENDED_MODEL_INTEL(cpi); 3509 break; 3510 case X86_VENDOR_AMD: 3511 create = CPI_FAMILY(cpi) == 0xf; 3512 break; 3513 default: 3514 create = 0; 3515 break; 3516 } 3517 if (create) 3518 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3519 "ext-model", CPI_MODEL_XTD(cpi)); 3520 3521 /* generation */ 3522 3523 switch (cpi->cpi_vendor) { 3524 case X86_VENDOR_AMD: 3525 /* 3526 * AMD K5 model 1 was the first part to support this 3527 */ 3528 create = cpi->cpi_xmaxeax >= 0x80000001; 3529 break; 3530 default: 3531 create = 0; 3532 break; 3533 } 3534 if (create) 3535 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3536 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3537 3538 /* brand-id */ 3539 3540 switch (cpi->cpi_vendor) { 3541 case X86_VENDOR_Intel: 3542 /* 3543 * brand id first appeared on Pentium III Xeon model 8, 3544 * and Celeron model 8 processors and Opteron 3545 */ 3546 create = cpi->cpi_family > 6 || 3547 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3548 break; 3549 case X86_VENDOR_AMD: 3550 create = cpi->cpi_family >= 0xf; 3551 break; 3552 default: 3553 create = 0; 3554 break; 3555 } 3556 if (create && cpi->cpi_brandid != 0) { 3557 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3558 "brand-id", cpi->cpi_brandid); 3559 } 3560 3561 /* chunks, and apic-id */ 3562 3563 switch (cpi->cpi_vendor) { 3564 /* 3565 * first available on Pentium IV and Opteron (K8) 3566 */ 3567 case X86_VENDOR_Intel: 3568 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3569 break; 3570 case X86_VENDOR_AMD: 3571 create = cpi->cpi_family >= 0xf; 3572 break; 3573 default: 3574 create = 0; 3575 break; 3576 } 3577 if (create) { 3578 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3579 "chunks", CPI_CHUNKS(cpi)); 3580 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3581 "apic-id", cpi->cpi_apicid); 3582 if (cpi->cpi_chipid >= 0) { 3583 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3584 "chip#", cpi->cpi_chipid); 3585 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3586 "clog#", cpi->cpi_clogid); 3587 } 3588 } 3589 3590 /* cpuid-features */ 3591 3592 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3593 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3594 3595 3596 /* cpuid-features-ecx */ 3597 3598 switch (cpi->cpi_vendor) { 3599 case X86_VENDOR_Intel: 3600 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3601 break; 3602 default: 3603 create = 0; 3604 break; 3605 } 3606 if (create) 3607 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3608 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3609 3610 /* ext-cpuid-features */ 3611 3612 switch (cpi->cpi_vendor) { 3613 case X86_VENDOR_Intel: 3614 case X86_VENDOR_AMD: 3615 case X86_VENDOR_Cyrix: 3616 case X86_VENDOR_TM: 3617 case X86_VENDOR_Centaur: 3618 create = cpi->cpi_xmaxeax >= 0x80000001; 3619 break; 3620 default: 3621 create = 0; 3622 break; 3623 } 3624 if (create) { 3625 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3626 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3627 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3628 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3629 } 3630 3631 /* 3632 * Brand String first appeared in Intel Pentium IV, AMD K5 3633 * model 1, and Cyrix GXm. On earlier models we try and 3634 * simulate something similar .. so this string should always 3635 * same -something- about the processor, however lame. 3636 */ 3637 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3638 "brand-string", cpi->cpi_brandstr); 3639 3640 /* 3641 * Finally, cache and tlb information 3642 */ 3643 switch (x86_which_cacheinfo(cpi)) { 3644 case X86_VENDOR_Intel: 3645 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3646 break; 3647 case X86_VENDOR_Cyrix: 3648 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3649 break; 3650 case X86_VENDOR_AMD: 3651 amd_cache_info(cpi, cpu_devi); 3652 break; 3653 default: 3654 break; 3655 } 3656 3657 mutex_exit(&cpu_node_lock); 3658 } 3659 3660 struct l2info { 3661 int *l2i_csz; 3662 int *l2i_lsz; 3663 int *l2i_assoc; 3664 int l2i_ret; 3665 }; 3666 3667 /* 3668 * A cacheinfo walker that fetches the size, line-size and associativity 3669 * of the L2 cache 3670 */ 3671 static int 3672 intel_l2cinfo(void *arg, const struct cachetab *ct) 3673 { 3674 struct l2info *l2i = arg; 3675 int *ip; 3676 3677 if (ct->ct_label != l2_cache_str && 3678 ct->ct_label != sl2_cache_str) 3679 return (0); /* not an L2 -- keep walking */ 3680 3681 if ((ip = l2i->l2i_csz) != NULL) 3682 *ip = ct->ct_size; 3683 if ((ip = l2i->l2i_lsz) != NULL) 3684 *ip = ct->ct_line_size; 3685 if ((ip = l2i->l2i_assoc) != NULL) 3686 *ip = ct->ct_assoc; 3687 l2i->l2i_ret = ct->ct_size; 3688 return (1); /* was an L2 -- terminate walk */ 3689 } 3690 3691 /* 3692 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3693 * 3694 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3695 * value is the associativity, the associativity for the L2 cache and 3696 * tlb is encoded in the following table. The 4 bit L2 value serves as 3697 * an index into the amd_afd[] array to determine the associativity. 3698 * -1 is undefined. 0 is fully associative. 3699 */ 3700 3701 static int amd_afd[] = 3702 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3703 3704 static void 3705 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3706 { 3707 struct cpuid_regs *cp; 3708 uint_t size, assoc; 3709 int i; 3710 int *ip; 3711 3712 if (cpi->cpi_xmaxeax < 0x80000006) 3713 return; 3714 cp = &cpi->cpi_extd[6]; 3715 3716 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3717 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3718 uint_t cachesz = size * 1024; 3719 assoc = amd_afd[i]; 3720 3721 ASSERT(assoc != -1); 3722 3723 if ((ip = l2i->l2i_csz) != NULL) 3724 *ip = cachesz; 3725 if ((ip = l2i->l2i_lsz) != NULL) 3726 *ip = BITX(cp->cp_ecx, 7, 0); 3727 if ((ip = l2i->l2i_assoc) != NULL) 3728 *ip = assoc; 3729 l2i->l2i_ret = cachesz; 3730 } 3731 } 3732 3733 int 3734 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3735 { 3736 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3737 struct l2info __l2info, *l2i = &__l2info; 3738 3739 l2i->l2i_csz = csz; 3740 l2i->l2i_lsz = lsz; 3741 l2i->l2i_assoc = assoc; 3742 l2i->l2i_ret = -1; 3743 3744 switch (x86_which_cacheinfo(cpi)) { 3745 case X86_VENDOR_Intel: 3746 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3747 break; 3748 case X86_VENDOR_Cyrix: 3749 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3750 break; 3751 case X86_VENDOR_AMD: 3752 amd_l2cacheinfo(cpi, l2i); 3753 break; 3754 default: 3755 break; 3756 } 3757 return (l2i->l2i_ret); 3758 } 3759 3760 #if !defined(__xpv) 3761 3762 uint32_t * 3763 cpuid_mwait_alloc(cpu_t *cpu) 3764 { 3765 uint32_t *ret; 3766 size_t mwait_size; 3767 3768 ASSERT(cpuid_checkpass(cpu, 2)); 3769 3770 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3771 if (mwait_size == 0) 3772 return (NULL); 3773 3774 /* 3775 * kmem_alloc() returns cache line size aligned data for mwait_size 3776 * allocations. mwait_size is currently cache line sized. Neither 3777 * of these implementation details are guarantied to be true in the 3778 * future. 3779 * 3780 * First try allocating mwait_size as kmem_alloc() currently returns 3781 * correctly aligned memory. If kmem_alloc() does not return 3782 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3783 * 3784 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3785 * decide to free this memory. 3786 */ 3787 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3788 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3789 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3790 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3791 *ret = MWAIT_RUNNING; 3792 return (ret); 3793 } else { 3794 kmem_free(ret, mwait_size); 3795 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3796 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3797 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3798 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3799 *ret = MWAIT_RUNNING; 3800 return (ret); 3801 } 3802 } 3803 3804 void 3805 cpuid_mwait_free(cpu_t *cpu) 3806 { 3807 ASSERT(cpuid_checkpass(cpu, 2)); 3808 3809 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3810 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3811 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3812 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3813 } 3814 3815 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3816 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3817 } 3818 3819 void 3820 patch_tsc_read(int flag) 3821 { 3822 size_t cnt; 3823 3824 switch (flag) { 3825 case X86_NO_TSC: 3826 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 3827 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 3828 break; 3829 case X86_HAVE_TSCP: 3830 cnt = &_tscp_end - &_tscp_start; 3831 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 3832 break; 3833 case X86_TSC_MFENCE: 3834 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 3835 (void) memcpy((void *)tsc_read, 3836 (void *)&_tsc_mfence_start, cnt); 3837 break; 3838 case X86_TSC_LFENCE: 3839 cnt = &_tsc_lfence_end - &_tsc_lfence_start; 3840 (void) memcpy((void *)tsc_read, 3841 (void *)&_tsc_lfence_start, cnt); 3842 break; 3843 default: 3844 break; 3845 } 3846 } 3847 3848 #if defined(__amd64) && !defined(__xpv) 3849 /* 3850 * Patch in versions of bcopy for high performance Intel Nhm processors 3851 * and later... 3852 */ 3853 void 3854 patch_memops(uint_t vendor) 3855 { 3856 size_t cnt, i; 3857 caddr_t to, from; 3858 3859 if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) { 3860 cnt = &bcopy_patch_end - &bcopy_patch_start; 3861 to = &bcopy_ck_size; 3862 from = &bcopy_patch_start; 3863 for (i = 0; i < cnt; i++) { 3864 *to++ = *from++; 3865 } 3866 } 3867 } 3868 #endif /* __amd64 && !__xpv */ 3869 3870 #endif /* !__xpv */ 3871