1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/sysmacros.h> 44 #include <sys/pg.h> 45 #include <sys/fp.h> 46 #include <sys/controlregs.h> 47 #include <sys/auxv_386.h> 48 #include <sys/bitmap.h> 49 #include <sys/memnode.h> 50 51 /* 52 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 53 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 54 * them accordingly. For most modern processors, feature detection occurs here 55 * in pass 1. 56 * 57 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 58 * for the boot CPU and does the basic analysis that the early kernel needs. 59 * x86_feature is set based on the return value of cpuid_pass1() of the boot 60 * CPU. 61 * 62 * Pass 1 includes: 63 * 64 * o Determining vendor/model/family/stepping and setting x86_type and 65 * x86_vendor accordingly. 66 * o Processing the feature flags returned by the cpuid instruction while 67 * applying any workarounds or tricks for the specific processor. 68 * o Mapping the feature flags into Solaris feature bits (X86_*). 69 * o Processing extended feature flags if supported by the processor, 70 * again while applying specific processor knowledge. 71 * o Determining the CMT characteristics of the system. 72 * 73 * Pass 1 is done on non-boot CPUs during their initialization and the results 74 * are used only as a meager attempt at ensuring that all processors within the 75 * system support the same features. 76 * 77 * Pass 2 of cpuid feature analysis happens just at the beginning 78 * of startup(). It just copies in and corrects the remainder 79 * of the cpuid data we depend on: standard cpuid functions that we didn't 80 * need for pass1 feature analysis, and extended cpuid functions beyond the 81 * simple feature processing done in pass1. 82 * 83 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 84 * particular kernel memory allocation has been made available. It creates a 85 * readable brand string based on the data collected in the first two passes. 86 * 87 * Pass 4 of cpuid analysis is invoked after post_startup() when all 88 * the support infrastructure for various hardware features has been 89 * initialized. It determines which processor features will be reported 90 * to userland via the aux vector. 91 * 92 * All passes are executed on all CPUs, but only the boot CPU determines what 93 * features the kernel will use. 94 * 95 * Much of the worst junk in this file is for the support of processors 96 * that didn't really implement the cpuid instruction properly. 97 * 98 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 99 * the pass numbers. Accordingly, changes to the pass code may require changes 100 * to the accessor code. 101 */ 102 103 uint_t x86_feature = 0; 104 uint_t x86_vendor = X86_VENDOR_IntelClone; 105 uint_t x86_type = X86_TYPE_OTHER; 106 107 uint_t pentiumpro_bug4046376; 108 uint_t pentiumpro_bug4064495; 109 110 uint_t enable486; 111 112 /* 113 * This set of strings are for processors rumored to support the cpuid 114 * instruction, and is used by locore.s to figure out how to set x86_vendor 115 */ 116 const char CyrixInstead[] = "CyrixInstead"; 117 118 /* 119 * monitor/mwait info. 120 * 121 * size_actual and buf_actual are the real address and size allocated to get 122 * proper mwait_buf alignement. buf_actual and size_actual should be passed 123 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 124 * processor cache-line alignment, but this is not guarantied in the furture. 125 */ 126 struct mwait_info { 127 size_t mon_min; /* min size to avoid missed wakeups */ 128 size_t mon_max; /* size to avoid false wakeups */ 129 size_t size_actual; /* size actually allocated */ 130 void *buf_actual; /* memory actually allocated */ 131 uint32_t support; /* processor support of monitor/mwait */ 132 }; 133 134 /* 135 * These constants determine how many of the elements of the 136 * cpuid we cache in the cpuid_info data structure; the 137 * remaining elements are accessible via the cpuid instruction. 138 */ 139 140 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 141 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 142 143 struct cpuid_info { 144 uint_t cpi_pass; /* last pass completed */ 145 /* 146 * standard function information 147 */ 148 uint_t cpi_maxeax; /* fn 0: %eax */ 149 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 150 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 151 152 uint_t cpi_family; /* fn 1: extended family */ 153 uint_t cpi_model; /* fn 1: extended model */ 154 uint_t cpi_step; /* fn 1: stepping */ 155 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 156 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 157 int cpi_clogid; /* fn 1: %ebx: thread # */ 158 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 159 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 160 uint_t cpi_ncache; /* fn 2: number of elements */ 161 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 162 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 163 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 164 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 165 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 166 /* 167 * extended function information 168 */ 169 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 170 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 171 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 172 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 173 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 174 id_t cpi_coreid; 175 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 176 /* Intel: fn 4: %eax[31-26] */ 177 /* 178 * supported feature information 179 */ 180 uint32_t cpi_support[5]; 181 #define STD_EDX_FEATURES 0 182 #define AMD_EDX_FEATURES 1 183 #define TM_EDX_FEATURES 2 184 #define STD_ECX_FEATURES 3 185 #define AMD_ECX_FEATURES 4 186 /* 187 * Synthesized information, where known. 188 */ 189 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 190 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 191 uint32_t cpi_socket; /* Chip package/socket type */ 192 193 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 194 }; 195 196 197 static struct cpuid_info cpuid_info0; 198 199 /* 200 * These bit fields are defined by the Intel Application Note AP-485 201 * "Intel Processor Identification and the CPUID Instruction" 202 */ 203 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 204 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 205 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 206 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 207 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 208 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 209 210 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 211 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 212 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 213 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 214 215 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 216 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 217 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 218 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 219 220 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 221 #define CPI_XMAXEAX_MAX 0x80000100 222 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 223 224 /* 225 * Function 4 (Deterministic Cache Parameters) macros 226 * Defined by Intel Application Note AP-485 227 */ 228 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 229 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 230 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 231 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 232 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 233 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 234 235 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 236 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 237 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 238 239 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 240 241 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 242 243 244 /* 245 * A couple of shorthand macros to identify "later" P6-family chips 246 * like the Pentium M and Core. First, the "older" P6-based stuff 247 * (loosely defined as "pre-Pentium-4"): 248 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 249 */ 250 251 #define IS_LEGACY_P6(cpi) ( \ 252 cpi->cpi_family == 6 && \ 253 (cpi->cpi_model == 1 || \ 254 cpi->cpi_model == 3 || \ 255 cpi->cpi_model == 5 || \ 256 cpi->cpi_model == 6 || \ 257 cpi->cpi_model == 7 || \ 258 cpi->cpi_model == 8 || \ 259 cpi->cpi_model == 0xA || \ 260 cpi->cpi_model == 0xB) \ 261 ) 262 263 /* A "new F6" is everything with family 6 that's not the above */ 264 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 265 266 /* Extended family/model support */ 267 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 268 cpi->cpi_family >= 0xf) 269 270 /* 271 * AMD family 0xf and family 0x10 socket types. 272 * First index : 273 * 0 for family 0xf, revs B thru E 274 * 1 for family 0xf, revs F and G 275 * 2 for family 0x10, rev B 276 * Second index by (model & 0x3) 277 */ 278 static uint32_t amd_skts[3][4] = { 279 /* 280 * Family 0xf revisions B through E 281 */ 282 #define A_SKTS_0 0 283 { 284 X86_SOCKET_754, /* 0b00 */ 285 X86_SOCKET_940, /* 0b01 */ 286 X86_SOCKET_754, /* 0b10 */ 287 X86_SOCKET_939 /* 0b11 */ 288 }, 289 /* 290 * Family 0xf revisions F and G 291 */ 292 #define A_SKTS_1 1 293 { 294 X86_SOCKET_S1g1, /* 0b00 */ 295 X86_SOCKET_F1207, /* 0b01 */ 296 X86_SOCKET_UNKNOWN, /* 0b10 */ 297 X86_SOCKET_AM2 /* 0b11 */ 298 }, 299 /* 300 * Family 0x10 revisions A and B 301 * It is not clear whether, as new sockets release, that 302 * model & 0x3 will id socket for this family 303 */ 304 #define A_SKTS_2 2 305 { 306 X86_SOCKET_F1207, /* 0b00 */ 307 X86_SOCKET_F1207, /* 0b01 */ 308 X86_SOCKET_F1207, /* 0b10 */ 309 X86_SOCKET_F1207, /* 0b11 */ 310 } 311 }; 312 313 /* 314 * Table for mapping AMD Family 0xf and AMD Family 0x10 model/stepping 315 * combination to chip "revision" and socket type. 316 * 317 * The first member of this array that matches a given family, extended model 318 * plus model range, and stepping range will be considered a match. 319 */ 320 static const struct amd_rev_mapent { 321 uint_t rm_family; 322 uint_t rm_modello; 323 uint_t rm_modelhi; 324 uint_t rm_steplo; 325 uint_t rm_stephi; 326 uint32_t rm_chiprev; 327 const char *rm_chiprevstr; 328 int rm_sktidx; 329 } amd_revmap[] = { 330 /* 331 * =============== AuthenticAMD Family 0xf =============== 332 */ 333 334 /* 335 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 336 */ 337 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 338 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 339 /* 340 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 341 */ 342 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", A_SKTS_0 }, 343 /* 344 * Rev CG is the rest of extended model 0x0 - i.e., everything 345 * but the rev B and C0 combinations covered above. 346 */ 347 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", A_SKTS_0 }, 348 /* 349 * Rev D has extended model 0x1. 350 */ 351 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", A_SKTS_0 }, 352 /* 353 * Rev E has extended model 0x2. 354 * Extended model 0x3 is unused but available to grow into. 355 */ 356 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", A_SKTS_0 }, 357 /* 358 * Rev F has extended models 0x4 and 0x5. 359 */ 360 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", A_SKTS_1 }, 361 /* 362 * Rev G has extended model 0x6. 363 */ 364 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", A_SKTS_1 }, 365 366 /* 367 * =============== AuthenticAMD Family 0x10 =============== 368 */ 369 370 /* 371 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}. 372 * Give all of model 0 stepping range to rev A. 373 */ 374 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_A, "A", A_SKTS_2 }, 375 376 /* 377 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}. 378 * Give all of model 2 stepping range to rev B. 379 */ 380 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_B, "B", A_SKTS_2 }, 381 }; 382 383 /* 384 * Info for monitor/mwait idle loop. 385 * 386 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 387 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 388 * 2006. 389 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 390 * Documentation Updates" #33633, Rev 2.05, December 2006. 391 */ 392 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 393 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 394 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 395 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 396 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 397 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 398 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 399 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 400 /* 401 * Number of sub-cstates for a given c-state. 402 */ 403 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 404 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 405 406 static void intel_cpuid_4_cache_info(void *, struct cpuid_info *); 407 408 static void 409 synth_amd_info(struct cpuid_info *cpi) 410 { 411 const struct amd_rev_mapent *rmp; 412 uint_t family, model, step; 413 int i; 414 415 /* 416 * Currently only AMD family 0xf and family 0x10 use these fields. 417 */ 418 if (cpi->cpi_family != 0xf && cpi->cpi_family != 0x10) 419 return; 420 421 family = cpi->cpi_family; 422 model = cpi->cpi_model; 423 step = cpi->cpi_step; 424 425 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); 426 i++, rmp++) { 427 if (family == rmp->rm_family && 428 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 429 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 430 cpi->cpi_chiprev = rmp->rm_chiprev; 431 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; 432 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; 433 return; 434 } 435 } 436 } 437 438 static void 439 synth_info(struct cpuid_info *cpi) 440 { 441 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; 442 cpi->cpi_chiprevstr = "Unknown"; 443 cpi->cpi_socket = X86_SOCKET_UNKNOWN; 444 445 switch (cpi->cpi_vendor) { 446 case X86_VENDOR_AMD: 447 synth_amd_info(cpi); 448 break; 449 450 default: 451 break; 452 453 } 454 } 455 456 /* 457 * Apply up various platform-dependent restrictions where the 458 * underlying platform restrictions mean the CPU can be marked 459 * as less capable than its cpuid instruction would imply. 460 */ 461 #if defined(__xpv) 462 static void 463 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 464 { 465 switch (eax) { 466 case 1: 467 cp->cp_edx &= 468 ~(CPUID_INTC_EDX_PSE | 469 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 470 CPUID_INTC_EDX_MCA | /* XXPV true on dom0? */ 471 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 472 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 473 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 474 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 475 break; 476 477 case 0x80000001: 478 cp->cp_edx &= 479 ~(CPUID_AMD_EDX_PSE | 480 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 481 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 482 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 483 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 484 CPUID_AMD_EDX_TSCP); 485 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 486 break; 487 default: 488 break; 489 } 490 491 switch (vendor) { 492 case X86_VENDOR_Intel: 493 switch (eax) { 494 case 4: 495 /* 496 * Zero out the (ncores-per-chip - 1) field 497 */ 498 cp->cp_eax &= 0x03fffffff; 499 break; 500 default: 501 break; 502 } 503 break; 504 case X86_VENDOR_AMD: 505 switch (eax) { 506 case 0x80000008: 507 /* 508 * Zero out the (ncores-per-chip - 1) field 509 */ 510 cp->cp_ecx &= 0xffffff00; 511 break; 512 default: 513 break; 514 } 515 break; 516 default: 517 break; 518 } 519 } 520 #else 521 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 522 #endif 523 524 /* 525 * Some undocumented ways of patching the results of the cpuid 526 * instruction to permit running Solaris 10 on future cpus that 527 * we don't currently support. Could be set to non-zero values 528 * via settings in eeprom. 529 */ 530 531 uint32_t cpuid_feature_ecx_include; 532 uint32_t cpuid_feature_ecx_exclude; 533 uint32_t cpuid_feature_edx_include; 534 uint32_t cpuid_feature_edx_exclude; 535 536 void 537 cpuid_alloc_space(cpu_t *cpu) 538 { 539 /* 540 * By convention, cpu0 is the boot cpu, which is set up 541 * before memory allocation is available. All other cpus get 542 * their cpuid_info struct allocated here. 543 */ 544 ASSERT(cpu->cpu_id != 0); 545 cpu->cpu_m.mcpu_cpi = 546 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 547 } 548 549 void 550 cpuid_free_space(cpu_t *cpu) 551 { 552 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 553 int i; 554 555 ASSERT(cpu->cpu_id != 0); 556 557 /* 558 * Free up any function 4 related dynamic storage 559 */ 560 for (i = 1; i < cpi->cpi_std_4_size; i++) 561 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 562 if (cpi->cpi_std_4_size > 0) 563 kmem_free(cpi->cpi_std_4, 564 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 565 566 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 567 } 568 569 uint_t 570 cpuid_pass1(cpu_t *cpu) 571 { 572 uint32_t mask_ecx, mask_edx; 573 uint_t feature = X86_CPUID; 574 struct cpuid_info *cpi; 575 struct cpuid_regs *cp; 576 int xcpuid; 577 #if !defined(__xpv) 578 extern int idle_cpu_prefer_mwait; 579 #endif 580 581 /* 582 * Space statically allocated for cpu0, ensure pointer is set 583 */ 584 if (cpu->cpu_id == 0) 585 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 586 cpi = cpu->cpu_m.mcpu_cpi; 587 ASSERT(cpi != NULL); 588 cp = &cpi->cpi_std[0]; 589 cp->cp_eax = 0; 590 cpi->cpi_maxeax = __cpuid_insn(cp); 591 { 592 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 593 *iptr++ = cp->cp_ebx; 594 *iptr++ = cp->cp_edx; 595 *iptr++ = cp->cp_ecx; 596 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 597 } 598 599 /* 600 * Map the vendor string to a type code 601 */ 602 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 603 cpi->cpi_vendor = X86_VENDOR_Intel; 604 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 605 cpi->cpi_vendor = X86_VENDOR_AMD; 606 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 607 cpi->cpi_vendor = X86_VENDOR_TM; 608 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 609 /* 610 * CyrixInstead is a variable used by the Cyrix detection code 611 * in locore. 612 */ 613 cpi->cpi_vendor = X86_VENDOR_Cyrix; 614 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 615 cpi->cpi_vendor = X86_VENDOR_UMC; 616 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 617 cpi->cpi_vendor = X86_VENDOR_NexGen; 618 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 619 cpi->cpi_vendor = X86_VENDOR_Centaur; 620 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 621 cpi->cpi_vendor = X86_VENDOR_Rise; 622 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 623 cpi->cpi_vendor = X86_VENDOR_SiS; 624 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 625 cpi->cpi_vendor = X86_VENDOR_NSC; 626 else 627 cpi->cpi_vendor = X86_VENDOR_IntelClone; 628 629 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 630 631 /* 632 * Limit the range in case of weird hardware 633 */ 634 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 635 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 636 if (cpi->cpi_maxeax < 1) 637 goto pass1_done; 638 639 cp = &cpi->cpi_std[1]; 640 cp->cp_eax = 1; 641 (void) __cpuid_insn(cp); 642 643 /* 644 * Extract identifying constants for easy access. 645 */ 646 cpi->cpi_model = CPI_MODEL(cpi); 647 cpi->cpi_family = CPI_FAMILY(cpi); 648 649 if (cpi->cpi_family == 0xf) 650 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 651 652 /* 653 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 654 * Intel, and presumably everyone else, uses model == 0xf, as 655 * one would expect (max value means possible overflow). Sigh. 656 */ 657 658 switch (cpi->cpi_vendor) { 659 case X86_VENDOR_Intel: 660 if (IS_EXTENDED_MODEL_INTEL(cpi)) 661 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 662 break; 663 case X86_VENDOR_AMD: 664 if (CPI_FAMILY(cpi) == 0xf) 665 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 666 break; 667 default: 668 if (cpi->cpi_model == 0xf) 669 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 670 break; 671 } 672 673 cpi->cpi_step = CPI_STEP(cpi); 674 cpi->cpi_brandid = CPI_BRANDID(cpi); 675 676 /* 677 * *default* assumptions: 678 * - believe %edx feature word 679 * - ignore %ecx feature word 680 * - 32-bit virtual and physical addressing 681 */ 682 mask_edx = 0xffffffff; 683 mask_ecx = 0; 684 685 cpi->cpi_pabits = cpi->cpi_vabits = 32; 686 687 switch (cpi->cpi_vendor) { 688 case X86_VENDOR_Intel: 689 if (cpi->cpi_family == 5) 690 x86_type = X86_TYPE_P5; 691 else if (IS_LEGACY_P6(cpi)) { 692 x86_type = X86_TYPE_P6; 693 pentiumpro_bug4046376 = 1; 694 pentiumpro_bug4064495 = 1; 695 /* 696 * Clear the SEP bit when it was set erroneously 697 */ 698 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 699 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 700 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 701 x86_type = X86_TYPE_P4; 702 /* 703 * We don't currently depend on any of the %ecx 704 * features until Prescott, so we'll only check 705 * this from P4 onwards. We might want to revisit 706 * that idea later. 707 */ 708 mask_ecx = 0xffffffff; 709 } else if (cpi->cpi_family > 0xf) 710 mask_ecx = 0xffffffff; 711 /* 712 * We don't support MONITOR/MWAIT if leaf 5 is not available 713 * to obtain the monitor linesize. 714 */ 715 if (cpi->cpi_maxeax < 5) 716 mask_ecx &= ~CPUID_INTC_ECX_MON; 717 break; 718 case X86_VENDOR_IntelClone: 719 default: 720 break; 721 case X86_VENDOR_AMD: 722 #if defined(OPTERON_ERRATUM_108) 723 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 724 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 725 cpi->cpi_model = 0xc; 726 } else 727 #endif 728 if (cpi->cpi_family == 5) { 729 /* 730 * AMD K5 and K6 731 * 732 * These CPUs have an incomplete implementation 733 * of MCA/MCE which we mask away. 734 */ 735 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 736 737 /* 738 * Model 0 uses the wrong (APIC) bit 739 * to indicate PGE. Fix it here. 740 */ 741 if (cpi->cpi_model == 0) { 742 if (cp->cp_edx & 0x200) { 743 cp->cp_edx &= ~0x200; 744 cp->cp_edx |= CPUID_INTC_EDX_PGE; 745 } 746 } 747 748 /* 749 * Early models had problems w/ MMX; disable. 750 */ 751 if (cpi->cpi_model < 6) 752 mask_edx &= ~CPUID_INTC_EDX_MMX; 753 } 754 755 /* 756 * For newer families, SSE3 and CX16, at least, are valid; 757 * enable all 758 */ 759 if (cpi->cpi_family >= 0xf) 760 mask_ecx = 0xffffffff; 761 /* 762 * We don't support MONITOR/MWAIT if leaf 5 is not available 763 * to obtain the monitor linesize. 764 */ 765 if (cpi->cpi_maxeax < 5) 766 mask_ecx &= ~CPUID_INTC_ECX_MON; 767 768 #if !defined(__xpv) 769 /* 770 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 771 * processors. AMD does not intend MWAIT to be used in the cpu 772 * idle loop on current and future processors. 10h and future 773 * AMD processors use more power in MWAIT than HLT. 774 * Pre-family-10h Opterons do not have the MWAIT instruction. 775 */ 776 idle_cpu_prefer_mwait = 0; 777 #endif 778 779 break; 780 case X86_VENDOR_TM: 781 /* 782 * workaround the NT workaround in CMS 4.1 783 */ 784 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 785 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 786 cp->cp_edx |= CPUID_INTC_EDX_CX8; 787 break; 788 case X86_VENDOR_Centaur: 789 /* 790 * workaround the NT workarounds again 791 */ 792 if (cpi->cpi_family == 6) 793 cp->cp_edx |= CPUID_INTC_EDX_CX8; 794 break; 795 case X86_VENDOR_Cyrix: 796 /* 797 * We rely heavily on the probing in locore 798 * to actually figure out what parts, if any, 799 * of the Cyrix cpuid instruction to believe. 800 */ 801 switch (x86_type) { 802 case X86_TYPE_CYRIX_486: 803 mask_edx = 0; 804 break; 805 case X86_TYPE_CYRIX_6x86: 806 mask_edx = 0; 807 break; 808 case X86_TYPE_CYRIX_6x86L: 809 mask_edx = 810 CPUID_INTC_EDX_DE | 811 CPUID_INTC_EDX_CX8; 812 break; 813 case X86_TYPE_CYRIX_6x86MX: 814 mask_edx = 815 CPUID_INTC_EDX_DE | 816 CPUID_INTC_EDX_MSR | 817 CPUID_INTC_EDX_CX8 | 818 CPUID_INTC_EDX_PGE | 819 CPUID_INTC_EDX_CMOV | 820 CPUID_INTC_EDX_MMX; 821 break; 822 case X86_TYPE_CYRIX_GXm: 823 mask_edx = 824 CPUID_INTC_EDX_MSR | 825 CPUID_INTC_EDX_CX8 | 826 CPUID_INTC_EDX_CMOV | 827 CPUID_INTC_EDX_MMX; 828 break; 829 case X86_TYPE_CYRIX_MediaGX: 830 break; 831 case X86_TYPE_CYRIX_MII: 832 case X86_TYPE_VIA_CYRIX_III: 833 mask_edx = 834 CPUID_INTC_EDX_DE | 835 CPUID_INTC_EDX_TSC | 836 CPUID_INTC_EDX_MSR | 837 CPUID_INTC_EDX_CX8 | 838 CPUID_INTC_EDX_PGE | 839 CPUID_INTC_EDX_CMOV | 840 CPUID_INTC_EDX_MMX; 841 break; 842 default: 843 break; 844 } 845 break; 846 } 847 848 #if defined(__xpv) 849 /* 850 * Do not support MONITOR/MWAIT under a hypervisor 851 */ 852 mask_ecx &= ~CPUID_INTC_ECX_MON; 853 #endif /* __xpv */ 854 855 /* 856 * Now we've figured out the masks that determine 857 * which bits we choose to believe, apply the masks 858 * to the feature words, then map the kernel's view 859 * of these feature words into its feature word. 860 */ 861 cp->cp_edx &= mask_edx; 862 cp->cp_ecx &= mask_ecx; 863 864 /* 865 * apply any platform restrictions (we don't call this 866 * immediately after __cpuid_insn here, because we need the 867 * workarounds applied above first) 868 */ 869 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 870 871 /* 872 * fold in overrides from the "eeprom" mechanism 873 */ 874 cp->cp_edx |= cpuid_feature_edx_include; 875 cp->cp_edx &= ~cpuid_feature_edx_exclude; 876 877 cp->cp_ecx |= cpuid_feature_ecx_include; 878 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 879 880 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 881 feature |= X86_LARGEPAGE; 882 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 883 feature |= X86_TSC; 884 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 885 feature |= X86_MSR; 886 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 887 feature |= X86_MTRR; 888 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 889 feature |= X86_PGE; 890 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 891 feature |= X86_CMOV; 892 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 893 feature |= X86_MMX; 894 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 895 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 896 feature |= X86_MCA; 897 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 898 feature |= X86_PAE; 899 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 900 feature |= X86_CX8; 901 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 902 feature |= X86_CX16; 903 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 904 feature |= X86_PAT; 905 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 906 feature |= X86_SEP; 907 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 908 /* 909 * In our implementation, fxsave/fxrstor 910 * are prerequisites before we'll even 911 * try and do SSE things. 912 */ 913 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 914 feature |= X86_SSE; 915 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 916 feature |= X86_SSE2; 917 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 918 feature |= X86_SSE3; 919 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 920 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 921 feature |= X86_SSSE3; 922 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 923 feature |= X86_SSE4_1; 924 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 925 feature |= X86_SSE4_2; 926 } 927 } 928 if (cp->cp_edx & CPUID_INTC_EDX_DE) 929 feature |= X86_DE; 930 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 931 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 932 feature |= X86_MWAIT; 933 } 934 935 if (feature & X86_PAE) 936 cpi->cpi_pabits = 36; 937 938 /* 939 * Hyperthreading configuration is slightly tricky on Intel 940 * and pure clones, and even trickier on AMD. 941 * 942 * (AMD chose to set the HTT bit on their CMP processors, 943 * even though they're not actually hyperthreaded. Thus it 944 * takes a bit more work to figure out what's really going 945 * on ... see the handling of the CMP_LGCY bit below) 946 */ 947 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 948 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 949 if (cpi->cpi_ncpu_per_chip > 1) 950 feature |= X86_HTT; 951 } else { 952 cpi->cpi_ncpu_per_chip = 1; 953 } 954 955 /* 956 * Work on the "extended" feature information, doing 957 * some basic initialization for cpuid_pass2() 958 */ 959 xcpuid = 0; 960 switch (cpi->cpi_vendor) { 961 case X86_VENDOR_Intel: 962 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 963 xcpuid++; 964 break; 965 case X86_VENDOR_AMD: 966 if (cpi->cpi_family > 5 || 967 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 968 xcpuid++; 969 break; 970 case X86_VENDOR_Cyrix: 971 /* 972 * Only these Cyrix CPUs are -known- to support 973 * extended cpuid operations. 974 */ 975 if (x86_type == X86_TYPE_VIA_CYRIX_III || 976 x86_type == X86_TYPE_CYRIX_GXm) 977 xcpuid++; 978 break; 979 case X86_VENDOR_Centaur: 980 case X86_VENDOR_TM: 981 default: 982 xcpuid++; 983 break; 984 } 985 986 if (xcpuid) { 987 cp = &cpi->cpi_extd[0]; 988 cp->cp_eax = 0x80000000; 989 cpi->cpi_xmaxeax = __cpuid_insn(cp); 990 } 991 992 if (cpi->cpi_xmaxeax & 0x80000000) { 993 994 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 995 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 996 997 switch (cpi->cpi_vendor) { 998 case X86_VENDOR_Intel: 999 case X86_VENDOR_AMD: 1000 if (cpi->cpi_xmaxeax < 0x80000001) 1001 break; 1002 cp = &cpi->cpi_extd[1]; 1003 cp->cp_eax = 0x80000001; 1004 (void) __cpuid_insn(cp); 1005 1006 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1007 cpi->cpi_family == 5 && 1008 cpi->cpi_model == 6 && 1009 cpi->cpi_step == 6) { 1010 /* 1011 * K6 model 6 uses bit 10 to indicate SYSC 1012 * Later models use bit 11. Fix it here. 1013 */ 1014 if (cp->cp_edx & 0x400) { 1015 cp->cp_edx &= ~0x400; 1016 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 1017 } 1018 } 1019 1020 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 1021 1022 /* 1023 * Compute the additions to the kernel's feature word. 1024 */ 1025 if (cp->cp_edx & CPUID_AMD_EDX_NX) 1026 feature |= X86_NX; 1027 1028 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 1029 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 1030 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 1031 feature |= X86_SSE4A; 1032 1033 /* 1034 * If both the HTT and CMP_LGCY bits are set, 1035 * then we're not actually HyperThreaded. Read 1036 * "AMD CPUID Specification" for more details. 1037 */ 1038 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1039 (feature & X86_HTT) && 1040 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 1041 feature &= ~X86_HTT; 1042 feature |= X86_CMP; 1043 } 1044 #if defined(__amd64) 1045 /* 1046 * It's really tricky to support syscall/sysret in 1047 * the i386 kernel; we rely on sysenter/sysexit 1048 * instead. In the amd64 kernel, things are -way- 1049 * better. 1050 */ 1051 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 1052 feature |= X86_ASYSC; 1053 1054 /* 1055 * While we're thinking about system calls, note 1056 * that AMD processors don't support sysenter 1057 * in long mode at all, so don't try to program them. 1058 */ 1059 if (x86_vendor == X86_VENDOR_AMD) 1060 feature &= ~X86_SEP; 1061 #endif 1062 if (x86_vendor == X86_VENDOR_AMD && 1063 cp->cp_edx & CPUID_AMD_EDX_TSCP) 1064 feature |= X86_TSCP; 1065 break; 1066 default: 1067 break; 1068 } 1069 1070 /* 1071 * Get CPUID data about processor cores and hyperthreads. 1072 */ 1073 switch (cpi->cpi_vendor) { 1074 case X86_VENDOR_Intel: 1075 if (cpi->cpi_maxeax >= 4) { 1076 cp = &cpi->cpi_std[4]; 1077 cp->cp_eax = 4; 1078 cp->cp_ecx = 0; 1079 (void) __cpuid_insn(cp); 1080 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 1081 } 1082 /*FALLTHROUGH*/ 1083 case X86_VENDOR_AMD: 1084 if (cpi->cpi_xmaxeax < 0x80000008) 1085 break; 1086 cp = &cpi->cpi_extd[8]; 1087 cp->cp_eax = 0x80000008; 1088 (void) __cpuid_insn(cp); 1089 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1090 1091 /* 1092 * Virtual and physical address limits from 1093 * cpuid override previously guessed values. 1094 */ 1095 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1096 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1097 break; 1098 default: 1099 break; 1100 } 1101 1102 /* 1103 * Derive the number of cores per chip 1104 */ 1105 switch (cpi->cpi_vendor) { 1106 case X86_VENDOR_Intel: 1107 if (cpi->cpi_maxeax < 4) { 1108 cpi->cpi_ncore_per_chip = 1; 1109 break; 1110 } else { 1111 cpi->cpi_ncore_per_chip = 1112 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1113 } 1114 break; 1115 case X86_VENDOR_AMD: 1116 if (cpi->cpi_xmaxeax < 0x80000008) { 1117 cpi->cpi_ncore_per_chip = 1; 1118 break; 1119 } else { 1120 cpi->cpi_ncore_per_chip = 1121 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1122 } 1123 break; 1124 default: 1125 cpi->cpi_ncore_per_chip = 1; 1126 break; 1127 } 1128 } else { 1129 cpi->cpi_ncore_per_chip = 1; 1130 } 1131 1132 /* 1133 * If more than one core, then this processor is CMP. 1134 */ 1135 if (cpi->cpi_ncore_per_chip > 1) 1136 feature |= X86_CMP; 1137 1138 /* 1139 * If the number of cores is the same as the number 1140 * of CPUs, then we cannot have HyperThreading. 1141 */ 1142 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1143 feature &= ~X86_HTT; 1144 1145 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1146 /* 1147 * Single-core single-threaded processors. 1148 */ 1149 cpi->cpi_chipid = -1; 1150 cpi->cpi_clogid = 0; 1151 cpi->cpi_coreid = cpu->cpu_id; 1152 } else if (cpi->cpi_ncpu_per_chip > 1) { 1153 uint_t i; 1154 uint_t chipid_shift = 0; 1155 uint_t coreid_shift = 0; 1156 uint_t apic_id = CPI_APIC_ID(cpi); 1157 1158 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1159 chipid_shift++; 1160 cpi->cpi_chipid = apic_id >> chipid_shift; 1161 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1162 1163 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1164 if (feature & X86_CMP) { 1165 /* 1166 * Multi-core (and possibly multi-threaded) 1167 * processors. 1168 */ 1169 uint_t ncpu_per_core; 1170 if (cpi->cpi_ncore_per_chip == 1) 1171 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1172 else if (cpi->cpi_ncore_per_chip > 1) 1173 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1174 cpi->cpi_ncore_per_chip; 1175 /* 1176 * 8bit APIC IDs on dual core Pentiums 1177 * look like this: 1178 * 1179 * +-----------------------+------+------+ 1180 * | Physical Package ID | MC | HT | 1181 * +-----------------------+------+------+ 1182 * <------- chipid --------> 1183 * <------- coreid ---------------> 1184 * <--- clogid --> 1185 * 1186 * Where the number of bits necessary to 1187 * represent MC and HT fields together equals 1188 * to the minimum number of bits necessary to 1189 * store the value of cpi->cpi_ncpu_per_chip. 1190 * Of those bits, the MC part uses the number 1191 * of bits necessary to store the value of 1192 * cpi->cpi_ncore_per_chip. 1193 */ 1194 for (i = 1; i < ncpu_per_core; i <<= 1) 1195 coreid_shift++; 1196 cpi->cpi_coreid = apic_id >> coreid_shift; 1197 } else if (feature & X86_HTT) { 1198 /* 1199 * Single-core multi-threaded processors. 1200 */ 1201 cpi->cpi_coreid = cpi->cpi_chipid; 1202 } 1203 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1204 /* 1205 * AMD currently only has dual-core processors with 1206 * single-threaded cores. If they ever release 1207 * multi-threaded processors, then this code 1208 * will have to be updated. 1209 */ 1210 cpi->cpi_coreid = cpu->cpu_id; 1211 } else { 1212 /* 1213 * All other processors are currently 1214 * assumed to have single cores. 1215 */ 1216 cpi->cpi_coreid = cpi->cpi_chipid; 1217 } 1218 } 1219 1220 /* 1221 * Synthesize chip "revision" and socket type 1222 */ 1223 synth_info(cpi); 1224 1225 pass1_done: 1226 cpi->cpi_pass = 1; 1227 return (feature); 1228 } 1229 1230 /* 1231 * Make copies of the cpuid table entries we depend on, in 1232 * part for ease of parsing now, in part so that we have only 1233 * one place to correct any of it, in part for ease of 1234 * later export to userland, and in part so we can look at 1235 * this stuff in a crash dump. 1236 */ 1237 1238 /*ARGSUSED*/ 1239 void 1240 cpuid_pass2(cpu_t *cpu) 1241 { 1242 uint_t n, nmax; 1243 int i; 1244 struct cpuid_regs *cp; 1245 uint8_t *dp; 1246 uint32_t *iptr; 1247 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1248 1249 ASSERT(cpi->cpi_pass == 1); 1250 1251 if (cpi->cpi_maxeax < 1) 1252 goto pass2_done; 1253 1254 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1255 nmax = NMAX_CPI_STD; 1256 /* 1257 * (We already handled n == 0 and n == 1 in pass 1) 1258 */ 1259 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1260 cp->cp_eax = n; 1261 1262 /* 1263 * CPUID function 4 expects %ecx to be initialized 1264 * with an index which indicates which cache to return 1265 * information about. The OS is expected to call function 4 1266 * with %ecx set to 0, 1, 2, ... until it returns with 1267 * EAX[4:0] set to 0, which indicates there are no more 1268 * caches. 1269 * 1270 * Here, populate cpi_std[4] with the information returned by 1271 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1272 * when dynamic memory allocation becomes available. 1273 * 1274 * Note: we need to explicitly initialize %ecx here, since 1275 * function 4 may have been previously invoked. 1276 */ 1277 if (n == 4) 1278 cp->cp_ecx = 0; 1279 1280 (void) __cpuid_insn(cp); 1281 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1282 switch (n) { 1283 case 2: 1284 /* 1285 * "the lower 8 bits of the %eax register 1286 * contain a value that identifies the number 1287 * of times the cpuid [instruction] has to be 1288 * executed to obtain a complete image of the 1289 * processor's caching systems." 1290 * 1291 * How *do* they make this stuff up? 1292 */ 1293 cpi->cpi_ncache = sizeof (*cp) * 1294 BITX(cp->cp_eax, 7, 0); 1295 if (cpi->cpi_ncache == 0) 1296 break; 1297 cpi->cpi_ncache--; /* skip count byte */ 1298 1299 /* 1300 * Well, for now, rather than attempt to implement 1301 * this slightly dubious algorithm, we just look 1302 * at the first 15 .. 1303 */ 1304 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1305 cpi->cpi_ncache = sizeof (*cp) - 1; 1306 1307 dp = cpi->cpi_cacheinfo; 1308 if (BITX(cp->cp_eax, 31, 31) == 0) { 1309 uint8_t *p = (void *)&cp->cp_eax; 1310 for (i = 1; i < 3; i++) 1311 if (p[i] != 0) 1312 *dp++ = p[i]; 1313 } 1314 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1315 uint8_t *p = (void *)&cp->cp_ebx; 1316 for (i = 0; i < 4; i++) 1317 if (p[i] != 0) 1318 *dp++ = p[i]; 1319 } 1320 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1321 uint8_t *p = (void *)&cp->cp_ecx; 1322 for (i = 0; i < 4; i++) 1323 if (p[i] != 0) 1324 *dp++ = p[i]; 1325 } 1326 if (BITX(cp->cp_edx, 31, 31) == 0) { 1327 uint8_t *p = (void *)&cp->cp_edx; 1328 for (i = 0; i < 4; i++) 1329 if (p[i] != 0) 1330 *dp++ = p[i]; 1331 } 1332 break; 1333 1334 case 3: /* Processor serial number, if PSN supported */ 1335 break; 1336 1337 case 4: /* Deterministic cache parameters */ 1338 break; 1339 1340 case 5: /* Monitor/Mwait parameters */ 1341 { 1342 size_t mwait_size; 1343 1344 /* 1345 * check cpi_mwait.support which was set in cpuid_pass1 1346 */ 1347 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1348 break; 1349 1350 /* 1351 * Protect ourself from insane mwait line size. 1352 * Workaround for incomplete hardware emulator(s). 1353 */ 1354 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1355 if (mwait_size < sizeof (uint32_t) || 1356 !ISP2(mwait_size)) { 1357 #if DEBUG 1358 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1359 "size %ld", 1360 cpu->cpu_id, (long)mwait_size); 1361 #endif 1362 break; 1363 } 1364 1365 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1366 cpi->cpi_mwait.mon_max = mwait_size; 1367 if (MWAIT_EXTENSION(cpi)) { 1368 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1369 if (MWAIT_INT_ENABLE(cpi)) 1370 cpi->cpi_mwait.support |= 1371 MWAIT_ECX_INT_ENABLE; 1372 } 1373 break; 1374 } 1375 default: 1376 break; 1377 } 1378 } 1379 1380 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1381 goto pass2_done; 1382 1383 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1384 nmax = NMAX_CPI_EXTD; 1385 /* 1386 * Copy the extended properties, fixing them as we go. 1387 * (We already handled n == 0 and n == 1 in pass 1) 1388 */ 1389 iptr = (void *)cpi->cpi_brandstr; 1390 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1391 cp->cp_eax = 0x80000000 + n; 1392 (void) __cpuid_insn(cp); 1393 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1394 switch (n) { 1395 case 2: 1396 case 3: 1397 case 4: 1398 /* 1399 * Extract the brand string 1400 */ 1401 *iptr++ = cp->cp_eax; 1402 *iptr++ = cp->cp_ebx; 1403 *iptr++ = cp->cp_ecx; 1404 *iptr++ = cp->cp_edx; 1405 break; 1406 case 5: 1407 switch (cpi->cpi_vendor) { 1408 case X86_VENDOR_AMD: 1409 /* 1410 * The Athlon and Duron were the first 1411 * parts to report the sizes of the 1412 * TLB for large pages. Before then, 1413 * we don't trust the data. 1414 */ 1415 if (cpi->cpi_family < 6 || 1416 (cpi->cpi_family == 6 && 1417 cpi->cpi_model < 1)) 1418 cp->cp_eax = 0; 1419 break; 1420 default: 1421 break; 1422 } 1423 break; 1424 case 6: 1425 switch (cpi->cpi_vendor) { 1426 case X86_VENDOR_AMD: 1427 /* 1428 * The Athlon and Duron were the first 1429 * AMD parts with L2 TLB's. 1430 * Before then, don't trust the data. 1431 */ 1432 if (cpi->cpi_family < 6 || 1433 cpi->cpi_family == 6 && 1434 cpi->cpi_model < 1) 1435 cp->cp_eax = cp->cp_ebx = 0; 1436 /* 1437 * AMD Duron rev A0 reports L2 1438 * cache size incorrectly as 1K 1439 * when it is really 64K 1440 */ 1441 if (cpi->cpi_family == 6 && 1442 cpi->cpi_model == 3 && 1443 cpi->cpi_step == 0) { 1444 cp->cp_ecx &= 0xffff; 1445 cp->cp_ecx |= 0x400000; 1446 } 1447 break; 1448 case X86_VENDOR_Cyrix: /* VIA C3 */ 1449 /* 1450 * VIA C3 processors are a bit messed 1451 * up w.r.t. encoding cache sizes in %ecx 1452 */ 1453 if (cpi->cpi_family != 6) 1454 break; 1455 /* 1456 * model 7 and 8 were incorrectly encoded 1457 * 1458 * xxx is model 8 really broken? 1459 */ 1460 if (cpi->cpi_model == 7 || 1461 cpi->cpi_model == 8) 1462 cp->cp_ecx = 1463 BITX(cp->cp_ecx, 31, 24) << 16 | 1464 BITX(cp->cp_ecx, 23, 16) << 12 | 1465 BITX(cp->cp_ecx, 15, 8) << 8 | 1466 BITX(cp->cp_ecx, 7, 0); 1467 /* 1468 * model 9 stepping 1 has wrong associativity 1469 */ 1470 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1471 cp->cp_ecx |= 8 << 12; 1472 break; 1473 case X86_VENDOR_Intel: 1474 /* 1475 * Extended L2 Cache features function. 1476 * First appeared on Prescott. 1477 */ 1478 default: 1479 break; 1480 } 1481 break; 1482 default: 1483 break; 1484 } 1485 } 1486 1487 pass2_done: 1488 cpi->cpi_pass = 2; 1489 } 1490 1491 static const char * 1492 intel_cpubrand(const struct cpuid_info *cpi) 1493 { 1494 int i; 1495 1496 if ((x86_feature & X86_CPUID) == 0 || 1497 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1498 return ("i486"); 1499 1500 switch (cpi->cpi_family) { 1501 case 5: 1502 return ("Intel Pentium(r)"); 1503 case 6: 1504 switch (cpi->cpi_model) { 1505 uint_t celeron, xeon; 1506 const struct cpuid_regs *cp; 1507 case 0: 1508 case 1: 1509 case 2: 1510 return ("Intel Pentium(r) Pro"); 1511 case 3: 1512 case 4: 1513 return ("Intel Pentium(r) II"); 1514 case 6: 1515 return ("Intel Celeron(r)"); 1516 case 5: 1517 case 7: 1518 celeron = xeon = 0; 1519 cp = &cpi->cpi_std[2]; /* cache info */ 1520 1521 for (i = 1; i < 3; i++) { 1522 uint_t tmp; 1523 1524 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1525 if (tmp == 0x40) 1526 celeron++; 1527 if (tmp >= 0x44 && tmp <= 0x45) 1528 xeon++; 1529 } 1530 1531 for (i = 0; i < 2; i++) { 1532 uint_t tmp; 1533 1534 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1535 if (tmp == 0x40) 1536 celeron++; 1537 else if (tmp >= 0x44 && tmp <= 0x45) 1538 xeon++; 1539 } 1540 1541 for (i = 0; i < 4; i++) { 1542 uint_t tmp; 1543 1544 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1545 if (tmp == 0x40) 1546 celeron++; 1547 else if (tmp >= 0x44 && tmp <= 0x45) 1548 xeon++; 1549 } 1550 1551 for (i = 0; i < 4; i++) { 1552 uint_t tmp; 1553 1554 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1555 if (tmp == 0x40) 1556 celeron++; 1557 else if (tmp >= 0x44 && tmp <= 0x45) 1558 xeon++; 1559 } 1560 1561 if (celeron) 1562 return ("Intel Celeron(r)"); 1563 if (xeon) 1564 return (cpi->cpi_model == 5 ? 1565 "Intel Pentium(r) II Xeon(tm)" : 1566 "Intel Pentium(r) III Xeon(tm)"); 1567 return (cpi->cpi_model == 5 ? 1568 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1569 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1570 default: 1571 break; 1572 } 1573 default: 1574 break; 1575 } 1576 1577 /* BrandID is present if the field is nonzero */ 1578 if (cpi->cpi_brandid != 0) { 1579 static const struct { 1580 uint_t bt_bid; 1581 const char *bt_str; 1582 } brand_tbl[] = { 1583 { 0x1, "Intel(r) Celeron(r)" }, 1584 { 0x2, "Intel(r) Pentium(r) III" }, 1585 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1586 { 0x4, "Intel(r) Pentium(r) III" }, 1587 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1588 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1589 { 0x8, "Intel(r) Pentium(r) 4" }, 1590 { 0x9, "Intel(r) Pentium(r) 4" }, 1591 { 0xa, "Intel(r) Celeron(r)" }, 1592 { 0xb, "Intel(r) Xeon(tm)" }, 1593 { 0xc, "Intel(r) Xeon(tm) MP" }, 1594 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1595 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1596 { 0x11, "Mobile Genuine Intel(r)" }, 1597 { 0x12, "Intel(r) Celeron(r) M" }, 1598 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1599 { 0x14, "Intel(r) Celeron(r)" }, 1600 { 0x15, "Mobile Genuine Intel(r)" }, 1601 { 0x16, "Intel(r) Pentium(r) M" }, 1602 { 0x17, "Mobile Intel(r) Celeron(r)" } 1603 }; 1604 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1605 uint_t sgn; 1606 1607 sgn = (cpi->cpi_family << 8) | 1608 (cpi->cpi_model << 4) | cpi->cpi_step; 1609 1610 for (i = 0; i < btblmax; i++) 1611 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1612 break; 1613 if (i < btblmax) { 1614 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1615 return ("Intel(r) Celeron(r)"); 1616 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1617 return ("Intel(r) Xeon(tm) MP"); 1618 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1619 return ("Intel(r) Xeon(tm)"); 1620 return (brand_tbl[i].bt_str); 1621 } 1622 } 1623 1624 return (NULL); 1625 } 1626 1627 static const char * 1628 amd_cpubrand(const struct cpuid_info *cpi) 1629 { 1630 if ((x86_feature & X86_CPUID) == 0 || 1631 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1632 return ("i486 compatible"); 1633 1634 switch (cpi->cpi_family) { 1635 case 5: 1636 switch (cpi->cpi_model) { 1637 case 0: 1638 case 1: 1639 case 2: 1640 case 3: 1641 case 4: 1642 case 5: 1643 return ("AMD-K5(r)"); 1644 case 6: 1645 case 7: 1646 return ("AMD-K6(r)"); 1647 case 8: 1648 return ("AMD-K6(r)-2"); 1649 case 9: 1650 return ("AMD-K6(r)-III"); 1651 default: 1652 return ("AMD (family 5)"); 1653 } 1654 case 6: 1655 switch (cpi->cpi_model) { 1656 case 1: 1657 return ("AMD-K7(tm)"); 1658 case 0: 1659 case 2: 1660 case 4: 1661 return ("AMD Athlon(tm)"); 1662 case 3: 1663 case 7: 1664 return ("AMD Duron(tm)"); 1665 case 6: 1666 case 8: 1667 case 10: 1668 /* 1669 * Use the L2 cache size to distinguish 1670 */ 1671 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1672 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1673 default: 1674 return ("AMD (family 6)"); 1675 } 1676 default: 1677 break; 1678 } 1679 1680 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1681 cpi->cpi_brandid != 0) { 1682 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1683 case 3: 1684 return ("AMD Opteron(tm) UP 1xx"); 1685 case 4: 1686 return ("AMD Opteron(tm) DP 2xx"); 1687 case 5: 1688 return ("AMD Opteron(tm) MP 8xx"); 1689 default: 1690 return ("AMD Opteron(tm)"); 1691 } 1692 } 1693 1694 return (NULL); 1695 } 1696 1697 static const char * 1698 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1699 { 1700 if ((x86_feature & X86_CPUID) == 0 || 1701 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1702 type == X86_TYPE_CYRIX_486) 1703 return ("i486 compatible"); 1704 1705 switch (type) { 1706 case X86_TYPE_CYRIX_6x86: 1707 return ("Cyrix 6x86"); 1708 case X86_TYPE_CYRIX_6x86L: 1709 return ("Cyrix 6x86L"); 1710 case X86_TYPE_CYRIX_6x86MX: 1711 return ("Cyrix 6x86MX"); 1712 case X86_TYPE_CYRIX_GXm: 1713 return ("Cyrix GXm"); 1714 case X86_TYPE_CYRIX_MediaGX: 1715 return ("Cyrix MediaGX"); 1716 case X86_TYPE_CYRIX_MII: 1717 return ("Cyrix M2"); 1718 case X86_TYPE_VIA_CYRIX_III: 1719 return ("VIA Cyrix M3"); 1720 default: 1721 /* 1722 * Have another wild guess .. 1723 */ 1724 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1725 return ("Cyrix 5x86"); 1726 else if (cpi->cpi_family == 5) { 1727 switch (cpi->cpi_model) { 1728 case 2: 1729 return ("Cyrix 6x86"); /* Cyrix M1 */ 1730 case 4: 1731 return ("Cyrix MediaGX"); 1732 default: 1733 break; 1734 } 1735 } else if (cpi->cpi_family == 6) { 1736 switch (cpi->cpi_model) { 1737 case 0: 1738 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1739 case 5: 1740 case 6: 1741 case 7: 1742 case 8: 1743 case 9: 1744 return ("VIA C3"); 1745 default: 1746 break; 1747 } 1748 } 1749 break; 1750 } 1751 return (NULL); 1752 } 1753 1754 /* 1755 * This only gets called in the case that the CPU extended 1756 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1757 * aren't available, or contain null bytes for some reason. 1758 */ 1759 static void 1760 fabricate_brandstr(struct cpuid_info *cpi) 1761 { 1762 const char *brand = NULL; 1763 1764 switch (cpi->cpi_vendor) { 1765 case X86_VENDOR_Intel: 1766 brand = intel_cpubrand(cpi); 1767 break; 1768 case X86_VENDOR_AMD: 1769 brand = amd_cpubrand(cpi); 1770 break; 1771 case X86_VENDOR_Cyrix: 1772 brand = cyrix_cpubrand(cpi, x86_type); 1773 break; 1774 case X86_VENDOR_NexGen: 1775 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1776 brand = "NexGen Nx586"; 1777 break; 1778 case X86_VENDOR_Centaur: 1779 if (cpi->cpi_family == 5) 1780 switch (cpi->cpi_model) { 1781 case 4: 1782 brand = "Centaur C6"; 1783 break; 1784 case 8: 1785 brand = "Centaur C2"; 1786 break; 1787 case 9: 1788 brand = "Centaur C3"; 1789 break; 1790 default: 1791 break; 1792 } 1793 break; 1794 case X86_VENDOR_Rise: 1795 if (cpi->cpi_family == 5 && 1796 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1797 brand = "Rise mP6"; 1798 break; 1799 case X86_VENDOR_SiS: 1800 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1801 brand = "SiS 55x"; 1802 break; 1803 case X86_VENDOR_TM: 1804 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1805 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1806 break; 1807 case X86_VENDOR_NSC: 1808 case X86_VENDOR_UMC: 1809 default: 1810 break; 1811 } 1812 if (brand) { 1813 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1814 return; 1815 } 1816 1817 /* 1818 * If all else fails ... 1819 */ 1820 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1821 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1822 cpi->cpi_model, cpi->cpi_step); 1823 } 1824 1825 /* 1826 * This routine is called just after kernel memory allocation 1827 * becomes available on cpu0, and as part of mp_startup() on 1828 * the other cpus. 1829 * 1830 * Fixup the brand string, and collect any information from cpuid 1831 * that requires dynamicically allocated storage to represent. 1832 */ 1833 /*ARGSUSED*/ 1834 void 1835 cpuid_pass3(cpu_t *cpu) 1836 { 1837 int i, max, shft, level, size; 1838 struct cpuid_regs regs; 1839 struct cpuid_regs *cp; 1840 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1841 1842 ASSERT(cpi->cpi_pass == 2); 1843 1844 /* 1845 * Function 4: Deterministic cache parameters 1846 * 1847 * Take this opportunity to detect the number of threads 1848 * sharing the last level cache, and construct a corresponding 1849 * cache id. The respective cpuid_info members are initialized 1850 * to the default case of "no last level cache sharing". 1851 */ 1852 cpi->cpi_ncpu_shr_last_cache = 1; 1853 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1854 1855 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1856 1857 /* 1858 * Find the # of elements (size) returned by fn 4, and along 1859 * the way detect last level cache sharing details. 1860 */ 1861 bzero(®s, sizeof (regs)); 1862 cp = ®s; 1863 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1864 cp->cp_eax = 4; 1865 cp->cp_ecx = i; 1866 1867 (void) __cpuid_insn(cp); 1868 1869 if (CPI_CACHE_TYPE(cp) == 0) 1870 break; 1871 level = CPI_CACHE_LVL(cp); 1872 if (level > max) { 1873 max = level; 1874 cpi->cpi_ncpu_shr_last_cache = 1875 CPI_NTHR_SHR_CACHE(cp) + 1; 1876 } 1877 } 1878 cpi->cpi_std_4_size = size = i; 1879 1880 /* 1881 * Allocate the cpi_std_4 array. The first element 1882 * references the regs for fn 4, %ecx == 0, which 1883 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1884 */ 1885 if (size > 0) { 1886 cpi->cpi_std_4 = 1887 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1888 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1889 1890 /* 1891 * Allocate storage to hold the additional regs 1892 * for function 4, %ecx == 1 .. cpi_std_4_size. 1893 * 1894 * The regs for fn 4, %ecx == 0 has already 1895 * been allocated as indicated above. 1896 */ 1897 for (i = 1; i < size; i++) { 1898 cp = cpi->cpi_std_4[i] = 1899 kmem_zalloc(sizeof (regs), KM_SLEEP); 1900 cp->cp_eax = 4; 1901 cp->cp_ecx = i; 1902 1903 (void) __cpuid_insn(cp); 1904 } 1905 } 1906 /* 1907 * Determine the number of bits needed to represent 1908 * the number of CPUs sharing the last level cache. 1909 * 1910 * Shift off that number of bits from the APIC id to 1911 * derive the cache id. 1912 */ 1913 shft = 0; 1914 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1915 shft++; 1916 cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft; 1917 } 1918 1919 /* 1920 * Now fixup the brand string 1921 */ 1922 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1923 fabricate_brandstr(cpi); 1924 } else { 1925 1926 /* 1927 * If we successfully extracted a brand string from the cpuid 1928 * instruction, clean it up by removing leading spaces and 1929 * similar junk. 1930 */ 1931 if (cpi->cpi_brandstr[0]) { 1932 size_t maxlen = sizeof (cpi->cpi_brandstr); 1933 char *src, *dst; 1934 1935 dst = src = (char *)cpi->cpi_brandstr; 1936 src[maxlen - 1] = '\0'; 1937 /* 1938 * strip leading spaces 1939 */ 1940 while (*src == ' ') 1941 src++; 1942 /* 1943 * Remove any 'Genuine' or "Authentic" prefixes 1944 */ 1945 if (strncmp(src, "Genuine ", 8) == 0) 1946 src += 8; 1947 if (strncmp(src, "Authentic ", 10) == 0) 1948 src += 10; 1949 1950 /* 1951 * Now do an in-place copy. 1952 * Map (R) to (r) and (TM) to (tm). 1953 * The era of teletypes is long gone, and there's 1954 * -really- no need to shout. 1955 */ 1956 while (*src != '\0') { 1957 if (src[0] == '(') { 1958 if (strncmp(src + 1, "R)", 2) == 0) { 1959 (void) strncpy(dst, "(r)", 3); 1960 src += 3; 1961 dst += 3; 1962 continue; 1963 } 1964 if (strncmp(src + 1, "TM)", 3) == 0) { 1965 (void) strncpy(dst, "(tm)", 4); 1966 src += 4; 1967 dst += 4; 1968 continue; 1969 } 1970 } 1971 *dst++ = *src++; 1972 } 1973 *dst = '\0'; 1974 1975 /* 1976 * Finally, remove any trailing spaces 1977 */ 1978 while (--dst > cpi->cpi_brandstr) 1979 if (*dst == ' ') 1980 *dst = '\0'; 1981 else 1982 break; 1983 } else 1984 fabricate_brandstr(cpi); 1985 } 1986 cpi->cpi_pass = 3; 1987 } 1988 1989 /* 1990 * This routine is called out of bind_hwcap() much later in the life 1991 * of the kernel (post_startup()). The job of this routine is to resolve 1992 * the hardware feature support and kernel support for those features into 1993 * what we're actually going to tell applications via the aux vector. 1994 */ 1995 uint_t 1996 cpuid_pass4(cpu_t *cpu) 1997 { 1998 struct cpuid_info *cpi; 1999 uint_t hwcap_flags = 0; 2000 2001 if (cpu == NULL) 2002 cpu = CPU; 2003 cpi = cpu->cpu_m.mcpu_cpi; 2004 2005 ASSERT(cpi->cpi_pass == 3); 2006 2007 if (cpi->cpi_maxeax >= 1) { 2008 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2009 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2010 2011 *edx = CPI_FEATURES_EDX(cpi); 2012 *ecx = CPI_FEATURES_ECX(cpi); 2013 2014 /* 2015 * [these require explicit kernel support] 2016 */ 2017 if ((x86_feature & X86_SEP) == 0) 2018 *edx &= ~CPUID_INTC_EDX_SEP; 2019 2020 if ((x86_feature & X86_SSE) == 0) 2021 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2022 if ((x86_feature & X86_SSE2) == 0) 2023 *edx &= ~CPUID_INTC_EDX_SSE2; 2024 2025 if ((x86_feature & X86_HTT) == 0) 2026 *edx &= ~CPUID_INTC_EDX_HTT; 2027 2028 if ((x86_feature & X86_SSE3) == 0) 2029 *ecx &= ~CPUID_INTC_ECX_SSE3; 2030 2031 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2032 if ((x86_feature & X86_SSSE3) == 0) 2033 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2034 if ((x86_feature & X86_SSE4_1) == 0) 2035 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2036 if ((x86_feature & X86_SSE4_2) == 0) 2037 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2038 } 2039 2040 /* 2041 * [no explicit support required beyond x87 fp context] 2042 */ 2043 if (!fpu_exists) 2044 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2045 2046 /* 2047 * Now map the supported feature vector to things that we 2048 * think userland will care about. 2049 */ 2050 if (*edx & CPUID_INTC_EDX_SEP) 2051 hwcap_flags |= AV_386_SEP; 2052 if (*edx & CPUID_INTC_EDX_SSE) 2053 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2054 if (*edx & CPUID_INTC_EDX_SSE2) 2055 hwcap_flags |= AV_386_SSE2; 2056 if (*ecx & CPUID_INTC_ECX_SSE3) 2057 hwcap_flags |= AV_386_SSE3; 2058 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2059 if (*ecx & CPUID_INTC_ECX_SSSE3) 2060 hwcap_flags |= AV_386_SSSE3; 2061 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2062 hwcap_flags |= AV_386_SSE4_1; 2063 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2064 hwcap_flags |= AV_386_SSE4_2; 2065 } 2066 if (*ecx & CPUID_INTC_ECX_POPCNT) 2067 hwcap_flags |= AV_386_POPCNT; 2068 if (*edx & CPUID_INTC_EDX_FPU) 2069 hwcap_flags |= AV_386_FPU; 2070 if (*edx & CPUID_INTC_EDX_MMX) 2071 hwcap_flags |= AV_386_MMX; 2072 2073 if (*edx & CPUID_INTC_EDX_TSC) 2074 hwcap_flags |= AV_386_TSC; 2075 if (*edx & CPUID_INTC_EDX_CX8) 2076 hwcap_flags |= AV_386_CX8; 2077 if (*edx & CPUID_INTC_EDX_CMOV) 2078 hwcap_flags |= AV_386_CMOV; 2079 if (*ecx & CPUID_INTC_ECX_MON) 2080 hwcap_flags |= AV_386_MON; 2081 if (*ecx & CPUID_INTC_ECX_CX16) 2082 hwcap_flags |= AV_386_CX16; 2083 } 2084 2085 if (x86_feature & X86_HTT) 2086 hwcap_flags |= AV_386_PAUSE; 2087 2088 if (cpi->cpi_xmaxeax < 0x80000001) 2089 goto pass4_done; 2090 2091 switch (cpi->cpi_vendor) { 2092 struct cpuid_regs cp; 2093 uint32_t *edx, *ecx; 2094 2095 case X86_VENDOR_Intel: 2096 /* 2097 * Seems like Intel duplicated what we necessary 2098 * here to make the initial crop of 64-bit OS's work. 2099 * Hopefully, those are the only "extended" bits 2100 * they'll add. 2101 */ 2102 /*FALLTHROUGH*/ 2103 2104 case X86_VENDOR_AMD: 2105 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2106 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2107 2108 *edx = CPI_FEATURES_XTD_EDX(cpi); 2109 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2110 2111 /* 2112 * [these features require explicit kernel support] 2113 */ 2114 switch (cpi->cpi_vendor) { 2115 case X86_VENDOR_Intel: 2116 break; 2117 2118 case X86_VENDOR_AMD: 2119 if ((x86_feature & X86_TSCP) == 0) 2120 *edx &= ~CPUID_AMD_EDX_TSCP; 2121 if ((x86_feature & X86_SSE4A) == 0) 2122 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2123 break; 2124 2125 default: 2126 break; 2127 } 2128 2129 /* 2130 * [no explicit support required beyond 2131 * x87 fp context and exception handlers] 2132 */ 2133 if (!fpu_exists) 2134 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2135 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2136 2137 if ((x86_feature & X86_NX) == 0) 2138 *edx &= ~CPUID_AMD_EDX_NX; 2139 #if !defined(__amd64) 2140 *edx &= ~CPUID_AMD_EDX_LM; 2141 #endif 2142 /* 2143 * Now map the supported feature vector to 2144 * things that we think userland will care about. 2145 */ 2146 #if defined(__amd64) 2147 if (*edx & CPUID_AMD_EDX_SYSC) 2148 hwcap_flags |= AV_386_AMD_SYSC; 2149 #endif 2150 if (*edx & CPUID_AMD_EDX_MMXamd) 2151 hwcap_flags |= AV_386_AMD_MMX; 2152 if (*edx & CPUID_AMD_EDX_3DNow) 2153 hwcap_flags |= AV_386_AMD_3DNow; 2154 if (*edx & CPUID_AMD_EDX_3DNowx) 2155 hwcap_flags |= AV_386_AMD_3DNowx; 2156 2157 switch (cpi->cpi_vendor) { 2158 case X86_VENDOR_AMD: 2159 if (*edx & CPUID_AMD_EDX_TSCP) 2160 hwcap_flags |= AV_386_TSCP; 2161 if (*ecx & CPUID_AMD_ECX_AHF64) 2162 hwcap_flags |= AV_386_AHF; 2163 if (*ecx & CPUID_AMD_ECX_SSE4A) 2164 hwcap_flags |= AV_386_AMD_SSE4A; 2165 if (*ecx & CPUID_AMD_ECX_LZCNT) 2166 hwcap_flags |= AV_386_AMD_LZCNT; 2167 break; 2168 2169 case X86_VENDOR_Intel: 2170 /* 2171 * Aarrgh. 2172 * Intel uses a different bit in the same word. 2173 */ 2174 if (*ecx & CPUID_INTC_ECX_AHF64) 2175 hwcap_flags |= AV_386_AHF; 2176 break; 2177 2178 default: 2179 break; 2180 } 2181 break; 2182 2183 case X86_VENDOR_TM: 2184 cp.cp_eax = 0x80860001; 2185 (void) __cpuid_insn(&cp); 2186 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2187 break; 2188 2189 default: 2190 break; 2191 } 2192 2193 pass4_done: 2194 cpi->cpi_pass = 4; 2195 return (hwcap_flags); 2196 } 2197 2198 2199 /* 2200 * Simulate the cpuid instruction using the data we previously 2201 * captured about this CPU. We try our best to return the truth 2202 * about the hardware, independently of kernel support. 2203 */ 2204 uint32_t 2205 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2206 { 2207 struct cpuid_info *cpi; 2208 struct cpuid_regs *xcp; 2209 2210 if (cpu == NULL) 2211 cpu = CPU; 2212 cpi = cpu->cpu_m.mcpu_cpi; 2213 2214 ASSERT(cpuid_checkpass(cpu, 3)); 2215 2216 /* 2217 * CPUID data is cached in two separate places: cpi_std for standard 2218 * CPUID functions, and cpi_extd for extended CPUID functions. 2219 */ 2220 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2221 xcp = &cpi->cpi_std[cp->cp_eax]; 2222 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2223 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2224 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2225 else 2226 /* 2227 * The caller is asking for data from an input parameter which 2228 * the kernel has not cached. In this case we go fetch from 2229 * the hardware and return the data directly to the user. 2230 */ 2231 return (__cpuid_insn(cp)); 2232 2233 cp->cp_eax = xcp->cp_eax; 2234 cp->cp_ebx = xcp->cp_ebx; 2235 cp->cp_ecx = xcp->cp_ecx; 2236 cp->cp_edx = xcp->cp_edx; 2237 return (cp->cp_eax); 2238 } 2239 2240 int 2241 cpuid_checkpass(cpu_t *cpu, int pass) 2242 { 2243 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2244 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2245 } 2246 2247 int 2248 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2249 { 2250 ASSERT(cpuid_checkpass(cpu, 3)); 2251 2252 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2253 } 2254 2255 int 2256 cpuid_is_cmt(cpu_t *cpu) 2257 { 2258 if (cpu == NULL) 2259 cpu = CPU; 2260 2261 ASSERT(cpuid_checkpass(cpu, 1)); 2262 2263 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2264 } 2265 2266 /* 2267 * AMD and Intel both implement the 64-bit variant of the syscall 2268 * instruction (syscallq), so if there's -any- support for syscall, 2269 * cpuid currently says "yes, we support this". 2270 * 2271 * However, Intel decided to -not- implement the 32-bit variant of the 2272 * syscall instruction, so we provide a predicate to allow our caller 2273 * to test that subtlety here. 2274 * 2275 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2276 * even in the case where the hardware would in fact support it. 2277 */ 2278 /*ARGSUSED*/ 2279 int 2280 cpuid_syscall32_insn(cpu_t *cpu) 2281 { 2282 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2283 2284 #if !defined(__xpv) 2285 if (cpu == NULL) 2286 cpu = CPU; 2287 2288 /*CSTYLED*/ 2289 { 2290 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2291 2292 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2293 cpi->cpi_xmaxeax >= 0x80000001 && 2294 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2295 return (1); 2296 } 2297 #endif 2298 return (0); 2299 } 2300 2301 int 2302 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2303 { 2304 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2305 2306 static const char fmt[] = 2307 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2308 static const char fmt_ht[] = 2309 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2310 2311 ASSERT(cpuid_checkpass(cpu, 1)); 2312 2313 if (cpuid_is_cmt(cpu)) 2314 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2315 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2316 cpi->cpi_family, cpi->cpi_model, 2317 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2318 return (snprintf(s, n, fmt, 2319 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2320 cpi->cpi_family, cpi->cpi_model, 2321 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2322 } 2323 2324 const char * 2325 cpuid_getvendorstr(cpu_t *cpu) 2326 { 2327 ASSERT(cpuid_checkpass(cpu, 1)); 2328 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2329 } 2330 2331 uint_t 2332 cpuid_getvendor(cpu_t *cpu) 2333 { 2334 ASSERT(cpuid_checkpass(cpu, 1)); 2335 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2336 } 2337 2338 uint_t 2339 cpuid_getfamily(cpu_t *cpu) 2340 { 2341 ASSERT(cpuid_checkpass(cpu, 1)); 2342 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2343 } 2344 2345 uint_t 2346 cpuid_getmodel(cpu_t *cpu) 2347 { 2348 ASSERT(cpuid_checkpass(cpu, 1)); 2349 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2350 } 2351 2352 uint_t 2353 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2354 { 2355 ASSERT(cpuid_checkpass(cpu, 1)); 2356 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2357 } 2358 2359 uint_t 2360 cpuid_get_ncore_per_chip(cpu_t *cpu) 2361 { 2362 ASSERT(cpuid_checkpass(cpu, 1)); 2363 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2364 } 2365 2366 uint_t 2367 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2368 { 2369 ASSERT(cpuid_checkpass(cpu, 2)); 2370 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2371 } 2372 2373 id_t 2374 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2375 { 2376 ASSERT(cpuid_checkpass(cpu, 2)); 2377 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2378 } 2379 2380 uint_t 2381 cpuid_getstep(cpu_t *cpu) 2382 { 2383 ASSERT(cpuid_checkpass(cpu, 1)); 2384 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2385 } 2386 2387 uint_t 2388 cpuid_getsig(struct cpu *cpu) 2389 { 2390 ASSERT(cpuid_checkpass(cpu, 1)); 2391 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2392 } 2393 2394 uint32_t 2395 cpuid_getchiprev(struct cpu *cpu) 2396 { 2397 ASSERT(cpuid_checkpass(cpu, 1)); 2398 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2399 } 2400 2401 const char * 2402 cpuid_getchiprevstr(struct cpu *cpu) 2403 { 2404 ASSERT(cpuid_checkpass(cpu, 1)); 2405 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2406 } 2407 2408 uint32_t 2409 cpuid_getsockettype(struct cpu *cpu) 2410 { 2411 ASSERT(cpuid_checkpass(cpu, 1)); 2412 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2413 } 2414 2415 int 2416 cpuid_get_chipid(cpu_t *cpu) 2417 { 2418 ASSERT(cpuid_checkpass(cpu, 1)); 2419 2420 if (cpuid_is_cmt(cpu)) 2421 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2422 return (cpu->cpu_id); 2423 } 2424 2425 id_t 2426 cpuid_get_coreid(cpu_t *cpu) 2427 { 2428 ASSERT(cpuid_checkpass(cpu, 1)); 2429 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2430 } 2431 2432 int 2433 cpuid_get_clogid(cpu_t *cpu) 2434 { 2435 ASSERT(cpuid_checkpass(cpu, 1)); 2436 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2437 } 2438 2439 void 2440 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2441 { 2442 struct cpuid_info *cpi; 2443 2444 if (cpu == NULL) 2445 cpu = CPU; 2446 cpi = cpu->cpu_m.mcpu_cpi; 2447 2448 ASSERT(cpuid_checkpass(cpu, 1)); 2449 2450 if (pabits) 2451 *pabits = cpi->cpi_pabits; 2452 if (vabits) 2453 *vabits = cpi->cpi_vabits; 2454 } 2455 2456 /* 2457 * Returns the number of data TLB entries for a corresponding 2458 * pagesize. If it can't be computed, or isn't known, the 2459 * routine returns zero. If you ask about an architecturally 2460 * impossible pagesize, the routine will panic (so that the 2461 * hat implementor knows that things are inconsistent.) 2462 */ 2463 uint_t 2464 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2465 { 2466 struct cpuid_info *cpi; 2467 uint_t dtlb_nent = 0; 2468 2469 if (cpu == NULL) 2470 cpu = CPU; 2471 cpi = cpu->cpu_m.mcpu_cpi; 2472 2473 ASSERT(cpuid_checkpass(cpu, 1)); 2474 2475 /* 2476 * Check the L2 TLB info 2477 */ 2478 if (cpi->cpi_xmaxeax >= 0x80000006) { 2479 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2480 2481 switch (pagesize) { 2482 2483 case 4 * 1024: 2484 /* 2485 * All zero in the top 16 bits of the register 2486 * indicates a unified TLB. Size is in low 16 bits. 2487 */ 2488 if ((cp->cp_ebx & 0xffff0000) == 0) 2489 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2490 else 2491 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2492 break; 2493 2494 case 2 * 1024 * 1024: 2495 if ((cp->cp_eax & 0xffff0000) == 0) 2496 dtlb_nent = cp->cp_eax & 0x0000ffff; 2497 else 2498 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2499 break; 2500 2501 default: 2502 panic("unknown L2 pagesize"); 2503 /*NOTREACHED*/ 2504 } 2505 } 2506 2507 if (dtlb_nent != 0) 2508 return (dtlb_nent); 2509 2510 /* 2511 * No L2 TLB support for this size, try L1. 2512 */ 2513 if (cpi->cpi_xmaxeax >= 0x80000005) { 2514 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2515 2516 switch (pagesize) { 2517 case 4 * 1024: 2518 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2519 break; 2520 case 2 * 1024 * 1024: 2521 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2522 break; 2523 default: 2524 panic("unknown L1 d-TLB pagesize"); 2525 /*NOTREACHED*/ 2526 } 2527 } 2528 2529 return (dtlb_nent); 2530 } 2531 2532 /* 2533 * Return 0 if the erratum is not present or not applicable, positive 2534 * if it is, and negative if the status of the erratum is unknown. 2535 * 2536 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2537 * Processors" #25759, Rev 3.57, August 2005 2538 */ 2539 int 2540 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2541 { 2542 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2543 uint_t eax; 2544 2545 /* 2546 * Bail out if this CPU isn't an AMD CPU, or if it's 2547 * a legacy (32-bit) AMD CPU. 2548 */ 2549 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2550 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2551 cpi->cpi_family == 6) 2552 2553 return (0); 2554 2555 eax = cpi->cpi_std[1].cp_eax; 2556 2557 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2558 #define SH_B3(eax) (eax == 0xf51) 2559 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2560 2561 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2562 2563 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2564 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2565 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2566 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2567 2568 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2569 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2570 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2571 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2572 2573 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2574 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2575 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2576 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2577 #define BH_E4(eax) (eax == 0x20fb1) 2578 #define SH_E5(eax) (eax == 0x20f42) 2579 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2580 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2581 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2582 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2583 DH_E6(eax) || JH_E6(eax)) 2584 2585 switch (erratum) { 2586 case 1: 2587 return (cpi->cpi_family < 0x10); 2588 case 51: /* what does the asterisk mean? */ 2589 return (B(eax) || SH_C0(eax) || CG(eax)); 2590 case 52: 2591 return (B(eax)); 2592 case 57: 2593 return (cpi->cpi_family <= 0x10); 2594 case 58: 2595 return (B(eax)); 2596 case 60: 2597 return (cpi->cpi_family <= 0x10); 2598 case 61: 2599 case 62: 2600 case 63: 2601 case 64: 2602 case 65: 2603 case 66: 2604 case 68: 2605 case 69: 2606 case 70: 2607 case 71: 2608 return (B(eax)); 2609 case 72: 2610 return (SH_B0(eax)); 2611 case 74: 2612 return (B(eax)); 2613 case 75: 2614 return (cpi->cpi_family < 0x10); 2615 case 76: 2616 return (B(eax)); 2617 case 77: 2618 return (cpi->cpi_family <= 0x10); 2619 case 78: 2620 return (B(eax) || SH_C0(eax)); 2621 case 79: 2622 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2623 case 80: 2624 case 81: 2625 case 82: 2626 return (B(eax)); 2627 case 83: 2628 return (B(eax) || SH_C0(eax) || CG(eax)); 2629 case 85: 2630 return (cpi->cpi_family < 0x10); 2631 case 86: 2632 return (SH_C0(eax) || CG(eax)); 2633 case 88: 2634 #if !defined(__amd64) 2635 return (0); 2636 #else 2637 return (B(eax) || SH_C0(eax)); 2638 #endif 2639 case 89: 2640 return (cpi->cpi_family < 0x10); 2641 case 90: 2642 return (B(eax) || SH_C0(eax) || CG(eax)); 2643 case 91: 2644 case 92: 2645 return (B(eax) || SH_C0(eax)); 2646 case 93: 2647 return (SH_C0(eax)); 2648 case 94: 2649 return (B(eax) || SH_C0(eax) || CG(eax)); 2650 case 95: 2651 #if !defined(__amd64) 2652 return (0); 2653 #else 2654 return (B(eax) || SH_C0(eax)); 2655 #endif 2656 case 96: 2657 return (B(eax) || SH_C0(eax) || CG(eax)); 2658 case 97: 2659 case 98: 2660 return (SH_C0(eax) || CG(eax)); 2661 case 99: 2662 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2663 case 100: 2664 return (B(eax) || SH_C0(eax)); 2665 case 101: 2666 case 103: 2667 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2668 case 104: 2669 return (SH_C0(eax) || CG(eax) || D0(eax)); 2670 case 105: 2671 case 106: 2672 case 107: 2673 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2674 case 108: 2675 return (DH_CG(eax)); 2676 case 109: 2677 return (SH_C0(eax) || CG(eax) || D0(eax)); 2678 case 110: 2679 return (D0(eax) || EX(eax)); 2680 case 111: 2681 return (CG(eax)); 2682 case 112: 2683 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2684 case 113: 2685 return (eax == 0x20fc0); 2686 case 114: 2687 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2688 case 115: 2689 return (SH_E0(eax) || JH_E1(eax)); 2690 case 116: 2691 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2692 case 117: 2693 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2694 case 118: 2695 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2696 JH_E6(eax)); 2697 case 121: 2698 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2699 case 122: 2700 return (cpi->cpi_family < 0x10); 2701 case 123: 2702 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2703 case 131: 2704 return (cpi->cpi_family < 0x10); 2705 case 6336786: 2706 /* 2707 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2708 * if this is a K8 family or newer processor 2709 */ 2710 if (CPI_FAMILY(cpi) == 0xf) { 2711 struct cpuid_regs regs; 2712 regs.cp_eax = 0x80000007; 2713 (void) __cpuid_insn(®s); 2714 return (!(regs.cp_edx & 0x100)); 2715 } 2716 return (0); 2717 case 6323525: 2718 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2719 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2720 2721 default: 2722 return (-1); 2723 } 2724 } 2725 2726 static const char assoc_str[] = "associativity"; 2727 static const char line_str[] = "line-size"; 2728 static const char size_str[] = "size"; 2729 2730 static void 2731 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2732 uint32_t val) 2733 { 2734 char buf[128]; 2735 2736 /* 2737 * ndi_prop_update_int() is used because it is desirable for 2738 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2739 */ 2740 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2741 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2742 } 2743 2744 /* 2745 * Intel-style cache/tlb description 2746 * 2747 * Standard cpuid level 2 gives a randomly ordered 2748 * selection of tags that index into a table that describes 2749 * cache and tlb properties. 2750 */ 2751 2752 static const char l1_icache_str[] = "l1-icache"; 2753 static const char l1_dcache_str[] = "l1-dcache"; 2754 static const char l2_cache_str[] = "l2-cache"; 2755 static const char l3_cache_str[] = "l3-cache"; 2756 static const char itlb4k_str[] = "itlb-4K"; 2757 static const char dtlb4k_str[] = "dtlb-4K"; 2758 static const char itlb4M_str[] = "itlb-4M"; 2759 static const char dtlb4M_str[] = "dtlb-4M"; 2760 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2761 static const char dtlb44_str[] = "dtlb-4K-4M"; 2762 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2763 static const char sl2_cache_str[] = "sectored-l2-cache"; 2764 static const char itrace_str[] = "itrace-cache"; 2765 static const char sl3_cache_str[] = "sectored-l3-cache"; 2766 2767 static const struct cachetab { 2768 uint8_t ct_code; 2769 uint8_t ct_assoc; 2770 uint16_t ct_line_size; 2771 size_t ct_size; 2772 const char *ct_label; 2773 } intel_ctab[] = { 2774 /* maintain descending order! */ 2775 { 0xb4, 4, 0, 256, dtlb4k_str }, 2776 { 0xb3, 4, 0, 128, dtlb4k_str }, 2777 { 0xb0, 4, 0, 128, itlb4k_str }, 2778 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2779 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2780 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2781 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2782 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2783 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2784 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2785 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2786 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2787 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2788 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2789 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2790 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2791 { 0x73, 8, 0, 64*1024, itrace_str}, 2792 { 0x72, 8, 0, 32*1024, itrace_str}, 2793 { 0x71, 8, 0, 16*1024, itrace_str}, 2794 { 0x70, 8, 0, 12*1024, itrace_str}, 2795 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2796 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2797 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2798 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2799 { 0x5d, 0, 0, 256, dtlb44_str}, 2800 { 0x5c, 0, 0, 128, dtlb44_str}, 2801 { 0x5b, 0, 0, 64, dtlb44_str}, 2802 { 0x52, 0, 0, 256, itlb424_str}, 2803 { 0x51, 0, 0, 128, itlb424_str}, 2804 { 0x50, 0, 0, 64, itlb424_str}, 2805 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2806 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2807 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2808 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2809 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2810 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2811 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2812 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2813 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2814 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2815 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2816 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2817 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2818 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2819 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2820 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2821 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2822 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2823 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2824 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2825 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2826 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2827 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2828 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2829 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2830 { 0x0b, 4, 0, 4, itlb4M_str}, 2831 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2832 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2833 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2834 { 0x04, 4, 0, 8, dtlb4M_str}, 2835 { 0x03, 4, 0, 64, dtlb4k_str}, 2836 { 0x02, 4, 0, 2, itlb4M_str}, 2837 { 0x01, 4, 0, 32, itlb4k_str}, 2838 { 0 } 2839 }; 2840 2841 static const struct cachetab cyrix_ctab[] = { 2842 { 0x70, 4, 0, 32, "tlb-4K" }, 2843 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2844 { 0 } 2845 }; 2846 2847 /* 2848 * Search a cache table for a matching entry 2849 */ 2850 static const struct cachetab * 2851 find_cacheent(const struct cachetab *ct, uint_t code) 2852 { 2853 if (code != 0) { 2854 for (; ct->ct_code != 0; ct++) 2855 if (ct->ct_code <= code) 2856 break; 2857 if (ct->ct_code == code) 2858 return (ct); 2859 } 2860 return (NULL); 2861 } 2862 2863 /* 2864 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2865 * The walk is terminated if the walker returns non-zero. 2866 */ 2867 static void 2868 intel_walk_cacheinfo(struct cpuid_info *cpi, 2869 void *arg, int (*func)(void *, const struct cachetab *)) 2870 { 2871 const struct cachetab *ct; 2872 uint8_t *dp; 2873 int i; 2874 2875 if ((dp = cpi->cpi_cacheinfo) == NULL) 2876 return; 2877 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2878 /* 2879 * For overloaded descriptor 0x49 we use cpuid function 4 2880 * if supported by the current processor, to update 2881 * cache information. 2882 */ 2883 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4) { 2884 intel_cpuid_4_cache_info(arg, cpi); 2885 continue; 2886 } 2887 2888 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2889 if (func(arg, ct) != 0) 2890 break; 2891 } 2892 } 2893 } 2894 2895 /* 2896 * (Like the Intel one, except for Cyrix CPUs) 2897 */ 2898 static void 2899 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2900 void *arg, int (*func)(void *, const struct cachetab *)) 2901 { 2902 const struct cachetab *ct; 2903 uint8_t *dp; 2904 int i; 2905 2906 if ((dp = cpi->cpi_cacheinfo) == NULL) 2907 return; 2908 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2909 /* 2910 * Search Cyrix-specific descriptor table first .. 2911 */ 2912 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2913 if (func(arg, ct) != 0) 2914 break; 2915 continue; 2916 } 2917 /* 2918 * .. else fall back to the Intel one 2919 */ 2920 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2921 if (func(arg, ct) != 0) 2922 break; 2923 continue; 2924 } 2925 } 2926 } 2927 2928 /* 2929 * A cacheinfo walker that adds associativity, line-size, and size properties 2930 * to the devinfo node it is passed as an argument. 2931 */ 2932 static int 2933 add_cacheent_props(void *arg, const struct cachetab *ct) 2934 { 2935 dev_info_t *devi = arg; 2936 2937 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2938 if (ct->ct_line_size != 0) 2939 add_cache_prop(devi, ct->ct_label, line_str, 2940 ct->ct_line_size); 2941 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2942 return (0); 2943 } 2944 2945 /* 2946 * Add L2 or L3 cache-information using cpuid function 4. This 2947 * function is called from intel_walk_cacheinfo() when descriptor 2948 * 0x49 is encountered. 2949 */ 2950 static void 2951 intel_cpuid_4_cache_info(void *arg, struct cpuid_info *cpi) 2952 { 2953 uint32_t level, i; 2954 2955 struct cachetab ct; 2956 2957 for (i = 0; i < cpi->cpi_std_4_size; i++) { 2958 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 2959 2960 if (level == 2 || level == 3) { 2961 ct.ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 2962 ct.ct_line_size = 2963 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 2964 ct.ct_size = ct.ct_assoc * 2965 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 2966 ct.ct_line_size * 2967 (cpi->cpi_std_4[i]->cp_ecx + 1); 2968 2969 if (level == 2) { 2970 ct.ct_label = l2_cache_str; 2971 } else if (level == 3) { 2972 ct.ct_label = l3_cache_str; 2973 } 2974 2975 (void) add_cacheent_props(arg, 2976 (const struct cachetab *) (&ct)); 2977 } 2978 } 2979 } 2980 2981 static const char fully_assoc[] = "fully-associative?"; 2982 2983 /* 2984 * AMD style cache/tlb description 2985 * 2986 * Extended functions 5 and 6 directly describe properties of 2987 * tlbs and various cache levels. 2988 */ 2989 static void 2990 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2991 { 2992 switch (assoc) { 2993 case 0: /* reserved; ignore */ 2994 break; 2995 default: 2996 add_cache_prop(devi, label, assoc_str, assoc); 2997 break; 2998 case 0xff: 2999 add_cache_prop(devi, label, fully_assoc, 1); 3000 break; 3001 } 3002 } 3003 3004 static void 3005 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3006 { 3007 if (size == 0) 3008 return; 3009 add_cache_prop(devi, label, size_str, size); 3010 add_amd_assoc(devi, label, assoc); 3011 } 3012 3013 static void 3014 add_amd_cache(dev_info_t *devi, const char *label, 3015 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3016 { 3017 if (size == 0 || line_size == 0) 3018 return; 3019 add_amd_assoc(devi, label, assoc); 3020 /* 3021 * Most AMD parts have a sectored cache. Multiple cache lines are 3022 * associated with each tag. A sector consists of all cache lines 3023 * associated with a tag. For example, the AMD K6-III has a sector 3024 * size of 2 cache lines per tag. 3025 */ 3026 if (lines_per_tag != 0) 3027 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3028 add_cache_prop(devi, label, line_str, line_size); 3029 add_cache_prop(devi, label, size_str, size * 1024); 3030 } 3031 3032 static void 3033 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3034 { 3035 switch (assoc) { 3036 case 0: /* off */ 3037 break; 3038 case 1: 3039 case 2: 3040 case 4: 3041 add_cache_prop(devi, label, assoc_str, assoc); 3042 break; 3043 case 6: 3044 add_cache_prop(devi, label, assoc_str, 8); 3045 break; 3046 case 8: 3047 add_cache_prop(devi, label, assoc_str, 16); 3048 break; 3049 case 0xf: 3050 add_cache_prop(devi, label, fully_assoc, 1); 3051 break; 3052 default: /* reserved; ignore */ 3053 break; 3054 } 3055 } 3056 3057 static void 3058 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3059 { 3060 if (size == 0 || assoc == 0) 3061 return; 3062 add_amd_l2_assoc(devi, label, assoc); 3063 add_cache_prop(devi, label, size_str, size); 3064 } 3065 3066 static void 3067 add_amd_l2_cache(dev_info_t *devi, const char *label, 3068 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3069 { 3070 if (size == 0 || assoc == 0 || line_size == 0) 3071 return; 3072 add_amd_l2_assoc(devi, label, assoc); 3073 if (lines_per_tag != 0) 3074 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3075 add_cache_prop(devi, label, line_str, line_size); 3076 add_cache_prop(devi, label, size_str, size * 1024); 3077 } 3078 3079 static void 3080 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3081 { 3082 struct cpuid_regs *cp; 3083 3084 if (cpi->cpi_xmaxeax < 0x80000005) 3085 return; 3086 cp = &cpi->cpi_extd[5]; 3087 3088 /* 3089 * 4M/2M L1 TLB configuration 3090 * 3091 * We report the size for 2M pages because AMD uses two 3092 * TLB entries for one 4M page. 3093 */ 3094 add_amd_tlb(devi, "dtlb-2M", 3095 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3096 add_amd_tlb(devi, "itlb-2M", 3097 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3098 3099 /* 3100 * 4K L1 TLB configuration 3101 */ 3102 3103 switch (cpi->cpi_vendor) { 3104 uint_t nentries; 3105 case X86_VENDOR_TM: 3106 if (cpi->cpi_family >= 5) { 3107 /* 3108 * Crusoe processors have 256 TLB entries, but 3109 * cpuid data format constrains them to only 3110 * reporting 255 of them. 3111 */ 3112 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3113 nentries = 256; 3114 /* 3115 * Crusoe processors also have a unified TLB 3116 */ 3117 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3118 nentries); 3119 break; 3120 } 3121 /*FALLTHROUGH*/ 3122 default: 3123 add_amd_tlb(devi, itlb4k_str, 3124 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3125 add_amd_tlb(devi, dtlb4k_str, 3126 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3127 break; 3128 } 3129 3130 /* 3131 * data L1 cache configuration 3132 */ 3133 3134 add_amd_cache(devi, l1_dcache_str, 3135 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3136 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3137 3138 /* 3139 * code L1 cache configuration 3140 */ 3141 3142 add_amd_cache(devi, l1_icache_str, 3143 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3144 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3145 3146 if (cpi->cpi_xmaxeax < 0x80000006) 3147 return; 3148 cp = &cpi->cpi_extd[6]; 3149 3150 /* Check for a unified L2 TLB for large pages */ 3151 3152 if (BITX(cp->cp_eax, 31, 16) == 0) 3153 add_amd_l2_tlb(devi, "l2-tlb-2M", 3154 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3155 else { 3156 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3157 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3158 add_amd_l2_tlb(devi, "l2-itlb-2M", 3159 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3160 } 3161 3162 /* Check for a unified L2 TLB for 4K pages */ 3163 3164 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3165 add_amd_l2_tlb(devi, "l2-tlb-4K", 3166 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3167 } else { 3168 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3169 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3170 add_amd_l2_tlb(devi, "l2-itlb-4K", 3171 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3172 } 3173 3174 add_amd_l2_cache(devi, l2_cache_str, 3175 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3176 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3177 } 3178 3179 /* 3180 * There are two basic ways that the x86 world describes it cache 3181 * and tlb architecture - Intel's way and AMD's way. 3182 * 3183 * Return which flavor of cache architecture we should use 3184 */ 3185 static int 3186 x86_which_cacheinfo(struct cpuid_info *cpi) 3187 { 3188 switch (cpi->cpi_vendor) { 3189 case X86_VENDOR_Intel: 3190 if (cpi->cpi_maxeax >= 2) 3191 return (X86_VENDOR_Intel); 3192 break; 3193 case X86_VENDOR_AMD: 3194 /* 3195 * The K5 model 1 was the first part from AMD that reported 3196 * cache sizes via extended cpuid functions. 3197 */ 3198 if (cpi->cpi_family > 5 || 3199 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3200 return (X86_VENDOR_AMD); 3201 break; 3202 case X86_VENDOR_TM: 3203 if (cpi->cpi_family >= 5) 3204 return (X86_VENDOR_AMD); 3205 /*FALLTHROUGH*/ 3206 default: 3207 /* 3208 * If they have extended CPU data for 0x80000005 3209 * then we assume they have AMD-format cache 3210 * information. 3211 * 3212 * If not, and the vendor happens to be Cyrix, 3213 * then try our-Cyrix specific handler. 3214 * 3215 * If we're not Cyrix, then assume we're using Intel's 3216 * table-driven format instead. 3217 */ 3218 if (cpi->cpi_xmaxeax >= 0x80000005) 3219 return (X86_VENDOR_AMD); 3220 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3221 return (X86_VENDOR_Cyrix); 3222 else if (cpi->cpi_maxeax >= 2) 3223 return (X86_VENDOR_Intel); 3224 break; 3225 } 3226 return (-1); 3227 } 3228 3229 /* 3230 * create a node for the given cpu under the prom root node. 3231 * Also, create a cpu node in the device tree. 3232 */ 3233 static dev_info_t *cpu_nex_devi = NULL; 3234 static kmutex_t cpu_node_lock; 3235 3236 /* 3237 * Called from post_startup() and mp_startup() 3238 */ 3239 void 3240 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3241 { 3242 dev_info_t *cpu_devi; 3243 int create; 3244 3245 mutex_enter(&cpu_node_lock); 3246 3247 /* 3248 * create a nexus node for all cpus identified as 'cpu_id' under 3249 * the root node. 3250 */ 3251 if (cpu_nex_devi == NULL) { 3252 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3253 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3254 mutex_exit(&cpu_node_lock); 3255 return; 3256 } 3257 (void) ndi_devi_online(cpu_nex_devi, 0); 3258 } 3259 3260 /* 3261 * create a child node for cpu identified as 'cpu_id' 3262 */ 3263 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3264 cpu_id); 3265 if (cpu_devi == NULL) { 3266 mutex_exit(&cpu_node_lock); 3267 return; 3268 } 3269 3270 /* device_type */ 3271 3272 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3273 "device_type", "cpu"); 3274 3275 /* reg */ 3276 3277 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3278 "reg", cpu_id); 3279 3280 /* cpu-mhz, and clock-frequency */ 3281 3282 if (cpu_freq > 0) { 3283 long long mul; 3284 3285 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3286 "cpu-mhz", cpu_freq); 3287 3288 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3289 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3290 "clock-frequency", (int)mul); 3291 } 3292 3293 (void) ndi_devi_online(cpu_devi, 0); 3294 3295 if ((x86_feature & X86_CPUID) == 0) { 3296 mutex_exit(&cpu_node_lock); 3297 return; 3298 } 3299 3300 /* vendor-id */ 3301 3302 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3303 "vendor-id", cpi->cpi_vendorstr); 3304 3305 if (cpi->cpi_maxeax == 0) { 3306 mutex_exit(&cpu_node_lock); 3307 return; 3308 } 3309 3310 /* 3311 * family, model, and step 3312 */ 3313 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3314 "family", CPI_FAMILY(cpi)); 3315 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3316 "cpu-model", CPI_MODEL(cpi)); 3317 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3318 "stepping-id", CPI_STEP(cpi)); 3319 3320 /* type */ 3321 3322 switch (cpi->cpi_vendor) { 3323 case X86_VENDOR_Intel: 3324 create = 1; 3325 break; 3326 default: 3327 create = 0; 3328 break; 3329 } 3330 if (create) 3331 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3332 "type", CPI_TYPE(cpi)); 3333 3334 /* ext-family */ 3335 3336 switch (cpi->cpi_vendor) { 3337 case X86_VENDOR_Intel: 3338 case X86_VENDOR_AMD: 3339 create = cpi->cpi_family >= 0xf; 3340 break; 3341 default: 3342 create = 0; 3343 break; 3344 } 3345 if (create) 3346 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3347 "ext-family", CPI_FAMILY_XTD(cpi)); 3348 3349 /* ext-model */ 3350 3351 switch (cpi->cpi_vendor) { 3352 case X86_VENDOR_Intel: 3353 create = CPI_MODEL(cpi) == 0xf; 3354 break; 3355 case X86_VENDOR_AMD: 3356 create = CPI_FAMILY(cpi) == 0xf; 3357 break; 3358 default: 3359 create = 0; 3360 break; 3361 } 3362 if (create) 3363 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3364 "ext-model", CPI_MODEL_XTD(cpi)); 3365 3366 /* generation */ 3367 3368 switch (cpi->cpi_vendor) { 3369 case X86_VENDOR_AMD: 3370 /* 3371 * AMD K5 model 1 was the first part to support this 3372 */ 3373 create = cpi->cpi_xmaxeax >= 0x80000001; 3374 break; 3375 default: 3376 create = 0; 3377 break; 3378 } 3379 if (create) 3380 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3381 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3382 3383 /* brand-id */ 3384 3385 switch (cpi->cpi_vendor) { 3386 case X86_VENDOR_Intel: 3387 /* 3388 * brand id first appeared on Pentium III Xeon model 8, 3389 * and Celeron model 8 processors and Opteron 3390 */ 3391 create = cpi->cpi_family > 6 || 3392 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3393 break; 3394 case X86_VENDOR_AMD: 3395 create = cpi->cpi_family >= 0xf; 3396 break; 3397 default: 3398 create = 0; 3399 break; 3400 } 3401 if (create && cpi->cpi_brandid != 0) { 3402 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3403 "brand-id", cpi->cpi_brandid); 3404 } 3405 3406 /* chunks, and apic-id */ 3407 3408 switch (cpi->cpi_vendor) { 3409 /* 3410 * first available on Pentium IV and Opteron (K8) 3411 */ 3412 case X86_VENDOR_Intel: 3413 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3414 break; 3415 case X86_VENDOR_AMD: 3416 create = cpi->cpi_family >= 0xf; 3417 break; 3418 default: 3419 create = 0; 3420 break; 3421 } 3422 if (create) { 3423 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3424 "chunks", CPI_CHUNKS(cpi)); 3425 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3426 "apic-id", CPI_APIC_ID(cpi)); 3427 if (cpi->cpi_chipid >= 0) { 3428 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3429 "chip#", cpi->cpi_chipid); 3430 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3431 "clog#", cpi->cpi_clogid); 3432 } 3433 } 3434 3435 /* cpuid-features */ 3436 3437 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3438 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3439 3440 3441 /* cpuid-features-ecx */ 3442 3443 switch (cpi->cpi_vendor) { 3444 case X86_VENDOR_Intel: 3445 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3446 break; 3447 default: 3448 create = 0; 3449 break; 3450 } 3451 if (create) 3452 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3453 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3454 3455 /* ext-cpuid-features */ 3456 3457 switch (cpi->cpi_vendor) { 3458 case X86_VENDOR_Intel: 3459 case X86_VENDOR_AMD: 3460 case X86_VENDOR_Cyrix: 3461 case X86_VENDOR_TM: 3462 case X86_VENDOR_Centaur: 3463 create = cpi->cpi_xmaxeax >= 0x80000001; 3464 break; 3465 default: 3466 create = 0; 3467 break; 3468 } 3469 if (create) { 3470 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3471 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3472 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3473 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3474 } 3475 3476 /* 3477 * Brand String first appeared in Intel Pentium IV, AMD K5 3478 * model 1, and Cyrix GXm. On earlier models we try and 3479 * simulate something similar .. so this string should always 3480 * same -something- about the processor, however lame. 3481 */ 3482 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3483 "brand-string", cpi->cpi_brandstr); 3484 3485 /* 3486 * Finally, cache and tlb information 3487 */ 3488 switch (x86_which_cacheinfo(cpi)) { 3489 case X86_VENDOR_Intel: 3490 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3491 break; 3492 case X86_VENDOR_Cyrix: 3493 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3494 break; 3495 case X86_VENDOR_AMD: 3496 amd_cache_info(cpi, cpu_devi); 3497 break; 3498 default: 3499 break; 3500 } 3501 3502 mutex_exit(&cpu_node_lock); 3503 } 3504 3505 struct l2info { 3506 int *l2i_csz; 3507 int *l2i_lsz; 3508 int *l2i_assoc; 3509 int l2i_ret; 3510 }; 3511 3512 /* 3513 * A cacheinfo walker that fetches the size, line-size and associativity 3514 * of the L2 cache 3515 */ 3516 static int 3517 intel_l2cinfo(void *arg, const struct cachetab *ct) 3518 { 3519 struct l2info *l2i = arg; 3520 int *ip; 3521 3522 if (ct->ct_label != l2_cache_str && 3523 ct->ct_label != sl2_cache_str) 3524 return (0); /* not an L2 -- keep walking */ 3525 3526 if ((ip = l2i->l2i_csz) != NULL) 3527 *ip = ct->ct_size; 3528 if ((ip = l2i->l2i_lsz) != NULL) 3529 *ip = ct->ct_line_size; 3530 if ((ip = l2i->l2i_assoc) != NULL) 3531 *ip = ct->ct_assoc; 3532 l2i->l2i_ret = ct->ct_size; 3533 return (1); /* was an L2 -- terminate walk */ 3534 } 3535 3536 /* 3537 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3538 * 3539 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3540 * value is the associativity, the associativity for the L2 cache and 3541 * tlb is encoded in the following table. The 4 bit L2 value serves as 3542 * an index into the amd_afd[] array to determine the associativity. 3543 * -1 is undefined. 0 is fully associative. 3544 */ 3545 3546 static int amd_afd[] = 3547 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3548 3549 static void 3550 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3551 { 3552 struct cpuid_regs *cp; 3553 uint_t size, assoc; 3554 int i; 3555 int *ip; 3556 3557 if (cpi->cpi_xmaxeax < 0x80000006) 3558 return; 3559 cp = &cpi->cpi_extd[6]; 3560 3561 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3562 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3563 uint_t cachesz = size * 1024; 3564 assoc = amd_afd[i]; 3565 3566 ASSERT(assoc != -1); 3567 3568 if ((ip = l2i->l2i_csz) != NULL) 3569 *ip = cachesz; 3570 if ((ip = l2i->l2i_lsz) != NULL) 3571 *ip = BITX(cp->cp_ecx, 7, 0); 3572 if ((ip = l2i->l2i_assoc) != NULL) 3573 *ip = assoc; 3574 l2i->l2i_ret = cachesz; 3575 } 3576 } 3577 3578 int 3579 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3580 { 3581 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3582 struct l2info __l2info, *l2i = &__l2info; 3583 3584 l2i->l2i_csz = csz; 3585 l2i->l2i_lsz = lsz; 3586 l2i->l2i_assoc = assoc; 3587 l2i->l2i_ret = -1; 3588 3589 switch (x86_which_cacheinfo(cpi)) { 3590 case X86_VENDOR_Intel: 3591 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3592 break; 3593 case X86_VENDOR_Cyrix: 3594 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3595 break; 3596 case X86_VENDOR_AMD: 3597 amd_l2cacheinfo(cpi, l2i); 3598 break; 3599 default: 3600 break; 3601 } 3602 return (l2i->l2i_ret); 3603 } 3604 3605 #if !defined(__xpv) 3606 3607 uint32_t * 3608 cpuid_mwait_alloc(cpu_t *cpu) 3609 { 3610 uint32_t *ret; 3611 size_t mwait_size; 3612 3613 ASSERT(cpuid_checkpass(cpu, 2)); 3614 3615 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3616 if (mwait_size == 0) 3617 return (NULL); 3618 3619 /* 3620 * kmem_alloc() returns cache line size aligned data for mwait_size 3621 * allocations. mwait_size is currently cache line sized. Neither 3622 * of these implementation details are guarantied to be true in the 3623 * future. 3624 * 3625 * First try allocating mwait_size as kmem_alloc() currently returns 3626 * correctly aligned memory. If kmem_alloc() does not return 3627 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3628 * 3629 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3630 * decide to free this memory. 3631 */ 3632 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3633 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3634 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3635 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3636 *ret = MWAIT_RUNNING; 3637 return (ret); 3638 } else { 3639 kmem_free(ret, mwait_size); 3640 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3641 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3642 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3643 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3644 *ret = MWAIT_RUNNING; 3645 return (ret); 3646 } 3647 } 3648 3649 void 3650 cpuid_mwait_free(cpu_t *cpu) 3651 { 3652 ASSERT(cpuid_checkpass(cpu, 2)); 3653 3654 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3655 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3656 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3657 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3658 } 3659 3660 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3661 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3662 } 3663 3664 void 3665 patch_tsc_read(int flag) 3666 { 3667 size_t cnt; 3668 3669 switch (flag) { 3670 case X86_NO_TSC: 3671 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 3672 memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 3673 break; 3674 case X86_HAVE_TSCP: 3675 cnt = &_tscp_end - &_tscp_start; 3676 memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 3677 break; 3678 case X86_TSC_MFENCE: 3679 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 3680 memcpy((void *)tsc_read, (void *)&_tsc_mfence_start, cnt); 3681 break; 3682 default: 3683 break; 3684 } 3685 } 3686 3687 #endif /* !__xpv */ 3688