1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/chip.h> 44 #include <sys/fp.h> 45 #include <sys/controlregs.h> 46 #include <sys/auxv_386.h> 47 #include <sys/bitmap.h> 48 #include <sys/controlregs.h> 49 #include <sys/memnode.h> 50 51 /* 52 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 53 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 54 * them accordingly. For most modern processors, feature detection occurs here 55 * in pass 1. 56 * 57 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 58 * for the boot CPU and does the basic analysis that the early kernel needs. 59 * x86_feature is set based on the return value of cpuid_pass1() of the boot 60 * CPU. 61 * 62 * Pass 1 includes: 63 * 64 * o Determining vendor/model/family/stepping and setting x86_type and 65 * x86_vendor accordingly. 66 * o Processing the feature flags returned by the cpuid instruction while 67 * applying any workarounds or tricks for the specific processor. 68 * o Mapping the feature flags into Solaris feature bits (X86_*). 69 * o Processing extended feature flags if supported by the processor, 70 * again while applying specific processor knowledge. 71 * o Determining the CMT characteristics of the system. 72 * 73 * Pass 1 is done on non-boot CPUs during their initialization and the results 74 * are used only as a meager attempt at ensuring that all processors within the 75 * system support the same features. 76 * 77 * Pass 2 of cpuid feature analysis happens just at the beginning 78 * of startup(). It just copies in and corrects the remainder 79 * of the cpuid data we depend on: standard cpuid functions that we didn't 80 * need for pass1 feature analysis, and extended cpuid functions beyond the 81 * simple feature processing done in pass1. 82 * 83 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 84 * particular kernel memory allocation has been made available. It creates a 85 * readable brand string based on the data collected in the first two passes. 86 * 87 * Pass 4 of cpuid analysis is invoked after post_startup() when all 88 * the support infrastructure for various hardware features has been 89 * initialized. It determines which processor features will be reported 90 * to userland via the aux vector. 91 * 92 * All passes are executed on all CPUs, but only the boot CPU determines what 93 * features the kernel will use. 94 * 95 * Much of the worst junk in this file is for the support of processors 96 * that didn't really implement the cpuid instruction properly. 97 * 98 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 99 * the pass numbers. Accordingly, changes to the pass code may require changes 100 * to the accessor code. 101 */ 102 103 uint_t x86_feature = 0; 104 uint_t x86_vendor = X86_VENDOR_IntelClone; 105 uint_t x86_type = X86_TYPE_OTHER; 106 107 ulong_t cr4_value; 108 uint_t pentiumpro_bug4046376; 109 uint_t pentiumpro_bug4064495; 110 111 uint_t enable486; 112 113 /* 114 * This set of strings are for processors rumored to support the cpuid 115 * instruction, and is used by locore.s to figure out how to set x86_vendor 116 */ 117 const char CyrixInstead[] = "CyrixInstead"; 118 119 /* 120 * These constants determine how many of the elements of the 121 * cpuid we cache in the cpuid_info data structure; the 122 * remaining elements are accessible via the cpuid instruction. 123 */ 124 125 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 126 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 127 128 struct cpuid_info { 129 uint_t cpi_pass; /* last pass completed */ 130 /* 131 * standard function information 132 */ 133 uint_t cpi_maxeax; /* fn 0: %eax */ 134 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 135 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 136 137 uint_t cpi_family; /* fn 1: extended family */ 138 uint_t cpi_model; /* fn 1: extended model */ 139 uint_t cpi_step; /* fn 1: stepping */ 140 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 141 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 142 int cpi_clogid; /* fn 1: %ebx: thread # */ 143 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 144 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 145 uint_t cpi_ncache; /* fn 2: number of elements */ 146 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 147 /* 148 * extended function information 149 */ 150 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 151 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 152 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 153 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 154 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 155 id_t cpi_coreid; 156 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 157 /* Intel: fn 4: %eax[31-26] */ 158 /* 159 * supported feature information 160 */ 161 uint32_t cpi_support[4]; 162 #define STD_EDX_FEATURES 0 163 #define AMD_EDX_FEATURES 1 164 #define TM_EDX_FEATURES 2 165 #define STD_ECX_FEATURES 3 166 167 }; 168 169 170 static struct cpuid_info cpuid_info0; 171 172 /* 173 * These bit fields are defined by the Intel Application Note AP-485 174 * "Intel Processor Identification and the CPUID Instruction" 175 */ 176 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 177 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 178 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 179 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 180 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 181 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 182 183 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 184 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 185 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 186 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 187 188 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 189 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 190 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 191 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 192 193 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 194 #define CPI_XMAXEAX_MAX 0x80000100 195 196 /* 197 * A couple of shorthand macros to identify "later" P6-family chips 198 * like the Pentium M and Core. First, the "older" P6-based stuff 199 * (loosely defined as "pre-Pentium-4"): 200 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 201 */ 202 203 #define IS_LEGACY_P6(cpi) ( \ 204 cpi->cpi_family == 6 && \ 205 (cpi->cpi_model == 1 || \ 206 cpi->cpi_model == 3 || \ 207 cpi->cpi_model == 5 || \ 208 cpi->cpi_model == 6 || \ 209 cpi->cpi_model == 7 || \ 210 cpi->cpi_model == 8 || \ 211 cpi->cpi_model == 0xA || \ 212 cpi->cpi_model == 0xB) \ 213 ) 214 215 /* A "new F6" is everything with family 6 that's not the above */ 216 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 217 218 /* 219 * Some undocumented ways of patching the results of the cpuid 220 * instruction to permit running Solaris 10 on future cpus that 221 * we don't currently support. Could be set to non-zero values 222 * via settings in eeprom. 223 */ 224 225 uint32_t cpuid_feature_ecx_include; 226 uint32_t cpuid_feature_ecx_exclude; 227 uint32_t cpuid_feature_edx_include; 228 uint32_t cpuid_feature_edx_exclude; 229 230 uint_t 231 cpuid_pass1(cpu_t *cpu) 232 { 233 uint32_t mask_ecx, mask_edx; 234 uint_t feature = X86_CPUID; 235 struct cpuid_info *cpi; 236 struct cpuid_regs *cp; 237 int xcpuid; 238 239 /* 240 * By convention, cpu0 is the boot cpu, which is called 241 * before memory allocation is available. Other cpus are 242 * initialized when memory becomes available. 243 */ 244 if (cpu->cpu_id == 0) 245 cpu->cpu_m.mcpu_cpi = cpi = &cpuid_info0; 246 else 247 cpu->cpu_m.mcpu_cpi = cpi = 248 kmem_zalloc(sizeof (*cpi), KM_SLEEP); 249 250 cp = &cpi->cpi_std[0]; 251 cp->cp_eax = 0; 252 cpi->cpi_maxeax = __cpuid_insn(cp); 253 { 254 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 255 *iptr++ = cp->cp_ebx; 256 *iptr++ = cp->cp_edx; 257 *iptr++ = cp->cp_ecx; 258 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 259 } 260 261 /* 262 * Map the vendor string to a type code 263 */ 264 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 265 cpi->cpi_vendor = X86_VENDOR_Intel; 266 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 267 cpi->cpi_vendor = X86_VENDOR_AMD; 268 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 269 cpi->cpi_vendor = X86_VENDOR_TM; 270 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 271 /* 272 * CyrixInstead is a variable used by the Cyrix detection code 273 * in locore. 274 */ 275 cpi->cpi_vendor = X86_VENDOR_Cyrix; 276 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 277 cpi->cpi_vendor = X86_VENDOR_UMC; 278 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 279 cpi->cpi_vendor = X86_VENDOR_NexGen; 280 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 281 cpi->cpi_vendor = X86_VENDOR_Centaur; 282 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 283 cpi->cpi_vendor = X86_VENDOR_Rise; 284 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 285 cpi->cpi_vendor = X86_VENDOR_SiS; 286 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 287 cpi->cpi_vendor = X86_VENDOR_NSC; 288 else 289 cpi->cpi_vendor = X86_VENDOR_IntelClone; 290 291 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 292 293 /* 294 * Limit the range in case of weird hardware 295 */ 296 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 297 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 298 if (cpi->cpi_maxeax < 1) 299 goto pass1_done; 300 301 cp = &cpi->cpi_std[1]; 302 cp->cp_eax = 1; 303 (void) __cpuid_insn(cp); 304 305 /* 306 * Extract identifying constants for easy access. 307 */ 308 cpi->cpi_model = CPI_MODEL(cpi); 309 cpi->cpi_family = CPI_FAMILY(cpi); 310 311 if (cpi->cpi_family == 0xf) 312 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 313 314 if (cpi->cpi_model == 0xf) 315 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 316 317 cpi->cpi_step = CPI_STEP(cpi); 318 cpi->cpi_brandid = CPI_BRANDID(cpi); 319 320 /* 321 * *default* assumptions: 322 * - believe %edx feature word 323 * - ignore %ecx feature word 324 * - 32-bit virtual and physical addressing 325 */ 326 mask_edx = 0xffffffff; 327 mask_ecx = 0; 328 329 cpi->cpi_pabits = cpi->cpi_vabits = 32; 330 331 switch (cpi->cpi_vendor) { 332 case X86_VENDOR_Intel: 333 if (cpi->cpi_family == 5) 334 x86_type = X86_TYPE_P5; 335 else if (IS_LEGACY_P6(cpi)) { 336 x86_type = X86_TYPE_P6; 337 pentiumpro_bug4046376 = 1; 338 pentiumpro_bug4064495 = 1; 339 /* 340 * Clear the SEP bit when it was set erroneously 341 */ 342 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 343 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 344 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 345 x86_type = X86_TYPE_P4; 346 /* 347 * We don't currently depend on any of the %ecx 348 * features until Prescott, so we'll only check 349 * this from P4 onwards. We might want to revisit 350 * that idea later. 351 */ 352 mask_ecx = 0xffffffff; 353 } else if (cpi->cpi_family > 0xf) 354 mask_ecx = 0xffffffff; 355 break; 356 case X86_VENDOR_IntelClone: 357 default: 358 break; 359 case X86_VENDOR_AMD: 360 #if defined(OPTERON_ERRATUM_108) 361 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 362 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 363 cpi->cpi_model = 0xc; 364 } else 365 #endif 366 if (cpi->cpi_family == 5) { 367 /* 368 * AMD K5 and K6 369 * 370 * These CPUs have an incomplete implementation 371 * of MCA/MCE which we mask away. 372 */ 373 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 374 375 /* 376 * Model 0 uses the wrong (APIC) bit 377 * to indicate PGE. Fix it here. 378 */ 379 if (cpi->cpi_model == 0) { 380 if (cp->cp_edx & 0x200) { 381 cp->cp_edx &= ~0x200; 382 cp->cp_edx |= CPUID_INTC_EDX_PGE; 383 } 384 } 385 386 /* 387 * Early models had problems w/ MMX; disable. 388 */ 389 if (cpi->cpi_model < 6) 390 mask_edx &= ~CPUID_INTC_EDX_MMX; 391 } 392 393 /* 394 * For newer families, SSE3 and CX16, at least, are valid; 395 * enable all 396 */ 397 if (cpi->cpi_family >= 0xf) 398 mask_ecx = 0xffffffff; 399 break; 400 case X86_VENDOR_TM: 401 /* 402 * workaround the NT workaround in CMS 4.1 403 */ 404 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 405 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 406 cp->cp_edx |= CPUID_INTC_EDX_CX8; 407 break; 408 case X86_VENDOR_Centaur: 409 /* 410 * workaround the NT workarounds again 411 */ 412 if (cpi->cpi_family == 6) 413 cp->cp_edx |= CPUID_INTC_EDX_CX8; 414 break; 415 case X86_VENDOR_Cyrix: 416 /* 417 * We rely heavily on the probing in locore 418 * to actually figure out what parts, if any, 419 * of the Cyrix cpuid instruction to believe. 420 */ 421 switch (x86_type) { 422 case X86_TYPE_CYRIX_486: 423 mask_edx = 0; 424 break; 425 case X86_TYPE_CYRIX_6x86: 426 mask_edx = 0; 427 break; 428 case X86_TYPE_CYRIX_6x86L: 429 mask_edx = 430 CPUID_INTC_EDX_DE | 431 CPUID_INTC_EDX_CX8; 432 break; 433 case X86_TYPE_CYRIX_6x86MX: 434 mask_edx = 435 CPUID_INTC_EDX_DE | 436 CPUID_INTC_EDX_MSR | 437 CPUID_INTC_EDX_CX8 | 438 CPUID_INTC_EDX_PGE | 439 CPUID_INTC_EDX_CMOV | 440 CPUID_INTC_EDX_MMX; 441 break; 442 case X86_TYPE_CYRIX_GXm: 443 mask_edx = 444 CPUID_INTC_EDX_MSR | 445 CPUID_INTC_EDX_CX8 | 446 CPUID_INTC_EDX_CMOV | 447 CPUID_INTC_EDX_MMX; 448 break; 449 case X86_TYPE_CYRIX_MediaGX: 450 break; 451 case X86_TYPE_CYRIX_MII: 452 case X86_TYPE_VIA_CYRIX_III: 453 mask_edx = 454 CPUID_INTC_EDX_DE | 455 CPUID_INTC_EDX_TSC | 456 CPUID_INTC_EDX_MSR | 457 CPUID_INTC_EDX_CX8 | 458 CPUID_INTC_EDX_PGE | 459 CPUID_INTC_EDX_CMOV | 460 CPUID_INTC_EDX_MMX; 461 break; 462 default: 463 break; 464 } 465 break; 466 } 467 468 /* 469 * Now we've figured out the masks that determine 470 * which bits we choose to believe, apply the masks 471 * to the feature words, then map the kernel's view 472 * of these feature words into its feature word. 473 */ 474 cp->cp_edx &= mask_edx; 475 cp->cp_ecx &= mask_ecx; 476 477 /* 478 * fold in fix ups 479 */ 480 481 cp->cp_edx |= cpuid_feature_edx_include; 482 cp->cp_edx &= ~cpuid_feature_edx_exclude; 483 484 485 cp->cp_ecx |= cpuid_feature_ecx_include; 486 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 487 488 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 489 feature |= X86_LARGEPAGE; 490 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 491 feature |= X86_TSC; 492 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 493 feature |= X86_MSR; 494 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 495 feature |= X86_MTRR; 496 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 497 feature |= X86_PGE; 498 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 499 feature |= X86_CMOV; 500 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 501 feature |= X86_MMX; 502 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 503 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 504 feature |= X86_MCA; 505 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 506 feature |= X86_PAE; 507 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 508 feature |= X86_CX8; 509 /* 510 * Once this bit was thought questionable, but it looks like it's 511 * back, as of Application Note 485 March 2005 (24161829.pdf) 512 */ 513 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 514 feature |= X86_CX16; 515 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 516 feature |= X86_PAT; 517 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 518 feature |= X86_SEP; 519 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 520 /* 521 * In our implementation, fxsave/fxrstor 522 * are prerequisites before we'll even 523 * try and do SSE things. 524 */ 525 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 526 feature |= X86_SSE; 527 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 528 feature |= X86_SSE2; 529 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 530 feature |= X86_SSE3; 531 } 532 if (cp->cp_edx & CPUID_INTC_EDX_DE) 533 cr4_value |= CR4_DE; 534 535 if (feature & X86_PAE) 536 cpi->cpi_pabits = 36; 537 538 /* 539 * Hyperthreading configuration is slightly tricky on Intel 540 * and pure clones, and even trickier on AMD. 541 * 542 * (AMD chose to set the HTT bit on their CMP processors, 543 * even though they're not actually hyperthreaded. Thus it 544 * takes a bit more work to figure out what's really going 545 * on ... see the handling of the CMP_LEGACY bit below) 546 */ 547 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 548 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 549 if (cpi->cpi_ncpu_per_chip > 1) 550 feature |= X86_HTT; 551 } else { 552 cpi->cpi_ncpu_per_chip = 1; 553 } 554 555 /* 556 * Work on the "extended" feature information, doing 557 * some basic initialization for cpuid_pass2() 558 */ 559 xcpuid = 0; 560 switch (cpi->cpi_vendor) { 561 case X86_VENDOR_Intel: 562 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 563 xcpuid++; 564 break; 565 case X86_VENDOR_AMD: 566 if (cpi->cpi_family > 5 || 567 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 568 xcpuid++; 569 break; 570 case X86_VENDOR_Cyrix: 571 /* 572 * Only these Cyrix CPUs are -known- to support 573 * extended cpuid operations. 574 */ 575 if (x86_type == X86_TYPE_VIA_CYRIX_III || 576 x86_type == X86_TYPE_CYRIX_GXm) 577 xcpuid++; 578 break; 579 case X86_VENDOR_Centaur: 580 case X86_VENDOR_TM: 581 default: 582 xcpuid++; 583 break; 584 } 585 586 if (xcpuid) { 587 cp = &cpi->cpi_extd[0]; 588 cp->cp_eax = 0x80000000; 589 cpi->cpi_xmaxeax = __cpuid_insn(cp); 590 } 591 592 if (cpi->cpi_xmaxeax & 0x80000000) { 593 594 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 595 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 596 597 switch (cpi->cpi_vendor) { 598 case X86_VENDOR_Intel: 599 case X86_VENDOR_AMD: 600 if (cpi->cpi_xmaxeax < 0x80000001) 601 break; 602 cp = &cpi->cpi_extd[1]; 603 cp->cp_eax = 0x80000001; 604 (void) __cpuid_insn(cp); 605 if (cpi->cpi_vendor == X86_VENDOR_AMD && 606 cpi->cpi_family == 5 && 607 cpi->cpi_model == 6 && 608 cpi->cpi_step == 6) { 609 /* 610 * K6 model 6 uses bit 10 to indicate SYSC 611 * Later models use bit 11. Fix it here. 612 */ 613 if (cp->cp_edx & 0x400) { 614 cp->cp_edx &= ~0x400; 615 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 616 } 617 } 618 619 /* 620 * Compute the additions to the kernel's feature word. 621 */ 622 if (cp->cp_edx & CPUID_AMD_EDX_NX) 623 feature |= X86_NX; 624 625 /* 626 * If both the HTT and CMP_LEGACY bits are set, 627 * then we're not actually HyperThreaded. Read 628 * "AMD CPUID Specification" for more details. 629 */ 630 if (cpi->cpi_vendor == X86_VENDOR_AMD && 631 (feature & X86_HTT) && 632 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LEGACY)) { 633 feature &= ~X86_HTT; 634 feature |= X86_CMP; 635 } 636 #if defined(_LP64) 637 /* 638 * It's really tricky to support syscall/sysret in 639 * the i386 kernel; we rely on sysenter/sysexit 640 * instead. In the amd64 kernel, things are -way- 641 * better. 642 */ 643 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 644 feature |= X86_ASYSC; 645 646 /* 647 * While we're thinking about system calls, note 648 * that AMD processors don't support sysenter 649 * in long mode at all, so don't try to program them. 650 */ 651 if (x86_vendor == X86_VENDOR_AMD) 652 feature &= ~X86_SEP; 653 #endif 654 break; 655 default: 656 break; 657 } 658 659 /* 660 * Get CPUID data about processor cores and hyperthreads. 661 */ 662 switch (cpi->cpi_vendor) { 663 case X86_VENDOR_Intel: 664 if (cpi->cpi_maxeax >= 4) { 665 cp = &cpi->cpi_std[4]; 666 cp->cp_eax = 4; 667 cp->cp_ecx = 0; 668 (void) __cpuid_insn(cp); 669 } 670 /*FALLTHROUGH*/ 671 case X86_VENDOR_AMD: 672 if (cpi->cpi_xmaxeax < 0x80000008) 673 break; 674 cp = &cpi->cpi_extd[8]; 675 cp->cp_eax = 0x80000008; 676 (void) __cpuid_insn(cp); 677 /* 678 * Virtual and physical address limits from 679 * cpuid override previously guessed values. 680 */ 681 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 682 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 683 break; 684 default: 685 break; 686 } 687 688 switch (cpi->cpi_vendor) { 689 case X86_VENDOR_Intel: 690 if (cpi->cpi_maxeax < 4) { 691 cpi->cpi_ncore_per_chip = 1; 692 break; 693 } else { 694 cpi->cpi_ncore_per_chip = 695 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 696 } 697 break; 698 case X86_VENDOR_AMD: 699 if (cpi->cpi_xmaxeax < 0x80000008) { 700 cpi->cpi_ncore_per_chip = 1; 701 break; 702 } else { 703 cpi->cpi_ncore_per_chip = 704 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 705 } 706 break; 707 default: 708 cpi->cpi_ncore_per_chip = 1; 709 break; 710 } 711 712 } 713 714 /* 715 * If more than one core, then this processor is CMP. 716 */ 717 if (cpi->cpi_ncore_per_chip > 1) 718 feature |= X86_CMP; 719 /* 720 * If the number of cores is the same as the number 721 * of CPUs, then we cannot have HyperThreading. 722 */ 723 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 724 feature &= ~X86_HTT; 725 726 if ((feature & (X86_HTT | X86_CMP)) == 0) { 727 /* 728 * Single-core single-threaded processors. 729 */ 730 cpi->cpi_chipid = -1; 731 cpi->cpi_clogid = 0; 732 cpi->cpi_coreid = cpu->cpu_id; 733 } else if (cpi->cpi_ncpu_per_chip > 1) { 734 uint_t i; 735 uint_t chipid_shift = 0; 736 uint_t coreid_shift = 0; 737 uint_t apic_id = CPI_APIC_ID(cpi); 738 739 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 740 chipid_shift++; 741 cpi->cpi_chipid = apic_id >> chipid_shift; 742 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 743 744 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 745 if (feature & X86_CMP) { 746 /* 747 * Multi-core (and possibly multi-threaded) 748 * processors. 749 */ 750 uint_t ncpu_per_core; 751 if (cpi->cpi_ncore_per_chip == 1) 752 ncpu_per_core = cpi->cpi_ncpu_per_chip; 753 else if (cpi->cpi_ncore_per_chip > 1) 754 ncpu_per_core = cpi->cpi_ncpu_per_chip / 755 cpi->cpi_ncore_per_chip; 756 /* 757 * 8bit APIC IDs on dual core Pentiums 758 * look like this: 759 * 760 * +-----------------------+------+------+ 761 * | Physical Package ID | MC | HT | 762 * +-----------------------+------+------+ 763 * <------- chipid --------> 764 * <------- coreid ---------------> 765 * <--- clogid --> 766 * 767 * Where the number of bits necessary to 768 * represent MC and HT fields together equals 769 * to the minimum number of bits necessary to 770 * store the value of cpi->cpi_ncpu_per_chip. 771 * Of those bits, the MC part uses the number 772 * of bits necessary to store the value of 773 * cpi->cpi_ncore_per_chip. 774 */ 775 for (i = 1; i < ncpu_per_core; i <<= 1) 776 coreid_shift++; 777 cpi->cpi_coreid = apic_id >> coreid_shift; 778 } else if (feature & X86_HTT) { 779 /* 780 * Single-core multi-threaded processors. 781 */ 782 cpi->cpi_coreid = cpi->cpi_chipid; 783 } 784 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 785 /* 786 * AMD currently only has dual-core processors with 787 * single-threaded cores. If they ever release 788 * multi-threaded processors, then this code 789 * will have to be updated. 790 */ 791 cpi->cpi_coreid = cpu->cpu_id; 792 } else { 793 /* 794 * All other processors are currently 795 * assumed to have single cores. 796 */ 797 cpi->cpi_coreid = cpi->cpi_chipid; 798 } 799 } 800 801 pass1_done: 802 cpi->cpi_pass = 1; 803 return (feature); 804 } 805 806 /* 807 * Make copies of the cpuid table entries we depend on, in 808 * part for ease of parsing now, in part so that we have only 809 * one place to correct any of it, in part for ease of 810 * later export to userland, and in part so we can look at 811 * this stuff in a crash dump. 812 */ 813 814 /*ARGSUSED*/ 815 void 816 cpuid_pass2(cpu_t *cpu) 817 { 818 uint_t n, nmax; 819 int i; 820 struct cpuid_regs *cp; 821 uint8_t *dp; 822 uint32_t *iptr; 823 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 824 825 ASSERT(cpi->cpi_pass == 1); 826 827 if (cpi->cpi_maxeax < 1) 828 goto pass2_done; 829 830 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 831 nmax = NMAX_CPI_STD; 832 /* 833 * (We already handled n == 0 and n == 1 in pass 1) 834 */ 835 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 836 cp->cp_eax = n; 837 (void) __cpuid_insn(cp); 838 switch (n) { 839 case 2: 840 /* 841 * "the lower 8 bits of the %eax register 842 * contain a value that identifies the number 843 * of times the cpuid [instruction] has to be 844 * executed to obtain a complete image of the 845 * processor's caching systems." 846 * 847 * How *do* they make this stuff up? 848 */ 849 cpi->cpi_ncache = sizeof (*cp) * 850 BITX(cp->cp_eax, 7, 0); 851 if (cpi->cpi_ncache == 0) 852 break; 853 cpi->cpi_ncache--; /* skip count byte */ 854 855 /* 856 * Well, for now, rather than attempt to implement 857 * this slightly dubious algorithm, we just look 858 * at the first 15 .. 859 */ 860 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 861 cpi->cpi_ncache = sizeof (*cp) - 1; 862 863 dp = cpi->cpi_cacheinfo; 864 if (BITX(cp->cp_eax, 31, 31) == 0) { 865 uint8_t *p = (void *)&cp->cp_eax; 866 for (i = 1; i < 3; i++) 867 if (p[i] != 0) 868 *dp++ = p[i]; 869 } 870 if (BITX(cp->cp_ebx, 31, 31) == 0) { 871 uint8_t *p = (void *)&cp->cp_ebx; 872 for (i = 0; i < 4; i++) 873 if (p[i] != 0) 874 *dp++ = p[i]; 875 } 876 if (BITX(cp->cp_ecx, 31, 31) == 0) { 877 uint8_t *p = (void *)&cp->cp_ecx; 878 for (i = 0; i < 4; i++) 879 if (p[i] != 0) 880 *dp++ = p[i]; 881 } 882 if (BITX(cp->cp_edx, 31, 31) == 0) { 883 uint8_t *p = (void *)&cp->cp_edx; 884 for (i = 0; i < 4; i++) 885 if (p[i] != 0) 886 *dp++ = p[i]; 887 } 888 break; 889 case 3: /* Processor serial number, if PSN supported */ 890 case 4: /* Deterministic cache parameters */ 891 case 5: /* Monitor/Mwait parameters */ 892 default: 893 break; 894 } 895 } 896 897 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 898 goto pass2_done; 899 900 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 901 nmax = NMAX_CPI_EXTD; 902 /* 903 * Copy the extended properties, fixing them as we go. 904 * (We already handled n == 0 and n == 1 in pass 1) 905 */ 906 iptr = (void *)cpi->cpi_brandstr; 907 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 908 cp->cp_eax = 0x80000000 + n; 909 (void) __cpuid_insn(cp); 910 switch (n) { 911 case 2: 912 case 3: 913 case 4: 914 /* 915 * Extract the brand string 916 */ 917 *iptr++ = cp->cp_eax; 918 *iptr++ = cp->cp_ebx; 919 *iptr++ = cp->cp_ecx; 920 *iptr++ = cp->cp_edx; 921 break; 922 case 5: 923 switch (cpi->cpi_vendor) { 924 case X86_VENDOR_AMD: 925 /* 926 * The Athlon and Duron were the first 927 * parts to report the sizes of the 928 * TLB for large pages. Before then, 929 * we don't trust the data. 930 */ 931 if (cpi->cpi_family < 6 || 932 (cpi->cpi_family == 6 && 933 cpi->cpi_model < 1)) 934 cp->cp_eax = 0; 935 break; 936 default: 937 break; 938 } 939 break; 940 case 6: 941 switch (cpi->cpi_vendor) { 942 case X86_VENDOR_AMD: 943 /* 944 * The Athlon and Duron were the first 945 * AMD parts with L2 TLB's. 946 * Before then, don't trust the data. 947 */ 948 if (cpi->cpi_family < 6 || 949 cpi->cpi_family == 6 && 950 cpi->cpi_model < 1) 951 cp->cp_eax = cp->cp_ebx = 0; 952 /* 953 * AMD Duron rev A0 reports L2 954 * cache size incorrectly as 1K 955 * when it is really 64K 956 */ 957 if (cpi->cpi_family == 6 && 958 cpi->cpi_model == 3 && 959 cpi->cpi_step == 0) { 960 cp->cp_ecx &= 0xffff; 961 cp->cp_ecx |= 0x400000; 962 } 963 break; 964 case X86_VENDOR_Cyrix: /* VIA C3 */ 965 /* 966 * VIA C3 processors are a bit messed 967 * up w.r.t. encoding cache sizes in %ecx 968 */ 969 if (cpi->cpi_family != 6) 970 break; 971 /* 972 * model 7 and 8 were incorrectly encoded 973 * 974 * xxx is model 8 really broken? 975 */ 976 if (cpi->cpi_model == 7 || 977 cpi->cpi_model == 8) 978 cp->cp_ecx = 979 BITX(cp->cp_ecx, 31, 24) << 16 | 980 BITX(cp->cp_ecx, 23, 16) << 12 | 981 BITX(cp->cp_ecx, 15, 8) << 8 | 982 BITX(cp->cp_ecx, 7, 0); 983 /* 984 * model 9 stepping 1 has wrong associativity 985 */ 986 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 987 cp->cp_ecx |= 8 << 12; 988 break; 989 case X86_VENDOR_Intel: 990 /* 991 * Extended L2 Cache features function. 992 * First appeared on Prescott. 993 */ 994 default: 995 break; 996 } 997 break; 998 default: 999 break; 1000 } 1001 } 1002 1003 pass2_done: 1004 cpi->cpi_pass = 2; 1005 } 1006 1007 static const char * 1008 intel_cpubrand(const struct cpuid_info *cpi) 1009 { 1010 int i; 1011 1012 if ((x86_feature & X86_CPUID) == 0 || 1013 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1014 return ("i486"); 1015 1016 switch (cpi->cpi_family) { 1017 case 5: 1018 return ("Intel Pentium(r)"); 1019 case 6: 1020 switch (cpi->cpi_model) { 1021 uint_t celeron, xeon; 1022 const struct cpuid_regs *cp; 1023 case 0: 1024 case 1: 1025 case 2: 1026 return ("Intel Pentium(r) Pro"); 1027 case 3: 1028 case 4: 1029 return ("Intel Pentium(r) II"); 1030 case 6: 1031 return ("Intel Celeron(r)"); 1032 case 5: 1033 case 7: 1034 celeron = xeon = 0; 1035 cp = &cpi->cpi_std[2]; /* cache info */ 1036 1037 for (i = 1; i < 3; i++) { 1038 uint_t tmp; 1039 1040 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1041 if (tmp == 0x40) 1042 celeron++; 1043 if (tmp >= 0x44 && tmp <= 0x45) 1044 xeon++; 1045 } 1046 1047 for (i = 0; i < 2; i++) { 1048 uint_t tmp; 1049 1050 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1051 if (tmp == 0x40) 1052 celeron++; 1053 else if (tmp >= 0x44 && tmp <= 0x45) 1054 xeon++; 1055 } 1056 1057 for (i = 0; i < 4; i++) { 1058 uint_t tmp; 1059 1060 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1061 if (tmp == 0x40) 1062 celeron++; 1063 else if (tmp >= 0x44 && tmp <= 0x45) 1064 xeon++; 1065 } 1066 1067 for (i = 0; i < 4; i++) { 1068 uint_t tmp; 1069 1070 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1071 if (tmp == 0x40) 1072 celeron++; 1073 else if (tmp >= 0x44 && tmp <= 0x45) 1074 xeon++; 1075 } 1076 1077 if (celeron) 1078 return ("Intel Celeron(r)"); 1079 if (xeon) 1080 return (cpi->cpi_model == 5 ? 1081 "Intel Pentium(r) II Xeon(tm)" : 1082 "Intel Pentium(r) III Xeon(tm)"); 1083 return (cpi->cpi_model == 5 ? 1084 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1085 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1086 default: 1087 break; 1088 } 1089 default: 1090 break; 1091 } 1092 1093 /* BrandID is present if the field is nonzero */ 1094 if (cpi->cpi_brandid != 0) { 1095 static const struct { 1096 uint_t bt_bid; 1097 const char *bt_str; 1098 } brand_tbl[] = { 1099 { 0x1, "Intel(r) Celeron(r)" }, 1100 { 0x2, "Intel(r) Pentium(r) III" }, 1101 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1102 { 0x4, "Intel(r) Pentium(r) III" }, 1103 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1104 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1105 { 0x8, "Intel(r) Pentium(r) 4" }, 1106 { 0x9, "Intel(r) Pentium(r) 4" }, 1107 { 0xa, "Intel(r) Celeron(r)" }, 1108 { 0xb, "Intel(r) Xeon(tm)" }, 1109 { 0xc, "Intel(r) Xeon(tm) MP" }, 1110 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1111 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1112 { 0x11, "Mobile Genuine Intel(r)" }, 1113 { 0x12, "Intel(r) Celeron(r) M" }, 1114 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1115 { 0x14, "Intel(r) Celeron(r)" }, 1116 { 0x15, "Mobile Genuine Intel(r)" }, 1117 { 0x16, "Intel(r) Pentium(r) M" }, 1118 { 0x17, "Mobile Intel(r) Celeron(r)" } 1119 }; 1120 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1121 uint_t sgn; 1122 1123 sgn = (cpi->cpi_family << 8) | 1124 (cpi->cpi_model << 4) | cpi->cpi_step; 1125 1126 for (i = 0; i < btblmax; i++) 1127 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1128 break; 1129 if (i < btblmax) { 1130 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1131 return ("Intel(r) Celeron(r)"); 1132 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1133 return ("Intel(r) Xeon(tm) MP"); 1134 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1135 return ("Intel(r) Xeon(tm)"); 1136 return (brand_tbl[i].bt_str); 1137 } 1138 } 1139 1140 return (NULL); 1141 } 1142 1143 static const char * 1144 amd_cpubrand(const struct cpuid_info *cpi) 1145 { 1146 if ((x86_feature & X86_CPUID) == 0 || 1147 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1148 return ("i486 compatible"); 1149 1150 switch (cpi->cpi_family) { 1151 case 5: 1152 switch (cpi->cpi_model) { 1153 case 0: 1154 case 1: 1155 case 2: 1156 case 3: 1157 case 4: 1158 case 5: 1159 return ("AMD-K5(r)"); 1160 case 6: 1161 case 7: 1162 return ("AMD-K6(r)"); 1163 case 8: 1164 return ("AMD-K6(r)-2"); 1165 case 9: 1166 return ("AMD-K6(r)-III"); 1167 default: 1168 return ("AMD (family 5)"); 1169 } 1170 case 6: 1171 switch (cpi->cpi_model) { 1172 case 1: 1173 return ("AMD-K7(tm)"); 1174 case 0: 1175 case 2: 1176 case 4: 1177 return ("AMD Athlon(tm)"); 1178 case 3: 1179 case 7: 1180 return ("AMD Duron(tm)"); 1181 case 6: 1182 case 8: 1183 case 10: 1184 /* 1185 * Use the L2 cache size to distinguish 1186 */ 1187 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1188 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1189 default: 1190 return ("AMD (family 6)"); 1191 } 1192 default: 1193 break; 1194 } 1195 1196 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1197 cpi->cpi_brandid != 0) { 1198 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1199 case 3: 1200 return ("AMD Opteron(tm) UP 1xx"); 1201 case 4: 1202 return ("AMD Opteron(tm) DP 2xx"); 1203 case 5: 1204 return ("AMD Opteron(tm) MP 8xx"); 1205 default: 1206 return ("AMD Opteron(tm)"); 1207 } 1208 } 1209 1210 return (NULL); 1211 } 1212 1213 static const char * 1214 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1215 { 1216 if ((x86_feature & X86_CPUID) == 0 || 1217 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1218 type == X86_TYPE_CYRIX_486) 1219 return ("i486 compatible"); 1220 1221 switch (type) { 1222 case X86_TYPE_CYRIX_6x86: 1223 return ("Cyrix 6x86"); 1224 case X86_TYPE_CYRIX_6x86L: 1225 return ("Cyrix 6x86L"); 1226 case X86_TYPE_CYRIX_6x86MX: 1227 return ("Cyrix 6x86MX"); 1228 case X86_TYPE_CYRIX_GXm: 1229 return ("Cyrix GXm"); 1230 case X86_TYPE_CYRIX_MediaGX: 1231 return ("Cyrix MediaGX"); 1232 case X86_TYPE_CYRIX_MII: 1233 return ("Cyrix M2"); 1234 case X86_TYPE_VIA_CYRIX_III: 1235 return ("VIA Cyrix M3"); 1236 default: 1237 /* 1238 * Have another wild guess .. 1239 */ 1240 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1241 return ("Cyrix 5x86"); 1242 else if (cpi->cpi_family == 5) { 1243 switch (cpi->cpi_model) { 1244 case 2: 1245 return ("Cyrix 6x86"); /* Cyrix M1 */ 1246 case 4: 1247 return ("Cyrix MediaGX"); 1248 default: 1249 break; 1250 } 1251 } else if (cpi->cpi_family == 6) { 1252 switch (cpi->cpi_model) { 1253 case 0: 1254 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1255 case 5: 1256 case 6: 1257 case 7: 1258 case 8: 1259 case 9: 1260 return ("VIA C3"); 1261 default: 1262 break; 1263 } 1264 } 1265 break; 1266 } 1267 return (NULL); 1268 } 1269 1270 /* 1271 * This only gets called in the case that the CPU extended 1272 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1273 * aren't available, or contain null bytes for some reason. 1274 */ 1275 static void 1276 fabricate_brandstr(struct cpuid_info *cpi) 1277 { 1278 const char *brand = NULL; 1279 1280 switch (cpi->cpi_vendor) { 1281 case X86_VENDOR_Intel: 1282 brand = intel_cpubrand(cpi); 1283 break; 1284 case X86_VENDOR_AMD: 1285 brand = amd_cpubrand(cpi); 1286 break; 1287 case X86_VENDOR_Cyrix: 1288 brand = cyrix_cpubrand(cpi, x86_type); 1289 break; 1290 case X86_VENDOR_NexGen: 1291 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1292 brand = "NexGen Nx586"; 1293 break; 1294 case X86_VENDOR_Centaur: 1295 if (cpi->cpi_family == 5) 1296 switch (cpi->cpi_model) { 1297 case 4: 1298 brand = "Centaur C6"; 1299 break; 1300 case 8: 1301 brand = "Centaur C2"; 1302 break; 1303 case 9: 1304 brand = "Centaur C3"; 1305 break; 1306 default: 1307 break; 1308 } 1309 break; 1310 case X86_VENDOR_Rise: 1311 if (cpi->cpi_family == 5 && 1312 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1313 brand = "Rise mP6"; 1314 break; 1315 case X86_VENDOR_SiS: 1316 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1317 brand = "SiS 55x"; 1318 break; 1319 case X86_VENDOR_TM: 1320 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1321 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1322 break; 1323 case X86_VENDOR_NSC: 1324 case X86_VENDOR_UMC: 1325 default: 1326 break; 1327 } 1328 if (brand) { 1329 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1330 return; 1331 } 1332 1333 /* 1334 * If all else fails ... 1335 */ 1336 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1337 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1338 cpi->cpi_model, cpi->cpi_step); 1339 } 1340 1341 /* 1342 * This routine is called just after kernel memory allocation 1343 * becomes available on cpu0, and as part of mp_startup() on 1344 * the other cpus. 1345 * 1346 * Fixup the brand string. 1347 */ 1348 /*ARGSUSED*/ 1349 void 1350 cpuid_pass3(cpu_t *cpu) 1351 { 1352 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1353 1354 ASSERT(cpi->cpi_pass == 2); 1355 1356 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1357 fabricate_brandstr(cpi); 1358 goto pass3_done; 1359 } 1360 1361 /* 1362 * If we successfully extracted a brand string from the cpuid 1363 * instruction, clean it up by removing leading spaces and 1364 * similar junk. 1365 */ 1366 if (cpi->cpi_brandstr[0]) { 1367 size_t maxlen = sizeof (cpi->cpi_brandstr); 1368 char *src, *dst; 1369 1370 dst = src = (char *)cpi->cpi_brandstr; 1371 src[maxlen - 1] = '\0'; 1372 /* 1373 * strip leading spaces 1374 */ 1375 while (*src == ' ') 1376 src++; 1377 /* 1378 * Remove any 'Genuine' or "Authentic" prefixes 1379 */ 1380 if (strncmp(src, "Genuine ", 8) == 0) 1381 src += 8; 1382 if (strncmp(src, "Authentic ", 10) == 0) 1383 src += 10; 1384 1385 /* 1386 * Now do an in-place copy. 1387 * Map (R) to (r) and (TM) to (tm). 1388 * The era of teletypes is long gone, and there's 1389 * -really- no need to shout. 1390 */ 1391 while (*src != '\0') { 1392 if (src[0] == '(') { 1393 if (strncmp(src + 1, "R)", 2) == 0) { 1394 (void) strncpy(dst, "(r)", 3); 1395 src += 3; 1396 dst += 3; 1397 continue; 1398 } 1399 if (strncmp(src + 1, "TM)", 3) == 0) { 1400 (void) strncpy(dst, "(tm)", 4); 1401 src += 4; 1402 dst += 4; 1403 continue; 1404 } 1405 } 1406 *dst++ = *src++; 1407 } 1408 *dst = '\0'; 1409 1410 /* 1411 * Finally, remove any trailing spaces 1412 */ 1413 while (--dst > cpi->cpi_brandstr) 1414 if (*dst == ' ') 1415 *dst = '\0'; 1416 else 1417 break; 1418 } else 1419 fabricate_brandstr(cpi); 1420 1421 pass3_done: 1422 cpi->cpi_pass = 3; 1423 } 1424 1425 /* 1426 * This routine is called out of bind_hwcap() much later in the life 1427 * of the kernel (post_startup()). The job of this routine is to resolve 1428 * the hardware feature support and kernel support for those features into 1429 * what we're actually going to tell applications via the aux vector. 1430 */ 1431 uint_t 1432 cpuid_pass4(cpu_t *cpu) 1433 { 1434 struct cpuid_info *cpi; 1435 uint_t hwcap_flags = 0; 1436 1437 if (cpu == NULL) 1438 cpu = CPU; 1439 cpi = cpu->cpu_m.mcpu_cpi; 1440 1441 ASSERT(cpi->cpi_pass == 3); 1442 1443 if (cpi->cpi_maxeax >= 1) { 1444 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1445 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1446 1447 *edx = CPI_FEATURES_EDX(cpi); 1448 *ecx = CPI_FEATURES_ECX(cpi); 1449 1450 /* 1451 * [these require explicit kernel support] 1452 */ 1453 if ((x86_feature & X86_SEP) == 0) 1454 *edx &= ~CPUID_INTC_EDX_SEP; 1455 1456 if ((x86_feature & X86_SSE) == 0) 1457 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 1458 if ((x86_feature & X86_SSE2) == 0) 1459 *edx &= ~CPUID_INTC_EDX_SSE2; 1460 1461 if ((x86_feature & X86_HTT) == 0) 1462 *edx &= ~CPUID_INTC_EDX_HTT; 1463 1464 if ((x86_feature & X86_SSE3) == 0) 1465 *ecx &= ~CPUID_INTC_ECX_SSE3; 1466 1467 /* 1468 * [no explicit support required beyond x87 fp context] 1469 */ 1470 if (!fpu_exists) 1471 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 1472 1473 /* 1474 * Now map the supported feature vector to things that we 1475 * think userland will care about. 1476 */ 1477 if (*edx & CPUID_INTC_EDX_SEP) 1478 hwcap_flags |= AV_386_SEP; 1479 if (*edx & CPUID_INTC_EDX_SSE) 1480 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 1481 if (*edx & CPUID_INTC_EDX_SSE2) 1482 hwcap_flags |= AV_386_SSE2; 1483 if (*ecx & CPUID_INTC_ECX_SSE3) 1484 hwcap_flags |= AV_386_SSE3; 1485 1486 if (*edx & CPUID_INTC_EDX_FPU) 1487 hwcap_flags |= AV_386_FPU; 1488 if (*edx & CPUID_INTC_EDX_MMX) 1489 hwcap_flags |= AV_386_MMX; 1490 1491 if (*edx & CPUID_INTC_EDX_TSC) 1492 hwcap_flags |= AV_386_TSC; 1493 if (*edx & CPUID_INTC_EDX_CX8) 1494 hwcap_flags |= AV_386_CX8; 1495 if (*edx & CPUID_INTC_EDX_CMOV) 1496 hwcap_flags |= AV_386_CMOV; 1497 if (*ecx & CPUID_INTC_ECX_MON) 1498 hwcap_flags |= AV_386_MON; 1499 #if defined(CPUID_INTC_ECX_CX16) 1500 if (*ecx & CPUID_INTC_ECX_CX16) 1501 hwcap_flags |= AV_386_CX16; 1502 #endif 1503 } 1504 1505 if (x86_feature & X86_HTT) 1506 hwcap_flags |= AV_386_PAUSE; 1507 1508 if (cpi->cpi_xmaxeax < 0x80000001) 1509 goto pass4_done; 1510 1511 switch (cpi->cpi_vendor) { 1512 struct cpuid_regs cp; 1513 uint32_t *edx; 1514 1515 case X86_VENDOR_Intel: /* sigh */ 1516 case X86_VENDOR_AMD: 1517 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 1518 1519 *edx = CPI_FEATURES_XTD_EDX(cpi); 1520 1521 /* 1522 * [no explicit support required beyond 1523 * x87 fp context and exception handlers] 1524 */ 1525 if (!fpu_exists) 1526 *edx &= ~(CPUID_AMD_EDX_MMXamd | 1527 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 1528 1529 if ((x86_feature & X86_ASYSC) == 0) 1530 *edx &= ~CPUID_AMD_EDX_SYSC; 1531 if ((x86_feature & X86_NX) == 0) 1532 *edx &= ~CPUID_AMD_EDX_NX; 1533 #if !defined(_LP64) 1534 *edx &= ~CPUID_AMD_EDX_LM; 1535 #endif 1536 /* 1537 * Now map the supported feature vector to 1538 * things that we think userland will care about. 1539 */ 1540 if (*edx & CPUID_AMD_EDX_SYSC) 1541 hwcap_flags |= AV_386_AMD_SYSC; 1542 if (*edx & CPUID_AMD_EDX_MMXamd) 1543 hwcap_flags |= AV_386_AMD_MMX; 1544 if (*edx & CPUID_AMD_EDX_3DNow) 1545 hwcap_flags |= AV_386_AMD_3DNow; 1546 if (*edx & CPUID_AMD_EDX_3DNowx) 1547 hwcap_flags |= AV_386_AMD_3DNowx; 1548 break; 1549 1550 case X86_VENDOR_TM: 1551 cp.cp_eax = 0x80860001; 1552 (void) __cpuid_insn(&cp); 1553 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 1554 break; 1555 1556 default: 1557 break; 1558 } 1559 1560 pass4_done: 1561 cpi->cpi_pass = 4; 1562 return (hwcap_flags); 1563 } 1564 1565 1566 /* 1567 * Simulate the cpuid instruction using the data we previously 1568 * captured about this CPU. We try our best to return the truth 1569 * about the hardware, independently of kernel support. 1570 */ 1571 uint32_t 1572 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 1573 { 1574 struct cpuid_info *cpi; 1575 struct cpuid_regs *xcp; 1576 1577 if (cpu == NULL) 1578 cpu = CPU; 1579 cpi = cpu->cpu_m.mcpu_cpi; 1580 1581 ASSERT(cpuid_checkpass(cpu, 3)); 1582 1583 /* 1584 * CPUID data is cached in two separate places: cpi_std for standard 1585 * CPUID functions, and cpi_extd for extended CPUID functions. 1586 */ 1587 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 1588 xcp = &cpi->cpi_std[cp->cp_eax]; 1589 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 1590 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 1591 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 1592 else 1593 /* 1594 * The caller is asking for data from an input parameter which 1595 * the kernel has not cached. In this case we go fetch from 1596 * the hardware and return the data directly to the user. 1597 */ 1598 return (__cpuid_insn(cp)); 1599 1600 cp->cp_eax = xcp->cp_eax; 1601 cp->cp_ebx = xcp->cp_ebx; 1602 cp->cp_ecx = xcp->cp_ecx; 1603 cp->cp_edx = xcp->cp_edx; 1604 return (cp->cp_eax); 1605 } 1606 1607 int 1608 cpuid_checkpass(cpu_t *cpu, int pass) 1609 { 1610 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 1611 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 1612 } 1613 1614 int 1615 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 1616 { 1617 ASSERT(cpuid_checkpass(cpu, 3)); 1618 1619 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 1620 } 1621 1622 int 1623 cpuid_is_cmt(cpu_t *cpu) 1624 { 1625 if (cpu == NULL) 1626 cpu = CPU; 1627 1628 ASSERT(cpuid_checkpass(cpu, 1)); 1629 1630 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 1631 } 1632 1633 /* 1634 * AMD and Intel both implement the 64-bit variant of the syscall 1635 * instruction (syscallq), so if there's -any- support for syscall, 1636 * cpuid currently says "yes, we support this". 1637 * 1638 * However, Intel decided to -not- implement the 32-bit variant of the 1639 * syscall instruction, so we provide a predicate to allow our caller 1640 * to test that subtlety here. 1641 */ 1642 /*ARGSUSED*/ 1643 int 1644 cpuid_syscall32_insn(cpu_t *cpu) 1645 { 1646 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 1647 1648 if (x86_feature & X86_ASYSC) 1649 return (x86_vendor != X86_VENDOR_Intel); 1650 return (0); 1651 } 1652 1653 int 1654 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 1655 { 1656 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1657 1658 static const char fmt[] = 1659 "x86 (%s family %d model %d step %d clock %d MHz)"; 1660 static const char fmt_ht[] = 1661 "x86 (chipid 0x%x %s family %d model %d step %d clock %d MHz)"; 1662 1663 ASSERT(cpuid_checkpass(cpu, 1)); 1664 1665 if (cpuid_is_cmt(cpu)) 1666 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 1667 cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model, 1668 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1669 return (snprintf(s, n, fmt, 1670 cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model, 1671 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1672 } 1673 1674 const char * 1675 cpuid_getvendorstr(cpu_t *cpu) 1676 { 1677 ASSERT(cpuid_checkpass(cpu, 1)); 1678 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 1679 } 1680 1681 uint_t 1682 cpuid_getvendor(cpu_t *cpu) 1683 { 1684 ASSERT(cpuid_checkpass(cpu, 1)); 1685 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 1686 } 1687 1688 uint_t 1689 cpuid_getfamily(cpu_t *cpu) 1690 { 1691 ASSERT(cpuid_checkpass(cpu, 1)); 1692 return (cpu->cpu_m.mcpu_cpi->cpi_family); 1693 } 1694 1695 uint_t 1696 cpuid_getmodel(cpu_t *cpu) 1697 { 1698 ASSERT(cpuid_checkpass(cpu, 1)); 1699 return (cpu->cpu_m.mcpu_cpi->cpi_model); 1700 } 1701 1702 uint_t 1703 cpuid_get_ncpu_per_chip(cpu_t *cpu) 1704 { 1705 ASSERT(cpuid_checkpass(cpu, 1)); 1706 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 1707 } 1708 1709 uint_t 1710 cpuid_get_ncore_per_chip(cpu_t *cpu) 1711 { 1712 ASSERT(cpuid_checkpass(cpu, 1)); 1713 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 1714 } 1715 1716 uint_t 1717 cpuid_getstep(cpu_t *cpu) 1718 { 1719 ASSERT(cpuid_checkpass(cpu, 1)); 1720 return (cpu->cpu_m.mcpu_cpi->cpi_step); 1721 } 1722 1723 chipid_t 1724 chip_plat_get_chipid(cpu_t *cpu) 1725 { 1726 ASSERT(cpuid_checkpass(cpu, 1)); 1727 1728 if (cpuid_is_cmt(cpu)) 1729 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 1730 return (cpu->cpu_id); 1731 } 1732 1733 id_t 1734 chip_plat_get_coreid(cpu_t *cpu) 1735 { 1736 ASSERT(cpuid_checkpass(cpu, 1)); 1737 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 1738 } 1739 1740 int 1741 chip_plat_get_clogid(cpu_t *cpu) 1742 { 1743 ASSERT(cpuid_checkpass(cpu, 1)); 1744 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 1745 } 1746 1747 void 1748 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 1749 { 1750 struct cpuid_info *cpi; 1751 1752 if (cpu == NULL) 1753 cpu = CPU; 1754 cpi = cpu->cpu_m.mcpu_cpi; 1755 1756 ASSERT(cpuid_checkpass(cpu, 1)); 1757 1758 if (pabits) 1759 *pabits = cpi->cpi_pabits; 1760 if (vabits) 1761 *vabits = cpi->cpi_vabits; 1762 } 1763 1764 /* 1765 * Returns the number of data TLB entries for a corresponding 1766 * pagesize. If it can't be computed, or isn't known, the 1767 * routine returns zero. If you ask about an architecturally 1768 * impossible pagesize, the routine will panic (so that the 1769 * hat implementor knows that things are inconsistent.) 1770 */ 1771 uint_t 1772 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 1773 { 1774 struct cpuid_info *cpi; 1775 uint_t dtlb_nent = 0; 1776 1777 if (cpu == NULL) 1778 cpu = CPU; 1779 cpi = cpu->cpu_m.mcpu_cpi; 1780 1781 ASSERT(cpuid_checkpass(cpu, 1)); 1782 1783 /* 1784 * Check the L2 TLB info 1785 */ 1786 if (cpi->cpi_xmaxeax >= 0x80000006) { 1787 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 1788 1789 switch (pagesize) { 1790 1791 case 4 * 1024: 1792 /* 1793 * All zero in the top 16 bits of the register 1794 * indicates a unified TLB. Size is in low 16 bits. 1795 */ 1796 if ((cp->cp_ebx & 0xffff0000) == 0) 1797 dtlb_nent = cp->cp_ebx & 0x0000ffff; 1798 else 1799 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 1800 break; 1801 1802 case 2 * 1024 * 1024: 1803 if ((cp->cp_eax & 0xffff0000) == 0) 1804 dtlb_nent = cp->cp_eax & 0x0000ffff; 1805 else 1806 dtlb_nent = BITX(cp->cp_eax, 27, 16); 1807 break; 1808 1809 default: 1810 panic("unknown L2 pagesize"); 1811 /*NOTREACHED*/ 1812 } 1813 } 1814 1815 if (dtlb_nent != 0) 1816 return (dtlb_nent); 1817 1818 /* 1819 * No L2 TLB support for this size, try L1. 1820 */ 1821 if (cpi->cpi_xmaxeax >= 0x80000005) { 1822 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 1823 1824 switch (pagesize) { 1825 case 4 * 1024: 1826 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 1827 break; 1828 case 2 * 1024 * 1024: 1829 dtlb_nent = BITX(cp->cp_eax, 23, 16); 1830 break; 1831 default: 1832 panic("unknown L1 d-TLB pagesize"); 1833 /*NOTREACHED*/ 1834 } 1835 } 1836 1837 return (dtlb_nent); 1838 } 1839 1840 /* 1841 * Return 0 if the erratum is not present or not applicable, positive 1842 * if it is, and negative if the status of the erratum is unknown. 1843 * 1844 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 1845 * Processors" #25759, Rev 3.57, August 2005 1846 */ 1847 int 1848 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 1849 { 1850 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1851 uint_t eax; 1852 1853 if (cpi->cpi_vendor != X86_VENDOR_AMD) 1854 return (0); 1855 1856 eax = cpi->cpi_std[1].cp_eax; 1857 1858 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 1859 #define SH_B3(eax) (eax == 0xf51) 1860 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 1861 1862 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 1863 1864 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 1865 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 1866 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 1867 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 1868 1869 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 1870 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 1871 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 1872 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 1873 1874 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 1875 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 1876 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 1877 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 1878 #define BH_E4(eax) (eax == 0x20fb1) 1879 #define SH_E5(eax) (eax == 0x20f42) 1880 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 1881 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 1882 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 1883 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 1884 DH_E6(eax) || JH_E6(eax)) 1885 1886 switch (erratum) { 1887 case 1: 1888 return (1); 1889 case 51: /* what does the asterisk mean? */ 1890 return (B(eax) || SH_C0(eax) || CG(eax)); 1891 case 52: 1892 return (B(eax)); 1893 case 57: 1894 return (1); 1895 case 58: 1896 return (B(eax)); 1897 case 60: 1898 return (1); 1899 case 61: 1900 case 62: 1901 case 63: 1902 case 64: 1903 case 65: 1904 case 66: 1905 case 68: 1906 case 69: 1907 case 70: 1908 case 71: 1909 return (B(eax)); 1910 case 72: 1911 return (SH_B0(eax)); 1912 case 74: 1913 return (B(eax)); 1914 case 75: 1915 return (1); 1916 case 76: 1917 return (B(eax)); 1918 case 77: 1919 return (1); 1920 case 78: 1921 return (B(eax) || SH_C0(eax)); 1922 case 79: 1923 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1924 case 80: 1925 case 81: 1926 case 82: 1927 return (B(eax)); 1928 case 83: 1929 return (B(eax) || SH_C0(eax) || CG(eax)); 1930 case 85: 1931 return (1); 1932 case 86: 1933 return (SH_C0(eax) || CG(eax)); 1934 case 88: 1935 #if !defined(__amd64) 1936 return (0); 1937 #else 1938 return (B(eax) || SH_C0(eax)); 1939 #endif 1940 case 89: 1941 return (1); 1942 case 90: 1943 return (B(eax) || SH_C0(eax) || CG(eax)); 1944 case 91: 1945 case 92: 1946 return (B(eax) || SH_C0(eax)); 1947 case 93: 1948 return (SH_C0(eax)); 1949 case 94: 1950 return (B(eax) || SH_C0(eax) || CG(eax)); 1951 case 95: 1952 #if !defined(__amd64) 1953 return (0); 1954 #else 1955 return (B(eax) || SH_C0(eax)); 1956 #endif 1957 case 96: 1958 return (B(eax) || SH_C0(eax) || CG(eax)); 1959 case 97: 1960 case 98: 1961 return (SH_C0(eax) || CG(eax)); 1962 case 99: 1963 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1964 case 100: 1965 return (B(eax) || SH_C0(eax)); 1966 case 101: 1967 case 103: 1968 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1969 case 104: 1970 return (SH_C0(eax) || CG(eax) || D0(eax)); 1971 case 105: 1972 case 106: 1973 case 107: 1974 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1975 case 108: 1976 return (DH_CG(eax)); 1977 case 109: 1978 return (SH_C0(eax) || CG(eax) || D0(eax)); 1979 case 110: 1980 return (D0(eax) || EX(eax)); 1981 case 111: 1982 return (CG(eax)); 1983 case 112: 1984 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1985 case 113: 1986 return (eax == 0x20fc0); 1987 case 114: 1988 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 1989 case 115: 1990 return (SH_E0(eax) || JH_E1(eax)); 1991 case 116: 1992 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 1993 case 117: 1994 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1995 case 118: 1996 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 1997 JH_E6(eax)); 1998 case 121: 1999 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2000 case 122: 2001 return (SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2002 case 123: 2003 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2004 case 131: 2005 return (1); 2006 case 6336786: 2007 /* 2008 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2009 * if this is a K8 family processor 2010 */ 2011 if (CPI_FAMILY(cpi) == 0xf) { 2012 struct cpuid_regs regs; 2013 regs.cp_eax = 0x80000007; 2014 (void) __cpuid_insn(®s); 2015 return (!(regs.cp_edx & 0x100)); 2016 } 2017 return (0); 2018 case 6323525: 2019 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2020 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2021 2022 default: 2023 return (-1); 2024 } 2025 } 2026 2027 static const char assoc_str[] = "associativity"; 2028 static const char line_str[] = "line-size"; 2029 static const char size_str[] = "size"; 2030 2031 static void 2032 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2033 uint32_t val) 2034 { 2035 char buf[128]; 2036 2037 /* 2038 * ndi_prop_update_int() is used because it is desirable for 2039 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2040 */ 2041 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2042 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2043 } 2044 2045 /* 2046 * Intel-style cache/tlb description 2047 * 2048 * Standard cpuid level 2 gives a randomly ordered 2049 * selection of tags that index into a table that describes 2050 * cache and tlb properties. 2051 */ 2052 2053 static const char l1_icache_str[] = "l1-icache"; 2054 static const char l1_dcache_str[] = "l1-dcache"; 2055 static const char l2_cache_str[] = "l2-cache"; 2056 static const char itlb4k_str[] = "itlb-4K"; 2057 static const char dtlb4k_str[] = "dtlb-4K"; 2058 static const char itlb4M_str[] = "itlb-4M"; 2059 static const char dtlb4M_str[] = "dtlb-4M"; 2060 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2061 static const char dtlb44_str[] = "dtlb-4K-4M"; 2062 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2063 static const char sl2_cache_str[] = "sectored-l2-cache"; 2064 static const char itrace_str[] = "itrace-cache"; 2065 static const char sl3_cache_str[] = "sectored-l3-cache"; 2066 2067 static const struct cachetab { 2068 uint8_t ct_code; 2069 uint8_t ct_assoc; 2070 uint16_t ct_line_size; 2071 size_t ct_size; 2072 const char *ct_label; 2073 } intel_ctab[] = { 2074 /* maintain descending order! */ 2075 { 0xb3, 4, 0, 128, dtlb4k_str }, 2076 { 0xb0, 4, 0, 128, itlb4k_str }, 2077 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2078 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2079 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2080 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2081 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2082 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2083 { 0x81, 8, 32, 128*1024, l2_cache_str}, /* suspect! */ 2084 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2085 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2086 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2087 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2088 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2089 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2090 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2091 { 0x72, 8, 0, 32*1024, itrace_str}, 2092 { 0x71, 8, 0, 16*1024, itrace_str}, 2093 { 0x70, 8, 0, 12*1024, itrace_str}, 2094 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2095 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2096 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2097 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2098 { 0x5d, 0, 0, 256, dtlb44_str}, 2099 { 0x5c, 0, 0, 128, dtlb44_str}, 2100 { 0x5b, 0, 0, 64, dtlb44_str}, 2101 { 0x52, 0, 0, 256, itlb424_str}, 2102 { 0x51, 0, 0, 128, itlb424_str}, 2103 { 0x50, 0, 0, 64, itlb424_str}, 2104 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2105 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2106 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2107 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2108 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2109 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2110 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2111 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2112 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2113 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2114 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2115 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2116 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2117 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2118 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2119 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2120 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2121 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2122 { 0x04, 4, 0, 8, dtlb4M_str}, 2123 { 0x03, 4, 0, 64, dtlb4k_str}, 2124 { 0x02, 4, 0, 2, itlb4M_str}, 2125 { 0x01, 4, 0, 32, itlb4k_str}, 2126 { 0 } 2127 }; 2128 2129 static const struct cachetab cyrix_ctab[] = { 2130 { 0x70, 4, 0, 32, "tlb-4K" }, 2131 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2132 { 0 } 2133 }; 2134 2135 /* 2136 * Search a cache table for a matching entry 2137 */ 2138 static const struct cachetab * 2139 find_cacheent(const struct cachetab *ct, uint_t code) 2140 { 2141 if (code != 0) { 2142 for (; ct->ct_code != 0; ct++) 2143 if (ct->ct_code <= code) 2144 break; 2145 if (ct->ct_code == code) 2146 return (ct); 2147 } 2148 return (NULL); 2149 } 2150 2151 /* 2152 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2153 * The walk is terminated if the walker returns non-zero. 2154 */ 2155 static void 2156 intel_walk_cacheinfo(struct cpuid_info *cpi, 2157 void *arg, int (*func)(void *, const struct cachetab *)) 2158 { 2159 const struct cachetab *ct; 2160 uint8_t *dp; 2161 int i; 2162 2163 if ((dp = cpi->cpi_cacheinfo) == NULL) 2164 return; 2165 for (i = 0; i < cpi->cpi_ncache; i++, dp++) 2166 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2167 if (func(arg, ct) != 0) 2168 break; 2169 } 2170 } 2171 2172 /* 2173 * (Like the Intel one, except for Cyrix CPUs) 2174 */ 2175 static void 2176 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2177 void *arg, int (*func)(void *, const struct cachetab *)) 2178 { 2179 const struct cachetab *ct; 2180 uint8_t *dp; 2181 int i; 2182 2183 if ((dp = cpi->cpi_cacheinfo) == NULL) 2184 return; 2185 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2186 /* 2187 * Search Cyrix-specific descriptor table first .. 2188 */ 2189 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2190 if (func(arg, ct) != 0) 2191 break; 2192 continue; 2193 } 2194 /* 2195 * .. else fall back to the Intel one 2196 */ 2197 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2198 if (func(arg, ct) != 0) 2199 break; 2200 continue; 2201 } 2202 } 2203 } 2204 2205 /* 2206 * A cacheinfo walker that adds associativity, line-size, and size properties 2207 * to the devinfo node it is passed as an argument. 2208 */ 2209 static int 2210 add_cacheent_props(void *arg, const struct cachetab *ct) 2211 { 2212 dev_info_t *devi = arg; 2213 2214 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2215 if (ct->ct_line_size != 0) 2216 add_cache_prop(devi, ct->ct_label, line_str, 2217 ct->ct_line_size); 2218 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2219 return (0); 2220 } 2221 2222 static const char fully_assoc[] = "fully-associative?"; 2223 2224 /* 2225 * AMD style cache/tlb description 2226 * 2227 * Extended functions 5 and 6 directly describe properties of 2228 * tlbs and various cache levels. 2229 */ 2230 static void 2231 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2232 { 2233 switch (assoc) { 2234 case 0: /* reserved; ignore */ 2235 break; 2236 default: 2237 add_cache_prop(devi, label, assoc_str, assoc); 2238 break; 2239 case 0xff: 2240 add_cache_prop(devi, label, fully_assoc, 1); 2241 break; 2242 } 2243 } 2244 2245 static void 2246 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2247 { 2248 if (size == 0) 2249 return; 2250 add_cache_prop(devi, label, size_str, size); 2251 add_amd_assoc(devi, label, assoc); 2252 } 2253 2254 static void 2255 add_amd_cache(dev_info_t *devi, const char *label, 2256 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2257 { 2258 if (size == 0 || line_size == 0) 2259 return; 2260 add_amd_assoc(devi, label, assoc); 2261 /* 2262 * Most AMD parts have a sectored cache. Multiple cache lines are 2263 * associated with each tag. A sector consists of all cache lines 2264 * associated with a tag. For example, the AMD K6-III has a sector 2265 * size of 2 cache lines per tag. 2266 */ 2267 if (lines_per_tag != 0) 2268 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2269 add_cache_prop(devi, label, line_str, line_size); 2270 add_cache_prop(devi, label, size_str, size * 1024); 2271 } 2272 2273 static void 2274 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2275 { 2276 switch (assoc) { 2277 case 0: /* off */ 2278 break; 2279 case 1: 2280 case 2: 2281 case 4: 2282 add_cache_prop(devi, label, assoc_str, assoc); 2283 break; 2284 case 6: 2285 add_cache_prop(devi, label, assoc_str, 8); 2286 break; 2287 case 8: 2288 add_cache_prop(devi, label, assoc_str, 16); 2289 break; 2290 case 0xf: 2291 add_cache_prop(devi, label, fully_assoc, 1); 2292 break; 2293 default: /* reserved; ignore */ 2294 break; 2295 } 2296 } 2297 2298 static void 2299 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2300 { 2301 if (size == 0 || assoc == 0) 2302 return; 2303 add_amd_l2_assoc(devi, label, assoc); 2304 add_cache_prop(devi, label, size_str, size); 2305 } 2306 2307 static void 2308 add_amd_l2_cache(dev_info_t *devi, const char *label, 2309 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2310 { 2311 if (size == 0 || assoc == 0 || line_size == 0) 2312 return; 2313 add_amd_l2_assoc(devi, label, assoc); 2314 if (lines_per_tag != 0) 2315 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2316 add_cache_prop(devi, label, line_str, line_size); 2317 add_cache_prop(devi, label, size_str, size * 1024); 2318 } 2319 2320 static void 2321 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 2322 { 2323 struct cpuid_regs *cp; 2324 2325 if (cpi->cpi_xmaxeax < 0x80000005) 2326 return; 2327 cp = &cpi->cpi_extd[5]; 2328 2329 /* 2330 * 4M/2M L1 TLB configuration 2331 * 2332 * We report the size for 2M pages because AMD uses two 2333 * TLB entries for one 4M page. 2334 */ 2335 add_amd_tlb(devi, "dtlb-2M", 2336 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 2337 add_amd_tlb(devi, "itlb-2M", 2338 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 2339 2340 /* 2341 * 4K L1 TLB configuration 2342 */ 2343 2344 switch (cpi->cpi_vendor) { 2345 uint_t nentries; 2346 case X86_VENDOR_TM: 2347 if (cpi->cpi_family >= 5) { 2348 /* 2349 * Crusoe processors have 256 TLB entries, but 2350 * cpuid data format constrains them to only 2351 * reporting 255 of them. 2352 */ 2353 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 2354 nentries = 256; 2355 /* 2356 * Crusoe processors also have a unified TLB 2357 */ 2358 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 2359 nentries); 2360 break; 2361 } 2362 /*FALLTHROUGH*/ 2363 default: 2364 add_amd_tlb(devi, itlb4k_str, 2365 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 2366 add_amd_tlb(devi, dtlb4k_str, 2367 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 2368 break; 2369 } 2370 2371 /* 2372 * data L1 cache configuration 2373 */ 2374 2375 add_amd_cache(devi, l1_dcache_str, 2376 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 2377 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 2378 2379 /* 2380 * code L1 cache configuration 2381 */ 2382 2383 add_amd_cache(devi, l1_icache_str, 2384 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 2385 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 2386 2387 if (cpi->cpi_xmaxeax < 0x80000006) 2388 return; 2389 cp = &cpi->cpi_extd[6]; 2390 2391 /* Check for a unified L2 TLB for large pages */ 2392 2393 if (BITX(cp->cp_eax, 31, 16) == 0) 2394 add_amd_l2_tlb(devi, "l2-tlb-2M", 2395 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2396 else { 2397 add_amd_l2_tlb(devi, "l2-dtlb-2M", 2398 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2399 add_amd_l2_tlb(devi, "l2-itlb-2M", 2400 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2401 } 2402 2403 /* Check for a unified L2 TLB for 4K pages */ 2404 2405 if (BITX(cp->cp_ebx, 31, 16) == 0) { 2406 add_amd_l2_tlb(devi, "l2-tlb-4K", 2407 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2408 } else { 2409 add_amd_l2_tlb(devi, "l2-dtlb-4K", 2410 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2411 add_amd_l2_tlb(devi, "l2-itlb-4K", 2412 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2413 } 2414 2415 add_amd_l2_cache(devi, l2_cache_str, 2416 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 2417 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 2418 } 2419 2420 /* 2421 * There are two basic ways that the x86 world describes it cache 2422 * and tlb architecture - Intel's way and AMD's way. 2423 * 2424 * Return which flavor of cache architecture we should use 2425 */ 2426 static int 2427 x86_which_cacheinfo(struct cpuid_info *cpi) 2428 { 2429 switch (cpi->cpi_vendor) { 2430 case X86_VENDOR_Intel: 2431 if (cpi->cpi_maxeax >= 2) 2432 return (X86_VENDOR_Intel); 2433 break; 2434 case X86_VENDOR_AMD: 2435 /* 2436 * The K5 model 1 was the first part from AMD that reported 2437 * cache sizes via extended cpuid functions. 2438 */ 2439 if (cpi->cpi_family > 5 || 2440 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 2441 return (X86_VENDOR_AMD); 2442 break; 2443 case X86_VENDOR_TM: 2444 if (cpi->cpi_family >= 5) 2445 return (X86_VENDOR_AMD); 2446 /*FALLTHROUGH*/ 2447 default: 2448 /* 2449 * If they have extended CPU data for 0x80000005 2450 * then we assume they have AMD-format cache 2451 * information. 2452 * 2453 * If not, and the vendor happens to be Cyrix, 2454 * then try our-Cyrix specific handler. 2455 * 2456 * If we're not Cyrix, then assume we're using Intel's 2457 * table-driven format instead. 2458 */ 2459 if (cpi->cpi_xmaxeax >= 0x80000005) 2460 return (X86_VENDOR_AMD); 2461 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 2462 return (X86_VENDOR_Cyrix); 2463 else if (cpi->cpi_maxeax >= 2) 2464 return (X86_VENDOR_Intel); 2465 break; 2466 } 2467 return (-1); 2468 } 2469 2470 /* 2471 * create a node for the given cpu under the prom root node. 2472 * Also, create a cpu node in the device tree. 2473 */ 2474 static dev_info_t *cpu_nex_devi = NULL; 2475 static kmutex_t cpu_node_lock; 2476 2477 /* 2478 * Called from post_startup() and mp_startup() 2479 */ 2480 void 2481 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 2482 { 2483 dev_info_t *cpu_devi; 2484 int create; 2485 2486 mutex_enter(&cpu_node_lock); 2487 2488 /* 2489 * create a nexus node for all cpus identified as 'cpu_id' under 2490 * the root node. 2491 */ 2492 if (cpu_nex_devi == NULL) { 2493 if (ndi_devi_alloc(ddi_root_node(), "cpus", 2494 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 2495 mutex_exit(&cpu_node_lock); 2496 return; 2497 } 2498 (void) ndi_devi_online(cpu_nex_devi, 0); 2499 } 2500 2501 /* 2502 * create a child node for cpu identified as 'cpu_id' 2503 */ 2504 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 2505 cpu_id); 2506 if (cpu_devi == NULL) { 2507 mutex_exit(&cpu_node_lock); 2508 return; 2509 } 2510 2511 /* device_type */ 2512 2513 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2514 "device_type", "cpu"); 2515 2516 /* reg */ 2517 2518 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2519 "reg", cpu_id); 2520 2521 /* cpu-mhz, and clock-frequency */ 2522 2523 if (cpu_freq > 0) { 2524 long long mul; 2525 2526 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2527 "cpu-mhz", cpu_freq); 2528 2529 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 2530 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2531 "clock-frequency", (int)mul); 2532 } 2533 2534 (void) ndi_devi_online(cpu_devi, 0); 2535 2536 if ((x86_feature & X86_CPUID) == 0) { 2537 mutex_exit(&cpu_node_lock); 2538 return; 2539 } 2540 2541 /* vendor-id */ 2542 2543 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2544 "vendor-id", cpi->cpi_vendorstr); 2545 2546 if (cpi->cpi_maxeax == 0) { 2547 mutex_exit(&cpu_node_lock); 2548 return; 2549 } 2550 2551 /* 2552 * family, model, and step 2553 */ 2554 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2555 "family", CPI_FAMILY(cpi)); 2556 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2557 "cpu-model", CPI_MODEL(cpi)); 2558 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2559 "stepping-id", CPI_STEP(cpi)); 2560 2561 /* type */ 2562 2563 switch (cpi->cpi_vendor) { 2564 case X86_VENDOR_Intel: 2565 create = 1; 2566 break; 2567 default: 2568 create = 0; 2569 break; 2570 } 2571 if (create) 2572 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2573 "type", CPI_TYPE(cpi)); 2574 2575 /* ext-family */ 2576 2577 switch (cpi->cpi_vendor) { 2578 case X86_VENDOR_Intel: 2579 case X86_VENDOR_AMD: 2580 create = cpi->cpi_family >= 0xf; 2581 break; 2582 default: 2583 create = 0; 2584 break; 2585 } 2586 if (create) 2587 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2588 "ext-family", CPI_FAMILY_XTD(cpi)); 2589 2590 /* ext-model */ 2591 2592 switch (cpi->cpi_vendor) { 2593 case X86_VENDOR_Intel: 2594 case X86_VENDOR_AMD: 2595 create = CPI_FAMILY(cpi) == 0xf; 2596 break; 2597 default: 2598 create = 0; 2599 break; 2600 } 2601 if (create) 2602 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2603 "ext-model", CPI_MODEL_XTD(cpi)); 2604 2605 /* generation */ 2606 2607 switch (cpi->cpi_vendor) { 2608 case X86_VENDOR_AMD: 2609 /* 2610 * AMD K5 model 1 was the first part to support this 2611 */ 2612 create = cpi->cpi_xmaxeax >= 0x80000001; 2613 break; 2614 default: 2615 create = 0; 2616 break; 2617 } 2618 if (create) 2619 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2620 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 2621 2622 /* brand-id */ 2623 2624 switch (cpi->cpi_vendor) { 2625 case X86_VENDOR_Intel: 2626 /* 2627 * brand id first appeared on Pentium III Xeon model 8, 2628 * and Celeron model 8 processors and Opteron 2629 */ 2630 create = cpi->cpi_family > 6 || 2631 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 2632 break; 2633 case X86_VENDOR_AMD: 2634 create = cpi->cpi_family >= 0xf; 2635 break; 2636 default: 2637 create = 0; 2638 break; 2639 } 2640 if (create && cpi->cpi_brandid != 0) { 2641 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2642 "brand-id", cpi->cpi_brandid); 2643 } 2644 2645 /* chunks, and apic-id */ 2646 2647 switch (cpi->cpi_vendor) { 2648 /* 2649 * first available on Pentium IV and Opteron (K8) 2650 */ 2651 case X86_VENDOR_Intel: 2652 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 2653 break; 2654 case X86_VENDOR_AMD: 2655 create = cpi->cpi_family >= 0xf; 2656 break; 2657 default: 2658 create = 0; 2659 break; 2660 } 2661 if (create) { 2662 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2663 "chunks", CPI_CHUNKS(cpi)); 2664 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2665 "apic-id", CPI_APIC_ID(cpi)); 2666 if (cpi->cpi_chipid >= 0) { 2667 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2668 "chip#", cpi->cpi_chipid); 2669 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2670 "clog#", cpi->cpi_clogid); 2671 } 2672 } 2673 2674 /* cpuid-features */ 2675 2676 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2677 "cpuid-features", CPI_FEATURES_EDX(cpi)); 2678 2679 2680 /* cpuid-features-ecx */ 2681 2682 switch (cpi->cpi_vendor) { 2683 case X86_VENDOR_Intel: 2684 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 2685 break; 2686 default: 2687 create = 0; 2688 break; 2689 } 2690 if (create) 2691 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2692 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 2693 2694 /* ext-cpuid-features */ 2695 2696 switch (cpi->cpi_vendor) { 2697 case X86_VENDOR_Intel: 2698 case X86_VENDOR_AMD: 2699 case X86_VENDOR_Cyrix: 2700 case X86_VENDOR_TM: 2701 case X86_VENDOR_Centaur: 2702 create = cpi->cpi_xmaxeax >= 0x80000001; 2703 break; 2704 default: 2705 create = 0; 2706 break; 2707 } 2708 if (create) { 2709 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2710 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 2711 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2712 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 2713 } 2714 2715 /* 2716 * Brand String first appeared in Intel Pentium IV, AMD K5 2717 * model 1, and Cyrix GXm. On earlier models we try and 2718 * simulate something similar .. so this string should always 2719 * same -something- about the processor, however lame. 2720 */ 2721 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2722 "brand-string", cpi->cpi_brandstr); 2723 2724 /* 2725 * Finally, cache and tlb information 2726 */ 2727 switch (x86_which_cacheinfo(cpi)) { 2728 case X86_VENDOR_Intel: 2729 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 2730 break; 2731 case X86_VENDOR_Cyrix: 2732 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 2733 break; 2734 case X86_VENDOR_AMD: 2735 amd_cache_info(cpi, cpu_devi); 2736 break; 2737 default: 2738 break; 2739 } 2740 2741 mutex_exit(&cpu_node_lock); 2742 } 2743 2744 struct l2info { 2745 int *l2i_csz; 2746 int *l2i_lsz; 2747 int *l2i_assoc; 2748 int l2i_ret; 2749 }; 2750 2751 /* 2752 * A cacheinfo walker that fetches the size, line-size and associativity 2753 * of the L2 cache 2754 */ 2755 static int 2756 intel_l2cinfo(void *arg, const struct cachetab *ct) 2757 { 2758 struct l2info *l2i = arg; 2759 int *ip; 2760 2761 if (ct->ct_label != l2_cache_str && 2762 ct->ct_label != sl2_cache_str) 2763 return (0); /* not an L2 -- keep walking */ 2764 2765 if ((ip = l2i->l2i_csz) != NULL) 2766 *ip = ct->ct_size; 2767 if ((ip = l2i->l2i_lsz) != NULL) 2768 *ip = ct->ct_line_size; 2769 if ((ip = l2i->l2i_assoc) != NULL) 2770 *ip = ct->ct_assoc; 2771 l2i->l2i_ret = ct->ct_size; 2772 return (1); /* was an L2 -- terminate walk */ 2773 } 2774 2775 static void 2776 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 2777 { 2778 struct cpuid_regs *cp; 2779 uint_t size, assoc; 2780 int *ip; 2781 2782 if (cpi->cpi_xmaxeax < 0x80000006) 2783 return; 2784 cp = &cpi->cpi_extd[6]; 2785 2786 if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && 2787 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 2788 uint_t cachesz = size * 1024; 2789 2790 2791 if ((ip = l2i->l2i_csz) != NULL) 2792 *ip = cachesz; 2793 if ((ip = l2i->l2i_lsz) != NULL) 2794 *ip = BITX(cp->cp_ecx, 7, 0); 2795 if ((ip = l2i->l2i_assoc) != NULL) 2796 *ip = assoc; 2797 l2i->l2i_ret = cachesz; 2798 } 2799 } 2800 2801 int 2802 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 2803 { 2804 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2805 struct l2info __l2info, *l2i = &__l2info; 2806 2807 l2i->l2i_csz = csz; 2808 l2i->l2i_lsz = lsz; 2809 l2i->l2i_assoc = assoc; 2810 l2i->l2i_ret = -1; 2811 2812 switch (x86_which_cacheinfo(cpi)) { 2813 case X86_VENDOR_Intel: 2814 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 2815 break; 2816 case X86_VENDOR_Cyrix: 2817 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 2818 break; 2819 case X86_VENDOR_AMD: 2820 amd_l2cacheinfo(cpi, l2i); 2821 break; 2822 default: 2823 break; 2824 } 2825 return (l2i->l2i_ret); 2826 } 2827