xref: /titanic_51/usr/src/uts/i86pc/os/cpuid.c (revision 15d9d0b528387242011cdcc6190c9e598cfe3a07)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  * Various routines to handle identification
30  * and classification of x86 processors.
31  */
32 
33 #include <sys/types.h>
34 #include <sys/archsystm.h>
35 #include <sys/x86_archext.h>
36 #include <sys/kmem.h>
37 #include <sys/systm.h>
38 #include <sys/cmn_err.h>
39 #include <sys/sunddi.h>
40 #include <sys/sunndi.h>
41 #include <sys/cpuvar.h>
42 #include <sys/processor.h>
43 #include <sys/sysmacros.h>
44 #include <sys/pg.h>
45 #include <sys/fp.h>
46 #include <sys/controlregs.h>
47 #include <sys/auxv_386.h>
48 #include <sys/bitmap.h>
49 #include <sys/memnode.h>
50 
51 /*
52  * Pass 0 of cpuid feature analysis happens in locore. It contains special code
53  * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
54  * them accordingly. For most modern processors, feature detection occurs here
55  * in pass 1.
56  *
57  * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
58  * for the boot CPU and does the basic analysis that the early kernel needs.
59  * x86_feature is set based on the return value of cpuid_pass1() of the boot
60  * CPU.
61  *
62  * Pass 1 includes:
63  *
64  *	o Determining vendor/model/family/stepping and setting x86_type and
65  *	  x86_vendor accordingly.
66  *	o Processing the feature flags returned by the cpuid instruction while
67  *	  applying any workarounds or tricks for the specific processor.
68  *	o Mapping the feature flags into Solaris feature bits (X86_*).
69  *	o Processing extended feature flags if supported by the processor,
70  *	  again while applying specific processor knowledge.
71  *	o Determining the CMT characteristics of the system.
72  *
73  * Pass 1 is done on non-boot CPUs during their initialization and the results
74  * are used only as a meager attempt at ensuring that all processors within the
75  * system support the same features.
76  *
77  * Pass 2 of cpuid feature analysis happens just at the beginning
78  * of startup().  It just copies in and corrects the remainder
79  * of the cpuid data we depend on: standard cpuid functions that we didn't
80  * need for pass1 feature analysis, and extended cpuid functions beyond the
81  * simple feature processing done in pass1.
82  *
83  * Pass 3 of cpuid analysis is invoked after basic kernel services; in
84  * particular kernel memory allocation has been made available. It creates a
85  * readable brand string based on the data collected in the first two passes.
86  *
87  * Pass 4 of cpuid analysis is invoked after post_startup() when all
88  * the support infrastructure for various hardware features has been
89  * initialized. It determines which processor features will be reported
90  * to userland via the aux vector.
91  *
92  * All passes are executed on all CPUs, but only the boot CPU determines what
93  * features the kernel will use.
94  *
95  * Much of the worst junk in this file is for the support of processors
96  * that didn't really implement the cpuid instruction properly.
97  *
98  * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
99  * the pass numbers.  Accordingly, changes to the pass code may require changes
100  * to the accessor code.
101  */
102 
103 uint_t x86_feature = 0;
104 uint_t x86_vendor = X86_VENDOR_IntelClone;
105 uint_t x86_type = X86_TYPE_OTHER;
106 
107 uint_t pentiumpro_bug4046376;
108 uint_t pentiumpro_bug4064495;
109 
110 uint_t enable486;
111 
112 /*
113  * This set of strings are for processors rumored to support the cpuid
114  * instruction, and is used by locore.s to figure out how to set x86_vendor
115  */
116 const char CyrixInstead[] = "CyrixInstead";
117 
118 /*
119  * monitor/mwait info.
120  *
121  * size_actual and buf_actual are the real address and size allocated to get
122  * proper mwait_buf alignement.  buf_actual and size_actual should be passed
123  * to kmem_free().  Currently kmem_alloc() and mwait happen to both use
124  * processor cache-line alignment, but this is not guarantied in the furture.
125  */
126 struct mwait_info {
127 	size_t		mon_min;	/* min size to avoid missed wakeups */
128 	size_t		mon_max;	/* size to avoid false wakeups */
129 	size_t		size_actual;	/* size actually allocated */
130 	void		*buf_actual;	/* memory actually allocated */
131 	uint32_t	support;	/* processor support of monitor/mwait */
132 };
133 
134 /*
135  * These constants determine how many of the elements of the
136  * cpuid we cache in the cpuid_info data structure; the
137  * remaining elements are accessible via the cpuid instruction.
138  */
139 
140 #define	NMAX_CPI_STD	6		/* eax = 0 .. 5 */
141 #define	NMAX_CPI_EXTD	9		/* eax = 0x80000000 .. 0x80000008 */
142 
143 struct cpuid_info {
144 	uint_t cpi_pass;		/* last pass completed */
145 	/*
146 	 * standard function information
147 	 */
148 	uint_t cpi_maxeax;		/* fn 0: %eax */
149 	char cpi_vendorstr[13];		/* fn 0: %ebx:%ecx:%edx */
150 	uint_t cpi_vendor;		/* enum of cpi_vendorstr */
151 
152 	uint_t cpi_family;		/* fn 1: extended family */
153 	uint_t cpi_model;		/* fn 1: extended model */
154 	uint_t cpi_step;		/* fn 1: stepping */
155 	chipid_t cpi_chipid;		/* fn 1: %ebx: chip # on ht cpus */
156 	uint_t cpi_brandid;		/* fn 1: %ebx: brand ID */
157 	int cpi_clogid;			/* fn 1: %ebx: thread # */
158 	uint_t cpi_ncpu_per_chip;	/* fn 1: %ebx: logical cpu count */
159 	uint8_t cpi_cacheinfo[16];	/* fn 2: intel-style cache desc */
160 	uint_t cpi_ncache;		/* fn 2: number of elements */
161 	uint_t cpi_ncpu_shr_last_cache;	/* fn 4: %eax: ncpus sharing cache */
162 	id_t cpi_last_lvl_cacheid;	/* fn 4: %eax: derived cache id */
163 	uint_t cpi_std_4_size;		/* fn 4: number of fn 4 elements */
164 	struct cpuid_regs **cpi_std_4;	/* fn 4: %ecx == 0 .. fn4_size */
165 	struct cpuid_regs cpi_std[NMAX_CPI_STD];	/* 0 .. 5 */
166 	/*
167 	 * extended function information
168 	 */
169 	uint_t cpi_xmaxeax;		/* fn 0x80000000: %eax */
170 	char cpi_brandstr[49];		/* fn 0x8000000[234] */
171 	uint8_t cpi_pabits;		/* fn 0x80000006: %eax */
172 	uint8_t cpi_vabits;		/* fn 0x80000006: %eax */
173 	struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */
174 	id_t cpi_coreid;		/* same coreid => strands share core */
175 	int cpi_pkgcoreid;		/* core number within single package */
176 	uint_t cpi_ncore_per_chip;	/* AMD: fn 0x80000008: %ecx[7-0] */
177 					/* Intel: fn 4: %eax[31-26] */
178 	/*
179 	 * supported feature information
180 	 */
181 	uint32_t cpi_support[5];
182 #define	STD_EDX_FEATURES	0
183 #define	AMD_EDX_FEATURES	1
184 #define	TM_EDX_FEATURES		2
185 #define	STD_ECX_FEATURES	3
186 #define	AMD_ECX_FEATURES	4
187 	/*
188 	 * Synthesized information, where known.
189 	 */
190 	uint32_t cpi_chiprev;		/* See X86_CHIPREV_* in x86_archext.h */
191 	const char *cpi_chiprevstr;	/* May be NULL if chiprev unknown */
192 	uint32_t cpi_socket;		/* Chip package/socket type */
193 
194 	struct mwait_info cpi_mwait;	/* fn 5: monitor/mwait info */
195 };
196 
197 
198 static struct cpuid_info cpuid_info0;
199 
200 /*
201  * These bit fields are defined by the Intel Application Note AP-485
202  * "Intel Processor Identification and the CPUID Instruction"
203  */
204 #define	CPI_FAMILY_XTD(cpi)	BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
205 #define	CPI_MODEL_XTD(cpi)	BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
206 #define	CPI_TYPE(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
207 #define	CPI_FAMILY(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
208 #define	CPI_STEP(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
209 #define	CPI_MODEL(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
210 
211 #define	CPI_FEATURES_EDX(cpi)		((cpi)->cpi_std[1].cp_edx)
212 #define	CPI_FEATURES_ECX(cpi)		((cpi)->cpi_std[1].cp_ecx)
213 #define	CPI_FEATURES_XTD_EDX(cpi)	((cpi)->cpi_extd[1].cp_edx)
214 #define	CPI_FEATURES_XTD_ECX(cpi)	((cpi)->cpi_extd[1].cp_ecx)
215 
216 #define	CPI_BRANDID(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
217 #define	CPI_CHUNKS(cpi)		BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
218 #define	CPI_CPU_COUNT(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
219 #define	CPI_APIC_ID(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
220 
221 #define	CPI_MAXEAX_MAX		0x100		/* sanity control */
222 #define	CPI_XMAXEAX_MAX		0x80000100
223 #define	CPI_FN4_ECX_MAX		0x20		/* sanity: max fn 4 levels */
224 
225 /*
226  * Function 4 (Deterministic Cache Parameters) macros
227  * Defined by Intel Application Note AP-485
228  */
229 #define	CPI_NUM_CORES(regs)		BITX((regs)->cp_eax, 31, 26)
230 #define	CPI_NTHR_SHR_CACHE(regs)	BITX((regs)->cp_eax, 25, 14)
231 #define	CPI_FULL_ASSOC_CACHE(regs)	BITX((regs)->cp_eax, 9, 9)
232 #define	CPI_SELF_INIT_CACHE(regs)	BITX((regs)->cp_eax, 8, 8)
233 #define	CPI_CACHE_LVL(regs)		BITX((regs)->cp_eax, 7, 5)
234 #define	CPI_CACHE_TYPE(regs)		BITX((regs)->cp_eax, 4, 0)
235 
236 #define	CPI_CACHE_WAYS(regs)		BITX((regs)->cp_ebx, 31, 22)
237 #define	CPI_CACHE_PARTS(regs)		BITX((regs)->cp_ebx, 21, 12)
238 #define	CPI_CACHE_COH_LN_SZ(regs)	BITX((regs)->cp_ebx, 11, 0)
239 
240 #define	CPI_CACHE_SETS(regs)		BITX((regs)->cp_ecx, 31, 0)
241 
242 #define	CPI_PREFCH_STRIDE(regs)		BITX((regs)->cp_edx, 9, 0)
243 
244 
245 /*
246  * A couple of shorthand macros to identify "later" P6-family chips
247  * like the Pentium M and Core.  First, the "older" P6-based stuff
248  * (loosely defined as "pre-Pentium-4"):
249  * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
250  */
251 
252 #define	IS_LEGACY_P6(cpi) (			\
253 	cpi->cpi_family == 6 && 		\
254 		(cpi->cpi_model == 1 ||		\
255 		cpi->cpi_model == 3 ||		\
256 		cpi->cpi_model == 5 ||		\
257 		cpi->cpi_model == 6 ||		\
258 		cpi->cpi_model == 7 ||		\
259 		cpi->cpi_model == 8 ||		\
260 		cpi->cpi_model == 0xA ||	\
261 		cpi->cpi_model == 0xB)		\
262 )
263 
264 /* A "new F6" is everything with family 6 that's not the above */
265 #define	IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
266 
267 /* Extended family/model support */
268 #define	IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \
269 	cpi->cpi_family >= 0xf)
270 
271 /*
272  * AMD family 0xf and family 0x10 socket types.
273  * First index :
274  *		0 for family 0xf, revs B thru E
275  *		1 for family 0xf, revs F and G
276  *		2 for family 0x10, rev B
277  * Second index by (model & 0x3)
278  */
279 static uint32_t amd_skts[3][4] = {
280 	/*
281 	 * Family 0xf revisions B through E
282 	 */
283 #define	A_SKTS_0			0
284 	{
285 		X86_SOCKET_754,		/* 0b00 */
286 		X86_SOCKET_940,		/* 0b01 */
287 		X86_SOCKET_754,		/* 0b10 */
288 		X86_SOCKET_939		/* 0b11 */
289 	},
290 	/*
291 	 * Family 0xf revisions F and G
292 	 */
293 #define	A_SKTS_1			1
294 	{
295 		X86_SOCKET_S1g1,	/* 0b00 */
296 		X86_SOCKET_F1207,	/* 0b01 */
297 		X86_SOCKET_UNKNOWN,	/* 0b10 */
298 		X86_SOCKET_AM2		/* 0b11 */
299 	},
300 	/*
301 	 * Family 0x10 revisions A and B
302 	 * It is not clear whether, as new sockets release, that
303 	 * model & 0x3 will id socket for this family
304 	 */
305 #define	A_SKTS_2			2
306 	{
307 		X86_SOCKET_F1207,	/* 0b00 */
308 		X86_SOCKET_F1207,	/* 0b01 */
309 		X86_SOCKET_F1207,	/* 0b10 */
310 		X86_SOCKET_F1207,	/* 0b11 */
311 	}
312 };
313 
314 /*
315  * Table for mapping AMD Family 0xf and AMD Family 0x10 model/stepping
316  * combination to chip "revision" and socket type.
317  *
318  * The first member of this array that matches a given family, extended model
319  * plus model range, and stepping range will be considered a match.
320  */
321 static const struct amd_rev_mapent {
322 	uint_t rm_family;
323 	uint_t rm_modello;
324 	uint_t rm_modelhi;
325 	uint_t rm_steplo;
326 	uint_t rm_stephi;
327 	uint32_t rm_chiprev;
328 	const char *rm_chiprevstr;
329 	int rm_sktidx;
330 } amd_revmap[] = {
331 	/*
332 	 * =============== AuthenticAMD Family 0xf ===============
333 	 */
334 
335 	/*
336 	 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1.
337 	 */
338 	{ 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 },
339 	{ 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 },
340 	/*
341 	 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8
342 	 */
343 	{ 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", A_SKTS_0 },
344 	/*
345 	 * Rev CG is the rest of extended model 0x0 - i.e., everything
346 	 * but the rev B and C0 combinations covered above.
347 	 */
348 	{ 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", A_SKTS_0 },
349 	/*
350 	 * Rev D has extended model 0x1.
351 	 */
352 	{ 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", A_SKTS_0 },
353 	/*
354 	 * Rev E has extended model 0x2.
355 	 * Extended model 0x3 is unused but available to grow into.
356 	 */
357 	{ 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", A_SKTS_0 },
358 	/*
359 	 * Rev F has extended models 0x4 and 0x5.
360 	 */
361 	{ 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", A_SKTS_1 },
362 	/*
363 	 * Rev G has extended model 0x6.
364 	 */
365 	{ 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", A_SKTS_1 },
366 
367 	/*
368 	 * =============== AuthenticAMD Family 0x10 ===============
369 	 */
370 
371 	/*
372 	 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}.
373 	 * Give all of model 0 stepping range to rev A.
374 	 */
375 	{ 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_A, "A", A_SKTS_2 },
376 
377 	/*
378 	 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}.
379 	 * Give all of model 2 stepping range to rev B.
380 	 */
381 	{ 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_B, "B", A_SKTS_2 },
382 };
383 
384 /*
385  * Info for monitor/mwait idle loop.
386  *
387  * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
388  * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
389  * 2006.
390  * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
391  * Documentation Updates" #33633, Rev 2.05, December 2006.
392  */
393 #define	MWAIT_SUPPORT		(0x00000001)	/* mwait supported */
394 #define	MWAIT_EXTENSIONS	(0x00000002)	/* extenstion supported */
395 #define	MWAIT_ECX_INT_ENABLE	(0x00000004)	/* ecx 1 extension supported */
396 #define	MWAIT_SUPPORTED(cpi)	((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
397 #define	MWAIT_INT_ENABLE(cpi)	((cpi)->cpi_std[5].cp_ecx & 0x2)
398 #define	MWAIT_EXTENSION(cpi)	((cpi)->cpi_std[5].cp_ecx & 0x1)
399 #define	MWAIT_SIZE_MIN(cpi)	BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
400 #define	MWAIT_SIZE_MAX(cpi)	BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
401 /*
402  * Number of sub-cstates for a given c-state.
403  */
404 #define	MWAIT_NUM_SUBC_STATES(cpi, c_state)			\
405 	BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
406 
407 static void
408 synth_amd_info(struct cpuid_info *cpi)
409 {
410 	const struct amd_rev_mapent *rmp;
411 	uint_t family, model, step;
412 	int i;
413 
414 	/*
415 	 * Currently only AMD family 0xf and family 0x10 use these fields.
416 	 */
417 	if (cpi->cpi_family != 0xf && cpi->cpi_family != 0x10)
418 		return;
419 
420 	family = cpi->cpi_family;
421 	model = cpi->cpi_model;
422 	step = cpi->cpi_step;
423 
424 	for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp);
425 	    i++, rmp++) {
426 		if (family == rmp->rm_family &&
427 		    model >= rmp->rm_modello && model <= rmp->rm_modelhi &&
428 		    step >= rmp->rm_steplo && step <= rmp->rm_stephi) {
429 			cpi->cpi_chiprev = rmp->rm_chiprev;
430 			cpi->cpi_chiprevstr = rmp->rm_chiprevstr;
431 			cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3];
432 			return;
433 		}
434 	}
435 }
436 
437 static void
438 synth_info(struct cpuid_info *cpi)
439 {
440 	cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN;
441 	cpi->cpi_chiprevstr = "Unknown";
442 	cpi->cpi_socket = X86_SOCKET_UNKNOWN;
443 
444 	switch (cpi->cpi_vendor) {
445 	case X86_VENDOR_AMD:
446 		synth_amd_info(cpi);
447 		break;
448 
449 	default:
450 		break;
451 
452 	}
453 }
454 
455 /*
456  * Apply up various platform-dependent restrictions where the
457  * underlying platform restrictions mean the CPU can be marked
458  * as less capable than its cpuid instruction would imply.
459  */
460 #if defined(__xpv)
461 static void
462 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
463 {
464 	switch (eax) {
465 	case 1:
466 		cp->cp_edx &=
467 		    ~(CPUID_INTC_EDX_PSE |
468 		    CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
469 		    CPUID_INTC_EDX_MCA |	/* XXPV true on dom0? */
470 		    CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR |
471 		    CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT |
472 		    CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
473 		    CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT);
474 		break;
475 
476 	case 0x80000001:
477 		cp->cp_edx &=
478 		    ~(CPUID_AMD_EDX_PSE |
479 		    CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
480 		    CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE |
481 		    CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 |
482 		    CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
483 		    CPUID_AMD_EDX_TSCP);
484 		cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
485 		break;
486 	default:
487 		break;
488 	}
489 
490 	switch (vendor) {
491 	case X86_VENDOR_Intel:
492 		switch (eax) {
493 		case 4:
494 			/*
495 			 * Zero out the (ncores-per-chip - 1) field
496 			 */
497 			cp->cp_eax &= 0x03fffffff;
498 			break;
499 		default:
500 			break;
501 		}
502 		break;
503 	case X86_VENDOR_AMD:
504 		switch (eax) {
505 		case 0x80000008:
506 			/*
507 			 * Zero out the (ncores-per-chip - 1) field
508 			 */
509 			cp->cp_ecx &= 0xffffff00;
510 			break;
511 		default:
512 			break;
513 		}
514 		break;
515 	default:
516 		break;
517 	}
518 }
519 #else
520 #define	platform_cpuid_mangle(vendor, eax, cp)	/* nothing */
521 #endif
522 
523 /*
524  *  Some undocumented ways of patching the results of the cpuid
525  *  instruction to permit running Solaris 10 on future cpus that
526  *  we don't currently support.  Could be set to non-zero values
527  *  via settings in eeprom.
528  */
529 
530 uint32_t cpuid_feature_ecx_include;
531 uint32_t cpuid_feature_ecx_exclude;
532 uint32_t cpuid_feature_edx_include;
533 uint32_t cpuid_feature_edx_exclude;
534 
535 void
536 cpuid_alloc_space(cpu_t *cpu)
537 {
538 	/*
539 	 * By convention, cpu0 is the boot cpu, which is set up
540 	 * before memory allocation is available.  All other cpus get
541 	 * their cpuid_info struct allocated here.
542 	 */
543 	ASSERT(cpu->cpu_id != 0);
544 	cpu->cpu_m.mcpu_cpi =
545 	    kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
546 }
547 
548 void
549 cpuid_free_space(cpu_t *cpu)
550 {
551 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
552 	int i;
553 
554 	ASSERT(cpu->cpu_id != 0);
555 
556 	/*
557 	 * Free up any function 4 related dynamic storage
558 	 */
559 	for (i = 1; i < cpi->cpi_std_4_size; i++)
560 		kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
561 	if (cpi->cpi_std_4_size > 0)
562 		kmem_free(cpi->cpi_std_4,
563 		    cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
564 
565 	kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi));
566 }
567 
568 #if !defined(__xpv)
569 
570 static void
571 check_for_hvm()
572 {
573 	struct cpuid_regs cp;
574 	char *xen_str;
575 	uint32_t xen_signature[4];
576 	extern int xpv_is_hvm;
577 
578 	/*
579 	 * In a fully virtualized domain, Xen's pseudo-cpuid function
580 	 * 0x40000000 returns a string representing the Xen signature in
581 	 * %ebx, %ecx, and %edx.  %eax contains the maximum supported cpuid
582 	 * function.
583 	 */
584 	cp.cp_eax = 0x40000000;
585 	(void) __cpuid_insn(&cp);
586 	xen_signature[0] = cp.cp_ebx;
587 	xen_signature[1] = cp.cp_ecx;
588 	xen_signature[2] = cp.cp_edx;
589 	xen_signature[3] = 0;
590 	xen_str = (char *)xen_signature;
591 	if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002)
592 		xpv_is_hvm = 1;
593 }
594 #endif	/* __xpv */
595 
596 uint_t
597 cpuid_pass1(cpu_t *cpu)
598 {
599 	uint32_t mask_ecx, mask_edx;
600 	uint_t feature = X86_CPUID;
601 	struct cpuid_info *cpi;
602 	struct cpuid_regs *cp;
603 	int xcpuid;
604 #if !defined(__xpv)
605 	extern int idle_cpu_prefer_mwait;
606 #endif
607 
608 	/*
609 	 * Space statically allocated for cpu0, ensure pointer is set
610 	 */
611 	if (cpu->cpu_id == 0)
612 		cpu->cpu_m.mcpu_cpi = &cpuid_info0;
613 	cpi = cpu->cpu_m.mcpu_cpi;
614 	ASSERT(cpi != NULL);
615 	cp = &cpi->cpi_std[0];
616 	cp->cp_eax = 0;
617 	cpi->cpi_maxeax = __cpuid_insn(cp);
618 	{
619 		uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;
620 		*iptr++ = cp->cp_ebx;
621 		*iptr++ = cp->cp_edx;
622 		*iptr++ = cp->cp_ecx;
623 		*(char *)&cpi->cpi_vendorstr[12] = '\0';
624 	}
625 
626 	/*
627 	 * Map the vendor string to a type code
628 	 */
629 	if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0)
630 		cpi->cpi_vendor = X86_VENDOR_Intel;
631 	else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0)
632 		cpi->cpi_vendor = X86_VENDOR_AMD;
633 	else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0)
634 		cpi->cpi_vendor = X86_VENDOR_TM;
635 	else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0)
636 		/*
637 		 * CyrixInstead is a variable used by the Cyrix detection code
638 		 * in locore.
639 		 */
640 		cpi->cpi_vendor = X86_VENDOR_Cyrix;
641 	else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0)
642 		cpi->cpi_vendor = X86_VENDOR_UMC;
643 	else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0)
644 		cpi->cpi_vendor = X86_VENDOR_NexGen;
645 	else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0)
646 		cpi->cpi_vendor = X86_VENDOR_Centaur;
647 	else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0)
648 		cpi->cpi_vendor = X86_VENDOR_Rise;
649 	else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0)
650 		cpi->cpi_vendor = X86_VENDOR_SiS;
651 	else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0)
652 		cpi->cpi_vendor = X86_VENDOR_NSC;
653 	else
654 		cpi->cpi_vendor = X86_VENDOR_IntelClone;
655 
656 	x86_vendor = cpi->cpi_vendor; /* for compatibility */
657 
658 	/*
659 	 * Limit the range in case of weird hardware
660 	 */
661 	if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
662 		cpi->cpi_maxeax = CPI_MAXEAX_MAX;
663 	if (cpi->cpi_maxeax < 1)
664 		goto pass1_done;
665 
666 	cp = &cpi->cpi_std[1];
667 	cp->cp_eax = 1;
668 	(void) __cpuid_insn(cp);
669 
670 	/*
671 	 * Extract identifying constants for easy access.
672 	 */
673 	cpi->cpi_model = CPI_MODEL(cpi);
674 	cpi->cpi_family = CPI_FAMILY(cpi);
675 
676 	if (cpi->cpi_family == 0xf)
677 		cpi->cpi_family += CPI_FAMILY_XTD(cpi);
678 
679 	/*
680 	 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf.
681 	 * Intel, and presumably everyone else, uses model == 0xf, as
682 	 * one would expect (max value means possible overflow).  Sigh.
683 	 */
684 
685 	switch (cpi->cpi_vendor) {
686 	case X86_VENDOR_Intel:
687 		if (IS_EXTENDED_MODEL_INTEL(cpi))
688 			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
689 		break;
690 	case X86_VENDOR_AMD:
691 		if (CPI_FAMILY(cpi) == 0xf)
692 			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
693 		break;
694 	default:
695 		if (cpi->cpi_model == 0xf)
696 			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
697 		break;
698 	}
699 
700 	cpi->cpi_step = CPI_STEP(cpi);
701 	cpi->cpi_brandid = CPI_BRANDID(cpi);
702 
703 	/*
704 	 * *default* assumptions:
705 	 * - believe %edx feature word
706 	 * - ignore %ecx feature word
707 	 * - 32-bit virtual and physical addressing
708 	 */
709 	mask_edx = 0xffffffff;
710 	mask_ecx = 0;
711 
712 	cpi->cpi_pabits = cpi->cpi_vabits = 32;
713 
714 	switch (cpi->cpi_vendor) {
715 	case X86_VENDOR_Intel:
716 		if (cpi->cpi_family == 5)
717 			x86_type = X86_TYPE_P5;
718 		else if (IS_LEGACY_P6(cpi)) {
719 			x86_type = X86_TYPE_P6;
720 			pentiumpro_bug4046376 = 1;
721 			pentiumpro_bug4064495 = 1;
722 			/*
723 			 * Clear the SEP bit when it was set erroneously
724 			 */
725 			if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
726 				cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
727 		} else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) {
728 			x86_type = X86_TYPE_P4;
729 			/*
730 			 * We don't currently depend on any of the %ecx
731 			 * features until Prescott, so we'll only check
732 			 * this from P4 onwards.  We might want to revisit
733 			 * that idea later.
734 			 */
735 			mask_ecx = 0xffffffff;
736 		} else if (cpi->cpi_family > 0xf)
737 			mask_ecx = 0xffffffff;
738 		/*
739 		 * We don't support MONITOR/MWAIT if leaf 5 is not available
740 		 * to obtain the monitor linesize.
741 		 */
742 		if (cpi->cpi_maxeax < 5)
743 			mask_ecx &= ~CPUID_INTC_ECX_MON;
744 		break;
745 	case X86_VENDOR_IntelClone:
746 	default:
747 		break;
748 	case X86_VENDOR_AMD:
749 #if defined(OPTERON_ERRATUM_108)
750 		if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
751 			cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0;
752 			cpi->cpi_model = 0xc;
753 		} else
754 #endif
755 		if (cpi->cpi_family == 5) {
756 			/*
757 			 * AMD K5 and K6
758 			 *
759 			 * These CPUs have an incomplete implementation
760 			 * of MCA/MCE which we mask away.
761 			 */
762 			mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA);
763 
764 			/*
765 			 * Model 0 uses the wrong (APIC) bit
766 			 * to indicate PGE.  Fix it here.
767 			 */
768 			if (cpi->cpi_model == 0) {
769 				if (cp->cp_edx & 0x200) {
770 					cp->cp_edx &= ~0x200;
771 					cp->cp_edx |= CPUID_INTC_EDX_PGE;
772 				}
773 			}
774 
775 			/*
776 			 * Early models had problems w/ MMX; disable.
777 			 */
778 			if (cpi->cpi_model < 6)
779 				mask_edx &= ~CPUID_INTC_EDX_MMX;
780 		}
781 
782 		/*
783 		 * For newer families, SSE3 and CX16, at least, are valid;
784 		 * enable all
785 		 */
786 		if (cpi->cpi_family >= 0xf)
787 			mask_ecx = 0xffffffff;
788 		/*
789 		 * We don't support MONITOR/MWAIT if leaf 5 is not available
790 		 * to obtain the monitor linesize.
791 		 */
792 		if (cpi->cpi_maxeax < 5)
793 			mask_ecx &= ~CPUID_INTC_ECX_MON;
794 
795 #if !defined(__xpv)
796 		/*
797 		 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
798 		 * processors.  AMD does not intend MWAIT to be used in the cpu
799 		 * idle loop on current and future processors.  10h and future
800 		 * AMD processors use more power in MWAIT than HLT.
801 		 * Pre-family-10h Opterons do not have the MWAIT instruction.
802 		 */
803 		idle_cpu_prefer_mwait = 0;
804 #endif
805 
806 		break;
807 	case X86_VENDOR_TM:
808 		/*
809 		 * workaround the NT workaround in CMS 4.1
810 		 */
811 		if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
812 		    (cpi->cpi_step == 2 || cpi->cpi_step == 3))
813 			cp->cp_edx |= CPUID_INTC_EDX_CX8;
814 		break;
815 	case X86_VENDOR_Centaur:
816 		/*
817 		 * workaround the NT workarounds again
818 		 */
819 		if (cpi->cpi_family == 6)
820 			cp->cp_edx |= CPUID_INTC_EDX_CX8;
821 		break;
822 	case X86_VENDOR_Cyrix:
823 		/*
824 		 * We rely heavily on the probing in locore
825 		 * to actually figure out what parts, if any,
826 		 * of the Cyrix cpuid instruction to believe.
827 		 */
828 		switch (x86_type) {
829 		case X86_TYPE_CYRIX_486:
830 			mask_edx = 0;
831 			break;
832 		case X86_TYPE_CYRIX_6x86:
833 			mask_edx = 0;
834 			break;
835 		case X86_TYPE_CYRIX_6x86L:
836 			mask_edx =
837 			    CPUID_INTC_EDX_DE |
838 			    CPUID_INTC_EDX_CX8;
839 			break;
840 		case X86_TYPE_CYRIX_6x86MX:
841 			mask_edx =
842 			    CPUID_INTC_EDX_DE |
843 			    CPUID_INTC_EDX_MSR |
844 			    CPUID_INTC_EDX_CX8 |
845 			    CPUID_INTC_EDX_PGE |
846 			    CPUID_INTC_EDX_CMOV |
847 			    CPUID_INTC_EDX_MMX;
848 			break;
849 		case X86_TYPE_CYRIX_GXm:
850 			mask_edx =
851 			    CPUID_INTC_EDX_MSR |
852 			    CPUID_INTC_EDX_CX8 |
853 			    CPUID_INTC_EDX_CMOV |
854 			    CPUID_INTC_EDX_MMX;
855 			break;
856 		case X86_TYPE_CYRIX_MediaGX:
857 			break;
858 		case X86_TYPE_CYRIX_MII:
859 		case X86_TYPE_VIA_CYRIX_III:
860 			mask_edx =
861 			    CPUID_INTC_EDX_DE |
862 			    CPUID_INTC_EDX_TSC |
863 			    CPUID_INTC_EDX_MSR |
864 			    CPUID_INTC_EDX_CX8 |
865 			    CPUID_INTC_EDX_PGE |
866 			    CPUID_INTC_EDX_CMOV |
867 			    CPUID_INTC_EDX_MMX;
868 			break;
869 		default:
870 			break;
871 		}
872 		break;
873 	}
874 
875 #if defined(__xpv)
876 	/*
877 	 * Do not support MONITOR/MWAIT under a hypervisor
878 	 */
879 	mask_ecx &= ~CPUID_INTC_ECX_MON;
880 #endif	/* __xpv */
881 
882 	/*
883 	 * Now we've figured out the masks that determine
884 	 * which bits we choose to believe, apply the masks
885 	 * to the feature words, then map the kernel's view
886 	 * of these feature words into its feature word.
887 	 */
888 	cp->cp_edx &= mask_edx;
889 	cp->cp_ecx &= mask_ecx;
890 
891 	/*
892 	 * apply any platform restrictions (we don't call this
893 	 * immediately after __cpuid_insn here, because we need the
894 	 * workarounds applied above first)
895 	 */
896 	platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
897 
898 	/*
899 	 * fold in overrides from the "eeprom" mechanism
900 	 */
901 	cp->cp_edx |= cpuid_feature_edx_include;
902 	cp->cp_edx &= ~cpuid_feature_edx_exclude;
903 
904 	cp->cp_ecx |= cpuid_feature_ecx_include;
905 	cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
906 
907 	if (cp->cp_edx & CPUID_INTC_EDX_PSE)
908 		feature |= X86_LARGEPAGE;
909 	if (cp->cp_edx & CPUID_INTC_EDX_TSC)
910 		feature |= X86_TSC;
911 	if (cp->cp_edx & CPUID_INTC_EDX_MSR)
912 		feature |= X86_MSR;
913 	if (cp->cp_edx & CPUID_INTC_EDX_MTRR)
914 		feature |= X86_MTRR;
915 	if (cp->cp_edx & CPUID_INTC_EDX_PGE)
916 		feature |= X86_PGE;
917 	if (cp->cp_edx & CPUID_INTC_EDX_CMOV)
918 		feature |= X86_CMOV;
919 	if (cp->cp_edx & CPUID_INTC_EDX_MMX)
920 		feature |= X86_MMX;
921 	if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
922 	    (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0)
923 		feature |= X86_MCA;
924 	if (cp->cp_edx & CPUID_INTC_EDX_PAE)
925 		feature |= X86_PAE;
926 	if (cp->cp_edx & CPUID_INTC_EDX_CX8)
927 		feature |= X86_CX8;
928 	if (cp->cp_ecx & CPUID_INTC_ECX_CX16)
929 		feature |= X86_CX16;
930 	if (cp->cp_edx & CPUID_INTC_EDX_PAT)
931 		feature |= X86_PAT;
932 	if (cp->cp_edx & CPUID_INTC_EDX_SEP)
933 		feature |= X86_SEP;
934 	if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
935 		/*
936 		 * In our implementation, fxsave/fxrstor
937 		 * are prerequisites before we'll even
938 		 * try and do SSE things.
939 		 */
940 		if (cp->cp_edx & CPUID_INTC_EDX_SSE)
941 			feature |= X86_SSE;
942 		if (cp->cp_edx & CPUID_INTC_EDX_SSE2)
943 			feature |= X86_SSE2;
944 		if (cp->cp_ecx & CPUID_INTC_ECX_SSE3)
945 			feature |= X86_SSE3;
946 		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
947 			if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3)
948 				feature |= X86_SSSE3;
949 			if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1)
950 				feature |= X86_SSE4_1;
951 			if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2)
952 				feature |= X86_SSE4_2;
953 		}
954 	}
955 	if (cp->cp_edx & CPUID_INTC_EDX_DE)
956 		feature |= X86_DE;
957 	if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
958 		cpi->cpi_mwait.support |= MWAIT_SUPPORT;
959 		feature |= X86_MWAIT;
960 	}
961 
962 	if (feature & X86_PAE)
963 		cpi->cpi_pabits = 36;
964 
965 	/*
966 	 * Hyperthreading configuration is slightly tricky on Intel
967 	 * and pure clones, and even trickier on AMD.
968 	 *
969 	 * (AMD chose to set the HTT bit on their CMP processors,
970 	 * even though they're not actually hyperthreaded.  Thus it
971 	 * takes a bit more work to figure out what's really going
972 	 * on ... see the handling of the CMP_LGCY bit below)
973 	 */
974 	if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
975 		cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
976 		if (cpi->cpi_ncpu_per_chip > 1)
977 			feature |= X86_HTT;
978 	} else {
979 		cpi->cpi_ncpu_per_chip = 1;
980 	}
981 
982 	/*
983 	 * Work on the "extended" feature information, doing
984 	 * some basic initialization for cpuid_pass2()
985 	 */
986 	xcpuid = 0;
987 	switch (cpi->cpi_vendor) {
988 	case X86_VENDOR_Intel:
989 		if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf)
990 			xcpuid++;
991 		break;
992 	case X86_VENDOR_AMD:
993 		if (cpi->cpi_family > 5 ||
994 		    (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
995 			xcpuid++;
996 		break;
997 	case X86_VENDOR_Cyrix:
998 		/*
999 		 * Only these Cyrix CPUs are -known- to support
1000 		 * extended cpuid operations.
1001 		 */
1002 		if (x86_type == X86_TYPE_VIA_CYRIX_III ||
1003 		    x86_type == X86_TYPE_CYRIX_GXm)
1004 			xcpuid++;
1005 		break;
1006 	case X86_VENDOR_Centaur:
1007 	case X86_VENDOR_TM:
1008 	default:
1009 		xcpuid++;
1010 		break;
1011 	}
1012 
1013 	if (xcpuid) {
1014 		cp = &cpi->cpi_extd[0];
1015 		cp->cp_eax = 0x80000000;
1016 		cpi->cpi_xmaxeax = __cpuid_insn(cp);
1017 	}
1018 
1019 	if (cpi->cpi_xmaxeax & 0x80000000) {
1020 
1021 		if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
1022 			cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
1023 
1024 		switch (cpi->cpi_vendor) {
1025 		case X86_VENDOR_Intel:
1026 		case X86_VENDOR_AMD:
1027 			if (cpi->cpi_xmaxeax < 0x80000001)
1028 				break;
1029 			cp = &cpi->cpi_extd[1];
1030 			cp->cp_eax = 0x80000001;
1031 			(void) __cpuid_insn(cp);
1032 
1033 			if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1034 			    cpi->cpi_family == 5 &&
1035 			    cpi->cpi_model == 6 &&
1036 			    cpi->cpi_step == 6) {
1037 				/*
1038 				 * K6 model 6 uses bit 10 to indicate SYSC
1039 				 * Later models use bit 11. Fix it here.
1040 				 */
1041 				if (cp->cp_edx & 0x400) {
1042 					cp->cp_edx &= ~0x400;
1043 					cp->cp_edx |= CPUID_AMD_EDX_SYSC;
1044 				}
1045 			}
1046 
1047 			platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
1048 
1049 			/*
1050 			 * Compute the additions to the kernel's feature word.
1051 			 */
1052 			if (cp->cp_edx & CPUID_AMD_EDX_NX)
1053 				feature |= X86_NX;
1054 
1055 #if defined(__amd64)
1056 			/* 1 GB large page - enable only for 64 bit kernel */
1057 			if (cp->cp_edx & CPUID_AMD_EDX_1GPG)
1058 				feature |= X86_1GPG;
1059 #endif
1060 
1061 			if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
1062 			    (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
1063 			    (cp->cp_ecx & CPUID_AMD_ECX_SSE4A))
1064 				feature |= X86_SSE4A;
1065 
1066 			/*
1067 			 * If both the HTT and CMP_LGCY bits are set,
1068 			 * then we're not actually HyperThreaded.  Read
1069 			 * "AMD CPUID Specification" for more details.
1070 			 */
1071 			if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1072 			    (feature & X86_HTT) &&
1073 			    (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
1074 				feature &= ~X86_HTT;
1075 				feature |= X86_CMP;
1076 			}
1077 #if defined(__amd64)
1078 			/*
1079 			 * It's really tricky to support syscall/sysret in
1080 			 * the i386 kernel; we rely on sysenter/sysexit
1081 			 * instead.  In the amd64 kernel, things are -way-
1082 			 * better.
1083 			 */
1084 			if (cp->cp_edx & CPUID_AMD_EDX_SYSC)
1085 				feature |= X86_ASYSC;
1086 
1087 			/*
1088 			 * While we're thinking about system calls, note
1089 			 * that AMD processors don't support sysenter
1090 			 * in long mode at all, so don't try to program them.
1091 			 */
1092 			if (x86_vendor == X86_VENDOR_AMD)
1093 				feature &= ~X86_SEP;
1094 #endif
1095 			if (x86_vendor == X86_VENDOR_AMD &&
1096 			    cp->cp_edx & CPUID_AMD_EDX_TSCP)
1097 				feature |= X86_TSCP;
1098 			break;
1099 		default:
1100 			break;
1101 		}
1102 
1103 		/*
1104 		 * Get CPUID data about processor cores and hyperthreads.
1105 		 */
1106 		switch (cpi->cpi_vendor) {
1107 		case X86_VENDOR_Intel:
1108 			if (cpi->cpi_maxeax >= 4) {
1109 				cp = &cpi->cpi_std[4];
1110 				cp->cp_eax = 4;
1111 				cp->cp_ecx = 0;
1112 				(void) __cpuid_insn(cp);
1113 				platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1114 			}
1115 			/*FALLTHROUGH*/
1116 		case X86_VENDOR_AMD:
1117 			if (cpi->cpi_xmaxeax < 0x80000008)
1118 				break;
1119 			cp = &cpi->cpi_extd[8];
1120 			cp->cp_eax = 0x80000008;
1121 			(void) __cpuid_insn(cp);
1122 			platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
1123 
1124 			/*
1125 			 * Virtual and physical address limits from
1126 			 * cpuid override previously guessed values.
1127 			 */
1128 			cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
1129 			cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
1130 			break;
1131 		default:
1132 			break;
1133 		}
1134 
1135 		/*
1136 		 * Derive the number of cores per chip
1137 		 */
1138 		switch (cpi->cpi_vendor) {
1139 		case X86_VENDOR_Intel:
1140 			if (cpi->cpi_maxeax < 4) {
1141 				cpi->cpi_ncore_per_chip = 1;
1142 				break;
1143 			} else {
1144 				cpi->cpi_ncore_per_chip =
1145 				    BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
1146 			}
1147 			break;
1148 		case X86_VENDOR_AMD:
1149 			if (cpi->cpi_xmaxeax < 0x80000008) {
1150 				cpi->cpi_ncore_per_chip = 1;
1151 				break;
1152 			} else {
1153 				/*
1154 				 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
1155 				 * 1 less than the number of physical cores on
1156 				 * the chip.  In family 0x10 this value can
1157 				 * be affected by "downcoring" - it reflects
1158 				 * 1 less than the number of cores actually
1159 				 * enabled on this node.
1160 				 */
1161 				cpi->cpi_ncore_per_chip =
1162 				    BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
1163 			}
1164 			break;
1165 		default:
1166 			cpi->cpi_ncore_per_chip = 1;
1167 			break;
1168 		}
1169 	} else {
1170 		cpi->cpi_ncore_per_chip = 1;
1171 	}
1172 
1173 	/*
1174 	 * If more than one core, then this processor is CMP.
1175 	 */
1176 	if (cpi->cpi_ncore_per_chip > 1)
1177 		feature |= X86_CMP;
1178 
1179 	/*
1180 	 * If the number of cores is the same as the number
1181 	 * of CPUs, then we cannot have HyperThreading.
1182 	 */
1183 	if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip)
1184 		feature &= ~X86_HTT;
1185 
1186 	if ((feature & (X86_HTT | X86_CMP)) == 0) {
1187 		/*
1188 		 * Single-core single-threaded processors.
1189 		 */
1190 		cpi->cpi_chipid = -1;
1191 		cpi->cpi_clogid = 0;
1192 		cpi->cpi_coreid = cpu->cpu_id;
1193 		cpi->cpi_pkgcoreid = 0;
1194 	} else if (cpi->cpi_ncpu_per_chip > 1) {
1195 		uint_t i;
1196 		uint_t chipid_shift = 0;
1197 		uint_t coreid_shift = 0;
1198 		uint_t apic_id = CPI_APIC_ID(cpi);
1199 
1200 		for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
1201 			chipid_shift++;
1202 		cpi->cpi_chipid = apic_id >> chipid_shift;
1203 		cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1);
1204 
1205 		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
1206 			if (feature & X86_CMP) {
1207 				/*
1208 				 * Multi-core (and possibly multi-threaded)
1209 				 * processors.
1210 				 */
1211 				uint_t ncpu_per_core;
1212 				if (cpi->cpi_ncore_per_chip == 1)
1213 					ncpu_per_core = cpi->cpi_ncpu_per_chip;
1214 				else if (cpi->cpi_ncore_per_chip > 1)
1215 					ncpu_per_core = cpi->cpi_ncpu_per_chip /
1216 					    cpi->cpi_ncore_per_chip;
1217 				/*
1218 				 * 8bit APIC IDs on dual core Pentiums
1219 				 * look like this:
1220 				 *
1221 				 * +-----------------------+------+------+
1222 				 * | Physical Package ID   |  MC  |  HT  |
1223 				 * +-----------------------+------+------+
1224 				 * <------- chipid -------->
1225 				 * <------- coreid --------------->
1226 				 *			   <--- clogid -->
1227 				 *			   <------>
1228 				 *			   pkgcoreid
1229 				 *
1230 				 * Where the number of bits necessary to
1231 				 * represent MC and HT fields together equals
1232 				 * to the minimum number of bits necessary to
1233 				 * store the value of cpi->cpi_ncpu_per_chip.
1234 				 * Of those bits, the MC part uses the number
1235 				 * of bits necessary to store the value of
1236 				 * cpi->cpi_ncore_per_chip.
1237 				 */
1238 				for (i = 1; i < ncpu_per_core; i <<= 1)
1239 					coreid_shift++;
1240 				cpi->cpi_coreid = apic_id >> coreid_shift;
1241 				cpi->cpi_pkgcoreid = cpi->cpi_clogid >>
1242 				    coreid_shift;
1243 			} else if (feature & X86_HTT) {
1244 				/*
1245 				 * Single-core multi-threaded processors.
1246 				 */
1247 				cpi->cpi_coreid = cpi->cpi_chipid;
1248 				cpi->cpi_pkgcoreid = 0;
1249 			}
1250 		} else if (cpi->cpi_vendor == X86_VENDOR_AMD) {
1251 			/*
1252 			 * AMD CMP chips currently have a single thread per
1253 			 * core, with 2 cores on family 0xf and 2, 3 or 4
1254 			 * cores on family 0x10.
1255 			 *
1256 			 * Since no two cpus share a core we must assign a
1257 			 * distinct coreid per cpu, and we do this by using
1258 			 * the cpu_id.  This scheme does not, however,
1259 			 * guarantee that sibling cores of a chip will have
1260 			 * sequential coreids starting at a multiple of the
1261 			 * number of cores per chip - that is usually the
1262 			 * case, but if the ACPI MADT table is presented
1263 			 * in a different order then we need to perform a
1264 			 * few more gymnastics for the pkgcoreid.
1265 			 *
1266 			 * In family 0xf CMPs there are 2 cores on all nodes
1267 			 * present - no mixing of single and dual core parts.
1268 			 *
1269 			 * In family 0x10 CMPs cpuid fn 2 ECX[15:12]
1270 			 * "ApicIdCoreIdSize[3:0]" tells us how
1271 			 * many least-significant bits in the ApicId
1272 			 * are used to represent the core number
1273 			 * within the node.  Cores are always
1274 			 * numbered sequentially from 0 regardless
1275 			 * of how many or which are disabled, and
1276 			 * there seems to be no way to discover the
1277 			 * real core id when some are disabled.
1278 			 */
1279 			cpi->cpi_coreid = cpu->cpu_id;
1280 
1281 			if (cpi->cpi_family == 0x10 &&
1282 			    cpi->cpi_xmaxeax >= 0x80000008) {
1283 				int coreidsz =
1284 				    BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
1285 
1286 				cpi->cpi_pkgcoreid =
1287 				    apic_id & ((1 << coreidsz) - 1);
1288 			} else {
1289 				cpi->cpi_pkgcoreid = cpi->cpi_clogid;
1290 			}
1291 		} else {
1292 			/*
1293 			 * All other processors are currently
1294 			 * assumed to have single cores.
1295 			 */
1296 			cpi->cpi_coreid = cpi->cpi_chipid;
1297 			cpi->cpi_pkgcoreid = 0;
1298 		}
1299 	}
1300 
1301 	/*
1302 	 * Synthesize chip "revision" and socket type
1303 	 */
1304 	synth_info(cpi);
1305 
1306 pass1_done:
1307 #if !defined(__xpv)
1308 	check_for_hvm();
1309 #endif
1310 	cpi->cpi_pass = 1;
1311 	return (feature);
1312 }
1313 
1314 /*
1315  * Make copies of the cpuid table entries we depend on, in
1316  * part for ease of parsing now, in part so that we have only
1317  * one place to correct any of it, in part for ease of
1318  * later export to userland, and in part so we can look at
1319  * this stuff in a crash dump.
1320  */
1321 
1322 /*ARGSUSED*/
1323 void
1324 cpuid_pass2(cpu_t *cpu)
1325 {
1326 	uint_t n, nmax;
1327 	int i;
1328 	struct cpuid_regs *cp;
1329 	uint8_t *dp;
1330 	uint32_t *iptr;
1331 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1332 
1333 	ASSERT(cpi->cpi_pass == 1);
1334 
1335 	if (cpi->cpi_maxeax < 1)
1336 		goto pass2_done;
1337 
1338 	if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
1339 		nmax = NMAX_CPI_STD;
1340 	/*
1341 	 * (We already handled n == 0 and n == 1 in pass 1)
1342 	 */
1343 	for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1344 		cp->cp_eax = n;
1345 
1346 		/*
1347 		 * CPUID function 4 expects %ecx to be initialized
1348 		 * with an index which indicates which cache to return
1349 		 * information about. The OS is expected to call function 4
1350 		 * with %ecx set to 0, 1, 2, ... until it returns with
1351 		 * EAX[4:0] set to 0, which indicates there are no more
1352 		 * caches.
1353 		 *
1354 		 * Here, populate cpi_std[4] with the information returned by
1355 		 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
1356 		 * when dynamic memory allocation becomes available.
1357 		 *
1358 		 * Note: we need to explicitly initialize %ecx here, since
1359 		 * function 4 may have been previously invoked.
1360 		 */
1361 		if (n == 4)
1362 			cp->cp_ecx = 0;
1363 
1364 		(void) __cpuid_insn(cp);
1365 		platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
1366 		switch (n) {
1367 		case 2:
1368 			/*
1369 			 * "the lower 8 bits of the %eax register
1370 			 * contain a value that identifies the number
1371 			 * of times the cpuid [instruction] has to be
1372 			 * executed to obtain a complete image of the
1373 			 * processor's caching systems."
1374 			 *
1375 			 * How *do* they make this stuff up?
1376 			 */
1377 			cpi->cpi_ncache = sizeof (*cp) *
1378 			    BITX(cp->cp_eax, 7, 0);
1379 			if (cpi->cpi_ncache == 0)
1380 				break;
1381 			cpi->cpi_ncache--;	/* skip count byte */
1382 
1383 			/*
1384 			 * Well, for now, rather than attempt to implement
1385 			 * this slightly dubious algorithm, we just look
1386 			 * at the first 15 ..
1387 			 */
1388 			if (cpi->cpi_ncache > (sizeof (*cp) - 1))
1389 				cpi->cpi_ncache = sizeof (*cp) - 1;
1390 
1391 			dp = cpi->cpi_cacheinfo;
1392 			if (BITX(cp->cp_eax, 31, 31) == 0) {
1393 				uint8_t *p = (void *)&cp->cp_eax;
1394 				for (i = 1; i < 3; i++)
1395 					if (p[i] != 0)
1396 						*dp++ = p[i];
1397 			}
1398 			if (BITX(cp->cp_ebx, 31, 31) == 0) {
1399 				uint8_t *p = (void *)&cp->cp_ebx;
1400 				for (i = 0; i < 4; i++)
1401 					if (p[i] != 0)
1402 						*dp++ = p[i];
1403 			}
1404 			if (BITX(cp->cp_ecx, 31, 31) == 0) {
1405 				uint8_t *p = (void *)&cp->cp_ecx;
1406 				for (i = 0; i < 4; i++)
1407 					if (p[i] != 0)
1408 						*dp++ = p[i];
1409 			}
1410 			if (BITX(cp->cp_edx, 31, 31) == 0) {
1411 				uint8_t *p = (void *)&cp->cp_edx;
1412 				for (i = 0; i < 4; i++)
1413 					if (p[i] != 0)
1414 						*dp++ = p[i];
1415 			}
1416 			break;
1417 
1418 		case 3:	/* Processor serial number, if PSN supported */
1419 			break;
1420 
1421 		case 4:	/* Deterministic cache parameters */
1422 			break;
1423 
1424 		case 5:	/* Monitor/Mwait parameters */
1425 		{
1426 			size_t mwait_size;
1427 
1428 			/*
1429 			 * check cpi_mwait.support which was set in cpuid_pass1
1430 			 */
1431 			if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
1432 				break;
1433 
1434 			/*
1435 			 * Protect ourself from insane mwait line size.
1436 			 * Workaround for incomplete hardware emulator(s).
1437 			 */
1438 			mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
1439 			if (mwait_size < sizeof (uint32_t) ||
1440 			    !ISP2(mwait_size)) {
1441 #if DEBUG
1442 				cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
1443 				    "size %ld",
1444 				    cpu->cpu_id, (long)mwait_size);
1445 #endif
1446 				break;
1447 			}
1448 
1449 			cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
1450 			cpi->cpi_mwait.mon_max = mwait_size;
1451 			if (MWAIT_EXTENSION(cpi)) {
1452 				cpi->cpi_mwait.support |= MWAIT_EXTENSIONS;
1453 				if (MWAIT_INT_ENABLE(cpi))
1454 					cpi->cpi_mwait.support |=
1455 					    MWAIT_ECX_INT_ENABLE;
1456 			}
1457 			break;
1458 		}
1459 		default:
1460 			break;
1461 		}
1462 	}
1463 
1464 	if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
1465 		goto pass2_done;
1466 
1467 	if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
1468 		nmax = NMAX_CPI_EXTD;
1469 	/*
1470 	 * Copy the extended properties, fixing them as we go.
1471 	 * (We already handled n == 0 and n == 1 in pass 1)
1472 	 */
1473 	iptr = (void *)cpi->cpi_brandstr;
1474 	for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
1475 		cp->cp_eax = 0x80000000 + n;
1476 		(void) __cpuid_insn(cp);
1477 		platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
1478 		switch (n) {
1479 		case 2:
1480 		case 3:
1481 		case 4:
1482 			/*
1483 			 * Extract the brand string
1484 			 */
1485 			*iptr++ = cp->cp_eax;
1486 			*iptr++ = cp->cp_ebx;
1487 			*iptr++ = cp->cp_ecx;
1488 			*iptr++ = cp->cp_edx;
1489 			break;
1490 		case 5:
1491 			switch (cpi->cpi_vendor) {
1492 			case X86_VENDOR_AMD:
1493 				/*
1494 				 * The Athlon and Duron were the first
1495 				 * parts to report the sizes of the
1496 				 * TLB for large pages. Before then,
1497 				 * we don't trust the data.
1498 				 */
1499 				if (cpi->cpi_family < 6 ||
1500 				    (cpi->cpi_family == 6 &&
1501 				    cpi->cpi_model < 1))
1502 					cp->cp_eax = 0;
1503 				break;
1504 			default:
1505 				break;
1506 			}
1507 			break;
1508 		case 6:
1509 			switch (cpi->cpi_vendor) {
1510 			case X86_VENDOR_AMD:
1511 				/*
1512 				 * The Athlon and Duron were the first
1513 				 * AMD parts with L2 TLB's.
1514 				 * Before then, don't trust the data.
1515 				 */
1516 				if (cpi->cpi_family < 6 ||
1517 				    cpi->cpi_family == 6 &&
1518 				    cpi->cpi_model < 1)
1519 					cp->cp_eax = cp->cp_ebx = 0;
1520 				/*
1521 				 * AMD Duron rev A0 reports L2
1522 				 * cache size incorrectly as 1K
1523 				 * when it is really 64K
1524 				 */
1525 				if (cpi->cpi_family == 6 &&
1526 				    cpi->cpi_model == 3 &&
1527 				    cpi->cpi_step == 0) {
1528 					cp->cp_ecx &= 0xffff;
1529 					cp->cp_ecx |= 0x400000;
1530 				}
1531 				break;
1532 			case X86_VENDOR_Cyrix:	/* VIA C3 */
1533 				/*
1534 				 * VIA C3 processors are a bit messed
1535 				 * up w.r.t. encoding cache sizes in %ecx
1536 				 */
1537 				if (cpi->cpi_family != 6)
1538 					break;
1539 				/*
1540 				 * model 7 and 8 were incorrectly encoded
1541 				 *
1542 				 * xxx is model 8 really broken?
1543 				 */
1544 				if (cpi->cpi_model == 7 ||
1545 				    cpi->cpi_model == 8)
1546 					cp->cp_ecx =
1547 					    BITX(cp->cp_ecx, 31, 24) << 16 |
1548 					    BITX(cp->cp_ecx, 23, 16) << 12 |
1549 					    BITX(cp->cp_ecx, 15, 8) << 8 |
1550 					    BITX(cp->cp_ecx, 7, 0);
1551 				/*
1552 				 * model 9 stepping 1 has wrong associativity
1553 				 */
1554 				if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
1555 					cp->cp_ecx |= 8 << 12;
1556 				break;
1557 			case X86_VENDOR_Intel:
1558 				/*
1559 				 * Extended L2 Cache features function.
1560 				 * First appeared on Prescott.
1561 				 */
1562 			default:
1563 				break;
1564 			}
1565 			break;
1566 		default:
1567 			break;
1568 		}
1569 	}
1570 
1571 pass2_done:
1572 	cpi->cpi_pass = 2;
1573 }
1574 
1575 static const char *
1576 intel_cpubrand(const struct cpuid_info *cpi)
1577 {
1578 	int i;
1579 
1580 	if ((x86_feature & X86_CPUID) == 0 ||
1581 	    cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
1582 		return ("i486");
1583 
1584 	switch (cpi->cpi_family) {
1585 	case 5:
1586 		return ("Intel Pentium(r)");
1587 	case 6:
1588 		switch (cpi->cpi_model) {
1589 			uint_t celeron, xeon;
1590 			const struct cpuid_regs *cp;
1591 		case 0:
1592 		case 1:
1593 		case 2:
1594 			return ("Intel Pentium(r) Pro");
1595 		case 3:
1596 		case 4:
1597 			return ("Intel Pentium(r) II");
1598 		case 6:
1599 			return ("Intel Celeron(r)");
1600 		case 5:
1601 		case 7:
1602 			celeron = xeon = 0;
1603 			cp = &cpi->cpi_std[2];	/* cache info */
1604 
1605 			for (i = 1; i < 3; i++) {
1606 				uint_t tmp;
1607 
1608 				tmp = (cp->cp_eax >> (8 * i)) & 0xff;
1609 				if (tmp == 0x40)
1610 					celeron++;
1611 				if (tmp >= 0x44 && tmp <= 0x45)
1612 					xeon++;
1613 			}
1614 
1615 			for (i = 0; i < 2; i++) {
1616 				uint_t tmp;
1617 
1618 				tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
1619 				if (tmp == 0x40)
1620 					celeron++;
1621 				else if (tmp >= 0x44 && tmp <= 0x45)
1622 					xeon++;
1623 			}
1624 
1625 			for (i = 0; i < 4; i++) {
1626 				uint_t tmp;
1627 
1628 				tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
1629 				if (tmp == 0x40)
1630 					celeron++;
1631 				else if (tmp >= 0x44 && tmp <= 0x45)
1632 					xeon++;
1633 			}
1634 
1635 			for (i = 0; i < 4; i++) {
1636 				uint_t tmp;
1637 
1638 				tmp = (cp->cp_edx >> (8 * i)) & 0xff;
1639 				if (tmp == 0x40)
1640 					celeron++;
1641 				else if (tmp >= 0x44 && tmp <= 0x45)
1642 					xeon++;
1643 			}
1644 
1645 			if (celeron)
1646 				return ("Intel Celeron(r)");
1647 			if (xeon)
1648 				return (cpi->cpi_model == 5 ?
1649 				    "Intel Pentium(r) II Xeon(tm)" :
1650 				    "Intel Pentium(r) III Xeon(tm)");
1651 			return (cpi->cpi_model == 5 ?
1652 			    "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
1653 			    "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
1654 		default:
1655 			break;
1656 		}
1657 	default:
1658 		break;
1659 	}
1660 
1661 	/* BrandID is present if the field is nonzero */
1662 	if (cpi->cpi_brandid != 0) {
1663 		static const struct {
1664 			uint_t bt_bid;
1665 			const char *bt_str;
1666 		} brand_tbl[] = {
1667 			{ 0x1,	"Intel(r) Celeron(r)" },
1668 			{ 0x2,	"Intel(r) Pentium(r) III" },
1669 			{ 0x3,	"Intel(r) Pentium(r) III Xeon(tm)" },
1670 			{ 0x4,	"Intel(r) Pentium(r) III" },
1671 			{ 0x6,	"Mobile Intel(r) Pentium(r) III" },
1672 			{ 0x7,	"Mobile Intel(r) Celeron(r)" },
1673 			{ 0x8,	"Intel(r) Pentium(r) 4" },
1674 			{ 0x9,	"Intel(r) Pentium(r) 4" },
1675 			{ 0xa,	"Intel(r) Celeron(r)" },
1676 			{ 0xb,	"Intel(r) Xeon(tm)" },
1677 			{ 0xc,	"Intel(r) Xeon(tm) MP" },
1678 			{ 0xe,	"Mobile Intel(r) Pentium(r) 4" },
1679 			{ 0xf,	"Mobile Intel(r) Celeron(r)" },
1680 			{ 0x11, "Mobile Genuine Intel(r)" },
1681 			{ 0x12, "Intel(r) Celeron(r) M" },
1682 			{ 0x13, "Mobile Intel(r) Celeron(r)" },
1683 			{ 0x14, "Intel(r) Celeron(r)" },
1684 			{ 0x15, "Mobile Genuine Intel(r)" },
1685 			{ 0x16,	"Intel(r) Pentium(r) M" },
1686 			{ 0x17, "Mobile Intel(r) Celeron(r)" }
1687 		};
1688 		uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
1689 		uint_t sgn;
1690 
1691 		sgn = (cpi->cpi_family << 8) |
1692 		    (cpi->cpi_model << 4) | cpi->cpi_step;
1693 
1694 		for (i = 0; i < btblmax; i++)
1695 			if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
1696 				break;
1697 		if (i < btblmax) {
1698 			if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
1699 				return ("Intel(r) Celeron(r)");
1700 			if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
1701 				return ("Intel(r) Xeon(tm) MP");
1702 			if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
1703 				return ("Intel(r) Xeon(tm)");
1704 			return (brand_tbl[i].bt_str);
1705 		}
1706 	}
1707 
1708 	return (NULL);
1709 }
1710 
1711 static const char *
1712 amd_cpubrand(const struct cpuid_info *cpi)
1713 {
1714 	if ((x86_feature & X86_CPUID) == 0 ||
1715 	    cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
1716 		return ("i486 compatible");
1717 
1718 	switch (cpi->cpi_family) {
1719 	case 5:
1720 		switch (cpi->cpi_model) {
1721 		case 0:
1722 		case 1:
1723 		case 2:
1724 		case 3:
1725 		case 4:
1726 		case 5:
1727 			return ("AMD-K5(r)");
1728 		case 6:
1729 		case 7:
1730 			return ("AMD-K6(r)");
1731 		case 8:
1732 			return ("AMD-K6(r)-2");
1733 		case 9:
1734 			return ("AMD-K6(r)-III");
1735 		default:
1736 			return ("AMD (family 5)");
1737 		}
1738 	case 6:
1739 		switch (cpi->cpi_model) {
1740 		case 1:
1741 			return ("AMD-K7(tm)");
1742 		case 0:
1743 		case 2:
1744 		case 4:
1745 			return ("AMD Athlon(tm)");
1746 		case 3:
1747 		case 7:
1748 			return ("AMD Duron(tm)");
1749 		case 6:
1750 		case 8:
1751 		case 10:
1752 			/*
1753 			 * Use the L2 cache size to distinguish
1754 			 */
1755 			return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
1756 			    "AMD Athlon(tm)" : "AMD Duron(tm)");
1757 		default:
1758 			return ("AMD (family 6)");
1759 		}
1760 	default:
1761 		break;
1762 	}
1763 
1764 	if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
1765 	    cpi->cpi_brandid != 0) {
1766 		switch (BITX(cpi->cpi_brandid, 7, 5)) {
1767 		case 3:
1768 			return ("AMD Opteron(tm) UP 1xx");
1769 		case 4:
1770 			return ("AMD Opteron(tm) DP 2xx");
1771 		case 5:
1772 			return ("AMD Opteron(tm) MP 8xx");
1773 		default:
1774 			return ("AMD Opteron(tm)");
1775 		}
1776 	}
1777 
1778 	return (NULL);
1779 }
1780 
1781 static const char *
1782 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
1783 {
1784 	if ((x86_feature & X86_CPUID) == 0 ||
1785 	    cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 ||
1786 	    type == X86_TYPE_CYRIX_486)
1787 		return ("i486 compatible");
1788 
1789 	switch (type) {
1790 	case X86_TYPE_CYRIX_6x86:
1791 		return ("Cyrix 6x86");
1792 	case X86_TYPE_CYRIX_6x86L:
1793 		return ("Cyrix 6x86L");
1794 	case X86_TYPE_CYRIX_6x86MX:
1795 		return ("Cyrix 6x86MX");
1796 	case X86_TYPE_CYRIX_GXm:
1797 		return ("Cyrix GXm");
1798 	case X86_TYPE_CYRIX_MediaGX:
1799 		return ("Cyrix MediaGX");
1800 	case X86_TYPE_CYRIX_MII:
1801 		return ("Cyrix M2");
1802 	case X86_TYPE_VIA_CYRIX_III:
1803 		return ("VIA Cyrix M3");
1804 	default:
1805 		/*
1806 		 * Have another wild guess ..
1807 		 */
1808 		if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
1809 			return ("Cyrix 5x86");
1810 		else if (cpi->cpi_family == 5) {
1811 			switch (cpi->cpi_model) {
1812 			case 2:
1813 				return ("Cyrix 6x86");	/* Cyrix M1 */
1814 			case 4:
1815 				return ("Cyrix MediaGX");
1816 			default:
1817 				break;
1818 			}
1819 		} else if (cpi->cpi_family == 6) {
1820 			switch (cpi->cpi_model) {
1821 			case 0:
1822 				return ("Cyrix 6x86MX"); /* Cyrix M2? */
1823 			case 5:
1824 			case 6:
1825 			case 7:
1826 			case 8:
1827 			case 9:
1828 				return ("VIA C3");
1829 			default:
1830 				break;
1831 			}
1832 		}
1833 		break;
1834 	}
1835 	return (NULL);
1836 }
1837 
1838 /*
1839  * This only gets called in the case that the CPU extended
1840  * feature brand string (0x80000002, 0x80000003, 0x80000004)
1841  * aren't available, or contain null bytes for some reason.
1842  */
1843 static void
1844 fabricate_brandstr(struct cpuid_info *cpi)
1845 {
1846 	const char *brand = NULL;
1847 
1848 	switch (cpi->cpi_vendor) {
1849 	case X86_VENDOR_Intel:
1850 		brand = intel_cpubrand(cpi);
1851 		break;
1852 	case X86_VENDOR_AMD:
1853 		brand = amd_cpubrand(cpi);
1854 		break;
1855 	case X86_VENDOR_Cyrix:
1856 		brand = cyrix_cpubrand(cpi, x86_type);
1857 		break;
1858 	case X86_VENDOR_NexGen:
1859 		if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
1860 			brand = "NexGen Nx586";
1861 		break;
1862 	case X86_VENDOR_Centaur:
1863 		if (cpi->cpi_family == 5)
1864 			switch (cpi->cpi_model) {
1865 			case 4:
1866 				brand = "Centaur C6";
1867 				break;
1868 			case 8:
1869 				brand = "Centaur C2";
1870 				break;
1871 			case 9:
1872 				brand = "Centaur C3";
1873 				break;
1874 			default:
1875 				break;
1876 			}
1877 		break;
1878 	case X86_VENDOR_Rise:
1879 		if (cpi->cpi_family == 5 &&
1880 		    (cpi->cpi_model == 0 || cpi->cpi_model == 2))
1881 			brand = "Rise mP6";
1882 		break;
1883 	case X86_VENDOR_SiS:
1884 		if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
1885 			brand = "SiS 55x";
1886 		break;
1887 	case X86_VENDOR_TM:
1888 		if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
1889 			brand = "Transmeta Crusoe TM3x00 or TM5x00";
1890 		break;
1891 	case X86_VENDOR_NSC:
1892 	case X86_VENDOR_UMC:
1893 	default:
1894 		break;
1895 	}
1896 	if (brand) {
1897 		(void) strcpy((char *)cpi->cpi_brandstr, brand);
1898 		return;
1899 	}
1900 
1901 	/*
1902 	 * If all else fails ...
1903 	 */
1904 	(void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
1905 	    "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
1906 	    cpi->cpi_model, cpi->cpi_step);
1907 }
1908 
1909 /*
1910  * This routine is called just after kernel memory allocation
1911  * becomes available on cpu0, and as part of mp_startup() on
1912  * the other cpus.
1913  *
1914  * Fixup the brand string, and collect any information from cpuid
1915  * that requires dynamicically allocated storage to represent.
1916  */
1917 /*ARGSUSED*/
1918 void
1919 cpuid_pass3(cpu_t *cpu)
1920 {
1921 	int	i, max, shft, level, size;
1922 	struct cpuid_regs regs;
1923 	struct cpuid_regs *cp;
1924 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1925 
1926 	ASSERT(cpi->cpi_pass == 2);
1927 
1928 	/*
1929 	 * Function 4: Deterministic cache parameters
1930 	 *
1931 	 * Take this opportunity to detect the number of threads
1932 	 * sharing the last level cache, and construct a corresponding
1933 	 * cache id. The respective cpuid_info members are initialized
1934 	 * to the default case of "no last level cache sharing".
1935 	 */
1936 	cpi->cpi_ncpu_shr_last_cache = 1;
1937 	cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
1938 
1939 	if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
1940 
1941 		/*
1942 		 * Find the # of elements (size) returned by fn 4, and along
1943 		 * the way detect last level cache sharing details.
1944 		 */
1945 		bzero(&regs, sizeof (regs));
1946 		cp = &regs;
1947 		for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
1948 			cp->cp_eax = 4;
1949 			cp->cp_ecx = i;
1950 
1951 			(void) __cpuid_insn(cp);
1952 
1953 			if (CPI_CACHE_TYPE(cp) == 0)
1954 				break;
1955 			level = CPI_CACHE_LVL(cp);
1956 			if (level > max) {
1957 				max = level;
1958 				cpi->cpi_ncpu_shr_last_cache =
1959 				    CPI_NTHR_SHR_CACHE(cp) + 1;
1960 			}
1961 		}
1962 		cpi->cpi_std_4_size = size = i;
1963 
1964 		/*
1965 		 * Allocate the cpi_std_4 array. The first element
1966 		 * references the regs for fn 4, %ecx == 0, which
1967 		 * cpuid_pass2() stashed in cpi->cpi_std[4].
1968 		 */
1969 		if (size > 0) {
1970 			cpi->cpi_std_4 =
1971 			    kmem_alloc(size * sizeof (cp), KM_SLEEP);
1972 			cpi->cpi_std_4[0] = &cpi->cpi_std[4];
1973 
1974 			/*
1975 			 * Allocate storage to hold the additional regs
1976 			 * for function 4, %ecx == 1 .. cpi_std_4_size.
1977 			 *
1978 			 * The regs for fn 4, %ecx == 0 has already
1979 			 * been allocated as indicated above.
1980 			 */
1981 			for (i = 1; i < size; i++) {
1982 				cp = cpi->cpi_std_4[i] =
1983 				    kmem_zalloc(sizeof (regs), KM_SLEEP);
1984 				cp->cp_eax = 4;
1985 				cp->cp_ecx = i;
1986 
1987 				(void) __cpuid_insn(cp);
1988 			}
1989 		}
1990 		/*
1991 		 * Determine the number of bits needed to represent
1992 		 * the number of CPUs sharing the last level cache.
1993 		 *
1994 		 * Shift off that number of bits from the APIC id to
1995 		 * derive the cache id.
1996 		 */
1997 		shft = 0;
1998 		for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
1999 			shft++;
2000 		cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft;
2001 	}
2002 
2003 	/*
2004 	 * Now fixup the brand string
2005 	 */
2006 	if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
2007 		fabricate_brandstr(cpi);
2008 	} else {
2009 
2010 		/*
2011 		 * If we successfully extracted a brand string from the cpuid
2012 		 * instruction, clean it up by removing leading spaces and
2013 		 * similar junk.
2014 		 */
2015 		if (cpi->cpi_brandstr[0]) {
2016 			size_t maxlen = sizeof (cpi->cpi_brandstr);
2017 			char *src, *dst;
2018 
2019 			dst = src = (char *)cpi->cpi_brandstr;
2020 			src[maxlen - 1] = '\0';
2021 			/*
2022 			 * strip leading spaces
2023 			 */
2024 			while (*src == ' ')
2025 				src++;
2026 			/*
2027 			 * Remove any 'Genuine' or "Authentic" prefixes
2028 			 */
2029 			if (strncmp(src, "Genuine ", 8) == 0)
2030 				src += 8;
2031 			if (strncmp(src, "Authentic ", 10) == 0)
2032 				src += 10;
2033 
2034 			/*
2035 			 * Now do an in-place copy.
2036 			 * Map (R) to (r) and (TM) to (tm).
2037 			 * The era of teletypes is long gone, and there's
2038 			 * -really- no need to shout.
2039 			 */
2040 			while (*src != '\0') {
2041 				if (src[0] == '(') {
2042 					if (strncmp(src + 1, "R)", 2) == 0) {
2043 						(void) strncpy(dst, "(r)", 3);
2044 						src += 3;
2045 						dst += 3;
2046 						continue;
2047 					}
2048 					if (strncmp(src + 1, "TM)", 3) == 0) {
2049 						(void) strncpy(dst, "(tm)", 4);
2050 						src += 4;
2051 						dst += 4;
2052 						continue;
2053 					}
2054 				}
2055 				*dst++ = *src++;
2056 			}
2057 			*dst = '\0';
2058 
2059 			/*
2060 			 * Finally, remove any trailing spaces
2061 			 */
2062 			while (--dst > cpi->cpi_brandstr)
2063 				if (*dst == ' ')
2064 					*dst = '\0';
2065 				else
2066 					break;
2067 		} else
2068 			fabricate_brandstr(cpi);
2069 	}
2070 	cpi->cpi_pass = 3;
2071 }
2072 
2073 /*
2074  * This routine is called out of bind_hwcap() much later in the life
2075  * of the kernel (post_startup()).  The job of this routine is to resolve
2076  * the hardware feature support and kernel support for those features into
2077  * what we're actually going to tell applications via the aux vector.
2078  */
2079 uint_t
2080 cpuid_pass4(cpu_t *cpu)
2081 {
2082 	struct cpuid_info *cpi;
2083 	uint_t hwcap_flags = 0;
2084 
2085 	if (cpu == NULL)
2086 		cpu = CPU;
2087 	cpi = cpu->cpu_m.mcpu_cpi;
2088 
2089 	ASSERT(cpi->cpi_pass == 3);
2090 
2091 	if (cpi->cpi_maxeax >= 1) {
2092 		uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
2093 		uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
2094 
2095 		*edx = CPI_FEATURES_EDX(cpi);
2096 		*ecx = CPI_FEATURES_ECX(cpi);
2097 
2098 		/*
2099 		 * [these require explicit kernel support]
2100 		 */
2101 		if ((x86_feature & X86_SEP) == 0)
2102 			*edx &= ~CPUID_INTC_EDX_SEP;
2103 
2104 		if ((x86_feature & X86_SSE) == 0)
2105 			*edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE);
2106 		if ((x86_feature & X86_SSE2) == 0)
2107 			*edx &= ~CPUID_INTC_EDX_SSE2;
2108 
2109 		if ((x86_feature & X86_HTT) == 0)
2110 			*edx &= ~CPUID_INTC_EDX_HTT;
2111 
2112 		if ((x86_feature & X86_SSE3) == 0)
2113 			*ecx &= ~CPUID_INTC_ECX_SSE3;
2114 
2115 		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
2116 			if ((x86_feature & X86_SSSE3) == 0)
2117 				*ecx &= ~CPUID_INTC_ECX_SSSE3;
2118 			if ((x86_feature & X86_SSE4_1) == 0)
2119 				*ecx &= ~CPUID_INTC_ECX_SSE4_1;
2120 			if ((x86_feature & X86_SSE4_2) == 0)
2121 				*ecx &= ~CPUID_INTC_ECX_SSE4_2;
2122 		}
2123 
2124 		/*
2125 		 * [no explicit support required beyond x87 fp context]
2126 		 */
2127 		if (!fpu_exists)
2128 			*edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX);
2129 
2130 		/*
2131 		 * Now map the supported feature vector to things that we
2132 		 * think userland will care about.
2133 		 */
2134 		if (*edx & CPUID_INTC_EDX_SEP)
2135 			hwcap_flags |= AV_386_SEP;
2136 		if (*edx & CPUID_INTC_EDX_SSE)
2137 			hwcap_flags |= AV_386_FXSR | AV_386_SSE;
2138 		if (*edx & CPUID_INTC_EDX_SSE2)
2139 			hwcap_flags |= AV_386_SSE2;
2140 		if (*ecx & CPUID_INTC_ECX_SSE3)
2141 			hwcap_flags |= AV_386_SSE3;
2142 		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
2143 			if (*ecx & CPUID_INTC_ECX_SSSE3)
2144 				hwcap_flags |= AV_386_SSSE3;
2145 			if (*ecx & CPUID_INTC_ECX_SSE4_1)
2146 				hwcap_flags |= AV_386_SSE4_1;
2147 			if (*ecx & CPUID_INTC_ECX_SSE4_2)
2148 				hwcap_flags |= AV_386_SSE4_2;
2149 		}
2150 		if (*ecx & CPUID_INTC_ECX_POPCNT)
2151 			hwcap_flags |= AV_386_POPCNT;
2152 		if (*edx & CPUID_INTC_EDX_FPU)
2153 			hwcap_flags |= AV_386_FPU;
2154 		if (*edx & CPUID_INTC_EDX_MMX)
2155 			hwcap_flags |= AV_386_MMX;
2156 
2157 		if (*edx & CPUID_INTC_EDX_TSC)
2158 			hwcap_flags |= AV_386_TSC;
2159 		if (*edx & CPUID_INTC_EDX_CX8)
2160 			hwcap_flags |= AV_386_CX8;
2161 		if (*edx & CPUID_INTC_EDX_CMOV)
2162 			hwcap_flags |= AV_386_CMOV;
2163 		if (*ecx & CPUID_INTC_ECX_MON)
2164 			hwcap_flags |= AV_386_MON;
2165 		if (*ecx & CPUID_INTC_ECX_CX16)
2166 			hwcap_flags |= AV_386_CX16;
2167 	}
2168 
2169 	if (x86_feature & X86_HTT)
2170 		hwcap_flags |= AV_386_PAUSE;
2171 
2172 	if (cpi->cpi_xmaxeax < 0x80000001)
2173 		goto pass4_done;
2174 
2175 	switch (cpi->cpi_vendor) {
2176 		struct cpuid_regs cp;
2177 		uint32_t *edx, *ecx;
2178 
2179 	case X86_VENDOR_Intel:
2180 		/*
2181 		 * Seems like Intel duplicated what we necessary
2182 		 * here to make the initial crop of 64-bit OS's work.
2183 		 * Hopefully, those are the only "extended" bits
2184 		 * they'll add.
2185 		 */
2186 		/*FALLTHROUGH*/
2187 
2188 	case X86_VENDOR_AMD:
2189 		edx = &cpi->cpi_support[AMD_EDX_FEATURES];
2190 		ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
2191 
2192 		*edx = CPI_FEATURES_XTD_EDX(cpi);
2193 		*ecx = CPI_FEATURES_XTD_ECX(cpi);
2194 
2195 		/*
2196 		 * [these features require explicit kernel support]
2197 		 */
2198 		switch (cpi->cpi_vendor) {
2199 		case X86_VENDOR_Intel:
2200 			break;
2201 
2202 		case X86_VENDOR_AMD:
2203 			if ((x86_feature & X86_TSCP) == 0)
2204 				*edx &= ~CPUID_AMD_EDX_TSCP;
2205 			if ((x86_feature & X86_SSE4A) == 0)
2206 				*ecx &= ~CPUID_AMD_ECX_SSE4A;
2207 			break;
2208 
2209 		default:
2210 			break;
2211 		}
2212 
2213 		/*
2214 		 * [no explicit support required beyond
2215 		 * x87 fp context and exception handlers]
2216 		 */
2217 		if (!fpu_exists)
2218 			*edx &= ~(CPUID_AMD_EDX_MMXamd |
2219 			    CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx);
2220 
2221 		if ((x86_feature & X86_NX) == 0)
2222 			*edx &= ~CPUID_AMD_EDX_NX;
2223 #if !defined(__amd64)
2224 		*edx &= ~CPUID_AMD_EDX_LM;
2225 #endif
2226 		/*
2227 		 * Now map the supported feature vector to
2228 		 * things that we think userland will care about.
2229 		 */
2230 #if defined(__amd64)
2231 		if (*edx & CPUID_AMD_EDX_SYSC)
2232 			hwcap_flags |= AV_386_AMD_SYSC;
2233 #endif
2234 		if (*edx & CPUID_AMD_EDX_MMXamd)
2235 			hwcap_flags |= AV_386_AMD_MMX;
2236 		if (*edx & CPUID_AMD_EDX_3DNow)
2237 			hwcap_flags |= AV_386_AMD_3DNow;
2238 		if (*edx & CPUID_AMD_EDX_3DNowx)
2239 			hwcap_flags |= AV_386_AMD_3DNowx;
2240 
2241 		switch (cpi->cpi_vendor) {
2242 		case X86_VENDOR_AMD:
2243 			if (*edx & CPUID_AMD_EDX_TSCP)
2244 				hwcap_flags |= AV_386_TSCP;
2245 			if (*ecx & CPUID_AMD_ECX_AHF64)
2246 				hwcap_flags |= AV_386_AHF;
2247 			if (*ecx & CPUID_AMD_ECX_SSE4A)
2248 				hwcap_flags |= AV_386_AMD_SSE4A;
2249 			if (*ecx & CPUID_AMD_ECX_LZCNT)
2250 				hwcap_flags |= AV_386_AMD_LZCNT;
2251 			break;
2252 
2253 		case X86_VENDOR_Intel:
2254 			/*
2255 			 * Aarrgh.
2256 			 * Intel uses a different bit in the same word.
2257 			 */
2258 			if (*ecx & CPUID_INTC_ECX_AHF64)
2259 				hwcap_flags |= AV_386_AHF;
2260 			break;
2261 
2262 		default:
2263 			break;
2264 		}
2265 		break;
2266 
2267 	case X86_VENDOR_TM:
2268 		cp.cp_eax = 0x80860001;
2269 		(void) __cpuid_insn(&cp);
2270 		cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
2271 		break;
2272 
2273 	default:
2274 		break;
2275 	}
2276 
2277 pass4_done:
2278 	cpi->cpi_pass = 4;
2279 	return (hwcap_flags);
2280 }
2281 
2282 
2283 /*
2284  * Simulate the cpuid instruction using the data we previously
2285  * captured about this CPU.  We try our best to return the truth
2286  * about the hardware, independently of kernel support.
2287  */
2288 uint32_t
2289 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp)
2290 {
2291 	struct cpuid_info *cpi;
2292 	struct cpuid_regs *xcp;
2293 
2294 	if (cpu == NULL)
2295 		cpu = CPU;
2296 	cpi = cpu->cpu_m.mcpu_cpi;
2297 
2298 	ASSERT(cpuid_checkpass(cpu, 3));
2299 
2300 	/*
2301 	 * CPUID data is cached in two separate places: cpi_std for standard
2302 	 * CPUID functions, and cpi_extd for extended CPUID functions.
2303 	 */
2304 	if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
2305 		xcp = &cpi->cpi_std[cp->cp_eax];
2306 	else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
2307 	    cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
2308 		xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
2309 	else
2310 		/*
2311 		 * The caller is asking for data from an input parameter which
2312 		 * the kernel has not cached.  In this case we go fetch from
2313 		 * the hardware and return the data directly to the user.
2314 		 */
2315 		return (__cpuid_insn(cp));
2316 
2317 	cp->cp_eax = xcp->cp_eax;
2318 	cp->cp_ebx = xcp->cp_ebx;
2319 	cp->cp_ecx = xcp->cp_ecx;
2320 	cp->cp_edx = xcp->cp_edx;
2321 	return (cp->cp_eax);
2322 }
2323 
2324 int
2325 cpuid_checkpass(cpu_t *cpu, int pass)
2326 {
2327 	return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
2328 	    cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
2329 }
2330 
2331 int
2332 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n)
2333 {
2334 	ASSERT(cpuid_checkpass(cpu, 3));
2335 
2336 	return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
2337 }
2338 
2339 int
2340 cpuid_is_cmt(cpu_t *cpu)
2341 {
2342 	if (cpu == NULL)
2343 		cpu = CPU;
2344 
2345 	ASSERT(cpuid_checkpass(cpu, 1));
2346 
2347 	return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
2348 }
2349 
2350 /*
2351  * AMD and Intel both implement the 64-bit variant of the syscall
2352  * instruction (syscallq), so if there's -any- support for syscall,
2353  * cpuid currently says "yes, we support this".
2354  *
2355  * However, Intel decided to -not- implement the 32-bit variant of the
2356  * syscall instruction, so we provide a predicate to allow our caller
2357  * to test that subtlety here.
2358  *
2359  * XXPV	Currently, 32-bit syscall instructions don't work via the hypervisor,
2360  *	even in the case where the hardware would in fact support it.
2361  */
2362 /*ARGSUSED*/
2363 int
2364 cpuid_syscall32_insn(cpu_t *cpu)
2365 {
2366 	ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
2367 
2368 #if !defined(__xpv)
2369 	if (cpu == NULL)
2370 		cpu = CPU;
2371 
2372 	/*CSTYLED*/
2373 	{
2374 		struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2375 
2376 		if (cpi->cpi_vendor == X86_VENDOR_AMD &&
2377 		    cpi->cpi_xmaxeax >= 0x80000001 &&
2378 		    (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
2379 			return (1);
2380 	}
2381 #endif
2382 	return (0);
2383 }
2384 
2385 int
2386 cpuid_getidstr(cpu_t *cpu, char *s, size_t n)
2387 {
2388 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2389 
2390 	static const char fmt[] =
2391 	    "x86 (%s %X family %d model %d step %d clock %d MHz)";
2392 	static const char fmt_ht[] =
2393 	    "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
2394 
2395 	ASSERT(cpuid_checkpass(cpu, 1));
2396 
2397 	if (cpuid_is_cmt(cpu))
2398 		return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
2399 		    cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
2400 		    cpi->cpi_family, cpi->cpi_model,
2401 		    cpi->cpi_step, cpu->cpu_type_info.pi_clock));
2402 	return (snprintf(s, n, fmt,
2403 	    cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
2404 	    cpi->cpi_family, cpi->cpi_model,
2405 	    cpi->cpi_step, cpu->cpu_type_info.pi_clock));
2406 }
2407 
2408 const char *
2409 cpuid_getvendorstr(cpu_t *cpu)
2410 {
2411 	ASSERT(cpuid_checkpass(cpu, 1));
2412 	return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
2413 }
2414 
2415 uint_t
2416 cpuid_getvendor(cpu_t *cpu)
2417 {
2418 	ASSERT(cpuid_checkpass(cpu, 1));
2419 	return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
2420 }
2421 
2422 uint_t
2423 cpuid_getfamily(cpu_t *cpu)
2424 {
2425 	ASSERT(cpuid_checkpass(cpu, 1));
2426 	return (cpu->cpu_m.mcpu_cpi->cpi_family);
2427 }
2428 
2429 uint_t
2430 cpuid_getmodel(cpu_t *cpu)
2431 {
2432 	ASSERT(cpuid_checkpass(cpu, 1));
2433 	return (cpu->cpu_m.mcpu_cpi->cpi_model);
2434 }
2435 
2436 uint_t
2437 cpuid_get_ncpu_per_chip(cpu_t *cpu)
2438 {
2439 	ASSERT(cpuid_checkpass(cpu, 1));
2440 	return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
2441 }
2442 
2443 uint_t
2444 cpuid_get_ncore_per_chip(cpu_t *cpu)
2445 {
2446 	ASSERT(cpuid_checkpass(cpu, 1));
2447 	return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
2448 }
2449 
2450 uint_t
2451 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
2452 {
2453 	ASSERT(cpuid_checkpass(cpu, 2));
2454 	return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
2455 }
2456 
2457 id_t
2458 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
2459 {
2460 	ASSERT(cpuid_checkpass(cpu, 2));
2461 	return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
2462 }
2463 
2464 uint_t
2465 cpuid_getstep(cpu_t *cpu)
2466 {
2467 	ASSERT(cpuid_checkpass(cpu, 1));
2468 	return (cpu->cpu_m.mcpu_cpi->cpi_step);
2469 }
2470 
2471 uint_t
2472 cpuid_getsig(struct cpu *cpu)
2473 {
2474 	ASSERT(cpuid_checkpass(cpu, 1));
2475 	return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
2476 }
2477 
2478 uint32_t
2479 cpuid_getchiprev(struct cpu *cpu)
2480 {
2481 	ASSERT(cpuid_checkpass(cpu, 1));
2482 	return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
2483 }
2484 
2485 const char *
2486 cpuid_getchiprevstr(struct cpu *cpu)
2487 {
2488 	ASSERT(cpuid_checkpass(cpu, 1));
2489 	return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
2490 }
2491 
2492 uint32_t
2493 cpuid_getsockettype(struct cpu *cpu)
2494 {
2495 	ASSERT(cpuid_checkpass(cpu, 1));
2496 	return (cpu->cpu_m.mcpu_cpi->cpi_socket);
2497 }
2498 
2499 int
2500 cpuid_get_chipid(cpu_t *cpu)
2501 {
2502 	ASSERT(cpuid_checkpass(cpu, 1));
2503 
2504 	if (cpuid_is_cmt(cpu))
2505 		return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
2506 	return (cpu->cpu_id);
2507 }
2508 
2509 id_t
2510 cpuid_get_coreid(cpu_t *cpu)
2511 {
2512 	ASSERT(cpuid_checkpass(cpu, 1));
2513 	return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
2514 }
2515 
2516 int
2517 cpuid_get_pkgcoreid(cpu_t *cpu)
2518 {
2519 	ASSERT(cpuid_checkpass(cpu, 1));
2520 	return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
2521 }
2522 
2523 int
2524 cpuid_get_clogid(cpu_t *cpu)
2525 {
2526 	ASSERT(cpuid_checkpass(cpu, 1));
2527 	return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
2528 }
2529 
2530 void
2531 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits)
2532 {
2533 	struct cpuid_info *cpi;
2534 
2535 	if (cpu == NULL)
2536 		cpu = CPU;
2537 	cpi = cpu->cpu_m.mcpu_cpi;
2538 
2539 	ASSERT(cpuid_checkpass(cpu, 1));
2540 
2541 	if (pabits)
2542 		*pabits = cpi->cpi_pabits;
2543 	if (vabits)
2544 		*vabits = cpi->cpi_vabits;
2545 }
2546 
2547 /*
2548  * Returns the number of data TLB entries for a corresponding
2549  * pagesize.  If it can't be computed, or isn't known, the
2550  * routine returns zero.  If you ask about an architecturally
2551  * impossible pagesize, the routine will panic (so that the
2552  * hat implementor knows that things are inconsistent.)
2553  */
2554 uint_t
2555 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
2556 {
2557 	struct cpuid_info *cpi;
2558 	uint_t dtlb_nent = 0;
2559 
2560 	if (cpu == NULL)
2561 		cpu = CPU;
2562 	cpi = cpu->cpu_m.mcpu_cpi;
2563 
2564 	ASSERT(cpuid_checkpass(cpu, 1));
2565 
2566 	/*
2567 	 * Check the L2 TLB info
2568 	 */
2569 	if (cpi->cpi_xmaxeax >= 0x80000006) {
2570 		struct cpuid_regs *cp = &cpi->cpi_extd[6];
2571 
2572 		switch (pagesize) {
2573 
2574 		case 4 * 1024:
2575 			/*
2576 			 * All zero in the top 16 bits of the register
2577 			 * indicates a unified TLB. Size is in low 16 bits.
2578 			 */
2579 			if ((cp->cp_ebx & 0xffff0000) == 0)
2580 				dtlb_nent = cp->cp_ebx & 0x0000ffff;
2581 			else
2582 				dtlb_nent = BITX(cp->cp_ebx, 27, 16);
2583 			break;
2584 
2585 		case 2 * 1024 * 1024:
2586 			if ((cp->cp_eax & 0xffff0000) == 0)
2587 				dtlb_nent = cp->cp_eax & 0x0000ffff;
2588 			else
2589 				dtlb_nent = BITX(cp->cp_eax, 27, 16);
2590 			break;
2591 
2592 		default:
2593 			panic("unknown L2 pagesize");
2594 			/*NOTREACHED*/
2595 		}
2596 	}
2597 
2598 	if (dtlb_nent != 0)
2599 		return (dtlb_nent);
2600 
2601 	/*
2602 	 * No L2 TLB support for this size, try L1.
2603 	 */
2604 	if (cpi->cpi_xmaxeax >= 0x80000005) {
2605 		struct cpuid_regs *cp = &cpi->cpi_extd[5];
2606 
2607 		switch (pagesize) {
2608 		case 4 * 1024:
2609 			dtlb_nent = BITX(cp->cp_ebx, 23, 16);
2610 			break;
2611 		case 2 * 1024 * 1024:
2612 			dtlb_nent = BITX(cp->cp_eax, 23, 16);
2613 			break;
2614 		default:
2615 			panic("unknown L1 d-TLB pagesize");
2616 			/*NOTREACHED*/
2617 		}
2618 	}
2619 
2620 	return (dtlb_nent);
2621 }
2622 
2623 /*
2624  * Return 0 if the erratum is not present or not applicable, positive
2625  * if it is, and negative if the status of the erratum is unknown.
2626  *
2627  * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
2628  * Processors" #25759, Rev 3.57, August 2005
2629  */
2630 int
2631 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
2632 {
2633 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2634 	uint_t eax;
2635 
2636 	/*
2637 	 * Bail out if this CPU isn't an AMD CPU, or if it's
2638 	 * a legacy (32-bit) AMD CPU.
2639 	 */
2640 	if (cpi->cpi_vendor != X86_VENDOR_AMD ||
2641 	    cpi->cpi_family == 4 || cpi->cpi_family == 5 ||
2642 	    cpi->cpi_family == 6)
2643 
2644 		return (0);
2645 
2646 	eax = cpi->cpi_std[1].cp_eax;
2647 
2648 #define	SH_B0(eax)	(eax == 0xf40 || eax == 0xf50)
2649 #define	SH_B3(eax) 	(eax == 0xf51)
2650 #define	B(eax)		(SH_B0(eax) || SH_B3(eax))
2651 
2652 #define	SH_C0(eax)	(eax == 0xf48 || eax == 0xf58)
2653 
2654 #define	SH_CG(eax)	(eax == 0xf4a || eax == 0xf5a || eax == 0xf7a)
2655 #define	DH_CG(eax)	(eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0)
2656 #define	CH_CG(eax)	(eax == 0xf82 || eax == 0xfb2)
2657 #define	CG(eax)		(SH_CG(eax) || DH_CG(eax) || CH_CG(eax))
2658 
2659 #define	SH_D0(eax)	(eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70)
2660 #define	DH_D0(eax)	(eax == 0x10fc0 || eax == 0x10ff0)
2661 #define	CH_D0(eax)	(eax == 0x10f80 || eax == 0x10fb0)
2662 #define	D0(eax)		(SH_D0(eax) || DH_D0(eax) || CH_D0(eax))
2663 
2664 #define	SH_E0(eax)	(eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70)
2665 #define	JH_E1(eax)	(eax == 0x20f10)	/* JH8_E0 had 0x20f30 */
2666 #define	DH_E3(eax)	(eax == 0x20fc0 || eax == 0x20ff0)
2667 #define	SH_E4(eax)	(eax == 0x20f51 || eax == 0x20f71)
2668 #define	BH_E4(eax)	(eax == 0x20fb1)
2669 #define	SH_E5(eax)	(eax == 0x20f42)
2670 #define	DH_E6(eax)	(eax == 0x20ff2 || eax == 0x20fc2)
2671 #define	JH_E6(eax)	(eax == 0x20f12 || eax == 0x20f32)
2672 #define	EX(eax)		(SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \
2673 			    SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \
2674 			    DH_E6(eax) || JH_E6(eax))
2675 
2676 	switch (erratum) {
2677 	case 1:
2678 		return (cpi->cpi_family < 0x10);
2679 	case 51:	/* what does the asterisk mean? */
2680 		return (B(eax) || SH_C0(eax) || CG(eax));
2681 	case 52:
2682 		return (B(eax));
2683 	case 57:
2684 		return (cpi->cpi_family <= 0x10);
2685 	case 58:
2686 		return (B(eax));
2687 	case 60:
2688 		return (cpi->cpi_family <= 0x10);
2689 	case 61:
2690 	case 62:
2691 	case 63:
2692 	case 64:
2693 	case 65:
2694 	case 66:
2695 	case 68:
2696 	case 69:
2697 	case 70:
2698 	case 71:
2699 		return (B(eax));
2700 	case 72:
2701 		return (SH_B0(eax));
2702 	case 74:
2703 		return (B(eax));
2704 	case 75:
2705 		return (cpi->cpi_family < 0x10);
2706 	case 76:
2707 		return (B(eax));
2708 	case 77:
2709 		return (cpi->cpi_family <= 0x10);
2710 	case 78:
2711 		return (B(eax) || SH_C0(eax));
2712 	case 79:
2713 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
2714 	case 80:
2715 	case 81:
2716 	case 82:
2717 		return (B(eax));
2718 	case 83:
2719 		return (B(eax) || SH_C0(eax) || CG(eax));
2720 	case 85:
2721 		return (cpi->cpi_family < 0x10);
2722 	case 86:
2723 		return (SH_C0(eax) || CG(eax));
2724 	case 88:
2725 #if !defined(__amd64)
2726 		return (0);
2727 #else
2728 		return (B(eax) || SH_C0(eax));
2729 #endif
2730 	case 89:
2731 		return (cpi->cpi_family < 0x10);
2732 	case 90:
2733 		return (B(eax) || SH_C0(eax) || CG(eax));
2734 	case 91:
2735 	case 92:
2736 		return (B(eax) || SH_C0(eax));
2737 	case 93:
2738 		return (SH_C0(eax));
2739 	case 94:
2740 		return (B(eax) || SH_C0(eax) || CG(eax));
2741 	case 95:
2742 #if !defined(__amd64)
2743 		return (0);
2744 #else
2745 		return (B(eax) || SH_C0(eax));
2746 #endif
2747 	case 96:
2748 		return (B(eax) || SH_C0(eax) || CG(eax));
2749 	case 97:
2750 	case 98:
2751 		return (SH_C0(eax) || CG(eax));
2752 	case 99:
2753 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
2754 	case 100:
2755 		return (B(eax) || SH_C0(eax));
2756 	case 101:
2757 	case 103:
2758 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
2759 	case 104:
2760 		return (SH_C0(eax) || CG(eax) || D0(eax));
2761 	case 105:
2762 	case 106:
2763 	case 107:
2764 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
2765 	case 108:
2766 		return (DH_CG(eax));
2767 	case 109:
2768 		return (SH_C0(eax) || CG(eax) || D0(eax));
2769 	case 110:
2770 		return (D0(eax) || EX(eax));
2771 	case 111:
2772 		return (CG(eax));
2773 	case 112:
2774 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
2775 	case 113:
2776 		return (eax == 0x20fc0);
2777 	case 114:
2778 		return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
2779 	case 115:
2780 		return (SH_E0(eax) || JH_E1(eax));
2781 	case 116:
2782 		return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
2783 	case 117:
2784 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
2785 	case 118:
2786 		return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) ||
2787 		    JH_E6(eax));
2788 	case 121:
2789 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
2790 	case 122:
2791 		return (cpi->cpi_family < 0x10);
2792 	case 123:
2793 		return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax));
2794 	case 131:
2795 		return (cpi->cpi_family < 0x10);
2796 	case 6336786:
2797 		/*
2798 		 * Test for AdvPowerMgmtInfo.TscPStateInvariant
2799 		 * if this is a K8 family or newer processor
2800 		 */
2801 		if (CPI_FAMILY(cpi) == 0xf) {
2802 			struct cpuid_regs regs;
2803 			regs.cp_eax = 0x80000007;
2804 			(void) __cpuid_insn(&regs);
2805 			return (!(regs.cp_edx & 0x100));
2806 		}
2807 		return (0);
2808 	case 6323525:
2809 		return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) |
2810 		    (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40);
2811 
2812 	default:
2813 		return (-1);
2814 	}
2815 }
2816 
2817 static const char assoc_str[] = "associativity";
2818 static const char line_str[] = "line-size";
2819 static const char size_str[] = "size";
2820 
2821 static void
2822 add_cache_prop(dev_info_t *devi, const char *label, const char *type,
2823     uint32_t val)
2824 {
2825 	char buf[128];
2826 
2827 	/*
2828 	 * ndi_prop_update_int() is used because it is desirable for
2829 	 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
2830 	 */
2831 	if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
2832 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
2833 }
2834 
2835 /*
2836  * Intel-style cache/tlb description
2837  *
2838  * Standard cpuid level 2 gives a randomly ordered
2839  * selection of tags that index into a table that describes
2840  * cache and tlb properties.
2841  */
2842 
2843 static const char l1_icache_str[] = "l1-icache";
2844 static const char l1_dcache_str[] = "l1-dcache";
2845 static const char l2_cache_str[] = "l2-cache";
2846 static const char l3_cache_str[] = "l3-cache";
2847 static const char itlb4k_str[] = "itlb-4K";
2848 static const char dtlb4k_str[] = "dtlb-4K";
2849 static const char itlb4M_str[] = "itlb-4M";
2850 static const char dtlb4M_str[] = "dtlb-4M";
2851 static const char itlb424_str[] = "itlb-4K-2M-4M";
2852 static const char dtlb44_str[] = "dtlb-4K-4M";
2853 static const char sl1_dcache_str[] = "sectored-l1-dcache";
2854 static const char sl2_cache_str[] = "sectored-l2-cache";
2855 static const char itrace_str[] = "itrace-cache";
2856 static const char sl3_cache_str[] = "sectored-l3-cache";
2857 
2858 static const struct cachetab {
2859 	uint8_t 	ct_code;
2860 	uint8_t		ct_assoc;
2861 	uint16_t 	ct_line_size;
2862 	size_t		ct_size;
2863 	const char	*ct_label;
2864 } intel_ctab[] = {
2865 	/* maintain descending order! */
2866 	{ 0xb4, 4, 0, 256, dtlb4k_str },
2867 	{ 0xb3, 4, 0, 128, dtlb4k_str },
2868 	{ 0xb0, 4, 0, 128, itlb4k_str },
2869 	{ 0x87, 8, 64, 1024*1024, l2_cache_str},
2870 	{ 0x86, 4, 64, 512*1024, l2_cache_str},
2871 	{ 0x85, 8, 32, 2*1024*1024, l2_cache_str},
2872 	{ 0x84, 8, 32, 1024*1024, l2_cache_str},
2873 	{ 0x83, 8, 32, 512*1024, l2_cache_str},
2874 	{ 0x82, 8, 32, 256*1024, l2_cache_str},
2875 	{ 0x7f, 2, 64, 512*1024, l2_cache_str},
2876 	{ 0x7d, 8, 64, 2*1024*1024, sl2_cache_str},
2877 	{ 0x7c, 8, 64, 1024*1024, sl2_cache_str},
2878 	{ 0x7b, 8, 64, 512*1024, sl2_cache_str},
2879 	{ 0x7a, 8, 64, 256*1024, sl2_cache_str},
2880 	{ 0x79, 8, 64, 128*1024, sl2_cache_str},
2881 	{ 0x78, 8, 64, 1024*1024, l2_cache_str},
2882 	{ 0x73, 8, 0, 64*1024, itrace_str},
2883 	{ 0x72, 8, 0, 32*1024, itrace_str},
2884 	{ 0x71, 8, 0, 16*1024, itrace_str},
2885 	{ 0x70, 8, 0, 12*1024, itrace_str},
2886 	{ 0x68, 4, 64, 32*1024, sl1_dcache_str},
2887 	{ 0x67, 4, 64, 16*1024, sl1_dcache_str},
2888 	{ 0x66, 4, 64, 8*1024, sl1_dcache_str},
2889 	{ 0x60, 8, 64, 16*1024, sl1_dcache_str},
2890 	{ 0x5d, 0, 0, 256, dtlb44_str},
2891 	{ 0x5c, 0, 0, 128, dtlb44_str},
2892 	{ 0x5b, 0, 0, 64, dtlb44_str},
2893 	{ 0x52, 0, 0, 256, itlb424_str},
2894 	{ 0x51, 0, 0, 128, itlb424_str},
2895 	{ 0x50, 0, 0, 64, itlb424_str},
2896 	{ 0x4d, 16, 64, 16*1024*1024, l3_cache_str},
2897 	{ 0x4c, 12, 64, 12*1024*1024, l3_cache_str},
2898 	{ 0x4b, 16, 64, 8*1024*1024, l3_cache_str},
2899 	{ 0x4a, 12, 64, 6*1024*1024, l3_cache_str},
2900 	{ 0x49, 16, 64, 4*1024*1024, l3_cache_str},
2901 	{ 0x47, 8, 64, 8*1024*1024, l3_cache_str},
2902 	{ 0x46, 4, 64, 4*1024*1024, l3_cache_str},
2903 	{ 0x45, 4, 32, 2*1024*1024, l2_cache_str},
2904 	{ 0x44, 4, 32, 1024*1024, l2_cache_str},
2905 	{ 0x43, 4, 32, 512*1024, l2_cache_str},
2906 	{ 0x42, 4, 32, 256*1024, l2_cache_str},
2907 	{ 0x41, 4, 32, 128*1024, l2_cache_str},
2908 	{ 0x3e, 4, 64, 512*1024, sl2_cache_str},
2909 	{ 0x3d, 6, 64, 384*1024, sl2_cache_str},
2910 	{ 0x3c, 4, 64, 256*1024, sl2_cache_str},
2911 	{ 0x3b, 2, 64, 128*1024, sl2_cache_str},
2912 	{ 0x3a, 6, 64, 192*1024, sl2_cache_str},
2913 	{ 0x39, 4, 64, 128*1024, sl2_cache_str},
2914 	{ 0x30, 8, 64, 32*1024, l1_icache_str},
2915 	{ 0x2c, 8, 64, 32*1024, l1_dcache_str},
2916 	{ 0x29, 8, 64, 4096*1024, sl3_cache_str},
2917 	{ 0x25, 8, 64, 2048*1024, sl3_cache_str},
2918 	{ 0x23, 8, 64, 1024*1024, sl3_cache_str},
2919 	{ 0x22, 4, 64, 512*1024, sl3_cache_str},
2920 	{ 0x0c, 4, 32, 16*1024, l1_dcache_str},
2921 	{ 0x0b, 4, 0, 4, itlb4M_str},
2922 	{ 0x0a, 2, 32, 8*1024, l1_dcache_str},
2923 	{ 0x08, 4, 32, 16*1024, l1_icache_str},
2924 	{ 0x06, 4, 32, 8*1024, l1_icache_str},
2925 	{ 0x04, 4, 0, 8, dtlb4M_str},
2926 	{ 0x03, 4, 0, 64, dtlb4k_str},
2927 	{ 0x02, 4, 0, 2, itlb4M_str},
2928 	{ 0x01, 4, 0, 32, itlb4k_str},
2929 	{ 0 }
2930 };
2931 
2932 static const struct cachetab cyrix_ctab[] = {
2933 	{ 0x70, 4, 0, 32, "tlb-4K" },
2934 	{ 0x80, 4, 16, 16*1024, "l1-cache" },
2935 	{ 0 }
2936 };
2937 
2938 /*
2939  * Search a cache table for a matching entry
2940  */
2941 static const struct cachetab *
2942 find_cacheent(const struct cachetab *ct, uint_t code)
2943 {
2944 	if (code != 0) {
2945 		for (; ct->ct_code != 0; ct++)
2946 			if (ct->ct_code <= code)
2947 				break;
2948 		if (ct->ct_code == code)
2949 			return (ct);
2950 	}
2951 	return (NULL);
2952 }
2953 
2954 /*
2955  * Populate cachetab entry with L2 or L3 cache-information using
2956  * cpuid function 4. This function is called from intel_walk_cacheinfo()
2957  * when descriptor 0x49 is encountered. It returns 0 if no such cache
2958  * information is found.
2959  */
2960 static int
2961 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi)
2962 {
2963 	uint32_t level, i;
2964 	int ret = 0;
2965 
2966 	for (i = 0; i < cpi->cpi_std_4_size; i++) {
2967 		level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
2968 
2969 		if (level == 2 || level == 3) {
2970 			ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
2971 			ct->ct_line_size =
2972 			    CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
2973 			ct->ct_size = ct->ct_assoc *
2974 			    (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
2975 			    ct->ct_line_size *
2976 			    (cpi->cpi_std_4[i]->cp_ecx + 1);
2977 
2978 			if (level == 2) {
2979 				ct->ct_label = l2_cache_str;
2980 			} else if (level == 3) {
2981 				ct->ct_label = l3_cache_str;
2982 			}
2983 			ret = 1;
2984 		}
2985 	}
2986 
2987 	return (ret);
2988 }
2989 
2990 /*
2991  * Walk the cacheinfo descriptor, applying 'func' to every valid element
2992  * The walk is terminated if the walker returns non-zero.
2993  */
2994 static void
2995 intel_walk_cacheinfo(struct cpuid_info *cpi,
2996     void *arg, int (*func)(void *, const struct cachetab *))
2997 {
2998 	const struct cachetab *ct;
2999 	struct cachetab des_49_ct;
3000 	uint8_t *dp;
3001 	int i;
3002 
3003 	if ((dp = cpi->cpi_cacheinfo) == NULL)
3004 		return;
3005 	for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3006 		/*
3007 		 * For overloaded descriptor 0x49 we use cpuid function 4
3008 		 * if supported by the current processor, to create
3009 		 * cache information.
3010 		 */
3011 		if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
3012 		    intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
3013 				ct = &des_49_ct;
3014 		} else {
3015 			if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
3016 				continue;
3017 			}
3018 		}
3019 
3020 		if (func(arg, ct) != 0) {
3021 			break;
3022 		}
3023 	}
3024 }
3025 
3026 /*
3027  * (Like the Intel one, except for Cyrix CPUs)
3028  */
3029 static void
3030 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
3031     void *arg, int (*func)(void *, const struct cachetab *))
3032 {
3033 	const struct cachetab *ct;
3034 	uint8_t *dp;
3035 	int i;
3036 
3037 	if ((dp = cpi->cpi_cacheinfo) == NULL)
3038 		return;
3039 	for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3040 		/*
3041 		 * Search Cyrix-specific descriptor table first ..
3042 		 */
3043 		if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
3044 			if (func(arg, ct) != 0)
3045 				break;
3046 			continue;
3047 		}
3048 		/*
3049 		 * .. else fall back to the Intel one
3050 		 */
3051 		if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
3052 			if (func(arg, ct) != 0)
3053 				break;
3054 			continue;
3055 		}
3056 	}
3057 }
3058 
3059 /*
3060  * A cacheinfo walker that adds associativity, line-size, and size properties
3061  * to the devinfo node it is passed as an argument.
3062  */
3063 static int
3064 add_cacheent_props(void *arg, const struct cachetab *ct)
3065 {
3066 	dev_info_t *devi = arg;
3067 
3068 	add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
3069 	if (ct->ct_line_size != 0)
3070 		add_cache_prop(devi, ct->ct_label, line_str,
3071 		    ct->ct_line_size);
3072 	add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
3073 	return (0);
3074 }
3075 
3076 
3077 static const char fully_assoc[] = "fully-associative?";
3078 
3079 /*
3080  * AMD style cache/tlb description
3081  *
3082  * Extended functions 5 and 6 directly describe properties of
3083  * tlbs and various cache levels.
3084  */
3085 static void
3086 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc)
3087 {
3088 	switch (assoc) {
3089 	case 0:	/* reserved; ignore */
3090 		break;
3091 	default:
3092 		add_cache_prop(devi, label, assoc_str, assoc);
3093 		break;
3094 	case 0xff:
3095 		add_cache_prop(devi, label, fully_assoc, 1);
3096 		break;
3097 	}
3098 }
3099 
3100 static void
3101 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
3102 {
3103 	if (size == 0)
3104 		return;
3105 	add_cache_prop(devi, label, size_str, size);
3106 	add_amd_assoc(devi, label, assoc);
3107 }
3108 
3109 static void
3110 add_amd_cache(dev_info_t *devi, const char *label,
3111     uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
3112 {
3113 	if (size == 0 || line_size == 0)
3114 		return;
3115 	add_amd_assoc(devi, label, assoc);
3116 	/*
3117 	 * Most AMD parts have a sectored cache. Multiple cache lines are
3118 	 * associated with each tag. A sector consists of all cache lines
3119 	 * associated with a tag. For example, the AMD K6-III has a sector
3120 	 * size of 2 cache lines per tag.
3121 	 */
3122 	if (lines_per_tag != 0)
3123 		add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
3124 	add_cache_prop(devi, label, line_str, line_size);
3125 	add_cache_prop(devi, label, size_str, size * 1024);
3126 }
3127 
3128 static void
3129 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc)
3130 {
3131 	switch (assoc) {
3132 	case 0:	/* off */
3133 		break;
3134 	case 1:
3135 	case 2:
3136 	case 4:
3137 		add_cache_prop(devi, label, assoc_str, assoc);
3138 		break;
3139 	case 6:
3140 		add_cache_prop(devi, label, assoc_str, 8);
3141 		break;
3142 	case 8:
3143 		add_cache_prop(devi, label, assoc_str, 16);
3144 		break;
3145 	case 0xf:
3146 		add_cache_prop(devi, label, fully_assoc, 1);
3147 		break;
3148 	default: /* reserved; ignore */
3149 		break;
3150 	}
3151 }
3152 
3153 static void
3154 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
3155 {
3156 	if (size == 0 || assoc == 0)
3157 		return;
3158 	add_amd_l2_assoc(devi, label, assoc);
3159 	add_cache_prop(devi, label, size_str, size);
3160 }
3161 
3162 static void
3163 add_amd_l2_cache(dev_info_t *devi, const char *label,
3164     uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
3165 {
3166 	if (size == 0 || assoc == 0 || line_size == 0)
3167 		return;
3168 	add_amd_l2_assoc(devi, label, assoc);
3169 	if (lines_per_tag != 0)
3170 		add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
3171 	add_cache_prop(devi, label, line_str, line_size);
3172 	add_cache_prop(devi, label, size_str, size * 1024);
3173 }
3174 
3175 static void
3176 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi)
3177 {
3178 	struct cpuid_regs *cp;
3179 
3180 	if (cpi->cpi_xmaxeax < 0x80000005)
3181 		return;
3182 	cp = &cpi->cpi_extd[5];
3183 
3184 	/*
3185 	 * 4M/2M L1 TLB configuration
3186 	 *
3187 	 * We report the size for 2M pages because AMD uses two
3188 	 * TLB entries for one 4M page.
3189 	 */
3190 	add_amd_tlb(devi, "dtlb-2M",
3191 	    BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
3192 	add_amd_tlb(devi, "itlb-2M",
3193 	    BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
3194 
3195 	/*
3196 	 * 4K L1 TLB configuration
3197 	 */
3198 
3199 	switch (cpi->cpi_vendor) {
3200 		uint_t nentries;
3201 	case X86_VENDOR_TM:
3202 		if (cpi->cpi_family >= 5) {
3203 			/*
3204 			 * Crusoe processors have 256 TLB entries, but
3205 			 * cpuid data format constrains them to only
3206 			 * reporting 255 of them.
3207 			 */
3208 			if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
3209 				nentries = 256;
3210 			/*
3211 			 * Crusoe processors also have a unified TLB
3212 			 */
3213 			add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
3214 			    nentries);
3215 			break;
3216 		}
3217 		/*FALLTHROUGH*/
3218 	default:
3219 		add_amd_tlb(devi, itlb4k_str,
3220 		    BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
3221 		add_amd_tlb(devi, dtlb4k_str,
3222 		    BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
3223 		break;
3224 	}
3225 
3226 	/*
3227 	 * data L1 cache configuration
3228 	 */
3229 
3230 	add_amd_cache(devi, l1_dcache_str,
3231 	    BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
3232 	    BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
3233 
3234 	/*
3235 	 * code L1 cache configuration
3236 	 */
3237 
3238 	add_amd_cache(devi, l1_icache_str,
3239 	    BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
3240 	    BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
3241 
3242 	if (cpi->cpi_xmaxeax < 0x80000006)
3243 		return;
3244 	cp = &cpi->cpi_extd[6];
3245 
3246 	/* Check for a unified L2 TLB for large pages */
3247 
3248 	if (BITX(cp->cp_eax, 31, 16) == 0)
3249 		add_amd_l2_tlb(devi, "l2-tlb-2M",
3250 		    BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
3251 	else {
3252 		add_amd_l2_tlb(devi, "l2-dtlb-2M",
3253 		    BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
3254 		add_amd_l2_tlb(devi, "l2-itlb-2M",
3255 		    BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
3256 	}
3257 
3258 	/* Check for a unified L2 TLB for 4K pages */
3259 
3260 	if (BITX(cp->cp_ebx, 31, 16) == 0) {
3261 		add_amd_l2_tlb(devi, "l2-tlb-4K",
3262 		    BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
3263 	} else {
3264 		add_amd_l2_tlb(devi, "l2-dtlb-4K",
3265 		    BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
3266 		add_amd_l2_tlb(devi, "l2-itlb-4K",
3267 		    BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
3268 	}
3269 
3270 	add_amd_l2_cache(devi, l2_cache_str,
3271 	    BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
3272 	    BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
3273 }
3274 
3275 /*
3276  * There are two basic ways that the x86 world describes it cache
3277  * and tlb architecture - Intel's way and AMD's way.
3278  *
3279  * Return which flavor of cache architecture we should use
3280  */
3281 static int
3282 x86_which_cacheinfo(struct cpuid_info *cpi)
3283 {
3284 	switch (cpi->cpi_vendor) {
3285 	case X86_VENDOR_Intel:
3286 		if (cpi->cpi_maxeax >= 2)
3287 			return (X86_VENDOR_Intel);
3288 		break;
3289 	case X86_VENDOR_AMD:
3290 		/*
3291 		 * The K5 model 1 was the first part from AMD that reported
3292 		 * cache sizes via extended cpuid functions.
3293 		 */
3294 		if (cpi->cpi_family > 5 ||
3295 		    (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
3296 			return (X86_VENDOR_AMD);
3297 		break;
3298 	case X86_VENDOR_TM:
3299 		if (cpi->cpi_family >= 5)
3300 			return (X86_VENDOR_AMD);
3301 		/*FALLTHROUGH*/
3302 	default:
3303 		/*
3304 		 * If they have extended CPU data for 0x80000005
3305 		 * then we assume they have AMD-format cache
3306 		 * information.
3307 		 *
3308 		 * If not, and the vendor happens to be Cyrix,
3309 		 * then try our-Cyrix specific handler.
3310 		 *
3311 		 * If we're not Cyrix, then assume we're using Intel's
3312 		 * table-driven format instead.
3313 		 */
3314 		if (cpi->cpi_xmaxeax >= 0x80000005)
3315 			return (X86_VENDOR_AMD);
3316 		else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
3317 			return (X86_VENDOR_Cyrix);
3318 		else if (cpi->cpi_maxeax >= 2)
3319 			return (X86_VENDOR_Intel);
3320 		break;
3321 	}
3322 	return (-1);
3323 }
3324 
3325 /*
3326  * create a node for the given cpu under the prom root node.
3327  * Also, create a cpu node in the device tree.
3328  */
3329 static dev_info_t *cpu_nex_devi = NULL;
3330 static kmutex_t cpu_node_lock;
3331 
3332 /*
3333  * Called from post_startup() and mp_startup()
3334  */
3335 void
3336 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi)
3337 {
3338 	dev_info_t *cpu_devi;
3339 	int create;
3340 
3341 	mutex_enter(&cpu_node_lock);
3342 
3343 	/*
3344 	 * create a nexus node for all cpus identified as 'cpu_id' under
3345 	 * the root node.
3346 	 */
3347 	if (cpu_nex_devi == NULL) {
3348 		if (ndi_devi_alloc(ddi_root_node(), "cpus",
3349 		    (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) {
3350 			mutex_exit(&cpu_node_lock);
3351 			return;
3352 		}
3353 		(void) ndi_devi_online(cpu_nex_devi, 0);
3354 	}
3355 
3356 	/*
3357 	 * create a child node for cpu identified as 'cpu_id'
3358 	 */
3359 	cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID,
3360 	    cpu_id);
3361 	if (cpu_devi == NULL) {
3362 		mutex_exit(&cpu_node_lock);
3363 		return;
3364 	}
3365 
3366 	/* device_type */
3367 
3368 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
3369 	    "device_type", "cpu");
3370 
3371 	/* reg */
3372 
3373 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3374 	    "reg", cpu_id);
3375 
3376 	/* cpu-mhz, and clock-frequency */
3377 
3378 	if (cpu_freq > 0) {
3379 		long long mul;
3380 
3381 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3382 		    "cpu-mhz", cpu_freq);
3383 
3384 		if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
3385 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3386 			    "clock-frequency", (int)mul);
3387 	}
3388 
3389 	(void) ndi_devi_online(cpu_devi, 0);
3390 
3391 	if ((x86_feature & X86_CPUID) == 0) {
3392 		mutex_exit(&cpu_node_lock);
3393 		return;
3394 	}
3395 
3396 	/* vendor-id */
3397 
3398 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
3399 	    "vendor-id", cpi->cpi_vendorstr);
3400 
3401 	if (cpi->cpi_maxeax == 0) {
3402 		mutex_exit(&cpu_node_lock);
3403 		return;
3404 	}
3405 
3406 	/*
3407 	 * family, model, and step
3408 	 */
3409 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3410 	    "family", CPI_FAMILY(cpi));
3411 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3412 	    "cpu-model", CPI_MODEL(cpi));
3413 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3414 	    "stepping-id", CPI_STEP(cpi));
3415 
3416 	/* type */
3417 
3418 	switch (cpi->cpi_vendor) {
3419 	case X86_VENDOR_Intel:
3420 		create = 1;
3421 		break;
3422 	default:
3423 		create = 0;
3424 		break;
3425 	}
3426 	if (create)
3427 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3428 		    "type", CPI_TYPE(cpi));
3429 
3430 	/* ext-family */
3431 
3432 	switch (cpi->cpi_vendor) {
3433 	case X86_VENDOR_Intel:
3434 	case X86_VENDOR_AMD:
3435 		create = cpi->cpi_family >= 0xf;
3436 		break;
3437 	default:
3438 		create = 0;
3439 		break;
3440 	}
3441 	if (create)
3442 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3443 		    "ext-family", CPI_FAMILY_XTD(cpi));
3444 
3445 	/* ext-model */
3446 
3447 	switch (cpi->cpi_vendor) {
3448 	case X86_VENDOR_Intel:
3449 		create = CPI_MODEL(cpi) == 0xf;
3450 		break;
3451 	case X86_VENDOR_AMD:
3452 		create = CPI_FAMILY(cpi) == 0xf;
3453 		break;
3454 	default:
3455 		create = 0;
3456 		break;
3457 	}
3458 	if (create)
3459 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3460 		    "ext-model", CPI_MODEL_XTD(cpi));
3461 
3462 	/* generation */
3463 
3464 	switch (cpi->cpi_vendor) {
3465 	case X86_VENDOR_AMD:
3466 		/*
3467 		 * AMD K5 model 1 was the first part to support this
3468 		 */
3469 		create = cpi->cpi_xmaxeax >= 0x80000001;
3470 		break;
3471 	default:
3472 		create = 0;
3473 		break;
3474 	}
3475 	if (create)
3476 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3477 		    "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
3478 
3479 	/* brand-id */
3480 
3481 	switch (cpi->cpi_vendor) {
3482 	case X86_VENDOR_Intel:
3483 		/*
3484 		 * brand id first appeared on Pentium III Xeon model 8,
3485 		 * and Celeron model 8 processors and Opteron
3486 		 */
3487 		create = cpi->cpi_family > 6 ||
3488 		    (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
3489 		break;
3490 	case X86_VENDOR_AMD:
3491 		create = cpi->cpi_family >= 0xf;
3492 		break;
3493 	default:
3494 		create = 0;
3495 		break;
3496 	}
3497 	if (create && cpi->cpi_brandid != 0) {
3498 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3499 		    "brand-id", cpi->cpi_brandid);
3500 	}
3501 
3502 	/* chunks, and apic-id */
3503 
3504 	switch (cpi->cpi_vendor) {
3505 		/*
3506 		 * first available on Pentium IV and Opteron (K8)
3507 		 */
3508 	case X86_VENDOR_Intel:
3509 		create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
3510 		break;
3511 	case X86_VENDOR_AMD:
3512 		create = cpi->cpi_family >= 0xf;
3513 		break;
3514 	default:
3515 		create = 0;
3516 		break;
3517 	}
3518 	if (create) {
3519 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3520 		    "chunks", CPI_CHUNKS(cpi));
3521 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3522 		    "apic-id", CPI_APIC_ID(cpi));
3523 		if (cpi->cpi_chipid >= 0) {
3524 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3525 			    "chip#", cpi->cpi_chipid);
3526 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3527 			    "clog#", cpi->cpi_clogid);
3528 		}
3529 	}
3530 
3531 	/* cpuid-features */
3532 
3533 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3534 	    "cpuid-features", CPI_FEATURES_EDX(cpi));
3535 
3536 
3537 	/* cpuid-features-ecx */
3538 
3539 	switch (cpi->cpi_vendor) {
3540 	case X86_VENDOR_Intel:
3541 		create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
3542 		break;
3543 	default:
3544 		create = 0;
3545 		break;
3546 	}
3547 	if (create)
3548 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3549 		    "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
3550 
3551 	/* ext-cpuid-features */
3552 
3553 	switch (cpi->cpi_vendor) {
3554 	case X86_VENDOR_Intel:
3555 	case X86_VENDOR_AMD:
3556 	case X86_VENDOR_Cyrix:
3557 	case X86_VENDOR_TM:
3558 	case X86_VENDOR_Centaur:
3559 		create = cpi->cpi_xmaxeax >= 0x80000001;
3560 		break;
3561 	default:
3562 		create = 0;
3563 		break;
3564 	}
3565 	if (create) {
3566 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3567 		    "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
3568 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
3569 		    "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
3570 	}
3571 
3572 	/*
3573 	 * Brand String first appeared in Intel Pentium IV, AMD K5
3574 	 * model 1, and Cyrix GXm.  On earlier models we try and
3575 	 * simulate something similar .. so this string should always
3576 	 * same -something- about the processor, however lame.
3577 	 */
3578 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
3579 	    "brand-string", cpi->cpi_brandstr);
3580 
3581 	/*
3582 	 * Finally, cache and tlb information
3583 	 */
3584 	switch (x86_which_cacheinfo(cpi)) {
3585 	case X86_VENDOR_Intel:
3586 		intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
3587 		break;
3588 	case X86_VENDOR_Cyrix:
3589 		cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
3590 		break;
3591 	case X86_VENDOR_AMD:
3592 		amd_cache_info(cpi, cpu_devi);
3593 		break;
3594 	default:
3595 		break;
3596 	}
3597 
3598 	mutex_exit(&cpu_node_lock);
3599 }
3600 
3601 struct l2info {
3602 	int *l2i_csz;
3603 	int *l2i_lsz;
3604 	int *l2i_assoc;
3605 	int l2i_ret;
3606 };
3607 
3608 /*
3609  * A cacheinfo walker that fetches the size, line-size and associativity
3610  * of the L2 cache
3611  */
3612 static int
3613 intel_l2cinfo(void *arg, const struct cachetab *ct)
3614 {
3615 	struct l2info *l2i = arg;
3616 	int *ip;
3617 
3618 	if (ct->ct_label != l2_cache_str &&
3619 	    ct->ct_label != sl2_cache_str)
3620 		return (0);	/* not an L2 -- keep walking */
3621 
3622 	if ((ip = l2i->l2i_csz) != NULL)
3623 		*ip = ct->ct_size;
3624 	if ((ip = l2i->l2i_lsz) != NULL)
3625 		*ip = ct->ct_line_size;
3626 	if ((ip = l2i->l2i_assoc) != NULL)
3627 		*ip = ct->ct_assoc;
3628 	l2i->l2i_ret = ct->ct_size;
3629 	return (1);		/* was an L2 -- terminate walk */
3630 }
3631 
3632 /*
3633  * AMD L2/L3 Cache and TLB Associativity Field Definition:
3634  *
3635  *	Unlike the associativity for the L1 cache and tlb where the 8 bit
3636  *	value is the associativity, the associativity for the L2 cache and
3637  *	tlb is encoded in the following table. The 4 bit L2 value serves as
3638  *	an index into the amd_afd[] array to determine the associativity.
3639  *	-1 is undefined. 0 is fully associative.
3640  */
3641 
3642 static int amd_afd[] =
3643 	{-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
3644 
3645 static void
3646 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i)
3647 {
3648 	struct cpuid_regs *cp;
3649 	uint_t size, assoc;
3650 	int i;
3651 	int *ip;
3652 
3653 	if (cpi->cpi_xmaxeax < 0x80000006)
3654 		return;
3655 	cp = &cpi->cpi_extd[6];
3656 
3657 	if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
3658 	    (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
3659 		uint_t cachesz = size * 1024;
3660 		assoc = amd_afd[i];
3661 
3662 		ASSERT(assoc != -1);
3663 
3664 		if ((ip = l2i->l2i_csz) != NULL)
3665 			*ip = cachesz;
3666 		if ((ip = l2i->l2i_lsz) != NULL)
3667 			*ip = BITX(cp->cp_ecx, 7, 0);
3668 		if ((ip = l2i->l2i_assoc) != NULL)
3669 			*ip = assoc;
3670 		l2i->l2i_ret = cachesz;
3671 	}
3672 }
3673 
3674 int
3675 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
3676 {
3677 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3678 	struct l2info __l2info, *l2i = &__l2info;
3679 
3680 	l2i->l2i_csz = csz;
3681 	l2i->l2i_lsz = lsz;
3682 	l2i->l2i_assoc = assoc;
3683 	l2i->l2i_ret = -1;
3684 
3685 	switch (x86_which_cacheinfo(cpi)) {
3686 	case X86_VENDOR_Intel:
3687 		intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
3688 		break;
3689 	case X86_VENDOR_Cyrix:
3690 		cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
3691 		break;
3692 	case X86_VENDOR_AMD:
3693 		amd_l2cacheinfo(cpi, l2i);
3694 		break;
3695 	default:
3696 		break;
3697 	}
3698 	return (l2i->l2i_ret);
3699 }
3700 
3701 #if !defined(__xpv)
3702 
3703 uint32_t *
3704 cpuid_mwait_alloc(cpu_t *cpu)
3705 {
3706 	uint32_t	*ret;
3707 	size_t		mwait_size;
3708 
3709 	ASSERT(cpuid_checkpass(cpu, 2));
3710 
3711 	mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
3712 	if (mwait_size == 0)
3713 		return (NULL);
3714 
3715 	/*
3716 	 * kmem_alloc() returns cache line size aligned data for mwait_size
3717 	 * allocations.  mwait_size is currently cache line sized.  Neither
3718 	 * of these implementation details are guarantied to be true in the
3719 	 * future.
3720 	 *
3721 	 * First try allocating mwait_size as kmem_alloc() currently returns
3722 	 * correctly aligned memory.  If kmem_alloc() does not return
3723 	 * mwait_size aligned memory, then use mwait_size ROUNDUP.
3724 	 *
3725 	 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
3726 	 * decide to free this memory.
3727 	 */
3728 	ret = kmem_zalloc(mwait_size, KM_SLEEP);
3729 	if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
3730 		cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
3731 		cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
3732 		*ret = MWAIT_RUNNING;
3733 		return (ret);
3734 	} else {
3735 		kmem_free(ret, mwait_size);
3736 		ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
3737 		cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
3738 		cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
3739 		ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
3740 		*ret = MWAIT_RUNNING;
3741 		return (ret);
3742 	}
3743 }
3744 
3745 void
3746 cpuid_mwait_free(cpu_t *cpu)
3747 {
3748 	ASSERT(cpuid_checkpass(cpu, 2));
3749 
3750 	if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
3751 	    cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
3752 		kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
3753 		    cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
3754 	}
3755 
3756 	cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
3757 	cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
3758 }
3759 
3760 void
3761 patch_tsc_read(int flag)
3762 {
3763 	size_t cnt;
3764 	switch (flag) {
3765 	case X86_NO_TSC:
3766 		cnt = &_no_rdtsc_end - &_no_rdtsc_start;
3767 		(void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt);
3768 		break;
3769 	case X86_HAVE_TSCP:
3770 		cnt = &_tscp_end - &_tscp_start;
3771 		(void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt);
3772 		break;
3773 	case X86_TSC_MFENCE:
3774 		cnt = &_tsc_mfence_end - &_tsc_mfence_start;
3775 		(void) memcpy((void *)tsc_read,
3776 		    (void *)&_tsc_mfence_start, cnt);
3777 		break;
3778 	default:
3779 		break;
3780 	}
3781 }
3782 
3783 #endif	/* !__xpv */
3784