xref: /titanic_51/usr/src/uts/i86pc/ml/ia32.il (revision 9697ae98dd505d4c445dd4336b4defa36e722f79)
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#pragma ident	"%Z%%M%	%I%	%E% SMI"
28
29/
30/ Inline functions specific to the i86pc kernel running on bare metal.
31/
32
33/
34/ return value of cr3 register
35/
36	.inline	getcr3,0
37	movl	%cr3, %eax
38	.end
39
40/
41/ reload cr3 register with its current value
42/
43	.inline	reload_cr3,0
44	movl	%cr3, %eax
45	movl	%eax, %cr3
46	.end
47
48/*
49 * Put a new value into cr3 (page table base register
50 *	void setcr3(void *value)
51 */
52	.inline	setcr3,4
53	movl	(%esp), %eax
54	movl	%eax, %cr3
55	.end
56
57/
58/ enable interrupts
59/
60	.inline	sti,0
61	sti
62	.end
63
64/
65/ disable interrupts
66/
67	.inline cli,0
68	cli
69	.end
70
71/
72/ disable interrupts and return value describing if interrupts were enabled
73/
74	.inline	clear_int_flag,0
75	pushfl
76	cli
77	popl	%eax
78	.end
79
80	.inline	intr_clear,0
81	pushfl
82	cli
83	popl	%eax
84	.end
85
86/
87/ return the flags register
88/
89	.inline getflags,0
90	pushfl
91	popl	%eax
92	.end
93
94/
95/ restore interrupt enable flag to value returned from 'clear_int_flag' above
96/
97	.inline restore_int_flag,4
98	testl	$0x200, (%esp)
99	jz	1f
100	sti
1011:
102	.end
103
104	.inline intr_restore,4
105	testl	$0x200, (%esp)
106	jz	1f
107	sti
1081:
109	.end
110
111/
112/ in and out
113/
114	.inline	inb,4
115	movl	(%esp), %edx
116	xorl    %eax, %eax
117	inb	(%dx)
118	.end
119
120	.inline	inw,4
121	movl	(%esp), %edx
122	xorl    %eax, %eax
123	inw	(%dx)
124	.end
125
126	.inline	inl,4
127	movl	(%esp), %edx
128	xorl    %eax, %eax
129	inl	(%dx)
130	.end
131
132	.inline	outb,8
133	movl	(%esp), %edx
134	movl    4(%esp), %eax
135	outb	(%dx)
136	.end
137
138	.inline	outw,8
139	movl	(%esp), %edx
140	movl    4(%esp), %eax
141	outw	(%dx)
142	.end
143
144	.inline	outl,8
145	movl	(%esp), %edx
146	movl    4(%esp), %eax
147	outl	(%dx)
148	.end
149
150/*
151 * Invalidate TLB translation to 1 page.
152 *	void mmu_tlbflush_entry(void *addr)
153 */
154	.inline	mmu_tlbflush_entry,4
155	movl	(%esp), %eax
156	invlpg	(%eax)
157	.end
158
159/*
160 * Call the halt instruction. This will put the CPU to sleep until
161 * it is again awoken via an interrupt.
162 * This function should be called with interrupts already disabled
163 * for the CPU.
164 * Note that "sti" will only enable interrupts at the end of the
165 * subsequent instruction...in this case: "hlt".
166 */
167	.inline i86_halt,0
168	sti
169	hlt
170	.end
171
172/*
173 * execute the bsrw instruction
174 *	int bsrw_insn(uint16_t)
175 */
176	.inline	bsrw_insn,4
177	xorl	%eax, %eax
178	movw	(%esp), %cx
179	bsrw	%cx, %ax
180	.end
181