1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/cpuvar.h> 27 #include <sys/psm.h> 28 #include <sys/archsystm.h> 29 #include <sys/apic.h> 30 #include <sys/sunddi.h> 31 #include <sys/ddi_impldefs.h> 32 #include <sys/mach_intr.h> 33 #include <sys/sysmacros.h> 34 #include <sys/trap.h> 35 #include <sys/x86_archext.h> 36 #include <sys/privregs.h> 37 #include <sys/psm_common.h> 38 39 /* Function prototypes of local apic and X2APIC */ 40 static uint64_t local_apic_read(uint32_t reg); 41 static void local_apic_write(uint32_t reg, uint64_t value); 42 static int get_local_apic_pri(void); 43 static void local_apic_write_task_reg(uint64_t value); 44 static void local_apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1); 45 static uint64_t local_x2apic_read(uint32_t msr); 46 static void local_x2apic_write(uint32_t msr, uint64_t value); 47 static int get_local_x2apic_pri(void); 48 static void local_x2apic_write_task_reg(uint64_t value); 49 static void local_x2apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1); 50 51 /* 52 * According to the X2APIC specification: 53 * 54 * xAPIC global enable X2APIC enable Description 55 * (IA32_APIC_BASE[11]) (IA32_APIC_BASE[10]) 56 * ----------------------------------------------------------- 57 * 0 0 APIC is disabled 58 * 0 1 Invalid 59 * 1 0 APIC is enabled in xAPIC mode 60 * 1 1 APIC is enabled in X2APIC mode 61 * ----------------------------------------------------------- 62 */ 63 int x2apic_enable = 1; 64 int apic_mode = LOCAL_APIC; /* Default mode is Local APIC */ 65 66 /* Uses MMIO (Memory Mapped IO) */ 67 static apic_reg_ops_t local_apic_regs_ops = { 68 local_apic_read, 69 local_apic_write, 70 get_local_apic_pri, 71 local_apic_write_task_reg, 72 local_apic_write_int_cmd, 73 apic_send_EOI, 74 }; 75 76 /* X2APIC : Uses RDMSR/WRMSR instructions to access APIC registers */ 77 static apic_reg_ops_t x2apic_regs_ops = { 78 local_x2apic_read, 79 local_x2apic_write, 80 get_local_x2apic_pri, 81 local_x2apic_write_task_reg, 82 local_x2apic_write_int_cmd, 83 apic_send_EOI, 84 }; 85 86 87 /* The default ops is local APIC (Memory Mapped IO) */ 88 apic_reg_ops_t *apic_reg_ops = &local_apic_regs_ops; 89 90 /* 91 * APIC register ops related data sturctures and functions. 92 */ 93 int apic_direct_EOI = 0; /* Directed EOI Support */ 94 95 void apic_send_EOI(); 96 void apic_send_directed_EOI(uint32_t irq); 97 98 #define X2APIC_CPUID_BIT 21 99 #define X2APIC_ENABLE_BIT 10 100 101 /* 102 * Local APIC Implementation 103 */ 104 static uint64_t 105 local_apic_read(uint32_t reg) 106 { 107 return ((uint32_t)apicadr[reg]); 108 } 109 110 static void 111 local_apic_write(uint32_t reg, uint64_t value) 112 { 113 apicadr[reg] = (uint32_t)value; 114 } 115 116 static int 117 get_local_apic_pri(void) 118 { 119 #if defined(__amd64) 120 return ((int)getcr8()); 121 #else 122 return (apicadr[APIC_TASK_REG]); 123 #endif 124 } 125 126 static void 127 local_apic_write_task_reg(uint64_t value) 128 { 129 #if defined(__amd64) 130 setcr8((ulong_t)(value >> APIC_IPL_SHIFT)); 131 #else 132 apicadr[APIC_TASK_REG] = (uint32_t)value; 133 #endif 134 } 135 136 static void 137 local_apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1) 138 { 139 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 140 apicadr[APIC_INT_CMD1] = cmd1; 141 } 142 143 /* 144 * X2APIC Implementation. 145 */ 146 static uint64_t 147 local_x2apic_read(uint32_t msr) 148 { 149 uint64_t i; 150 151 i = (uint64_t)(rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)) & 0xffffffff); 152 return (i); 153 } 154 155 static void 156 local_x2apic_write(uint32_t msr, uint64_t value) 157 { 158 uint64_t tmp; 159 160 if (msr != APIC_EOI_REG) { 161 tmp = rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)); 162 tmp = (tmp & 0xffffffff00000000) | value; 163 } else { 164 tmp = 0; 165 } 166 167 wrmsr((REG_X2APIC_BASE_MSR + (msr >> 2)), tmp); 168 } 169 170 static int 171 get_local_x2apic_pri(void) 172 { 173 return (rdmsr(REG_X2APIC_BASE_MSR + (APIC_TASK_REG >> 2))); 174 } 175 176 static void 177 local_x2apic_write_task_reg(uint64_t value) 178 { 179 X2APIC_WRITE(APIC_TASK_REG, value); 180 } 181 182 static void 183 local_x2apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1) 184 { 185 wrmsr((REG_X2APIC_BASE_MSR + (APIC_INT_CMD1 >> 2)), 186 (((uint64_t)cpu_id << 32) | cmd1)); 187 } 188 189 /*ARGSUSED*/ 190 void 191 apic_send_EOI(uint32_t irq) 192 { 193 apic_reg_ops->apic_write(APIC_EOI_REG, 0); 194 } 195 196 void 197 apic_send_directed_EOI(uint32_t irq) 198 { 199 uchar_t ioapicindex; 200 uchar_t vector; 201 apic_irq_t *apic_irq; 202 short intr_index; 203 204 ASSERT(apic_mode == LOCAL_X2APIC); 205 206 apic_irq = apic_irq_table[irq]; 207 208 while (apic_irq) { 209 intr_index = apic_irq->airq_mps_intr_index; 210 if (intr_index == ACPI_INDEX || intr_index >= 0) { 211 ioapicindex = apic_irq->airq_ioapicindex; 212 vector = apic_irq->airq_vector; 213 ioapic_write_eoi(ioapicindex, vector); 214 } 215 apic_irq = apic_irq->airq_next; 216 } 217 } 218 219 int 220 apic_detect_x2apic(void) 221 { 222 struct cpuid_regs cp; 223 224 if (x2apic_enable == 0) 225 return (0); 226 227 cp.cp_eax = 1; 228 (void) __cpuid_insn(&cp); 229 230 return ((cp.cp_ecx & (0x1 << X2APIC_CPUID_BIT)) ? 1 : 0); 231 } 232 233 void 234 apic_enable_x2apic(void) 235 { 236 uint64_t apic_base_msr; 237 238 if (apic_local_mode() == LOCAL_X2APIC) { 239 /* BIOS apparently has enabled X2APIC */ 240 if (apic_mode != LOCAL_X2APIC) 241 x2apic_update_psm(); 242 return; 243 } 244 245 /* 246 * This is the first time we are enabling X2APIC on this CPU 247 */ 248 apic_base_msr = rdmsr(REG_APIC_BASE_MSR); 249 apic_base_msr = apic_base_msr | (0x1 << X2APIC_ENABLE_BIT); 250 wrmsr(REG_APIC_BASE_MSR, apic_base_msr); 251 252 if (apic_mode != LOCAL_X2APIC) 253 x2apic_update_psm(); 254 } 255 256 /* 257 * Determine which mode the current CPU is in. See the table above. 258 * (IA32_APIC_BASE[11]) (IA32_APIC_BASE[10]) 259 */ 260 int 261 apic_local_mode(void) 262 { 263 uint64_t apic_base_msr; 264 int bit = ((0x1 << (X2APIC_ENABLE_BIT + 1)) | 265 (0x1 << X2APIC_ENABLE_BIT)); 266 267 apic_base_msr = rdmsr(REG_APIC_BASE_MSR); 268 269 if ((apic_base_msr & bit) == bit) 270 return (LOCAL_X2APIC); 271 else 272 return (LOCAL_APIC); 273 } 274 275 void 276 apic_change_eoi() 277 { 278 apic_reg_ops->apic_send_eoi = apic_send_directed_EOI; 279 } 280 281 /* 282 * Change apic_reg_ops depending upon the apic_mode. 283 */ 284 void 285 apic_change_ops() 286 { 287 if (apic_mode == LOCAL_APIC) 288 apic_reg_ops = &local_apic_regs_ops; 289 else if (apic_mode == LOCAL_X2APIC) 290 apic_reg_ops = &x2apic_regs_ops; 291 } 292 293 /* 294 * Generates an interprocessor interrupt to another CPU when X2APIC mode is 295 * enabled. 296 */ 297 void 298 x2apic_send_ipi(int cpun, int ipl) 299 { 300 int vector; 301 ulong_t flag; 302 303 /* 304 * With X2APIC, Intel relaxed the semantics of the 305 * WRMSR instruction such that references to the X2APIC 306 * MSR registers are no longer serializing instructions. 307 * The code that initiates IPIs assumes that some sort 308 * of memory serialization occurs. The old APIC code 309 * did a write to uncachable memory mapped registers. 310 * Any reference to uncached memory is a serializing 311 * operation. To mimic those semantics here, we do an 312 * atomic operation, which translates to a LOCK OR instruction, 313 * which is serializing. 314 */ 315 atomic_or_ulong(&flag, 1); 316 317 vector = apic_resv_vector[ipl]; 318 319 flag = intr_clear(); 320 321 /* 322 * According to X2APIC specification in section '2.3.5.1' of 323 * Interrupt Command Register Semantics, the semantics of 324 * programming Interrupt Command Register to dispatch an interrupt 325 * is simplified. A single MSR write to the 64-bit ICR is required 326 * for dispatching an interrupt. Specifically with the 64-bit MSR 327 * interface to ICR, system software is not required to check the 328 * status of the delivery status bit prior to writing to the ICR 329 * to send an IPI. With the removal of the Delivery Status bit, 330 * system software no longer has a reason to read the ICR. It remains 331 * readable only to aid in debugging. 332 */ 333 #ifdef DEBUG 334 APIC_AV_PENDING_SET(); 335 #endif /* DEBUG */ 336 337 if ((cpun == psm_get_cpu_id())) 338 apic_reg_ops->apic_write(X2APIC_SELF_IPI, vector); 339 else 340 apic_reg_ops->apic_write_int_cmd( 341 apic_cpus[cpun].aci_local_id, vector); 342 343 intr_restore(flag); 344 } 345 346 /* 347 * Generates IPI to another CPU depending on the local APIC mode. 348 * apic_send_ipi() and x2apic_send_ipi() depends on the configured 349 * mode of the local APIC, but that may not match the actual mode 350 * early in CPU startup. 351 * 352 * Any changes made to this routine must be accompanied by similar 353 * changes to apic_send_ipi(). 354 */ 355 void 356 apic_common_send_ipi(int cpun, int ipl) 357 { 358 int vector; 359 ulong_t flag; 360 int mode = apic_local_mode(); 361 362 if (mode == LOCAL_X2APIC) { 363 x2apic_send_ipi(cpun, ipl); 364 return; 365 } 366 367 ASSERT(mode == LOCAL_APIC); 368 369 vector = apic_resv_vector[ipl]; 370 ASSERT((vector >= APIC_BASE_VECT) && (vector <= APIC_SPUR_INTR)); 371 flag = intr_clear(); 372 while (local_apic_regs_ops.apic_read(APIC_INT_CMD1) & AV_PENDING) 373 apic_ret(); 374 local_apic_regs_ops.apic_write_int_cmd(apic_cpus[cpun].aci_local_id, 375 vector); 376 intr_restore(flag); 377 } 378