1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 29 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 30 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 31 * PSMI 1.5 extensions are supported in Solaris Nevada. 32 * PSMI 1.6 extensions are supported in Solaris Nevada. 33 */ 34 #define PSMI_1_6 35 36 #include <sys/processor.h> 37 #include <sys/time.h> 38 #include <sys/psm.h> 39 #include <sys/smp_impldefs.h> 40 #include <sys/cram.h> 41 #include <sys/acpi/acpi.h> 42 #include <sys/acpica.h> 43 #include <sys/psm_common.h> 44 #include <sys/apic.h> 45 #include <sys/pit.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/ddi_impldefs.h> 49 #include <sys/pci.h> 50 #include <sys/promif.h> 51 #include <sys/x86_archext.h> 52 #include <sys/cpc_impl.h> 53 #include <sys/uadmin.h> 54 #include <sys/panic.h> 55 #include <sys/debug.h> 56 #include <sys/archsystm.h> 57 #include <sys/trap.h> 58 #include <sys/machsystm.h> 59 #include <sys/sysmacros.h> 60 #include <sys/cpuvar.h> 61 #include <sys/rm_platter.h> 62 #include <sys/privregs.h> 63 #include <sys/note.h> 64 #include <sys/pci_intr_lib.h> 65 #include <sys/spl.h> 66 #include <sys/clock.h> 67 #include <sys/dditypes.h> 68 #include <sys/sunddi.h> 69 #include <sys/x_call.h> 70 #include <sys/reboot.h> 71 72 /* 73 * Local Function Prototypes 74 */ 75 static void apic_init_intr(); 76 static void apic_nmi_intr(caddr_t arg, struct regs *rp); 77 78 /* 79 * standard MP entries 80 */ 81 static int apic_probe(); 82 static int apic_clkinit(); 83 static int apic_getclkirq(int ipl); 84 static uint_t apic_calibrate(volatile uint32_t *addr, 85 uint16_t *pit_ticks_adj); 86 static hrtime_t apic_gettime(); 87 static hrtime_t apic_gethrtime(); 88 static void apic_init(); 89 static void apic_picinit(void); 90 static int apic_cpu_start(processorid_t, caddr_t); 91 static int apic_post_cpu_start(void); 92 static void apic_send_ipi(int cpun, int ipl); 93 static void apic_set_idlecpu(processorid_t cpun); 94 static void apic_unset_idlecpu(processorid_t cpun); 95 static int apic_intr_enter(int ipl, int *vect); 96 static void apic_setspl(int ipl); 97 static void x2apic_setspl(int ipl); 98 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 99 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 100 static void apic_shutdown(int cmd, int fcn); 101 static void apic_preshutdown(int cmd, int fcn); 102 static int apic_disable_intr(processorid_t cpun); 103 static void apic_enable_intr(processorid_t cpun); 104 static processorid_t apic_get_next_processorid(processorid_t cpun); 105 static int apic_get_ipivect(int ipl, int type); 106 static void apic_timer_reprogram(hrtime_t time); 107 static void apic_timer_enable(void); 108 static void apic_timer_disable(void); 109 static void apic_post_cyclic_setup(void *arg); 110 static void apic_intrr_init(int apic_mode); 111 static void apic_record_ioapic_rdt(apic_irq_t *irq_ptr, ioapic_rdt_t *irdt); 112 static void apic_record_msi(apic_irq_t *irq_ptr, msi_regs_t *mregs); 113 114 static int apic_oneshot = 0; 115 int apic_oneshot_enable = 1; /* to allow disabling one-shot capability */ 116 117 /* Now the ones for Dynamic Interrupt distribution */ 118 int apic_enable_dynamic_migration = 0; 119 120 121 /* 122 * These variables are frequently accessed in apic_intr_enter(), 123 * apic_intr_exit and apic_setspl, so group them together 124 */ 125 volatile uint32_t *apicadr = NULL; /* virtual addr of local APIC */ 126 int apic_setspl_delay = 1; /* apic_setspl - delay enable */ 127 int apic_clkvect; 128 129 /* vector at which error interrupts come in */ 130 int apic_errvect; 131 int apic_enable_error_intr = 1; 132 int apic_error_display_delay = 100; 133 134 /* vector at which performance counter overflow interrupts come in */ 135 int apic_cpcovf_vect; 136 int apic_enable_cpcovf_intr = 1; 137 138 /* vector at which CMCI interrupts come in */ 139 int apic_cmci_vect; 140 extern int cmi_enable_cmci; 141 extern void cmi_cmci_trap(void); 142 143 static kmutex_t cmci_cpu_setup_lock; /* protects cmci_cpu_setup_registered */ 144 static int cmci_cpu_setup_registered; 145 146 /* 147 * The following vector assignments influence the value of ipltopri and 148 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 149 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 150 * we care to do so in future. Note some IPLs which are rarely used 151 * will share the vector ranges and heavily used IPLs (5 and 6) have 152 * a wide range. 153 * 154 * This array is used to initialize apic_ipls[] (in apic_init()). 155 * 156 * IPL Vector range. as passed to intr_enter 157 * 0 none. 158 * 1,2,3 0x20-0x2f 0x0-0xf 159 * 4 0x30-0x3f 0x10-0x1f 160 * 5 0x40-0x5f 0x20-0x3f 161 * 6 0x60-0x7f 0x40-0x5f 162 * 7,8,9 0x80-0x8f 0x60-0x6f 163 * 10 0x90-0x9f 0x70-0x7f 164 * 11 0xa0-0xaf 0x80-0x8f 165 * ... ... 166 * 15 0xe0-0xef 0xc0-0xcf 167 * 15 0xf0-0xff 0xd0-0xdf 168 */ 169 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 170 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 171 }; 172 /* 173 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 174 * NOTE that this is vector as passed into intr_enter which is 175 * programmed vector - 0x20 (APIC_BASE_VECT) 176 */ 177 178 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 179 /* The taskpri to be programmed into apic to mask given ipl */ 180 181 #if defined(__amd64) 182 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */ 183 #endif 184 185 /* 186 * Correlation of the hardware vector to the IPL in use, initialized 187 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 188 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 189 * connected to errata-stricken IOAPICs 190 */ 191 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 192 193 /* 194 * Patchable global variables. 195 */ 196 int apic_forceload = 0; 197 198 int apic_coarse_hrtime = 1; /* 0 - use accurate slow gethrtime() */ 199 /* 1 - use gettime() for performance */ 200 int apic_flat_model = 0; /* 0 - clustered. 1 - flat */ 201 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 202 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 203 int apic_panic_on_nmi = 0; 204 int apic_panic_on_apic_error = 0; 205 206 int apic_verbose = 0; 207 208 /* minimum number of timer ticks to program to */ 209 int apic_min_timer_ticks = 1; 210 /* 211 * Local static data 212 */ 213 static struct psm_ops apic_ops = { 214 apic_probe, 215 216 apic_init, 217 apic_picinit, 218 apic_intr_enter, 219 apic_intr_exit, 220 apic_setspl, 221 apic_addspl, 222 apic_delspl, 223 apic_disable_intr, 224 apic_enable_intr, 225 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 226 (void (*)(int))NULL, /* psm_set_softintr */ 227 228 apic_set_idlecpu, 229 apic_unset_idlecpu, 230 231 apic_clkinit, 232 apic_getclkirq, 233 (void (*)(void))NULL, /* psm_hrtimeinit */ 234 apic_gethrtime, 235 236 apic_get_next_processorid, 237 apic_cpu_start, 238 apic_post_cpu_start, 239 apic_shutdown, 240 apic_get_ipivect, 241 apic_send_ipi, 242 243 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 244 (void (*)(int, char *))NULL, /* psm_notify_error */ 245 (void (*)(int))NULL, /* psm_notify_func */ 246 apic_timer_reprogram, 247 apic_timer_enable, 248 apic_timer_disable, 249 apic_post_cyclic_setup, 250 apic_preshutdown, 251 apic_intr_ops, /* Advanced DDI Interrupt framework */ 252 apic_state, /* save, restore apic state for S3 */ 253 }; 254 255 256 static struct psm_info apic_psm_info = { 257 PSM_INFO_VER01_6, /* version */ 258 PSM_OWN_EXCLUSIVE, /* ownership */ 259 (struct psm_ops *)&apic_ops, /* operation */ 260 APIC_PCPLUSMP_NAME, /* machine name */ 261 "pcplusmp v1.4 compatible", 262 }; 263 264 static void *apic_hdlp; 265 266 #ifdef DEBUG 267 int apic_debug = 0; 268 int apic_restrict_vector = 0; 269 270 int apic_debug_msgbuf[APIC_DEBUG_MSGBUFSIZE]; 271 int apic_debug_msgbufindex = 0; 272 273 #endif /* DEBUG */ 274 275 apic_cpus_info_t *apic_cpus; 276 277 cpuset_t apic_cpumask; 278 uint_t apic_picinit_called; 279 280 /* Flag to indicate that we need to shut down all processors */ 281 static uint_t apic_shutdown_processors; 282 283 uint_t apic_nsec_per_intr = 0; 284 285 /* 286 * apic_let_idle_redistribute can have the following values: 287 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute. 288 * apic_redistribute_lock prevents multiple idle cpus from redistributing 289 */ 290 int apic_num_idle_redistributions = 0; 291 static int apic_let_idle_redistribute = 0; 292 static uint_t apic_nticks = 0; 293 static uint_t apic_skipped_redistribute = 0; 294 295 /* to gather intr data and redistribute */ 296 static void apic_redistribute_compute(void); 297 298 static uint_t last_count_read = 0; 299 static lock_t apic_gethrtime_lock; 300 volatile int apic_hrtime_stamp = 0; 301 volatile hrtime_t apic_nsec_since_boot = 0; 302 static uint_t apic_hertz_count; 303 304 uint64_t apic_ticks_per_SFnsecs; /* # of ticks in SF nsecs */ 305 306 static hrtime_t apic_nsec_max; 307 308 static hrtime_t apic_last_hrtime = 0; 309 int apic_hrtime_error = 0; 310 int apic_remote_hrterr = 0; 311 int apic_num_nmis = 0; 312 int apic_apic_error = 0; 313 int apic_num_apic_errors = 0; 314 int apic_num_cksum_errors = 0; 315 316 int apic_error = 0; 317 static int apic_cmos_ssb_set = 0; 318 319 /* use to make sure only one cpu handles the nmi */ 320 static lock_t apic_nmi_lock; 321 /* use to make sure only one cpu handles the error interrupt */ 322 static lock_t apic_error_lock; 323 324 static struct { 325 uchar_t cntl; 326 uchar_t data; 327 } aspen_bmc[] = { 328 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 329 { CC_SMS_WR_NEXT, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 330 { CC_SMS_WR_NEXT, 0x84 }, /* DataByte 1: SMS/OS no log */ 331 { CC_SMS_WR_NEXT, 0x2 }, /* DataByte 2: Power Down */ 332 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 3: no pre-timeout */ 333 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 4: timer expir. */ 334 { CC_SMS_WR_NEXT, 0xa }, /* DataByte 5: init countdown */ 335 { CC_SMS_WR_END, 0x0 }, /* DataByte 6: init countdown */ 336 337 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 338 { CC_SMS_WR_END, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 339 }; 340 341 static struct { 342 int port; 343 uchar_t data; 344 } sitka_bmc[] = { 345 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 346 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 347 { SMS_DATA_REGISTER, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 348 { SMS_DATA_REGISTER, 0x84 }, /* DataByte 1: SMS/OS no log */ 349 { SMS_DATA_REGISTER, 0x2 }, /* DataByte 2: Power Down */ 350 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 3: no pre-timeout */ 351 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 4: timer expir. */ 352 { SMS_DATA_REGISTER, 0xa }, /* DataByte 5: init countdown */ 353 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 354 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 6: init countdown */ 355 356 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 357 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 358 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 359 { SMS_DATA_REGISTER, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 360 }; 361 362 /* Patchable global variables. */ 363 int apic_kmdb_on_nmi = 0; /* 0 - no, 1 - yes enter kmdb */ 364 uint32_t apic_divide_reg_init = 0; /* 0 - divide by 2 */ 365 366 /* default apic ops without interrupt remapping */ 367 static apic_intrr_ops_t apic_nointrr_ops = { 368 (int (*)(int))return_instr, 369 (void (*)(void))return_instr, 370 (void (*)(apic_irq_t *))return_instr, 371 (void (*)(apic_irq_t *, void *))return_instr, 372 (void (*)(apic_irq_t *))return_instr, 373 apic_record_ioapic_rdt, 374 apic_record_msi, 375 }; 376 377 apic_intrr_ops_t *apic_vt_ops = &apic_nointrr_ops; 378 379 /* 380 * This is the loadable module wrapper 381 */ 382 383 int 384 _init(void) 385 { 386 if (apic_coarse_hrtime) 387 apic_ops.psm_gethrtime = &apic_gettime; 388 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 389 } 390 391 int 392 _fini(void) 393 { 394 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 395 } 396 397 int 398 _info(struct modinfo *modinfop) 399 { 400 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 401 } 402 403 404 static int 405 apic_probe() 406 { 407 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 408 } 409 410 void 411 apic_init() 412 { 413 int i; 414 int j = 1; 415 416 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 417 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 418 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 419 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 420 /* get to highest vector at the same ipl */ 421 continue; 422 for (; j <= apic_vectortoipl[i]; j++) { 423 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 424 APIC_BASE_VECT; 425 } 426 } 427 for (; j < MAXIPL + 1; j++) 428 /* fill up any empty ipltopri slots */ 429 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 430 apic_init_common(); 431 #if defined(__amd64) 432 /* 433 * Make cpu-specific interrupt info point to cr8pri vector 434 */ 435 for (i = 0; i <= MAXIPL; i++) 436 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT; 437 CPU->cpu_pri_data = apic_cr8pri; 438 #endif /* __amd64 */ 439 440 /* 441 * initialize interrupt remapping before apic 442 * hardware initialization 443 */ 444 apic_intrr_init(apic_mode); 445 } 446 447 /* 448 * handler for APIC Error interrupt. Just print a warning and continue 449 */ 450 static int 451 apic_error_intr() 452 { 453 uint_t error0, error1, error; 454 uint_t i; 455 456 /* 457 * We need to write before read as per 7.4.17 of system prog manual. 458 * We do both and or the results to be safe 459 */ 460 error0 = apic_reg_ops->apic_read(APIC_ERROR_STATUS); 461 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 462 error1 = apic_reg_ops->apic_read(APIC_ERROR_STATUS); 463 error = error0 | error1; 464 465 /* 466 * Clear the APIC error status (do this on all cpus that enter here) 467 * (two writes are required due to the semantics of accessing the 468 * error status register.) 469 */ 470 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 471 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 472 473 /* 474 * Prevent more than 1 CPU from handling error interrupt causing 475 * double printing (interleave of characters from multiple 476 * CPU's when using prom_printf) 477 */ 478 if (lock_try(&apic_error_lock) == 0) 479 return (error ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 480 if (error) { 481 #if DEBUG 482 if (apic_debug) 483 debug_enter("pcplusmp: APIC Error interrupt received"); 484 #endif /* DEBUG */ 485 if (apic_panic_on_apic_error) 486 cmn_err(CE_PANIC, 487 "APIC Error interrupt on CPU %d. Status = %x\n", 488 psm_get_cpu_id(), error); 489 else { 490 if ((error & ~APIC_CS_ERRORS) == 0) { 491 /* cksum error only */ 492 apic_error |= APIC_ERR_APIC_ERROR; 493 apic_apic_error |= error; 494 apic_num_apic_errors++; 495 apic_num_cksum_errors++; 496 } else { 497 /* 498 * prom_printf is the best shot we have of 499 * something which is problem free from 500 * high level/NMI type of interrupts 501 */ 502 prom_printf("APIC Error interrupt on CPU %d. " 503 "Status 0 = %x, Status 1 = %x\n", 504 psm_get_cpu_id(), error0, error1); 505 apic_error |= APIC_ERR_APIC_ERROR; 506 apic_apic_error |= error; 507 apic_num_apic_errors++; 508 for (i = 0; i < apic_error_display_delay; i++) { 509 tenmicrosec(); 510 } 511 /* 512 * provide more delay next time limited to 513 * roughly 1 clock tick time 514 */ 515 if (apic_error_display_delay < 500) 516 apic_error_display_delay *= 2; 517 } 518 } 519 lock_clear(&apic_error_lock); 520 return (DDI_INTR_CLAIMED); 521 } else { 522 lock_clear(&apic_error_lock); 523 return (DDI_INTR_UNCLAIMED); 524 } 525 /* NOTREACHED */ 526 } 527 528 /* 529 * Turn off the mask bit in the performance counter Local Vector Table entry. 530 */ 531 static void 532 apic_cpcovf_mask_clear(void) 533 { 534 apic_reg_ops->apic_write(APIC_PCINT_VECT, 535 (apic_reg_ops->apic_read(APIC_PCINT_VECT) & ~APIC_LVT_MASK)); 536 } 537 538 /*ARGSUSED*/ 539 static int 540 apic_cmci_enable(xc_arg_t arg1, xc_arg_t arg2, xc_arg_t arg3) 541 { 542 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 543 return (0); 544 } 545 546 /*ARGSUSED*/ 547 static int 548 apic_cmci_disable(xc_arg_t arg1, xc_arg_t arg2, xc_arg_t arg3) 549 { 550 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect | AV_MASK); 551 return (0); 552 } 553 554 /*ARGSUSED*/ 555 static int 556 cmci_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 557 { 558 cpuset_t cpu_set; 559 560 CPUSET_ONLY(cpu_set, cpuid); 561 562 switch (what) { 563 case CPU_ON: 564 xc_call(NULL, NULL, NULL, X_CALL_HIPRI, cpu_set, 565 (xc_func_t)apic_cmci_enable); 566 break; 567 568 case CPU_OFF: 569 xc_call(NULL, NULL, NULL, X_CALL_HIPRI, cpu_set, 570 (xc_func_t)apic_cmci_disable); 571 break; 572 573 default: 574 break; 575 } 576 577 return (0); 578 } 579 580 static void 581 apic_init_intr() 582 { 583 processorid_t cpun = psm_get_cpu_id(); 584 uint_t nlvt; 585 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 586 587 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 588 589 if (apic_mode == LOCAL_APIC) { 590 /* 591 * We are running APIC in MMIO mode. 592 */ 593 if (apic_flat_model) { 594 apic_reg_ops->apic_write(APIC_FORMAT_REG, 595 APIC_FLAT_MODEL); 596 } else { 597 apic_reg_ops->apic_write(APIC_FORMAT_REG, 598 APIC_CLUSTER_MODEL); 599 } 600 601 apic_reg_ops->apic_write(APIC_DEST_REG, 602 AV_HIGH_ORDER >> cpun); 603 } 604 605 if (apic_direct_EOI) { 606 /* 607 * Set 12th bit in Spurious Interrupt Vector 608 * Register to support level triggered interrupt 609 * directed EOI. 610 */ 611 svr |= (0x1 << APIC_SVR); 612 } 613 614 /* need to enable APIC before unmasking NMI */ 615 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 616 617 /* 618 * Presence of an invalid vector with delivery mode AV_FIXED can 619 * cause an error interrupt, even if the entry is masked...so 620 * write a valid vector to LVT entries along with the mask bit 621 */ 622 623 /* All APICs have timer and LINT0/1 */ 624 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 625 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 626 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 627 628 /* 629 * On integrated APICs, the number of LVT entries is 630 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 631 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 632 */ 633 634 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 635 nlvt = 3; 636 } else { 637 nlvt = ((apicadr[APIC_VERS_REG] >> 16) & 0xFF) + 1; 638 } 639 640 if (nlvt >= 5) { 641 /* Enable performance counter overflow interrupt */ 642 643 if ((x86_feature & X86_MSR) != X86_MSR) 644 apic_enable_cpcovf_intr = 0; 645 if (apic_enable_cpcovf_intr) { 646 if (apic_cpcovf_vect == 0) { 647 int ipl = APIC_PCINT_IPL; 648 int irq = apic_get_ipivect(ipl, -1); 649 650 ASSERT(irq != -1); 651 apic_cpcovf_vect = 652 apic_irq_table[irq]->airq_vector; 653 ASSERT(apic_cpcovf_vect); 654 (void) add_avintr(NULL, ipl, 655 (avfunc)kcpc_hw_overflow_intr, 656 "apic pcint", irq, NULL, NULL, NULL, NULL); 657 kcpc_hw_overflow_intr_installed = 1; 658 kcpc_hw_enable_cpc_intr = 659 apic_cpcovf_mask_clear; 660 } 661 apic_reg_ops->apic_write(APIC_PCINT_VECT, 662 apic_cpcovf_vect); 663 } 664 } 665 666 if (nlvt >= 6) { 667 /* Only mask TM intr if the BIOS apparently doesn't use it */ 668 669 uint32_t lvtval; 670 671 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 672 if (((lvtval & AV_MASK) == AV_MASK) || 673 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 674 apic_reg_ops->apic_write(APIC_THERM_VECT, 675 AV_MASK|APIC_RESV_IRQ); 676 } 677 } 678 679 /* Enable error interrupt */ 680 681 if (nlvt >= 4 && apic_enable_error_intr) { 682 if (apic_errvect == 0) { 683 int ipl = 0xf; /* get highest priority intr */ 684 int irq = apic_get_ipivect(ipl, -1); 685 686 ASSERT(irq != -1); 687 apic_errvect = apic_irq_table[irq]->airq_vector; 688 ASSERT(apic_errvect); 689 /* 690 * Not PSMI compliant, but we are going to merge 691 * with ON anyway 692 */ 693 (void) add_avintr((void *)NULL, ipl, 694 (avfunc)apic_error_intr, "apic error intr", 695 irq, NULL, NULL, NULL, NULL); 696 } 697 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 698 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 699 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 700 } 701 702 /* Enable CMCI interrupt */ 703 if (cmi_enable_cmci) { 704 705 mutex_enter(&cmci_cpu_setup_lock); 706 if (cmci_cpu_setup_registered == 0) { 707 mutex_enter(&cpu_lock); 708 register_cpu_setup_func(cmci_cpu_setup, NULL); 709 mutex_exit(&cpu_lock); 710 cmci_cpu_setup_registered = 1; 711 } 712 mutex_exit(&cmci_cpu_setup_lock); 713 714 if (apic_cmci_vect == 0) { 715 int ipl = 0x2; 716 int irq = apic_get_ipivect(ipl, -1); 717 718 ASSERT(irq != -1); 719 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 720 ASSERT(apic_cmci_vect); 721 722 (void) add_avintr(NULL, ipl, 723 (avfunc)cmi_cmci_trap, 724 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 725 } 726 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 727 } 728 } 729 730 static void 731 apic_disable_local_apic() 732 { 733 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 734 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK); 735 736 /* local intr reg 0 */ 737 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK); 738 739 /* disable NMI */ 740 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_MASK); 741 742 /* and error interrupt */ 743 apic_reg_ops->apic_write(APIC_ERR_VECT, AV_MASK); 744 745 /* and perf counter intr */ 746 apic_reg_ops->apic_write(APIC_PCINT_VECT, AV_MASK); 747 748 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, APIC_SPUR_INTR); 749 } 750 751 static void 752 apic_picinit(void) 753 { 754 int i, j; 755 uint_t isr; 756 uint32_t ver; 757 758 /* 759 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 760 * bit on without clearing it with EOI. Since softint 761 * uses vector 0x20 to interrupt itself, so softint will 762 * not work on this machine. In order to fix this problem 763 * a check is made to verify all the isr bits are clear. 764 * If not, EOIs are issued to clear the bits. 765 */ 766 for (i = 7; i >= 1; i--) { 767 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 768 if (isr != 0) 769 for (j = 0; ((j < 32) && (isr != 0)); j++) 770 if (isr & (1 << j)) { 771 apic_reg_ops->apic_write( 772 APIC_EOI_REG, 0); 773 isr &= ~(1 << j); 774 apic_error |= APIC_ERR_BOOT_EOI; 775 } 776 } 777 778 /* set a flag so we know we have run apic_picinit() */ 779 apic_picinit_called = 1; 780 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 781 LOCK_INIT_CLEAR(&apic_ioapic_lock); 782 LOCK_INIT_CLEAR(&apic_error_lock); 783 784 picsetup(); /* initialise the 8259 */ 785 786 /* add nmi handler - least priority nmi handler */ 787 LOCK_INIT_CLEAR(&apic_nmi_lock); 788 789 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 790 "pcplusmp NMI handler", (caddr_t)NULL)) 791 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 792 793 ver = apic_reg_ops->apic_read(APIC_VERS_REG); 794 /* 795 * In order to determine support for Directed EOI capability, 796 * we check for 24th bit in Local APIC Version Register. 797 */ 798 if (ver & (0x1 << APIC_DIRECTED_EOI)) { 799 apic_direct_EOI = 1; 800 apic_change_eoi(); 801 } 802 803 apic_init_intr(); 804 805 /* enable apic mode if imcr present */ 806 if (apic_imcrp) { 807 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 808 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 809 } 810 811 ioapic_init_intr(IOAPIC_MASK); 812 } 813 814 815 /*ARGSUSED1*/ 816 static int 817 apic_cpu_start(processorid_t cpun, caddr_t arg) 818 { 819 int loop_count; 820 uint32_t vector; 821 uint_t cpu_id; 822 ulong_t iflag; 823 824 cpu_id = apic_cpus[cpun].aci_local_id; 825 826 apic_cmos_ssb_set = 1; 827 828 /* 829 * Interrupts on BSP cpu will be disabled during these startup 830 * steps in order to avoid unwanted side effects from 831 * executing interrupt handlers on a problematic BIOS. 832 */ 833 834 iflag = intr_clear(); 835 outb(CMOS_ADDR, SSB); 836 outb(CMOS_DATA, BIOS_SHUTDOWN); 837 838 /* 839 * According to X2APIC specification in section '2.3.5.1' of 840 * Interrupt Command Register Semantics, the semantics of 841 * programming the Interrupt Command Register to dispatch an interrupt 842 * is simplified. A single MSR write to the 64-bit ICR is required 843 * for dispatching an interrupt. Specifically, with the 64-bit MSR 844 * interface to ICR, system software is not required to check the 845 * status of the delivery status bit prior to writing to the ICR 846 * to send an IPI. With the removal of the Delivery Status bit, 847 * system software no longer has a reason to read the ICR. It remains 848 * readable only to aid in debugging. 849 */ 850 #ifdef DEBUG 851 APIC_AV_PENDING_SET(); 852 #else 853 if (apic_mode == LOCAL_APIC) { 854 APIC_AV_PENDING_SET(); 855 } 856 #endif /* DEBUG */ 857 858 /* for integrated - make sure there is one INIT IPI in buffer */ 859 /* for external - it will wake up the cpu */ 860 apic_reg_ops->apic_write_int_cmd(cpu_id, AV_ASSERT | AV_RESET); 861 862 /* If only 1 CPU is installed, PENDING bit will not go low */ 863 for (loop_count = 0x1000; loop_count; loop_count--) { 864 if (apic_mode == LOCAL_APIC && 865 apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) 866 apic_ret(); 867 else 868 break; 869 } 870 871 apic_reg_ops->apic_write_int_cmd(cpu_id, AV_DEASSERT | AV_RESET); 872 873 drv_usecwait(20000); /* 20 milli sec */ 874 875 if (apic_cpus[cpun].aci_local_ver >= APIC_INTEGRATED_VERS) { 876 /* integrated apic */ 877 878 vector = (rm_platter_pa >> MMU_PAGESHIFT) & 879 (APIC_VECTOR_MASK | APIC_IPL_MASK); 880 881 /* to offset the INIT IPI queue up in the buffer */ 882 apic_reg_ops->apic_write_int_cmd(cpu_id, vector | AV_STARTUP); 883 884 drv_usecwait(200); /* 20 micro sec */ 885 886 apic_reg_ops->apic_write_int_cmd(cpu_id, vector | AV_STARTUP); 887 888 drv_usecwait(200); /* 20 micro sec */ 889 } 890 intr_restore(iflag); 891 return (0); 892 } 893 894 895 #ifdef DEBUG 896 int apic_break_on_cpu = 9; 897 int apic_stretch_interrupts = 0; 898 int apic_stretch_ISR = 1 << 3; /* IPL of 3 matches nothing now */ 899 900 void 901 apic_break() 902 { 903 } 904 #endif /* DEBUG */ 905 906 /* 907 * platform_intr_enter 908 * 909 * Called at the beginning of the interrupt service routine to 910 * mask all level equal to and below the interrupt priority 911 * of the interrupting vector. An EOI should be given to 912 * the interrupt controller to enable other HW interrupts. 913 * 914 * Return -1 for spurious interrupts 915 * 916 */ 917 /*ARGSUSED*/ 918 static int 919 apic_intr_enter(int ipl, int *vectorp) 920 { 921 uchar_t vector; 922 int nipl; 923 int irq; 924 ulong_t iflag; 925 apic_cpus_info_t *cpu_infop; 926 927 /* 928 * The real vector delivered is (*vectorp + 0x20), but our caller 929 * subtracts 0x20 from the vector before passing it to us. 930 * (That's why APIC_BASE_VECT is 0x20.) 931 */ 932 vector = (uchar_t)*vectorp; 933 934 /* if interrupted by the clock, increment apic_nsec_since_boot */ 935 if (vector == apic_clkvect) { 936 if (!apic_oneshot) { 937 /* NOTE: this is not MT aware */ 938 apic_hrtime_stamp++; 939 apic_nsec_since_boot += apic_nsec_per_intr; 940 apic_hrtime_stamp++; 941 last_count_read = apic_hertz_count; 942 apic_redistribute_compute(); 943 } 944 945 /* We will avoid all the book keeping overhead for clock */ 946 nipl = apic_ipls[vector]; 947 948 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 949 if (apic_mode == LOCAL_APIC) { 950 #if defined(__amd64) 951 setcr8((ulong_t)(apic_ipltopri[nipl] >> 952 APIC_IPL_SHIFT)); 953 #else 954 LOCAL_APIC_WRITE_REG(APIC_TASK_REG, 955 (uint32_t)apic_ipltopri[nipl]); 956 #endif 957 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 958 } else { 959 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]); 960 X2APIC_WRITE(APIC_EOI_REG, 0); 961 } 962 963 return (nipl); 964 } 965 966 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 967 968 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 969 cpu_infop->aci_spur_cnt++; 970 return (APIC_INT_SPURIOUS); 971 } 972 973 /* Check if the vector we got is really what we need */ 974 if (apic_revector_pending) { 975 /* 976 * Disable interrupts for the duration of 977 * the vector translation to prevent a self-race for 978 * the apic_revector_lock. This cannot be done 979 * in apic_xlate_vector because it is recursive and 980 * we want the vector translation to be atomic with 981 * respect to other (higher-priority) interrupts. 982 */ 983 iflag = intr_clear(); 984 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 985 APIC_BASE_VECT; 986 intr_restore(iflag); 987 } 988 989 nipl = apic_ipls[vector]; 990 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 991 992 if (apic_mode == LOCAL_APIC) { 993 #if defined(__amd64) 994 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT)); 995 #else 996 LOCAL_APIC_WRITE_REG(APIC_TASK_REG, 997 (uint32_t)apic_ipltopri[nipl]); 998 #endif 999 } else { 1000 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]); 1001 } 1002 1003 cpu_infop->aci_current[nipl] = (uchar_t)irq; 1004 cpu_infop->aci_curipl = (uchar_t)nipl; 1005 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 1006 1007 /* 1008 * apic_level_intr could have been assimilated into the irq struct. 1009 * but, having it as a character array is more efficient in terms of 1010 * cache usage. So, we leave it as is. 1011 */ 1012 if (!apic_level_intr[irq]) { 1013 if (apic_mode == LOCAL_APIC) 1014 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 1015 else 1016 X2APIC_WRITE(APIC_EOI_REG, 0); 1017 } 1018 1019 #ifdef DEBUG 1020 APIC_DEBUG_BUF_PUT(vector); 1021 APIC_DEBUG_BUF_PUT(irq); 1022 APIC_DEBUG_BUF_PUT(nipl); 1023 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 1024 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 1025 drv_usecwait(apic_stretch_interrupts); 1026 1027 if (apic_break_on_cpu == psm_get_cpu_id()) 1028 apic_break(); 1029 #endif /* DEBUG */ 1030 return (nipl); 1031 } 1032 1033 /* 1034 * This macro is a common code used by MMIO local apic and X2APIC 1035 * local apic. 1036 */ 1037 #define APIC_INTR_EXIT() \ 1038 { \ 1039 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \ 1040 if (apic_level_intr[irq]) \ 1041 apic_reg_ops->apic_send_eoi(irq); \ 1042 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \ 1043 /* ISR above current pri could not be in progress */ \ 1044 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \ 1045 } 1046 1047 /* 1048 * Any changes made to this function must also change X2APIC 1049 * version of intr_exit. 1050 */ 1051 void 1052 apic_intr_exit(int prev_ipl, int irq) 1053 { 1054 apic_cpus_info_t *cpu_infop; 1055 1056 #if defined(__amd64) 1057 setcr8((ulong_t)apic_cr8pri[prev_ipl]); 1058 #else 1059 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl]; 1060 #endif 1061 1062 APIC_INTR_EXIT(); 1063 } 1064 1065 /* 1066 * Same as apic_intr_exit() except it uses MSR rather than MMIO 1067 * to access local apic registers. 1068 */ 1069 void 1070 x2apic_intr_exit(int prev_ipl, int irq) 1071 { 1072 apic_cpus_info_t *cpu_infop; 1073 1074 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]); 1075 APIC_INTR_EXIT(); 1076 } 1077 1078 intr_exit_fn_t 1079 psm_intr_exit_fn(void) 1080 { 1081 if (apic_mode == LOCAL_X2APIC) 1082 return (x2apic_intr_exit); 1083 1084 return (apic_intr_exit); 1085 } 1086 1087 /* 1088 * Mask all interrupts below or equal to the given IPL. 1089 * Any changes made to this function must also change X2APIC 1090 * version of setspl. 1091 */ 1092 static void 1093 apic_setspl(int ipl) 1094 { 1095 #if defined(__amd64) 1096 setcr8((ulong_t)apic_cr8pri[ipl]); 1097 #else 1098 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl]; 1099 #endif 1100 1101 /* interrupts at ipl above this cannot be in progress */ 1102 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 1103 /* 1104 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 1105 * have enough time to come in before the priority is raised again 1106 * during the idle() loop. 1107 */ 1108 if (apic_setspl_delay) 1109 (void) apic_reg_ops->apic_get_pri(); 1110 } 1111 1112 /* 1113 * X2APIC version of setspl. 1114 * Mask all interrupts below or equal to the given IPL 1115 */ 1116 static void 1117 x2apic_setspl(int ipl) 1118 { 1119 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]); 1120 1121 /* interrupts at ipl above this cannot be in progress */ 1122 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 1123 } 1124 1125 /* 1126 * generates an interprocessor interrupt to another CPU. Any changes made to 1127 * this routine must be accompanied by similar changes to 1128 * apic_common_send_ipi(). 1129 */ 1130 static void 1131 apic_send_ipi(int cpun, int ipl) 1132 { 1133 int vector; 1134 ulong_t flag; 1135 1136 vector = apic_resv_vector[ipl]; 1137 1138 ASSERT((vector >= APIC_BASE_VECT) && (vector <= APIC_SPUR_INTR)); 1139 1140 flag = intr_clear(); 1141 1142 APIC_AV_PENDING_SET(); 1143 1144 apic_reg_ops->apic_write_int_cmd(apic_cpus[cpun].aci_local_id, 1145 vector); 1146 1147 intr_restore(flag); 1148 } 1149 1150 1151 /*ARGSUSED*/ 1152 static void 1153 apic_set_idlecpu(processorid_t cpun) 1154 { 1155 } 1156 1157 /*ARGSUSED*/ 1158 static void 1159 apic_unset_idlecpu(processorid_t cpun) 1160 { 1161 } 1162 1163 1164 void 1165 apic_ret() 1166 { 1167 } 1168 1169 /* 1170 * If apic_coarse_time == 1, then apic_gettime() is used instead of 1171 * apic_gethrtime(). This is used for performance instead of accuracy. 1172 */ 1173 1174 static hrtime_t 1175 apic_gettime() 1176 { 1177 int old_hrtime_stamp; 1178 hrtime_t temp; 1179 1180 /* 1181 * In one-shot mode, we do not keep time, so if anyone 1182 * calls psm_gettime() directly, we vector over to 1183 * gethrtime(). 1184 * one-shot mode MUST NOT be enabled if this psm is the source of 1185 * hrtime. 1186 */ 1187 1188 if (apic_oneshot) 1189 return (gethrtime()); 1190 1191 1192 gettime_again: 1193 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 1194 apic_ret(); 1195 1196 temp = apic_nsec_since_boot; 1197 1198 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 1199 goto gettime_again; 1200 } 1201 return (temp); 1202 } 1203 1204 /* 1205 * Here we return the number of nanoseconds since booting. Note every 1206 * clock interrupt increments apic_nsec_since_boot by the appropriate 1207 * amount. 1208 */ 1209 static hrtime_t 1210 apic_gethrtime() 1211 { 1212 int curr_timeval, countval, elapsed_ticks; 1213 int old_hrtime_stamp, status; 1214 hrtime_t temp; 1215 uint32_t cpun; 1216 ulong_t oflags; 1217 1218 /* 1219 * In one-shot mode, we do not keep time, so if anyone 1220 * calls psm_gethrtime() directly, we vector over to 1221 * gethrtime(). 1222 * one-shot mode MUST NOT be enabled if this psm is the source of 1223 * hrtime. 1224 */ 1225 1226 if (apic_oneshot) 1227 return (gethrtime()); 1228 1229 oflags = intr_clear(); /* prevent migration */ 1230 1231 cpun = apic_reg_ops->apic_read(APIC_LID_REG); 1232 if (apic_mode == LOCAL_APIC) 1233 cpun >>= APIC_ID_BIT_OFFSET; 1234 1235 lock_set(&apic_gethrtime_lock); 1236 1237 gethrtime_again: 1238 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 1239 apic_ret(); 1240 1241 /* 1242 * Check to see which CPU we are on. Note the time is kept on 1243 * the local APIC of CPU 0. If on CPU 0, simply read the current 1244 * counter. If on another CPU, issue a remote read command to CPU 0. 1245 */ 1246 if (cpun == apic_cpus[0].aci_local_id) { 1247 countval = apic_reg_ops->apic_read(APIC_CURR_COUNT); 1248 } else { 1249 #ifdef DEBUG 1250 APIC_AV_PENDING_SET(); 1251 #else 1252 if (apic_mode == LOCAL_APIC) 1253 APIC_AV_PENDING_SET(); 1254 #endif /* DEBUG */ 1255 1256 apic_reg_ops->apic_write_int_cmd( 1257 apic_cpus[0].aci_local_id, APIC_CURR_ADD | AV_REMOTE); 1258 1259 while ((status = apic_reg_ops->apic_read(APIC_INT_CMD1)) 1260 & AV_READ_PENDING) { 1261 apic_ret(); 1262 } 1263 1264 if (status & AV_REMOTE_STATUS) /* 1 = valid */ 1265 countval = apic_reg_ops->apic_read(APIC_REMOTE_READ); 1266 else { /* 0 = invalid */ 1267 apic_remote_hrterr++; 1268 /* 1269 * return last hrtime right now, will need more 1270 * testing if change to retry 1271 */ 1272 temp = apic_last_hrtime; 1273 1274 lock_clear(&apic_gethrtime_lock); 1275 1276 intr_restore(oflags); 1277 1278 return (temp); 1279 } 1280 } 1281 if (countval > last_count_read) 1282 countval = 0; 1283 else 1284 last_count_read = countval; 1285 1286 elapsed_ticks = apic_hertz_count - countval; 1287 1288 curr_timeval = APIC_TICKS_TO_NSECS(elapsed_ticks); 1289 temp = apic_nsec_since_boot + curr_timeval; 1290 1291 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 1292 /* we might have clobbered last_count_read. Restore it */ 1293 last_count_read = apic_hertz_count; 1294 goto gethrtime_again; 1295 } 1296 1297 if (temp < apic_last_hrtime) { 1298 /* return last hrtime if error occurs */ 1299 apic_hrtime_error++; 1300 temp = apic_last_hrtime; 1301 } 1302 else 1303 apic_last_hrtime = temp; 1304 1305 lock_clear(&apic_gethrtime_lock); 1306 intr_restore(oflags); 1307 1308 return (temp); 1309 } 1310 1311 /* apic NMI handler */ 1312 /*ARGSUSED*/ 1313 static void 1314 apic_nmi_intr(caddr_t arg, struct regs *rp) 1315 { 1316 if (apic_shutdown_processors) { 1317 apic_disable_local_apic(); 1318 return; 1319 } 1320 1321 apic_error |= APIC_ERR_NMI; 1322 1323 if (!lock_try(&apic_nmi_lock)) 1324 return; 1325 apic_num_nmis++; 1326 1327 if (apic_kmdb_on_nmi && psm_debugger()) { 1328 debug_enter("NMI received: entering kmdb\n"); 1329 } else if (apic_panic_on_nmi) { 1330 /* Keep panic from entering kmdb. */ 1331 nopanicdebug = 1; 1332 panic("NMI received\n"); 1333 } else { 1334 /* 1335 * prom_printf is the best shot we have of something which is 1336 * problem free from high level/NMI type of interrupts 1337 */ 1338 prom_printf("NMI received\n"); 1339 } 1340 1341 lock_clear(&apic_nmi_lock); 1342 } 1343 1344 /*ARGSUSED*/ 1345 static int 1346 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 1347 { 1348 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 1349 } 1350 1351 static int 1352 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 1353 { 1354 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 1355 } 1356 1357 static int 1358 apic_post_cpu_start() 1359 { 1360 int cpun; 1361 static int cpus_started = 1; 1362 struct psm_ops *pops = &apic_ops; 1363 1364 /* We know this CPU + BSP started successfully. */ 1365 cpus_started++; 1366 1367 /* 1368 * On BSP we would have enabled X2APIC, if supported by processor, 1369 * in acpi_probe(), but on AP we do it here. 1370 * 1371 * We enable X2APIC mode only if BSP is running in X2APIC & the 1372 * local APIC mode of the current CPU is MMIO (xAPIC). 1373 */ 1374 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() && 1375 apic_local_mode() == LOCAL_APIC) { 1376 apic_enable_x2apic(); 1377 } 1378 1379 /* 1380 * We change psm_send_ipi and send_dirintf only if Solaris 1381 * is booted in kmdb & the current CPU is the last CPU being 1382 * brought up. We don't need to do anything if Solaris is running 1383 * in MMIO mode (xAPIC). 1384 */ 1385 if ((boothowto & RB_DEBUG) && 1386 (cpus_started == boot_ncpus || cpus_started == apic_nproc) && 1387 apic_mode == LOCAL_X2APIC) { 1388 /* 1389 * We no longer need help from apic_common_send_ipi() 1390 * since we will not start any more CPUs. 1391 * 1392 * We will need to revisit this if we start supporting 1393 * hot-plugging of CPUs. 1394 */ 1395 pops->psm_send_ipi = x2apic_send_ipi; 1396 send_dirintf = pops->psm_send_ipi; 1397 } 1398 1399 splx(ipltospl(LOCK_LEVEL)); 1400 apic_init_intr(); 1401 1402 /* 1403 * since some systems don't enable the internal cache on the non-boot 1404 * cpus, so we have to enable them here 1405 */ 1406 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 1407 1408 #ifdef DEBUG 1409 APIC_AV_PENDING_SET(); 1410 #else 1411 if (apic_mode == LOCAL_APIC) 1412 APIC_AV_PENDING_SET(); 1413 #endif /* DEBUG */ 1414 1415 /* 1416 * We may be booting, or resuming from suspend; aci_status will 1417 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 1418 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 1419 */ 1420 cpun = psm_get_cpu_id(); 1421 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 1422 1423 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 1424 return (PSM_SUCCESS); 1425 } 1426 1427 processorid_t 1428 apic_get_next_processorid(processorid_t cpu_id) 1429 { 1430 1431 int i; 1432 1433 if (cpu_id == -1) 1434 return ((processorid_t)0); 1435 1436 for (i = cpu_id + 1; i < NCPU; i++) { 1437 if (CPU_IN_SET(apic_cpumask, i)) 1438 return (i); 1439 } 1440 1441 return ((processorid_t)-1); 1442 } 1443 1444 1445 /* 1446 * type == -1 indicates it is an internal request. Do not change 1447 * resv_vector for these requests 1448 */ 1449 static int 1450 apic_get_ipivect(int ipl, int type) 1451 { 1452 uchar_t vector; 1453 int irq; 1454 1455 if (irq = apic_allocate_irq(APIC_VECTOR(ipl))) { 1456 if (vector = apic_allocate_vector(ipl, irq, 1)) { 1457 apic_irq_table[irq]->airq_mps_intr_index = 1458 RESERVE_INDEX; 1459 apic_irq_table[irq]->airq_vector = vector; 1460 if (type != -1) { 1461 apic_resv_vector[ipl] = vector; 1462 } 1463 return (irq); 1464 } 1465 } 1466 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 1467 return (-1); /* shouldn't happen */ 1468 } 1469 1470 static int 1471 apic_getclkirq(int ipl) 1472 { 1473 int irq; 1474 1475 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 1476 return (-1); 1477 /* 1478 * Note the vector in apic_clkvect for per clock handling. 1479 */ 1480 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 1481 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 1482 apic_clkvect)); 1483 return (irq); 1484 } 1485 1486 1487 /* 1488 * Return the number of APIC clock ticks elapsed for 8245 to decrement 1489 * (APIC_TIME_COUNT + pit_ticks_adj) ticks. 1490 */ 1491 static uint_t 1492 apic_calibrate(volatile uint32_t *addr, uint16_t *pit_ticks_adj) 1493 { 1494 uint8_t pit_tick_lo; 1495 uint16_t pit_tick, target_pit_tick; 1496 uint32_t start_apic_tick, end_apic_tick; 1497 ulong_t iflag; 1498 uint32_t reg; 1499 1500 reg = addr + APIC_CURR_COUNT - apicadr; 1501 1502 iflag = intr_clear(); 1503 1504 do { 1505 pit_tick_lo = inb(PITCTR0_PORT); 1506 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1507 } while (pit_tick < APIC_TIME_MIN || 1508 pit_tick_lo <= APIC_LB_MIN || pit_tick_lo >= APIC_LB_MAX); 1509 1510 /* 1511 * Wait for the 8254 to decrement by 5 ticks to ensure 1512 * we didn't start in the middle of a tick. 1513 * Compare with 0x10 for the wrap around case. 1514 */ 1515 target_pit_tick = pit_tick - 5; 1516 do { 1517 pit_tick_lo = inb(PITCTR0_PORT); 1518 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1519 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 1520 1521 start_apic_tick = apic_reg_ops->apic_read(reg); 1522 1523 /* 1524 * Wait for the 8254 to decrement by 1525 * (APIC_TIME_COUNT + pit_ticks_adj) ticks 1526 */ 1527 target_pit_tick = pit_tick - APIC_TIME_COUNT; 1528 do { 1529 pit_tick_lo = inb(PITCTR0_PORT); 1530 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1531 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 1532 1533 end_apic_tick = apic_reg_ops->apic_read(reg); 1534 1535 *pit_ticks_adj = target_pit_tick - pit_tick; 1536 1537 intr_restore(iflag); 1538 1539 return (start_apic_tick - end_apic_tick); 1540 } 1541 1542 /* 1543 * Initialise the APIC timer on the local APIC of CPU 0 to the desired 1544 * frequency. Note at this stage in the boot sequence, the boot processor 1545 * is the only active processor. 1546 * hertz value of 0 indicates a one-shot mode request. In this case 1547 * the function returns the resolution (in nanoseconds) for the hardware 1548 * timer interrupt. If one-shot mode capability is not available, 1549 * the return value will be 0. apic_enable_oneshot is a global switch 1550 * for disabling the functionality. 1551 * A non-zero positive value for hertz indicates a periodic mode request. 1552 * In this case the hardware will be programmed to generate clock interrupts 1553 * at hertz frequency and returns the resolution of interrupts in 1554 * nanosecond. 1555 */ 1556 1557 static int 1558 apic_clkinit(int hertz) 1559 { 1560 uint_t apic_ticks = 0; 1561 uint_t pit_ticks; 1562 int ret; 1563 uint16_t pit_ticks_adj; 1564 static int firsttime = 1; 1565 1566 if (firsttime) { 1567 /* first time calibrate on CPU0 only */ 1568 1569 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 1570 apic_reg_ops->apic_write(APIC_INIT_COUNT, APIC_MAXVAL); 1571 apic_ticks = apic_calibrate(apicadr, &pit_ticks_adj); 1572 1573 /* total number of PIT ticks corresponding to apic_ticks */ 1574 pit_ticks = APIC_TIME_COUNT + pit_ticks_adj; 1575 1576 /* 1577 * Determine the number of nanoseconds per APIC clock tick 1578 * and then determine how many APIC ticks to interrupt at the 1579 * desired frequency 1580 * apic_ticks / (pitticks / PIT_HZ) = apic_ticks_per_s 1581 * (apic_ticks * PIT_HZ) / pitticks = apic_ticks_per_s 1582 * apic_ticks_per_ns = (apic_ticks * PIT_HZ) / (pitticks * 10^9) 1583 * pic_ticks_per_SFns = 1584 * (SF * apic_ticks * PIT_HZ) / (pitticks * 10^9) 1585 */ 1586 apic_ticks_per_SFnsecs = 1587 ((SF * apic_ticks * PIT_HZ) / 1588 ((uint64_t)pit_ticks * NANOSEC)); 1589 1590 /* the interval timer initial count is 32 bit max */ 1591 apic_nsec_max = APIC_TICKS_TO_NSECS(APIC_MAXVAL); 1592 firsttime = 0; 1593 } 1594 1595 if (hertz != 0) { 1596 /* periodic */ 1597 apic_nsec_per_intr = NANOSEC / hertz; 1598 apic_hertz_count = APIC_NSECS_TO_TICKS(apic_nsec_per_intr); 1599 } 1600 1601 apic_int_busy_mark = (apic_int_busy_mark * 1602 apic_sample_factor_redistribution) / 100; 1603 apic_int_free_mark = (apic_int_free_mark * 1604 apic_sample_factor_redistribution) / 100; 1605 apic_diff_for_redistribution = (apic_diff_for_redistribution * 1606 apic_sample_factor_redistribution) / 100; 1607 1608 if (hertz == 0) { 1609 /* requested one_shot */ 1610 if (!tsc_gethrtime_enable || !apic_oneshot_enable) 1611 return (0); 1612 apic_oneshot = 1; 1613 ret = (int)APIC_TICKS_TO_NSECS(1); 1614 } else { 1615 /* program the local APIC to interrupt at the given frequency */ 1616 apic_reg_ops->apic_write(APIC_INIT_COUNT, apic_hertz_count); 1617 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 1618 (apic_clkvect + APIC_BASE_VECT) | AV_TIME); 1619 apic_oneshot = 0; 1620 ret = NANOSEC / hertz; 1621 } 1622 1623 return (ret); 1624 1625 } 1626 1627 /* 1628 * apic_preshutdown: 1629 * Called early in shutdown whilst we can still access filesystems to do 1630 * things like loading modules which will be required to complete shutdown 1631 * after filesystems are all unmounted. 1632 */ 1633 static void 1634 apic_preshutdown(int cmd, int fcn) 1635 { 1636 APIC_VERBOSE_POWEROFF(("apic_preshutdown(%d,%d); m=%d a=%d\n", 1637 cmd, fcn, apic_poweroff_method, apic_enable_acpi)); 1638 1639 if ((cmd != A_SHUTDOWN) || (fcn != AD_POWEROFF)) { 1640 return; 1641 } 1642 } 1643 1644 static void 1645 apic_shutdown(int cmd, int fcn) 1646 { 1647 int restarts, attempts; 1648 int i; 1649 uchar_t byte; 1650 ulong_t iflag; 1651 1652 /* Send NMI to all CPUs except self to do per processor shutdown */ 1653 iflag = intr_clear(); 1654 #ifdef DEBUG 1655 APIC_AV_PENDING_SET(); 1656 #else 1657 if (apic_mode == LOCAL_APIC) 1658 APIC_AV_PENDING_SET(); 1659 #endif /* DEBUG */ 1660 apic_shutdown_processors = 1; 1661 apic_reg_ops->apic_write(APIC_INT_CMD1, 1662 AV_NMI | AV_LEVEL | AV_SH_ALL_EXCSELF); 1663 1664 /* restore cmos shutdown byte before reboot */ 1665 if (apic_cmos_ssb_set) { 1666 outb(CMOS_ADDR, SSB); 1667 outb(CMOS_DATA, 0); 1668 } 1669 1670 ioapic_disable_redirection(); 1671 1672 /* disable apic mode if imcr present */ 1673 if (apic_imcrp) { 1674 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 1675 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_PIC); 1676 } 1677 1678 apic_disable_local_apic(); 1679 1680 intr_restore(iflag); 1681 1682 /* remainder of function is for shutdown cases only */ 1683 if (cmd != A_SHUTDOWN) 1684 return; 1685 1686 /* 1687 * Switch system back into Legacy-Mode if using ACPI and 1688 * not powering-off. Some BIOSes need to remain in ACPI-mode 1689 * for power-off to succeed (Dell Dimension 4600) 1690 * Do not disable ACPI while doing fastreboot 1691 */ 1692 if (apic_enable_acpi && fcn != AD_POWEROFF && fcn != AD_FASTREBOOT) 1693 (void) AcpiDisable(); 1694 1695 if (fcn == AD_FASTREBOOT) { 1696 apicadr[APIC_INT_CMD1] = AV_ASSERT | AV_RESET | 1697 AV_SH_ALL_EXCSELF; 1698 } 1699 1700 /* remainder of function is for shutdown+poweroff case only */ 1701 if (fcn != AD_POWEROFF) 1702 return; 1703 1704 switch (apic_poweroff_method) { 1705 case APIC_POWEROFF_VIA_RTC: 1706 1707 /* select the extended NVRAM bank in the RTC */ 1708 outb(CMOS_ADDR, RTC_REGA); 1709 byte = inb(CMOS_DATA); 1710 outb(CMOS_DATA, (byte | EXT_BANK)); 1711 1712 outb(CMOS_ADDR, PFR_REG); 1713 1714 /* for Predator must toggle the PAB bit */ 1715 byte = inb(CMOS_DATA); 1716 1717 /* 1718 * clear power active bar, wakeup alarm and 1719 * kickstart 1720 */ 1721 byte &= ~(PAB_CBIT | WF_FLAG | KS_FLAG); 1722 outb(CMOS_DATA, byte); 1723 1724 /* delay before next write */ 1725 drv_usecwait(1000); 1726 1727 /* for S40 the following would suffice */ 1728 byte = inb(CMOS_DATA); 1729 1730 /* power active bar control bit */ 1731 byte |= PAB_CBIT; 1732 outb(CMOS_DATA, byte); 1733 1734 break; 1735 1736 case APIC_POWEROFF_VIA_ASPEN_BMC: 1737 restarts = 0; 1738 restart_aspen_bmc: 1739 if (++restarts == 3) 1740 break; 1741 attempts = 0; 1742 do { 1743 byte = inb(MISMIC_FLAG_REGISTER); 1744 byte &= MISMIC_BUSY_MASK; 1745 if (byte != 0) { 1746 drv_usecwait(1000); 1747 if (attempts >= 3) 1748 goto restart_aspen_bmc; 1749 ++attempts; 1750 } 1751 } while (byte != 0); 1752 outb(MISMIC_CNTL_REGISTER, CC_SMS_GET_STATUS); 1753 byte = inb(MISMIC_FLAG_REGISTER); 1754 byte |= 0x1; 1755 outb(MISMIC_FLAG_REGISTER, byte); 1756 i = 0; 1757 for (; i < (sizeof (aspen_bmc)/sizeof (aspen_bmc[0])); 1758 i++) { 1759 attempts = 0; 1760 do { 1761 byte = inb(MISMIC_FLAG_REGISTER); 1762 byte &= MISMIC_BUSY_MASK; 1763 if (byte != 0) { 1764 drv_usecwait(1000); 1765 if (attempts >= 3) 1766 goto restart_aspen_bmc; 1767 ++attempts; 1768 } 1769 } while (byte != 0); 1770 outb(MISMIC_CNTL_REGISTER, aspen_bmc[i].cntl); 1771 outb(MISMIC_DATA_REGISTER, aspen_bmc[i].data); 1772 byte = inb(MISMIC_FLAG_REGISTER); 1773 byte |= 0x1; 1774 outb(MISMIC_FLAG_REGISTER, byte); 1775 } 1776 break; 1777 1778 case APIC_POWEROFF_VIA_SITKA_BMC: 1779 restarts = 0; 1780 restart_sitka_bmc: 1781 if (++restarts == 3) 1782 break; 1783 attempts = 0; 1784 do { 1785 byte = inb(SMS_STATUS_REGISTER); 1786 byte &= SMS_STATE_MASK; 1787 if ((byte == SMS_READ_STATE) || 1788 (byte == SMS_WRITE_STATE)) { 1789 drv_usecwait(1000); 1790 if (attempts >= 3) 1791 goto restart_sitka_bmc; 1792 ++attempts; 1793 } 1794 } while ((byte == SMS_READ_STATE) || 1795 (byte == SMS_WRITE_STATE)); 1796 outb(SMS_COMMAND_REGISTER, SMS_GET_STATUS); 1797 i = 0; 1798 for (; i < (sizeof (sitka_bmc)/sizeof (sitka_bmc[0])); 1799 i++) { 1800 attempts = 0; 1801 do { 1802 byte = inb(SMS_STATUS_REGISTER); 1803 byte &= SMS_IBF_MASK; 1804 if (byte != 0) { 1805 drv_usecwait(1000); 1806 if (attempts >= 3) 1807 goto restart_sitka_bmc; 1808 ++attempts; 1809 } 1810 } while (byte != 0); 1811 outb(sitka_bmc[i].port, sitka_bmc[i].data); 1812 } 1813 break; 1814 1815 case APIC_POWEROFF_NONE: 1816 1817 /* If no APIC direct method, we will try using ACPI */ 1818 if (apic_enable_acpi) { 1819 if (acpi_poweroff() == 1) 1820 return; 1821 } else 1822 return; 1823 1824 break; 1825 } 1826 /* 1827 * Wait a limited time here for power to go off. 1828 * If the power does not go off, then there was a 1829 * problem and we should continue to the halt which 1830 * prints a message for the user to press a key to 1831 * reboot. 1832 */ 1833 drv_usecwait(7000000); /* wait seven seconds */ 1834 1835 } 1836 1837 /* 1838 * Try and disable all interrupts. We just assign interrupts to other 1839 * processors based on policy. If any were bound by user request, we 1840 * let them continue and return failure. We do not bother to check 1841 * for cache affinity while rebinding. 1842 */ 1843 1844 static int 1845 apic_disable_intr(processorid_t cpun) 1846 { 1847 int bind_cpu = 0, i, hardbound = 0; 1848 apic_irq_t *irq_ptr; 1849 ulong_t iflag; 1850 1851 iflag = intr_clear(); 1852 lock_set(&apic_ioapic_lock); 1853 1854 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1855 if (apic_reprogram_info[i].done == B_FALSE) { 1856 if (apic_reprogram_info[i].bindcpu == cpun) { 1857 /* 1858 * CPU is busy -- it's the target of 1859 * a pending reprogramming attempt 1860 */ 1861 lock_clear(&apic_ioapic_lock); 1862 intr_restore(iflag); 1863 return (PSM_FAILURE); 1864 } 1865 } 1866 } 1867 1868 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 1869 1870 apic_cpus[cpun].aci_curipl = 0; 1871 1872 i = apic_min_device_irq; 1873 for (; i <= apic_max_device_irq; i++) { 1874 /* 1875 * If there are bound interrupts on this cpu, then 1876 * rebind them to other processors. 1877 */ 1878 if ((irq_ptr = apic_irq_table[i]) != NULL) { 1879 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 1880 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 1881 ((irq_ptr->airq_temp_cpu & ~IRQ_USER_BOUND) < 1882 apic_nproc)); 1883 1884 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 1885 hardbound = 1; 1886 continue; 1887 } 1888 1889 if (irq_ptr->airq_temp_cpu == cpun) { 1890 do { 1891 bind_cpu = apic_next_bind_cpu++; 1892 if (bind_cpu >= apic_nproc) { 1893 apic_next_bind_cpu = 1; 1894 bind_cpu = 0; 1895 1896 } 1897 } while (apic_rebind_all(irq_ptr, bind_cpu)); 1898 } 1899 } 1900 } 1901 1902 lock_clear(&apic_ioapic_lock); 1903 intr_restore(iflag); 1904 1905 if (hardbound) { 1906 cmn_err(CE_WARN, "Could not disable interrupts on %d" 1907 "due to user bound interrupts", cpun); 1908 return (PSM_FAILURE); 1909 } 1910 else 1911 return (PSM_SUCCESS); 1912 } 1913 1914 /* 1915 * Bind interrupts to the CPU's local APIC. 1916 * Interrupts should not be bound to a CPU's local APIC until the CPU 1917 * is ready to receive interrupts. 1918 */ 1919 static void 1920 apic_enable_intr(processorid_t cpun) 1921 { 1922 int i; 1923 apic_irq_t *irq_ptr; 1924 ulong_t iflag; 1925 1926 iflag = intr_clear(); 1927 lock_set(&apic_ioapic_lock); 1928 1929 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 1930 1931 i = apic_min_device_irq; 1932 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 1933 if ((irq_ptr = apic_irq_table[i]) != NULL) { 1934 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 1935 (void) apic_rebind_all(irq_ptr, 1936 irq_ptr->airq_cpu); 1937 } 1938 } 1939 } 1940 1941 lock_clear(&apic_ioapic_lock); 1942 intr_restore(iflag); 1943 } 1944 1945 1946 /* 1947 * This function will reprogram the timer. 1948 * 1949 * When in oneshot mode the argument is the absolute time in future to 1950 * generate the interrupt at. 1951 * 1952 * When in periodic mode, the argument is the interval at which the 1953 * interrupts should be generated. There is no need to support the periodic 1954 * mode timer change at this time. 1955 */ 1956 static void 1957 apic_timer_reprogram(hrtime_t time) 1958 { 1959 hrtime_t now; 1960 uint_t ticks; 1961 int64_t delta; 1962 1963 /* 1964 * We should be called from high PIL context (CBE_HIGH_PIL), 1965 * so kpreempt is disabled. 1966 */ 1967 1968 if (!apic_oneshot) { 1969 /* time is the interval for periodic mode */ 1970 ticks = APIC_NSECS_TO_TICKS(time); 1971 } else { 1972 /* one shot mode */ 1973 1974 now = gethrtime(); 1975 delta = time - now; 1976 1977 if (delta <= 0) { 1978 /* 1979 * requested to generate an interrupt in the past 1980 * generate an interrupt as soon as possible 1981 */ 1982 ticks = apic_min_timer_ticks; 1983 } else if (delta > apic_nsec_max) { 1984 /* 1985 * requested to generate an interrupt at a time 1986 * further than what we are capable of. Set to max 1987 * the hardware can handle 1988 */ 1989 1990 ticks = APIC_MAXVAL; 1991 #ifdef DEBUG 1992 cmn_err(CE_CONT, "apic_timer_reprogram, request at" 1993 " %lld too far in future, current time" 1994 " %lld \n", time, now); 1995 #endif 1996 } else 1997 ticks = APIC_NSECS_TO_TICKS(delta); 1998 } 1999 2000 if (ticks < apic_min_timer_ticks) 2001 ticks = apic_min_timer_ticks; 2002 2003 apic_reg_ops->apic_write(APIC_INIT_COUNT, ticks); 2004 } 2005 2006 /* 2007 * This function will enable timer interrupts. 2008 */ 2009 static void 2010 apic_timer_enable(void) 2011 { 2012 /* 2013 * We should be Called from high PIL context (CBE_HIGH_PIL), 2014 * so kpreempt is disabled. 2015 */ 2016 2017 if (!apic_oneshot) { 2018 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 2019 (apic_clkvect + APIC_BASE_VECT) | AV_TIME); 2020 } else { 2021 /* one shot */ 2022 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 2023 (apic_clkvect + APIC_BASE_VECT)); 2024 } 2025 } 2026 2027 /* 2028 * This function will disable timer interrupts. 2029 */ 2030 static void 2031 apic_timer_disable(void) 2032 { 2033 /* 2034 * We should be Called from high PIL context (CBE_HIGH_PIL), 2035 * so kpreempt is disabled. 2036 */ 2037 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 2038 (apic_clkvect + APIC_BASE_VECT) | AV_MASK); 2039 } 2040 2041 2042 ddi_periodic_t apic_periodic_id; 2043 2044 /* 2045 * If this module needs a periodic handler for the interrupt distribution, it 2046 * can be added here. The argument to the periodic handler is not currently 2047 * used, but is reserved for future. 2048 */ 2049 static void 2050 apic_post_cyclic_setup(void *arg) 2051 { 2052 _NOTE(ARGUNUSED(arg)) 2053 /* cpu_lock is held */ 2054 /* set up a periodic handler for intr redistribution */ 2055 2056 /* 2057 * In peridoc mode intr redistribution processing is done in 2058 * apic_intr_enter during clk intr processing 2059 */ 2060 if (!apic_oneshot) 2061 return; 2062 /* 2063 * Register a periodical handler for the redistribution processing. 2064 * On X86, CY_LOW_LEVEL is mapped to the level 2 interrupt, so 2065 * DDI_IPL_2 should be passed to ddi_periodic_add() here. 2066 */ 2067 apic_periodic_id = ddi_periodic_add( 2068 (void (*)(void *))apic_redistribute_compute, NULL, 2069 apic_redistribute_sample_interval, DDI_IPL_2); 2070 } 2071 2072 static void 2073 apic_redistribute_compute(void) 2074 { 2075 int i, j, max_busy; 2076 2077 if (apic_enable_dynamic_migration) { 2078 if (++apic_nticks == apic_sample_factor_redistribution) { 2079 /* 2080 * Time to call apic_intr_redistribute(). 2081 * reset apic_nticks. This will cause max_busy 2082 * to be calculated below and if it is more than 2083 * apic_int_busy, we will do the whole thing 2084 */ 2085 apic_nticks = 0; 2086 } 2087 max_busy = 0; 2088 for (i = 0; i < apic_nproc; i++) { 2089 2090 /* 2091 * Check if curipl is non zero & if ISR is in 2092 * progress 2093 */ 2094 if (((j = apic_cpus[i].aci_curipl) != 0) && 2095 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 2096 2097 int irq; 2098 apic_cpus[i].aci_busy++; 2099 irq = apic_cpus[i].aci_current[j]; 2100 apic_irq_table[irq]->airq_busy++; 2101 } 2102 2103 if (!apic_nticks && 2104 (apic_cpus[i].aci_busy > max_busy)) 2105 max_busy = apic_cpus[i].aci_busy; 2106 } 2107 if (!apic_nticks) { 2108 if (max_busy > apic_int_busy_mark) { 2109 /* 2110 * We could make the following check be 2111 * skipped > 1 in which case, we get a 2112 * redistribution at half the busy mark (due to 2113 * double interval). Need to be able to collect 2114 * more empirical data to decide if that is a 2115 * good strategy. Punt for now. 2116 */ 2117 if (apic_skipped_redistribute) { 2118 apic_cleanup_busy(); 2119 apic_skipped_redistribute = 0; 2120 } else { 2121 apic_intr_redistribute(); 2122 } 2123 } else 2124 apic_skipped_redistribute++; 2125 } 2126 } 2127 } 2128 2129 2130 /* 2131 * The following functions are in the platform specific file so that they 2132 * can be different functions depending on whether we are running on 2133 * bare metal or a hypervisor. 2134 */ 2135 2136 /* 2137 * map an apic for memory-mapped access 2138 */ 2139 uint32_t * 2140 mapin_apic(uint32_t addr, size_t len, int flags) 2141 { 2142 /*LINTED: pointer cast may result in improper alignment */ 2143 return ((uint32_t *)psm_map_phys(addr, len, flags)); 2144 } 2145 2146 uint32_t * 2147 mapin_ioapic(uint32_t addr, size_t len, int flags) 2148 { 2149 return (mapin_apic(addr, len, flags)); 2150 } 2151 2152 /* 2153 * unmap an apic 2154 */ 2155 void 2156 mapout_apic(caddr_t addr, size_t len) 2157 { 2158 psm_unmap_phys(addr, len); 2159 } 2160 2161 void 2162 mapout_ioapic(caddr_t addr, size_t len) 2163 { 2164 mapout_apic(addr, len); 2165 } 2166 2167 /* 2168 * Check to make sure there are enough irq slots 2169 */ 2170 int 2171 apic_check_free_irqs(int count) 2172 { 2173 int i, avail; 2174 2175 avail = 0; 2176 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 2177 if ((apic_irq_table[i] == NULL) || 2178 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 2179 if (++avail >= count) 2180 return (PSM_SUCCESS); 2181 } 2182 } 2183 return (PSM_FAILURE); 2184 } 2185 2186 /* 2187 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 2188 */ 2189 int 2190 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 2191 int behavior) 2192 { 2193 int rcount, i; 2194 uchar_t start, irqno; 2195 uint32_t cpu; 2196 major_t major; 2197 apic_irq_t *irqptr; 2198 2199 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 2200 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 2201 (void *)dip, inum, pri, count, behavior)); 2202 2203 if (count > 1) { 2204 if (behavior == DDI_INTR_ALLOC_STRICT && 2205 (apic_multi_msi_enable == 0 || count > apic_multi_msi_max)) 2206 return (0); 2207 2208 if (apic_multi_msi_enable == 0) 2209 count = 1; 2210 else if (count > apic_multi_msi_max) 2211 count = apic_multi_msi_max; 2212 } 2213 2214 if ((rcount = apic_navail_vector(dip, pri)) > count) 2215 rcount = count; 2216 else if (rcount == 0 || (rcount < count && 2217 behavior == DDI_INTR_ALLOC_STRICT)) 2218 return (0); 2219 2220 /* if not ISP2, then round it down */ 2221 if (!ISP2(rcount)) 2222 rcount = 1 << (highbit(rcount) - 1); 2223 2224 mutex_enter(&airq_mutex); 2225 2226 for (start = 0; rcount > 0; rcount >>= 1) { 2227 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 2228 behavior == DDI_INTR_ALLOC_STRICT) 2229 break; 2230 } 2231 2232 if (start == 0) { 2233 /* no vector available */ 2234 mutex_exit(&airq_mutex); 2235 return (0); 2236 } 2237 2238 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 2239 /* not enough free irq slots available */ 2240 mutex_exit(&airq_mutex); 2241 return (0); 2242 } 2243 2244 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 2245 for (i = 0; i < rcount; i++) { 2246 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 2247 (uchar_t)-1) { 2248 /* 2249 * shouldn't happen because of the 2250 * apic_check_free_irqs() check earlier 2251 */ 2252 mutex_exit(&airq_mutex); 2253 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 2254 "apic_allocate_irq failed\n")); 2255 return (i); 2256 } 2257 apic_max_device_irq = max(irqno, apic_max_device_irq); 2258 apic_min_device_irq = min(irqno, apic_min_device_irq); 2259 irqptr = apic_irq_table[irqno]; 2260 #ifdef DEBUG 2261 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 2262 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 2263 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 2264 #endif 2265 apic_vector_to_irq[start + i] = (uchar_t)irqno; 2266 2267 irqptr->airq_vector = (uchar_t)(start + i); 2268 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 2269 irqptr->airq_intin_no = (uchar_t)rcount; 2270 irqptr->airq_ipl = pri; 2271 irqptr->airq_vector = start + i; 2272 irqptr->airq_origirq = (uchar_t)(inum + i); 2273 irqptr->airq_share_id = 0; 2274 irqptr->airq_mps_intr_index = MSI_INDEX; 2275 irqptr->airq_dip = dip; 2276 irqptr->airq_major = major; 2277 if (i == 0) /* they all bound to the same cpu */ 2278 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 2279 0xff, 0xff); 2280 else 2281 irqptr->airq_cpu = cpu; 2282 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 2283 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 2284 (void *)irqptr->airq_dip, irqptr->airq_vector, 2285 irqptr->airq_origirq, pri)); 2286 } 2287 mutex_exit(&airq_mutex); 2288 return (rcount); 2289 } 2290 2291 /* 2292 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 2293 */ 2294 int 2295 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 2296 int behavior) 2297 { 2298 int rcount, i; 2299 major_t major; 2300 2301 if (count > 1) { 2302 if (behavior == DDI_INTR_ALLOC_STRICT) { 2303 if (count > apic_msix_max) 2304 return (0); 2305 } else if (count > apic_msix_max) 2306 count = apic_msix_max; 2307 } 2308 2309 mutex_enter(&airq_mutex); 2310 2311 if ((rcount = apic_navail_vector(dip, pri)) > count) 2312 rcount = count; 2313 else if (rcount == 0 || (rcount < count && 2314 behavior == DDI_INTR_ALLOC_STRICT)) { 2315 rcount = 0; 2316 goto out; 2317 } 2318 2319 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 2320 /* not enough free irq slots available */ 2321 rcount = 0; 2322 goto out; 2323 } 2324 2325 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 2326 for (i = 0; i < rcount; i++) { 2327 uchar_t vector, irqno; 2328 apic_irq_t *irqptr; 2329 2330 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 2331 (uchar_t)-1) { 2332 /* 2333 * shouldn't happen because of the 2334 * apic_check_free_irqs() check earlier 2335 */ 2336 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 2337 "apic_allocate_irq failed\n")); 2338 rcount = i; 2339 goto out; 2340 } 2341 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 2342 /* 2343 * shouldn't happen because of the 2344 * apic_navail_vector() call earlier 2345 */ 2346 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 2347 "apic_allocate_vector failed\n")); 2348 rcount = i; 2349 goto out; 2350 } 2351 apic_max_device_irq = max(irqno, apic_max_device_irq); 2352 apic_min_device_irq = min(irqno, apic_min_device_irq); 2353 irqptr = apic_irq_table[irqno]; 2354 irqptr->airq_vector = (uchar_t)vector; 2355 irqptr->airq_ipl = pri; 2356 irqptr->airq_origirq = (uchar_t)(inum + i); 2357 irqptr->airq_share_id = 0; 2358 irqptr->airq_mps_intr_index = MSIX_INDEX; 2359 irqptr->airq_dip = dip; 2360 irqptr->airq_major = major; 2361 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 2362 } 2363 out: 2364 mutex_exit(&airq_mutex); 2365 return (rcount); 2366 } 2367 2368 /* 2369 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 2370 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 2371 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 2372 * requests and allocated only when pri is set. 2373 */ 2374 uchar_t 2375 apic_allocate_vector(int ipl, int irq, int pri) 2376 { 2377 int lowest, highest, i; 2378 2379 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 2380 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 2381 2382 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 2383 lowest -= APIC_VECTOR_PER_IPL; 2384 2385 #ifdef DEBUG 2386 if (apic_restrict_vector) /* for testing shared interrupt logic */ 2387 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 2388 #endif /* DEBUG */ 2389 if (pri == 0) 2390 highest -= APIC_HI_PRI_VECTS; 2391 2392 for (i = lowest; i < highest; i++) { 2393 if (APIC_CHECK_RESERVE_VECTORS(i)) 2394 continue; 2395 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 2396 apic_vector_to_irq[i] = (uchar_t)irq; 2397 return (i); 2398 } 2399 } 2400 2401 return (0); 2402 } 2403 2404 /* Mark vector as not being used by any irq */ 2405 void 2406 apic_free_vector(uchar_t vector) 2407 { 2408 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 2409 } 2410 2411 uint32_t 2412 ioapic_read(int ioapic_ix, uint32_t reg) 2413 { 2414 volatile uint32_t *ioapic; 2415 2416 ioapic = apicioadr[ioapic_ix]; 2417 ioapic[APIC_IO_REG] = reg; 2418 return (ioapic[APIC_IO_DATA]); 2419 } 2420 2421 void 2422 ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value) 2423 { 2424 volatile uint32_t *ioapic; 2425 2426 ioapic = apicioadr[ioapic_ix]; 2427 ioapic[APIC_IO_REG] = reg; 2428 ioapic[APIC_IO_DATA] = value; 2429 } 2430 2431 void 2432 ioapic_write_eoi(int ioapic_ix, uint32_t value) 2433 { 2434 volatile uint32_t *ioapic; 2435 2436 ioapic = apicioadr[ioapic_ix]; 2437 ioapic[APIC_IO_EOI] = value; 2438 } 2439 2440 static processorid_t 2441 apic_find_cpu(int flag) 2442 { 2443 processorid_t acid = 0; 2444 int i; 2445 2446 /* Find the first CPU with the passed-in flag set */ 2447 for (i = 0; i < apic_nproc; i++) { 2448 if (apic_cpus[i].aci_status & flag) { 2449 acid = i; 2450 break; 2451 } 2452 } 2453 2454 ASSERT((apic_cpus[acid].aci_status & flag) != 0); 2455 return (acid); 2456 } 2457 2458 /* 2459 * Call rebind to do the actual programming. 2460 * Must be called with interrupts disabled and apic_ioapic_lock held 2461 * 'p' is polymorphic -- if this function is called to process a deferred 2462 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 2463 * the irq pointer is retrieved. If not doing deferred reprogramming, 2464 * p is of the type 'apic_irq_t *'. 2465 * 2466 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 2467 * and it protects apic_find_cpu() from a race in which a CPU can be taken 2468 * offline after a cpu is selected, but before apic_rebind is called to 2469 * bind interrupts to it. 2470 */ 2471 int 2472 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 2473 { 2474 apic_irq_t *irqptr; 2475 struct ioapic_reprogram_data *drep = NULL; 2476 int rv; 2477 2478 if (deferred) { 2479 drep = (struct ioapic_reprogram_data *)p; 2480 ASSERT(drep != NULL); 2481 irqptr = drep->irqp; 2482 } else 2483 irqptr = (apic_irq_t *)p; 2484 2485 ASSERT(irqptr != NULL); 2486 2487 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 2488 if (rv) { 2489 /* 2490 * CPU is not up or interrupts are disabled. Fall back to 2491 * the first available CPU 2492 */ 2493 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 2494 drep); 2495 } 2496 2497 return (rv); 2498 } 2499 2500 2501 uchar_t 2502 apic_modify_vector(uchar_t vector, int irq) 2503 { 2504 apic_vector_to_irq[vector] = (uchar_t)irq; 2505 return (vector); 2506 } 2507 2508 char * 2509 apic_get_apic_type() 2510 { 2511 return (apic_psm_info.p_mach_idstring); 2512 } 2513 2514 void 2515 x2apic_update_psm() 2516 { 2517 struct psm_ops *pops = &apic_ops; 2518 2519 ASSERT(pops != NULL); 2520 2521 /* 2522 * We don't need to do any magic if one of the following 2523 * conditions is true : 2524 * - Not being run under kernel debugger. 2525 * - MP is not set. 2526 * - Booted with one CPU only. 2527 * - One CPU configured. 2528 * 2529 * We set apic_common_send_ipi() since kernel debuggers 2530 * attempt to send IPIs to other slave CPUs during 2531 * entry (exit) from (to) debugger. 2532 */ 2533 if (!(boothowto & RB_DEBUG) || use_mp == 0 || 2534 apic_nproc == 1 || boot_ncpus == 1) { 2535 pops->psm_send_ipi = x2apic_send_ipi; 2536 } else { 2537 pops->psm_send_ipi = apic_common_send_ipi; 2538 } 2539 2540 pops->psm_intr_exit = x2apic_intr_exit; 2541 pops->psm_setspl = x2apic_setspl; 2542 2543 send_dirintf = pops->psm_send_ipi; 2544 2545 apic_mode = LOCAL_X2APIC; 2546 apic_change_ops(); 2547 } 2548 2549 static void 2550 apic_intrr_init(int apic_mode) 2551 { 2552 if (psm_vt_ops != NULL) { 2553 if (((apic_intrr_ops_t *)psm_vt_ops)->apic_intrr_init(apic_mode) 2554 == DDI_SUCCESS) { 2555 apic_vt_ops = psm_vt_ops; 2556 apic_vt_ops->apic_intrr_enable(); 2557 } 2558 } 2559 } 2560 2561 /*ARGSUSED*/ 2562 static void 2563 apic_record_ioapic_rdt(apic_irq_t *irq_ptr, ioapic_rdt_t *irdt) 2564 { 2565 irdt->ir_hi <<= APIC_ID_BIT_OFFSET; 2566 } 2567 2568 /*ARGSUSED*/ 2569 static void 2570 apic_record_msi(apic_irq_t *irq_ptr, msi_regs_t *mregs) 2571 { 2572 mregs->mr_addr = MSI_ADDR_HDR | 2573 (MSI_ADDR_RH_FIXED << MSI_ADDR_RH_SHIFT) | 2574 (MSI_ADDR_DM_PHYSICAL << MSI_ADDR_DM_SHIFT) | 2575 (mregs->mr_addr << MSI_ADDR_DEST_SHIFT); 2576 mregs->mr_data = (MSI_DATA_TM_EDGE << MSI_DATA_TM_SHIFT) | 2577 mregs->mr_data; 2578 } 2579