1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 29 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 30 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 31 * PSMI 1.5 extensions are supported in Solaris Nevada. 32 * PSMI 1.6 extensions are supported in Solaris Nevada. 33 */ 34 #define PSMI_1_6 35 36 #include <sys/processor.h> 37 #include <sys/time.h> 38 #include <sys/psm.h> 39 #include <sys/smp_impldefs.h> 40 #include <sys/cram.h> 41 #include <sys/acpi/acpi.h> 42 #include <sys/acpica.h> 43 #include <sys/psm_common.h> 44 #include <sys/apic.h> 45 #include <sys/pit.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/ddi_impldefs.h> 49 #include <sys/pci.h> 50 #include <sys/promif.h> 51 #include <sys/x86_archext.h> 52 #include <sys/cpc_impl.h> 53 #include <sys/uadmin.h> 54 #include <sys/panic.h> 55 #include <sys/debug.h> 56 #include <sys/archsystm.h> 57 #include <sys/trap.h> 58 #include <sys/machsystm.h> 59 #include <sys/sysmacros.h> 60 #include <sys/cpuvar.h> 61 #include <sys/rm_platter.h> 62 #include <sys/privregs.h> 63 #include <sys/note.h> 64 #include <sys/pci_intr_lib.h> 65 #include <sys/spl.h> 66 #include <sys/clock.h> 67 #include <sys/dditypes.h> 68 #include <sys/sunddi.h> 69 #include <sys/x_call.h> 70 #include <sys/reboot.h> 71 72 /* 73 * Local Function Prototypes 74 */ 75 static void apic_init_intr(); 76 static void apic_nmi_intr(caddr_t arg, struct regs *rp); 77 78 /* 79 * standard MP entries 80 */ 81 static int apic_probe(); 82 static int apic_clkinit(); 83 static int apic_getclkirq(int ipl); 84 static uint_t apic_calibrate(volatile uint32_t *addr, 85 uint16_t *pit_ticks_adj); 86 static hrtime_t apic_gettime(); 87 static hrtime_t apic_gethrtime(); 88 static void apic_init(); 89 static void apic_picinit(void); 90 static int apic_cpu_start(processorid_t, caddr_t); 91 static int apic_post_cpu_start(void); 92 static void apic_send_ipi(int cpun, int ipl); 93 static void apic_set_idlecpu(processorid_t cpun); 94 static void apic_unset_idlecpu(processorid_t cpun); 95 static int apic_intr_enter(int ipl, int *vect); 96 static void apic_setspl(int ipl); 97 static void x2apic_setspl(int ipl); 98 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 99 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 100 static void apic_shutdown(int cmd, int fcn); 101 static void apic_preshutdown(int cmd, int fcn); 102 static int apic_disable_intr(processorid_t cpun); 103 static void apic_enable_intr(processorid_t cpun); 104 static processorid_t apic_get_next_processorid(processorid_t cpun); 105 static int apic_get_ipivect(int ipl, int type); 106 static void apic_timer_reprogram(hrtime_t time); 107 static void apic_timer_enable(void); 108 static void apic_timer_disable(void); 109 static void apic_post_cyclic_setup(void *arg); 110 111 static int apic_oneshot = 0; 112 int apic_oneshot_enable = 1; /* to allow disabling one-shot capability */ 113 114 /* Now the ones for Dynamic Interrupt distribution */ 115 int apic_enable_dynamic_migration = 0; 116 117 118 /* 119 * These variables are frequently accessed in apic_intr_enter(), 120 * apic_intr_exit and apic_setspl, so group them together 121 */ 122 volatile uint32_t *apicadr = NULL; /* virtual addr of local APIC */ 123 int apic_setspl_delay = 1; /* apic_setspl - delay enable */ 124 int apic_clkvect; 125 126 /* vector at which error interrupts come in */ 127 int apic_errvect; 128 int apic_enable_error_intr = 1; 129 int apic_error_display_delay = 100; 130 131 /* vector at which performance counter overflow interrupts come in */ 132 int apic_cpcovf_vect; 133 int apic_enable_cpcovf_intr = 1; 134 135 /* vector at which CMCI interrupts come in */ 136 int apic_cmci_vect; 137 extern int cmi_enable_cmci; 138 extern void cmi_cmci_trap(void); 139 140 static kmutex_t cmci_cpu_setup_lock; /* protects cmci_cpu_setup_registered */ 141 static int cmci_cpu_setup_registered; 142 143 /* 144 * The following vector assignments influence the value of ipltopri and 145 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 146 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 147 * we care to do so in future. Note some IPLs which are rarely used 148 * will share the vector ranges and heavily used IPLs (5 and 6) have 149 * a wide range. 150 * 151 * This array is used to initialize apic_ipls[] (in apic_init()). 152 * 153 * IPL Vector range. as passed to intr_enter 154 * 0 none. 155 * 1,2,3 0x20-0x2f 0x0-0xf 156 * 4 0x30-0x3f 0x10-0x1f 157 * 5 0x40-0x5f 0x20-0x3f 158 * 6 0x60-0x7f 0x40-0x5f 159 * 7,8,9 0x80-0x8f 0x60-0x6f 160 * 10 0x90-0x9f 0x70-0x7f 161 * 11 0xa0-0xaf 0x80-0x8f 162 * ... ... 163 * 15 0xe0-0xef 0xc0-0xcf 164 * 15 0xf0-0xff 0xd0-0xdf 165 */ 166 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 167 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 168 }; 169 /* 170 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 171 * NOTE that this is vector as passed into intr_enter which is 172 * programmed vector - 0x20 (APIC_BASE_VECT) 173 */ 174 175 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 176 /* The taskpri to be programmed into apic to mask given ipl */ 177 178 #if defined(__amd64) 179 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */ 180 #endif 181 182 /* 183 * Correlation of the hardware vector to the IPL in use, initialized 184 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 185 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 186 * connected to errata-stricken IOAPICs 187 */ 188 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 189 190 /* 191 * Patchable global variables. 192 */ 193 int apic_forceload = 0; 194 195 int apic_coarse_hrtime = 1; /* 0 - use accurate slow gethrtime() */ 196 /* 1 - use gettime() for performance */ 197 int apic_flat_model = 0; /* 0 - clustered. 1 - flat */ 198 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 199 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 200 int apic_panic_on_nmi = 0; 201 int apic_panic_on_apic_error = 0; 202 203 int apic_verbose = 0; 204 205 /* minimum number of timer ticks to program to */ 206 int apic_min_timer_ticks = 1; 207 /* 208 * Local static data 209 */ 210 static struct psm_ops apic_ops = { 211 apic_probe, 212 213 apic_init, 214 apic_picinit, 215 apic_intr_enter, 216 apic_intr_exit, 217 apic_setspl, 218 apic_addspl, 219 apic_delspl, 220 apic_disable_intr, 221 apic_enable_intr, 222 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 223 (void (*)(int))NULL, /* psm_set_softintr */ 224 225 apic_set_idlecpu, 226 apic_unset_idlecpu, 227 228 apic_clkinit, 229 apic_getclkirq, 230 (void (*)(void))NULL, /* psm_hrtimeinit */ 231 apic_gethrtime, 232 233 apic_get_next_processorid, 234 apic_cpu_start, 235 apic_post_cpu_start, 236 apic_shutdown, 237 apic_get_ipivect, 238 apic_send_ipi, 239 240 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 241 (void (*)(int, char *))NULL, /* psm_notify_error */ 242 (void (*)(int))NULL, /* psm_notify_func */ 243 apic_timer_reprogram, 244 apic_timer_enable, 245 apic_timer_disable, 246 apic_post_cyclic_setup, 247 apic_preshutdown, 248 apic_intr_ops, /* Advanced DDI Interrupt framework */ 249 apic_state, /* save, restore apic state for S3 */ 250 }; 251 252 253 static struct psm_info apic_psm_info = { 254 PSM_INFO_VER01_6, /* version */ 255 PSM_OWN_EXCLUSIVE, /* ownership */ 256 (struct psm_ops *)&apic_ops, /* operation */ 257 APIC_PCPLUSMP_NAME, /* machine name */ 258 "pcplusmp v1.4 compatible", 259 }; 260 261 static void *apic_hdlp; 262 263 #ifdef DEBUG 264 int apic_debug = 0; 265 int apic_restrict_vector = 0; 266 267 int apic_debug_msgbuf[APIC_DEBUG_MSGBUFSIZE]; 268 int apic_debug_msgbufindex = 0; 269 270 #endif /* DEBUG */ 271 272 apic_cpus_info_t *apic_cpus; 273 274 cpuset_t apic_cpumask; 275 uint_t apic_picinit_called; 276 277 /* Flag to indicate that we need to shut down all processors */ 278 static uint_t apic_shutdown_processors; 279 280 uint_t apic_nsec_per_intr = 0; 281 282 /* 283 * apic_let_idle_redistribute can have the following values: 284 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute. 285 * apic_redistribute_lock prevents multiple idle cpus from redistributing 286 */ 287 int apic_num_idle_redistributions = 0; 288 static int apic_let_idle_redistribute = 0; 289 static uint_t apic_nticks = 0; 290 static uint_t apic_skipped_redistribute = 0; 291 292 /* to gather intr data and redistribute */ 293 static void apic_redistribute_compute(void); 294 295 static uint_t last_count_read = 0; 296 static lock_t apic_gethrtime_lock; 297 volatile int apic_hrtime_stamp = 0; 298 volatile hrtime_t apic_nsec_since_boot = 0; 299 static uint_t apic_hertz_count; 300 301 uint64_t apic_ticks_per_SFnsecs; /* # of ticks in SF nsecs */ 302 303 static hrtime_t apic_nsec_max; 304 305 static hrtime_t apic_last_hrtime = 0; 306 int apic_hrtime_error = 0; 307 int apic_remote_hrterr = 0; 308 int apic_num_nmis = 0; 309 int apic_apic_error = 0; 310 int apic_num_apic_errors = 0; 311 int apic_num_cksum_errors = 0; 312 313 int apic_error = 0; 314 static int apic_cmos_ssb_set = 0; 315 316 /* use to make sure only one cpu handles the nmi */ 317 static lock_t apic_nmi_lock; 318 /* use to make sure only one cpu handles the error interrupt */ 319 static lock_t apic_error_lock; 320 321 static struct { 322 uchar_t cntl; 323 uchar_t data; 324 } aspen_bmc[] = { 325 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 326 { CC_SMS_WR_NEXT, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 327 { CC_SMS_WR_NEXT, 0x84 }, /* DataByte 1: SMS/OS no log */ 328 { CC_SMS_WR_NEXT, 0x2 }, /* DataByte 2: Power Down */ 329 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 3: no pre-timeout */ 330 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 4: timer expir. */ 331 { CC_SMS_WR_NEXT, 0xa }, /* DataByte 5: init countdown */ 332 { CC_SMS_WR_END, 0x0 }, /* DataByte 6: init countdown */ 333 334 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 335 { CC_SMS_WR_END, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 336 }; 337 338 static struct { 339 int port; 340 uchar_t data; 341 } sitka_bmc[] = { 342 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 343 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 344 { SMS_DATA_REGISTER, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 345 { SMS_DATA_REGISTER, 0x84 }, /* DataByte 1: SMS/OS no log */ 346 { SMS_DATA_REGISTER, 0x2 }, /* DataByte 2: Power Down */ 347 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 3: no pre-timeout */ 348 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 4: timer expir. */ 349 { SMS_DATA_REGISTER, 0xa }, /* DataByte 5: init countdown */ 350 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 351 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 6: init countdown */ 352 353 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 354 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 355 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 356 { SMS_DATA_REGISTER, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 357 }; 358 359 /* Patchable global variables. */ 360 int apic_kmdb_on_nmi = 0; /* 0 - no, 1 - yes enter kmdb */ 361 uint32_t apic_divide_reg_init = 0; /* 0 - divide by 2 */ 362 363 /* 364 * This is the loadable module wrapper 365 */ 366 367 int 368 _init(void) 369 { 370 if (apic_coarse_hrtime) 371 apic_ops.psm_gethrtime = &apic_gettime; 372 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 373 } 374 375 int 376 _fini(void) 377 { 378 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 379 } 380 381 int 382 _info(struct modinfo *modinfop) 383 { 384 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 385 } 386 387 388 static int 389 apic_probe() 390 { 391 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 392 } 393 394 void 395 apic_init() 396 { 397 int i; 398 int j = 1; 399 400 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 401 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 402 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 403 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 404 /* get to highest vector at the same ipl */ 405 continue; 406 for (; j <= apic_vectortoipl[i]; j++) { 407 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 408 APIC_BASE_VECT; 409 } 410 } 411 for (; j < MAXIPL + 1; j++) 412 /* fill up any empty ipltopri slots */ 413 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 414 apic_init_common(); 415 #if defined(__amd64) 416 /* 417 * Make cpu-specific interrupt info point to cr8pri vector 418 */ 419 for (i = 0; i <= MAXIPL; i++) 420 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT; 421 CPU->cpu_pri_data = apic_cr8pri; 422 #endif /* __amd64 */ 423 } 424 425 /* 426 * handler for APIC Error interrupt. Just print a warning and continue 427 */ 428 static int 429 apic_error_intr() 430 { 431 uint_t error0, error1, error; 432 uint_t i; 433 434 /* 435 * We need to write before read as per 7.4.17 of system prog manual. 436 * We do both and or the results to be safe 437 */ 438 error0 = apic_reg_ops->apic_read(APIC_ERROR_STATUS); 439 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 440 error1 = apic_reg_ops->apic_read(APIC_ERROR_STATUS); 441 error = error0 | error1; 442 443 /* 444 * Clear the APIC error status (do this on all cpus that enter here) 445 * (two writes are required due to the semantics of accessing the 446 * error status register.) 447 */ 448 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 449 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 450 451 /* 452 * Prevent more than 1 CPU from handling error interrupt causing 453 * double printing (interleave of characters from multiple 454 * CPU's when using prom_printf) 455 */ 456 if (lock_try(&apic_error_lock) == 0) 457 return (error ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 458 if (error) { 459 #if DEBUG 460 if (apic_debug) 461 debug_enter("pcplusmp: APIC Error interrupt received"); 462 #endif /* DEBUG */ 463 if (apic_panic_on_apic_error) 464 cmn_err(CE_PANIC, 465 "APIC Error interrupt on CPU %d. Status = %x\n", 466 psm_get_cpu_id(), error); 467 else { 468 if ((error & ~APIC_CS_ERRORS) == 0) { 469 /* cksum error only */ 470 apic_error |= APIC_ERR_APIC_ERROR; 471 apic_apic_error |= error; 472 apic_num_apic_errors++; 473 apic_num_cksum_errors++; 474 } else { 475 /* 476 * prom_printf is the best shot we have of 477 * something which is problem free from 478 * high level/NMI type of interrupts 479 */ 480 prom_printf("APIC Error interrupt on CPU %d. " 481 "Status 0 = %x, Status 1 = %x\n", 482 psm_get_cpu_id(), error0, error1); 483 apic_error |= APIC_ERR_APIC_ERROR; 484 apic_apic_error |= error; 485 apic_num_apic_errors++; 486 for (i = 0; i < apic_error_display_delay; i++) { 487 tenmicrosec(); 488 } 489 /* 490 * provide more delay next time limited to 491 * roughly 1 clock tick time 492 */ 493 if (apic_error_display_delay < 500) 494 apic_error_display_delay *= 2; 495 } 496 } 497 lock_clear(&apic_error_lock); 498 return (DDI_INTR_CLAIMED); 499 } else { 500 lock_clear(&apic_error_lock); 501 return (DDI_INTR_UNCLAIMED); 502 } 503 /* NOTREACHED */ 504 } 505 506 /* 507 * Turn off the mask bit in the performance counter Local Vector Table entry. 508 */ 509 static void 510 apic_cpcovf_mask_clear(void) 511 { 512 apic_reg_ops->apic_write(APIC_PCINT_VECT, 513 (apic_reg_ops->apic_read(APIC_PCINT_VECT) & ~APIC_LVT_MASK)); 514 } 515 516 /*ARGSUSED*/ 517 static int 518 apic_cmci_enable(xc_arg_t arg1, xc_arg_t arg2, xc_arg_t arg3) 519 { 520 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 521 return (0); 522 } 523 524 /*ARGSUSED*/ 525 static int 526 apic_cmci_disable(xc_arg_t arg1, xc_arg_t arg2, xc_arg_t arg3) 527 { 528 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect | AV_MASK); 529 return (0); 530 } 531 532 /*ARGSUSED*/ 533 static int 534 cmci_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 535 { 536 cpuset_t cpu_set; 537 538 CPUSET_ONLY(cpu_set, cpuid); 539 540 switch (what) { 541 case CPU_ON: 542 xc_call(NULL, NULL, NULL, X_CALL_HIPRI, cpu_set, 543 (xc_func_t)apic_cmci_enable); 544 break; 545 546 case CPU_OFF: 547 xc_call(NULL, NULL, NULL, X_CALL_HIPRI, cpu_set, 548 (xc_func_t)apic_cmci_disable); 549 break; 550 551 default: 552 break; 553 } 554 555 return (0); 556 } 557 558 static void 559 apic_init_intr() 560 { 561 processorid_t cpun = psm_get_cpu_id(); 562 uint_t nlvt; 563 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 564 565 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 566 567 if (apic_mode == LOCAL_APIC) { 568 /* 569 * We are running APIC in MMIO mode. 570 */ 571 if (apic_flat_model) { 572 apic_reg_ops->apic_write(APIC_FORMAT_REG, 573 APIC_FLAT_MODEL); 574 } else { 575 apic_reg_ops->apic_write(APIC_FORMAT_REG, 576 APIC_CLUSTER_MODEL); 577 } 578 579 apic_reg_ops->apic_write(APIC_DEST_REG, 580 AV_HIGH_ORDER >> cpun); 581 } 582 583 if (apic_direct_EOI) { 584 /* 585 * Set 12th bit in Spurious Interrupt Vector 586 * Register to support level triggered interrupt 587 * directed EOI. 588 */ 589 svr |= (0x1 << APIC_SVR); 590 } 591 592 /* need to enable APIC before unmasking NMI */ 593 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 594 595 /* 596 * Presence of an invalid vector with delivery mode AV_FIXED can 597 * cause an error interrupt, even if the entry is masked...so 598 * write a valid vector to LVT entries along with the mask bit 599 */ 600 601 /* All APICs have timer and LINT0/1 */ 602 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 603 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 604 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 605 606 /* 607 * On integrated APICs, the number of LVT entries is 608 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 609 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 610 */ 611 612 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 613 nlvt = 3; 614 } else { 615 nlvt = ((apicadr[APIC_VERS_REG] >> 16) & 0xFF) + 1; 616 } 617 618 if (nlvt >= 5) { 619 /* Enable performance counter overflow interrupt */ 620 621 if ((x86_feature & X86_MSR) != X86_MSR) 622 apic_enable_cpcovf_intr = 0; 623 if (apic_enable_cpcovf_intr) { 624 if (apic_cpcovf_vect == 0) { 625 int ipl = APIC_PCINT_IPL; 626 int irq = apic_get_ipivect(ipl, -1); 627 628 ASSERT(irq != -1); 629 apic_cpcovf_vect = 630 apic_irq_table[irq]->airq_vector; 631 ASSERT(apic_cpcovf_vect); 632 (void) add_avintr(NULL, ipl, 633 (avfunc)kcpc_hw_overflow_intr, 634 "apic pcint", irq, NULL, NULL, NULL, NULL); 635 kcpc_hw_overflow_intr_installed = 1; 636 kcpc_hw_enable_cpc_intr = 637 apic_cpcovf_mask_clear; 638 } 639 apic_reg_ops->apic_write(APIC_PCINT_VECT, 640 apic_cpcovf_vect); 641 } 642 } 643 644 if (nlvt >= 6) { 645 /* Only mask TM intr if the BIOS apparently doesn't use it */ 646 647 uint32_t lvtval; 648 649 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 650 if (((lvtval & AV_MASK) == AV_MASK) || 651 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 652 apic_reg_ops->apic_write(APIC_THERM_VECT, 653 AV_MASK|APIC_RESV_IRQ); 654 } 655 } 656 657 /* Enable error interrupt */ 658 659 if (nlvt >= 4 && apic_enable_error_intr) { 660 if (apic_errvect == 0) { 661 int ipl = 0xf; /* get highest priority intr */ 662 int irq = apic_get_ipivect(ipl, -1); 663 664 ASSERT(irq != -1); 665 apic_errvect = apic_irq_table[irq]->airq_vector; 666 ASSERT(apic_errvect); 667 /* 668 * Not PSMI compliant, but we are going to merge 669 * with ON anyway 670 */ 671 (void) add_avintr((void *)NULL, ipl, 672 (avfunc)apic_error_intr, "apic error intr", 673 irq, NULL, NULL, NULL, NULL); 674 } 675 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 676 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 677 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 678 } 679 680 /* Enable CMCI interrupt */ 681 if (cmi_enable_cmci) { 682 683 mutex_enter(&cmci_cpu_setup_lock); 684 if (cmci_cpu_setup_registered == 0) { 685 mutex_enter(&cpu_lock); 686 register_cpu_setup_func(cmci_cpu_setup, NULL); 687 mutex_exit(&cpu_lock); 688 cmci_cpu_setup_registered = 1; 689 } 690 mutex_exit(&cmci_cpu_setup_lock); 691 692 if (apic_cmci_vect == 0) { 693 int ipl = 0x2; 694 int irq = apic_get_ipivect(ipl, -1); 695 696 ASSERT(irq != -1); 697 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 698 ASSERT(apic_cmci_vect); 699 700 (void) add_avintr(NULL, ipl, 701 (avfunc)cmi_cmci_trap, 702 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 703 } 704 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 705 } 706 } 707 708 static void 709 apic_disable_local_apic() 710 { 711 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 712 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK); 713 714 /* local intr reg 0 */ 715 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK); 716 717 /* disable NMI */ 718 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_MASK); 719 720 /* and error interrupt */ 721 apic_reg_ops->apic_write(APIC_ERR_VECT, AV_MASK); 722 723 /* and perf counter intr */ 724 apic_reg_ops->apic_write(APIC_PCINT_VECT, AV_MASK); 725 726 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, APIC_SPUR_INTR); 727 } 728 729 static void 730 apic_picinit(void) 731 { 732 int i, j; 733 uint_t isr; 734 uint32_t ver; 735 736 /* 737 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 738 * bit on without clearing it with EOI. Since softint 739 * uses vector 0x20 to interrupt itself, so softint will 740 * not work on this machine. In order to fix this problem 741 * a check is made to verify all the isr bits are clear. 742 * If not, EOIs are issued to clear the bits. 743 */ 744 for (i = 7; i >= 1; i--) { 745 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 746 if (isr != 0) 747 for (j = 0; ((j < 32) && (isr != 0)); j++) 748 if (isr & (1 << j)) { 749 apic_reg_ops->apic_write( 750 APIC_EOI_REG, 0); 751 isr &= ~(1 << j); 752 apic_error |= APIC_ERR_BOOT_EOI; 753 } 754 } 755 756 /* set a flag so we know we have run apic_picinit() */ 757 apic_picinit_called = 1; 758 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 759 LOCK_INIT_CLEAR(&apic_ioapic_lock); 760 LOCK_INIT_CLEAR(&apic_error_lock); 761 762 picsetup(); /* initialise the 8259 */ 763 764 /* add nmi handler - least priority nmi handler */ 765 LOCK_INIT_CLEAR(&apic_nmi_lock); 766 767 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 768 "pcplusmp NMI handler", (caddr_t)NULL)) 769 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 770 771 ver = apic_reg_ops->apic_read(APIC_VERS_REG); 772 /* 773 * In order to determine support for Directed EOI capability, 774 * we check for 24th bit in Local APIC Version Register. 775 */ 776 if (ver & (0x1 << APIC_DIRECTED_EOI)) { 777 apic_direct_EOI = 1; 778 apic_change_eoi(); 779 } 780 781 apic_init_intr(); 782 783 /* enable apic mode if imcr present */ 784 if (apic_imcrp) { 785 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 786 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 787 } 788 789 ioapic_init_intr(IOAPIC_MASK); 790 } 791 792 793 /*ARGSUSED1*/ 794 static int 795 apic_cpu_start(processorid_t cpun, caddr_t arg) 796 { 797 int loop_count; 798 uint32_t vector; 799 uint_t cpu_id; 800 ulong_t iflag; 801 802 cpu_id = apic_cpus[cpun].aci_local_id; 803 804 apic_cmos_ssb_set = 1; 805 806 /* 807 * Interrupts on BSP cpu will be disabled during these startup 808 * steps in order to avoid unwanted side effects from 809 * executing interrupt handlers on a problematic BIOS. 810 */ 811 812 iflag = intr_clear(); 813 outb(CMOS_ADDR, SSB); 814 outb(CMOS_DATA, BIOS_SHUTDOWN); 815 816 /* 817 * According to X2APIC specification in section '2.3.5.1' of 818 * Interrupt Command Register Semantics, the semantics of 819 * programming the Interrupt Command Register to dispatch an interrupt 820 * is simplified. A single MSR write to the 64-bit ICR is required 821 * for dispatching an interrupt. Specifically, with the 64-bit MSR 822 * interface to ICR, system software is not required to check the 823 * status of the delivery status bit prior to writing to the ICR 824 * to send an IPI. With the removal of the Delivery Status bit, 825 * system software no longer has a reason to read the ICR. It remains 826 * readable only to aid in debugging. 827 */ 828 #ifdef DEBUG 829 APIC_AV_PENDING_SET(); 830 #else 831 if (apic_mode == LOCAL_APIC) { 832 APIC_AV_PENDING_SET(); 833 } 834 #endif /* DEBUG */ 835 836 /* for integrated - make sure there is one INIT IPI in buffer */ 837 /* for external - it will wake up the cpu */ 838 apic_reg_ops->apic_write_int_cmd(cpu_id, AV_ASSERT | AV_RESET); 839 840 /* If only 1 CPU is installed, PENDING bit will not go low */ 841 for (loop_count = 0x1000; loop_count; loop_count--) { 842 if (apic_mode == LOCAL_APIC && 843 apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) 844 apic_ret(); 845 else 846 break; 847 } 848 849 apic_reg_ops->apic_write_int_cmd(cpu_id, AV_DEASSERT | AV_RESET); 850 851 drv_usecwait(20000); /* 20 milli sec */ 852 853 if (apic_cpus[cpun].aci_local_ver >= APIC_INTEGRATED_VERS) { 854 /* integrated apic */ 855 856 vector = (rm_platter_pa >> MMU_PAGESHIFT) & 857 (APIC_VECTOR_MASK | APIC_IPL_MASK); 858 859 /* to offset the INIT IPI queue up in the buffer */ 860 apic_reg_ops->apic_write_int_cmd(cpu_id, vector | AV_STARTUP); 861 862 drv_usecwait(200); /* 20 micro sec */ 863 864 apic_reg_ops->apic_write_int_cmd(cpu_id, vector | AV_STARTUP); 865 866 drv_usecwait(200); /* 20 micro sec */ 867 } 868 intr_restore(iflag); 869 return (0); 870 } 871 872 873 #ifdef DEBUG 874 int apic_break_on_cpu = 9; 875 int apic_stretch_interrupts = 0; 876 int apic_stretch_ISR = 1 << 3; /* IPL of 3 matches nothing now */ 877 878 void 879 apic_break() 880 { 881 } 882 #endif /* DEBUG */ 883 884 /* 885 * platform_intr_enter 886 * 887 * Called at the beginning of the interrupt service routine to 888 * mask all level equal to and below the interrupt priority 889 * of the interrupting vector. An EOI should be given to 890 * the interrupt controller to enable other HW interrupts. 891 * 892 * Return -1 for spurious interrupts 893 * 894 */ 895 /*ARGSUSED*/ 896 static int 897 apic_intr_enter(int ipl, int *vectorp) 898 { 899 uchar_t vector; 900 int nipl; 901 int irq; 902 ulong_t iflag; 903 apic_cpus_info_t *cpu_infop; 904 905 /* 906 * The real vector delivered is (*vectorp + 0x20), but our caller 907 * subtracts 0x20 from the vector before passing it to us. 908 * (That's why APIC_BASE_VECT is 0x20.) 909 */ 910 vector = (uchar_t)*vectorp; 911 912 /* if interrupted by the clock, increment apic_nsec_since_boot */ 913 if (vector == apic_clkvect) { 914 if (!apic_oneshot) { 915 /* NOTE: this is not MT aware */ 916 apic_hrtime_stamp++; 917 apic_nsec_since_boot += apic_nsec_per_intr; 918 apic_hrtime_stamp++; 919 last_count_read = apic_hertz_count; 920 apic_redistribute_compute(); 921 } 922 923 /* We will avoid all the book keeping overhead for clock */ 924 nipl = apic_ipls[vector]; 925 926 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 927 if (apic_mode == LOCAL_APIC) { 928 #if defined(__amd64) 929 setcr8((ulong_t)(apic_ipltopri[nipl] >> 930 APIC_IPL_SHIFT)); 931 #else 932 LOCAL_APIC_WRITE_REG(APIC_TASK_REG, 933 (uint32_t)apic_ipltopri[nipl]); 934 #endif 935 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 936 } else { 937 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]); 938 X2APIC_WRITE(APIC_EOI_REG, 0); 939 } 940 941 return (nipl); 942 } 943 944 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 945 946 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 947 cpu_infop->aci_spur_cnt++; 948 return (APIC_INT_SPURIOUS); 949 } 950 951 /* Check if the vector we got is really what we need */ 952 if (apic_revector_pending) { 953 /* 954 * Disable interrupts for the duration of 955 * the vector translation to prevent a self-race for 956 * the apic_revector_lock. This cannot be done 957 * in apic_xlate_vector because it is recursive and 958 * we want the vector translation to be atomic with 959 * respect to other (higher-priority) interrupts. 960 */ 961 iflag = intr_clear(); 962 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 963 APIC_BASE_VECT; 964 intr_restore(iflag); 965 } 966 967 nipl = apic_ipls[vector]; 968 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 969 970 if (apic_mode == LOCAL_APIC) { 971 #if defined(__amd64) 972 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT)); 973 #else 974 LOCAL_APIC_WRITE_REG(APIC_TASK_REG, 975 (uint32_t)apic_ipltopri[nipl]); 976 #endif 977 } else { 978 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]); 979 } 980 981 cpu_infop->aci_current[nipl] = (uchar_t)irq; 982 cpu_infop->aci_curipl = (uchar_t)nipl; 983 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 984 985 /* 986 * apic_level_intr could have been assimilated into the irq struct. 987 * but, having it as a character array is more efficient in terms of 988 * cache usage. So, we leave it as is. 989 */ 990 if (!apic_level_intr[irq]) { 991 if (apic_mode == LOCAL_APIC) 992 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 993 else 994 X2APIC_WRITE(APIC_EOI_REG, 0); 995 } 996 997 #ifdef DEBUG 998 APIC_DEBUG_BUF_PUT(vector); 999 APIC_DEBUG_BUF_PUT(irq); 1000 APIC_DEBUG_BUF_PUT(nipl); 1001 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 1002 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 1003 drv_usecwait(apic_stretch_interrupts); 1004 1005 if (apic_break_on_cpu == psm_get_cpu_id()) 1006 apic_break(); 1007 #endif /* DEBUG */ 1008 return (nipl); 1009 } 1010 1011 /* 1012 * This macro is a common code used by MMIO local apic and X2APIC 1013 * local apic. 1014 */ 1015 #define APIC_INTR_EXIT() \ 1016 { \ 1017 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \ 1018 if (apic_level_intr[irq]) \ 1019 apic_reg_ops->apic_send_eoi(irq); \ 1020 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \ 1021 /* ISR above current pri could not be in progress */ \ 1022 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \ 1023 } 1024 1025 /* 1026 * Any changes made to this function must also change X2APIC 1027 * version of intr_exit. 1028 */ 1029 void 1030 apic_intr_exit(int prev_ipl, int irq) 1031 { 1032 apic_cpus_info_t *cpu_infop; 1033 1034 #if defined(__amd64) 1035 setcr8((ulong_t)apic_cr8pri[prev_ipl]); 1036 #else 1037 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl]; 1038 #endif 1039 1040 APIC_INTR_EXIT(); 1041 } 1042 1043 /* 1044 * Same as apic_intr_exit() except it uses MSR rather than MMIO 1045 * to access local apic registers. 1046 */ 1047 void 1048 x2apic_intr_exit(int prev_ipl, int irq) 1049 { 1050 apic_cpus_info_t *cpu_infop; 1051 1052 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]); 1053 APIC_INTR_EXIT(); 1054 } 1055 1056 intr_exit_fn_t 1057 psm_intr_exit_fn(void) 1058 { 1059 if (apic_mode == LOCAL_X2APIC) 1060 return (x2apic_intr_exit); 1061 1062 return (apic_intr_exit); 1063 } 1064 1065 /* 1066 * Mask all interrupts below or equal to the given IPL. 1067 * Any changes made to this function must also change X2APIC 1068 * version of setspl. 1069 */ 1070 static void 1071 apic_setspl(int ipl) 1072 { 1073 #if defined(__amd64) 1074 setcr8((ulong_t)apic_cr8pri[ipl]); 1075 #else 1076 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl]; 1077 #endif 1078 1079 /* interrupts at ipl above this cannot be in progress */ 1080 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 1081 /* 1082 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 1083 * have enough time to come in before the priority is raised again 1084 * during the idle() loop. 1085 */ 1086 if (apic_setspl_delay) 1087 (void) apic_reg_ops->apic_get_pri(); 1088 } 1089 1090 /* 1091 * X2APIC version of setspl. 1092 * Mask all interrupts below or equal to the given IPL 1093 */ 1094 static void 1095 x2apic_setspl(int ipl) 1096 { 1097 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]); 1098 1099 /* interrupts at ipl above this cannot be in progress */ 1100 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 1101 } 1102 1103 /* 1104 * generates an interprocessor interrupt to another CPU. Any changes made to 1105 * this routine must be accompanied by similar changes to 1106 * apic_common_send_ipi(). 1107 */ 1108 static void 1109 apic_send_ipi(int cpun, int ipl) 1110 { 1111 int vector; 1112 ulong_t flag; 1113 1114 vector = apic_resv_vector[ipl]; 1115 1116 ASSERT((vector >= APIC_BASE_VECT) && (vector <= APIC_SPUR_INTR)); 1117 1118 flag = intr_clear(); 1119 1120 APIC_AV_PENDING_SET(); 1121 1122 apic_reg_ops->apic_write_int_cmd(apic_cpus[cpun].aci_local_id, 1123 vector); 1124 1125 intr_restore(flag); 1126 } 1127 1128 1129 /*ARGSUSED*/ 1130 static void 1131 apic_set_idlecpu(processorid_t cpun) 1132 { 1133 } 1134 1135 /*ARGSUSED*/ 1136 static void 1137 apic_unset_idlecpu(processorid_t cpun) 1138 { 1139 } 1140 1141 1142 void 1143 apic_ret() 1144 { 1145 } 1146 1147 /* 1148 * If apic_coarse_time == 1, then apic_gettime() is used instead of 1149 * apic_gethrtime(). This is used for performance instead of accuracy. 1150 */ 1151 1152 static hrtime_t 1153 apic_gettime() 1154 { 1155 int old_hrtime_stamp; 1156 hrtime_t temp; 1157 1158 /* 1159 * In one-shot mode, we do not keep time, so if anyone 1160 * calls psm_gettime() directly, we vector over to 1161 * gethrtime(). 1162 * one-shot mode MUST NOT be enabled if this psm is the source of 1163 * hrtime. 1164 */ 1165 1166 if (apic_oneshot) 1167 return (gethrtime()); 1168 1169 1170 gettime_again: 1171 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 1172 apic_ret(); 1173 1174 temp = apic_nsec_since_boot; 1175 1176 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 1177 goto gettime_again; 1178 } 1179 return (temp); 1180 } 1181 1182 /* 1183 * Here we return the number of nanoseconds since booting. Note every 1184 * clock interrupt increments apic_nsec_since_boot by the appropriate 1185 * amount. 1186 */ 1187 static hrtime_t 1188 apic_gethrtime() 1189 { 1190 int curr_timeval, countval, elapsed_ticks; 1191 int old_hrtime_stamp, status; 1192 hrtime_t temp; 1193 uint32_t cpun; 1194 ulong_t oflags; 1195 1196 /* 1197 * In one-shot mode, we do not keep time, so if anyone 1198 * calls psm_gethrtime() directly, we vector over to 1199 * gethrtime(). 1200 * one-shot mode MUST NOT be enabled if this psm is the source of 1201 * hrtime. 1202 */ 1203 1204 if (apic_oneshot) 1205 return (gethrtime()); 1206 1207 oflags = intr_clear(); /* prevent migration */ 1208 1209 cpun = apic_reg_ops->apic_read(APIC_LID_REG); 1210 if (apic_mode == LOCAL_APIC) 1211 cpun >>= APIC_ID_BIT_OFFSET; 1212 1213 lock_set(&apic_gethrtime_lock); 1214 1215 gethrtime_again: 1216 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 1217 apic_ret(); 1218 1219 /* 1220 * Check to see which CPU we are on. Note the time is kept on 1221 * the local APIC of CPU 0. If on CPU 0, simply read the current 1222 * counter. If on another CPU, issue a remote read command to CPU 0. 1223 */ 1224 if (cpun == apic_cpus[0].aci_local_id) { 1225 countval = apic_reg_ops->apic_read(APIC_CURR_COUNT); 1226 } else { 1227 #ifdef DEBUG 1228 APIC_AV_PENDING_SET(); 1229 #else 1230 if (apic_mode == LOCAL_APIC) 1231 APIC_AV_PENDING_SET(); 1232 #endif /* DEBUG */ 1233 1234 apic_reg_ops->apic_write_int_cmd( 1235 apic_cpus[0].aci_local_id, APIC_CURR_ADD | AV_REMOTE); 1236 1237 while ((status = apic_reg_ops->apic_read(APIC_INT_CMD1)) 1238 & AV_READ_PENDING) { 1239 apic_ret(); 1240 } 1241 1242 if (status & AV_REMOTE_STATUS) /* 1 = valid */ 1243 countval = apic_reg_ops->apic_read(APIC_REMOTE_READ); 1244 else { /* 0 = invalid */ 1245 apic_remote_hrterr++; 1246 /* 1247 * return last hrtime right now, will need more 1248 * testing if change to retry 1249 */ 1250 temp = apic_last_hrtime; 1251 1252 lock_clear(&apic_gethrtime_lock); 1253 1254 intr_restore(oflags); 1255 1256 return (temp); 1257 } 1258 } 1259 if (countval > last_count_read) 1260 countval = 0; 1261 else 1262 last_count_read = countval; 1263 1264 elapsed_ticks = apic_hertz_count - countval; 1265 1266 curr_timeval = APIC_TICKS_TO_NSECS(elapsed_ticks); 1267 temp = apic_nsec_since_boot + curr_timeval; 1268 1269 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 1270 /* we might have clobbered last_count_read. Restore it */ 1271 last_count_read = apic_hertz_count; 1272 goto gethrtime_again; 1273 } 1274 1275 if (temp < apic_last_hrtime) { 1276 /* return last hrtime if error occurs */ 1277 apic_hrtime_error++; 1278 temp = apic_last_hrtime; 1279 } 1280 else 1281 apic_last_hrtime = temp; 1282 1283 lock_clear(&apic_gethrtime_lock); 1284 intr_restore(oflags); 1285 1286 return (temp); 1287 } 1288 1289 /* apic NMI handler */ 1290 /*ARGSUSED*/ 1291 static void 1292 apic_nmi_intr(caddr_t arg, struct regs *rp) 1293 { 1294 if (apic_shutdown_processors) { 1295 apic_disable_local_apic(); 1296 return; 1297 } 1298 1299 apic_error |= APIC_ERR_NMI; 1300 1301 if (!lock_try(&apic_nmi_lock)) 1302 return; 1303 apic_num_nmis++; 1304 1305 if (apic_kmdb_on_nmi && psm_debugger()) { 1306 debug_enter("NMI received: entering kmdb\n"); 1307 } else if (apic_panic_on_nmi) { 1308 /* Keep panic from entering kmdb. */ 1309 nopanicdebug = 1; 1310 panic("NMI received\n"); 1311 } else { 1312 /* 1313 * prom_printf is the best shot we have of something which is 1314 * problem free from high level/NMI type of interrupts 1315 */ 1316 prom_printf("NMI received\n"); 1317 } 1318 1319 lock_clear(&apic_nmi_lock); 1320 } 1321 1322 /*ARGSUSED*/ 1323 static int 1324 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 1325 { 1326 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 1327 } 1328 1329 static int 1330 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 1331 { 1332 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 1333 } 1334 1335 static int 1336 apic_post_cpu_start() 1337 { 1338 int cpun; 1339 static int cpus_started = 1; 1340 struct psm_ops *pops = &apic_ops; 1341 1342 /* We know this CPU + BSP started successfully. */ 1343 cpus_started++; 1344 1345 /* 1346 * On BSP we would have enabled X2APIC, if supported by processor, 1347 * in acpi_probe(), but on AP we do it here. 1348 * 1349 * We enable X2APIC mode only if BSP is running in X2APIC & the 1350 * local APIC mode of the current CPU is MMIO (xAPIC). 1351 */ 1352 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() && 1353 apic_local_mode() == LOCAL_APIC) { 1354 apic_enable_x2apic(); 1355 } 1356 1357 /* 1358 * We change psm_send_ipi and send_dirintf only if Solaris 1359 * is booted in kmdb & the current CPU is the last CPU being 1360 * brought up. We don't need to do anything if Solaris is running 1361 * in MMIO mode (xAPIC). 1362 */ 1363 if ((boothowto & RB_DEBUG) && 1364 (cpus_started == boot_ncpus || cpus_started == apic_nproc) && 1365 apic_mode == LOCAL_X2APIC) { 1366 /* 1367 * We no longer need help from apic_common_send_ipi() 1368 * since we will not start any more CPUs. 1369 * 1370 * We will need to revisit this if we start supporting 1371 * hot-plugging of CPUs. 1372 */ 1373 pops->psm_send_ipi = x2apic_send_ipi; 1374 send_dirintf = pops->psm_send_ipi; 1375 } 1376 1377 splx(ipltospl(LOCK_LEVEL)); 1378 apic_init_intr(); 1379 1380 /* 1381 * since some systems don't enable the internal cache on the non-boot 1382 * cpus, so we have to enable them here 1383 */ 1384 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 1385 1386 #ifdef DEBUG 1387 APIC_AV_PENDING_SET(); 1388 #else 1389 if (apic_mode == LOCAL_APIC) 1390 APIC_AV_PENDING_SET(); 1391 #endif /* DEBUG */ 1392 1393 /* 1394 * We may be booting, or resuming from suspend; aci_status will 1395 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 1396 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 1397 */ 1398 cpun = psm_get_cpu_id(); 1399 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 1400 1401 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 1402 return (PSM_SUCCESS); 1403 } 1404 1405 processorid_t 1406 apic_get_next_processorid(processorid_t cpu_id) 1407 { 1408 1409 int i; 1410 1411 if (cpu_id == -1) 1412 return ((processorid_t)0); 1413 1414 for (i = cpu_id + 1; i < NCPU; i++) { 1415 if (CPU_IN_SET(apic_cpumask, i)) 1416 return (i); 1417 } 1418 1419 return ((processorid_t)-1); 1420 } 1421 1422 1423 /* 1424 * type == -1 indicates it is an internal request. Do not change 1425 * resv_vector for these requests 1426 */ 1427 static int 1428 apic_get_ipivect(int ipl, int type) 1429 { 1430 uchar_t vector; 1431 int irq; 1432 1433 if (irq = apic_allocate_irq(APIC_VECTOR(ipl))) { 1434 if (vector = apic_allocate_vector(ipl, irq, 1)) { 1435 apic_irq_table[irq]->airq_mps_intr_index = 1436 RESERVE_INDEX; 1437 apic_irq_table[irq]->airq_vector = vector; 1438 if (type != -1) { 1439 apic_resv_vector[ipl] = vector; 1440 } 1441 return (irq); 1442 } 1443 } 1444 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 1445 return (-1); /* shouldn't happen */ 1446 } 1447 1448 static int 1449 apic_getclkirq(int ipl) 1450 { 1451 int irq; 1452 1453 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 1454 return (-1); 1455 /* 1456 * Note the vector in apic_clkvect for per clock handling. 1457 */ 1458 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 1459 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 1460 apic_clkvect)); 1461 return (irq); 1462 } 1463 1464 1465 /* 1466 * Return the number of APIC clock ticks elapsed for 8245 to decrement 1467 * (APIC_TIME_COUNT + pit_ticks_adj) ticks. 1468 */ 1469 static uint_t 1470 apic_calibrate(volatile uint32_t *addr, uint16_t *pit_ticks_adj) 1471 { 1472 uint8_t pit_tick_lo; 1473 uint16_t pit_tick, target_pit_tick; 1474 uint32_t start_apic_tick, end_apic_tick; 1475 ulong_t iflag; 1476 uint32_t reg; 1477 1478 reg = addr + APIC_CURR_COUNT - apicadr; 1479 1480 iflag = intr_clear(); 1481 1482 do { 1483 pit_tick_lo = inb(PITCTR0_PORT); 1484 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1485 } while (pit_tick < APIC_TIME_MIN || 1486 pit_tick_lo <= APIC_LB_MIN || pit_tick_lo >= APIC_LB_MAX); 1487 1488 /* 1489 * Wait for the 8254 to decrement by 5 ticks to ensure 1490 * we didn't start in the middle of a tick. 1491 * Compare with 0x10 for the wrap around case. 1492 */ 1493 target_pit_tick = pit_tick - 5; 1494 do { 1495 pit_tick_lo = inb(PITCTR0_PORT); 1496 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1497 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 1498 1499 start_apic_tick = apic_reg_ops->apic_read(reg); 1500 1501 /* 1502 * Wait for the 8254 to decrement by 1503 * (APIC_TIME_COUNT + pit_ticks_adj) ticks 1504 */ 1505 target_pit_tick = pit_tick - APIC_TIME_COUNT; 1506 do { 1507 pit_tick_lo = inb(PITCTR0_PORT); 1508 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1509 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 1510 1511 end_apic_tick = apic_reg_ops->apic_read(reg); 1512 1513 *pit_ticks_adj = target_pit_tick - pit_tick; 1514 1515 intr_restore(iflag); 1516 1517 return (start_apic_tick - end_apic_tick); 1518 } 1519 1520 /* 1521 * Initialise the APIC timer on the local APIC of CPU 0 to the desired 1522 * frequency. Note at this stage in the boot sequence, the boot processor 1523 * is the only active processor. 1524 * hertz value of 0 indicates a one-shot mode request. In this case 1525 * the function returns the resolution (in nanoseconds) for the hardware 1526 * timer interrupt. If one-shot mode capability is not available, 1527 * the return value will be 0. apic_enable_oneshot is a global switch 1528 * for disabling the functionality. 1529 * A non-zero positive value for hertz indicates a periodic mode request. 1530 * In this case the hardware will be programmed to generate clock interrupts 1531 * at hertz frequency and returns the resolution of interrupts in 1532 * nanosecond. 1533 */ 1534 1535 static int 1536 apic_clkinit(int hertz) 1537 { 1538 uint_t apic_ticks = 0; 1539 uint_t pit_ticks; 1540 int ret; 1541 uint16_t pit_ticks_adj; 1542 static int firsttime = 1; 1543 1544 if (firsttime) { 1545 /* first time calibrate on CPU0 only */ 1546 1547 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 1548 apic_reg_ops->apic_write(APIC_INIT_COUNT, APIC_MAXVAL); 1549 apic_ticks = apic_calibrate(apicadr, &pit_ticks_adj); 1550 1551 /* total number of PIT ticks corresponding to apic_ticks */ 1552 pit_ticks = APIC_TIME_COUNT + pit_ticks_adj; 1553 1554 /* 1555 * Determine the number of nanoseconds per APIC clock tick 1556 * and then determine how many APIC ticks to interrupt at the 1557 * desired frequency 1558 * apic_ticks / (pitticks / PIT_HZ) = apic_ticks_per_s 1559 * (apic_ticks * PIT_HZ) / pitticks = apic_ticks_per_s 1560 * apic_ticks_per_ns = (apic_ticks * PIT_HZ) / (pitticks * 10^9) 1561 * pic_ticks_per_SFns = 1562 * (SF * apic_ticks * PIT_HZ) / (pitticks * 10^9) 1563 */ 1564 apic_ticks_per_SFnsecs = 1565 ((SF * apic_ticks * PIT_HZ) / 1566 ((uint64_t)pit_ticks * NANOSEC)); 1567 1568 /* the interval timer initial count is 32 bit max */ 1569 apic_nsec_max = APIC_TICKS_TO_NSECS(APIC_MAXVAL); 1570 firsttime = 0; 1571 } 1572 1573 if (hertz != 0) { 1574 /* periodic */ 1575 apic_nsec_per_intr = NANOSEC / hertz; 1576 apic_hertz_count = APIC_NSECS_TO_TICKS(apic_nsec_per_intr); 1577 } 1578 1579 apic_int_busy_mark = (apic_int_busy_mark * 1580 apic_sample_factor_redistribution) / 100; 1581 apic_int_free_mark = (apic_int_free_mark * 1582 apic_sample_factor_redistribution) / 100; 1583 apic_diff_for_redistribution = (apic_diff_for_redistribution * 1584 apic_sample_factor_redistribution) / 100; 1585 1586 if (hertz == 0) { 1587 /* requested one_shot */ 1588 if (!tsc_gethrtime_enable || !apic_oneshot_enable) 1589 return (0); 1590 apic_oneshot = 1; 1591 ret = (int)APIC_TICKS_TO_NSECS(1); 1592 } else { 1593 /* program the local APIC to interrupt at the given frequency */ 1594 apic_reg_ops->apic_write(APIC_INIT_COUNT, apic_hertz_count); 1595 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 1596 (apic_clkvect + APIC_BASE_VECT) | AV_TIME); 1597 apic_oneshot = 0; 1598 ret = NANOSEC / hertz; 1599 } 1600 1601 return (ret); 1602 1603 } 1604 1605 /* 1606 * apic_preshutdown: 1607 * Called early in shutdown whilst we can still access filesystems to do 1608 * things like loading modules which will be required to complete shutdown 1609 * after filesystems are all unmounted. 1610 */ 1611 static void 1612 apic_preshutdown(int cmd, int fcn) 1613 { 1614 APIC_VERBOSE_POWEROFF(("apic_preshutdown(%d,%d); m=%d a=%d\n", 1615 cmd, fcn, apic_poweroff_method, apic_enable_acpi)); 1616 1617 if ((cmd != A_SHUTDOWN) || (fcn != AD_POWEROFF)) { 1618 return; 1619 } 1620 } 1621 1622 static void 1623 apic_shutdown(int cmd, int fcn) 1624 { 1625 int restarts, attempts; 1626 int i; 1627 uchar_t byte; 1628 ulong_t iflag; 1629 1630 /* Send NMI to all CPUs except self to do per processor shutdown */ 1631 iflag = intr_clear(); 1632 #ifdef DEBUG 1633 APIC_AV_PENDING_SET(); 1634 #else 1635 if (apic_mode == LOCAL_APIC) 1636 APIC_AV_PENDING_SET(); 1637 #endif /* DEBUG */ 1638 apic_shutdown_processors = 1; 1639 apic_reg_ops->apic_write(APIC_INT_CMD1, 1640 AV_NMI | AV_LEVEL | AV_SH_ALL_EXCSELF); 1641 1642 /* restore cmos shutdown byte before reboot */ 1643 if (apic_cmos_ssb_set) { 1644 outb(CMOS_ADDR, SSB); 1645 outb(CMOS_DATA, 0); 1646 } 1647 1648 ioapic_disable_redirection(); 1649 1650 /* disable apic mode if imcr present */ 1651 if (apic_imcrp) { 1652 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 1653 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_PIC); 1654 } 1655 1656 apic_disable_local_apic(); 1657 1658 intr_restore(iflag); 1659 1660 /* remainder of function is for shutdown cases only */ 1661 if (cmd != A_SHUTDOWN) 1662 return; 1663 1664 /* 1665 * Switch system back into Legacy-Mode if using ACPI and 1666 * not powering-off. Some BIOSes need to remain in ACPI-mode 1667 * for power-off to succeed (Dell Dimension 4600) 1668 * Do not disable ACPI while doing fastreboot 1669 */ 1670 if (apic_enable_acpi && fcn != AD_POWEROFF && fcn != AD_FASTREBOOT) 1671 (void) AcpiDisable(); 1672 1673 if (fcn == AD_FASTREBOOT) { 1674 apicadr[APIC_INT_CMD1] = AV_ASSERT | AV_RESET | 1675 AV_SH_ALL_EXCSELF; 1676 } 1677 1678 /* remainder of function is for shutdown+poweroff case only */ 1679 if (fcn != AD_POWEROFF) 1680 return; 1681 1682 switch (apic_poweroff_method) { 1683 case APIC_POWEROFF_VIA_RTC: 1684 1685 /* select the extended NVRAM bank in the RTC */ 1686 outb(CMOS_ADDR, RTC_REGA); 1687 byte = inb(CMOS_DATA); 1688 outb(CMOS_DATA, (byte | EXT_BANK)); 1689 1690 outb(CMOS_ADDR, PFR_REG); 1691 1692 /* for Predator must toggle the PAB bit */ 1693 byte = inb(CMOS_DATA); 1694 1695 /* 1696 * clear power active bar, wakeup alarm and 1697 * kickstart 1698 */ 1699 byte &= ~(PAB_CBIT | WF_FLAG | KS_FLAG); 1700 outb(CMOS_DATA, byte); 1701 1702 /* delay before next write */ 1703 drv_usecwait(1000); 1704 1705 /* for S40 the following would suffice */ 1706 byte = inb(CMOS_DATA); 1707 1708 /* power active bar control bit */ 1709 byte |= PAB_CBIT; 1710 outb(CMOS_DATA, byte); 1711 1712 break; 1713 1714 case APIC_POWEROFF_VIA_ASPEN_BMC: 1715 restarts = 0; 1716 restart_aspen_bmc: 1717 if (++restarts == 3) 1718 break; 1719 attempts = 0; 1720 do { 1721 byte = inb(MISMIC_FLAG_REGISTER); 1722 byte &= MISMIC_BUSY_MASK; 1723 if (byte != 0) { 1724 drv_usecwait(1000); 1725 if (attempts >= 3) 1726 goto restart_aspen_bmc; 1727 ++attempts; 1728 } 1729 } while (byte != 0); 1730 outb(MISMIC_CNTL_REGISTER, CC_SMS_GET_STATUS); 1731 byte = inb(MISMIC_FLAG_REGISTER); 1732 byte |= 0x1; 1733 outb(MISMIC_FLAG_REGISTER, byte); 1734 i = 0; 1735 for (; i < (sizeof (aspen_bmc)/sizeof (aspen_bmc[0])); 1736 i++) { 1737 attempts = 0; 1738 do { 1739 byte = inb(MISMIC_FLAG_REGISTER); 1740 byte &= MISMIC_BUSY_MASK; 1741 if (byte != 0) { 1742 drv_usecwait(1000); 1743 if (attempts >= 3) 1744 goto restart_aspen_bmc; 1745 ++attempts; 1746 } 1747 } while (byte != 0); 1748 outb(MISMIC_CNTL_REGISTER, aspen_bmc[i].cntl); 1749 outb(MISMIC_DATA_REGISTER, aspen_bmc[i].data); 1750 byte = inb(MISMIC_FLAG_REGISTER); 1751 byte |= 0x1; 1752 outb(MISMIC_FLAG_REGISTER, byte); 1753 } 1754 break; 1755 1756 case APIC_POWEROFF_VIA_SITKA_BMC: 1757 restarts = 0; 1758 restart_sitka_bmc: 1759 if (++restarts == 3) 1760 break; 1761 attempts = 0; 1762 do { 1763 byte = inb(SMS_STATUS_REGISTER); 1764 byte &= SMS_STATE_MASK; 1765 if ((byte == SMS_READ_STATE) || 1766 (byte == SMS_WRITE_STATE)) { 1767 drv_usecwait(1000); 1768 if (attempts >= 3) 1769 goto restart_sitka_bmc; 1770 ++attempts; 1771 } 1772 } while ((byte == SMS_READ_STATE) || 1773 (byte == SMS_WRITE_STATE)); 1774 outb(SMS_COMMAND_REGISTER, SMS_GET_STATUS); 1775 i = 0; 1776 for (; i < (sizeof (sitka_bmc)/sizeof (sitka_bmc[0])); 1777 i++) { 1778 attempts = 0; 1779 do { 1780 byte = inb(SMS_STATUS_REGISTER); 1781 byte &= SMS_IBF_MASK; 1782 if (byte != 0) { 1783 drv_usecwait(1000); 1784 if (attempts >= 3) 1785 goto restart_sitka_bmc; 1786 ++attempts; 1787 } 1788 } while (byte != 0); 1789 outb(sitka_bmc[i].port, sitka_bmc[i].data); 1790 } 1791 break; 1792 1793 case APIC_POWEROFF_NONE: 1794 1795 /* If no APIC direct method, we will try using ACPI */ 1796 if (apic_enable_acpi) { 1797 if (acpi_poweroff() == 1) 1798 return; 1799 } else 1800 return; 1801 1802 break; 1803 } 1804 /* 1805 * Wait a limited time here for power to go off. 1806 * If the power does not go off, then there was a 1807 * problem and we should continue to the halt which 1808 * prints a message for the user to press a key to 1809 * reboot. 1810 */ 1811 drv_usecwait(7000000); /* wait seven seconds */ 1812 1813 } 1814 1815 /* 1816 * Try and disable all interrupts. We just assign interrupts to other 1817 * processors based on policy. If any were bound by user request, we 1818 * let them continue and return failure. We do not bother to check 1819 * for cache affinity while rebinding. 1820 */ 1821 1822 static int 1823 apic_disable_intr(processorid_t cpun) 1824 { 1825 int bind_cpu = 0, i, hardbound = 0; 1826 apic_irq_t *irq_ptr; 1827 ulong_t iflag; 1828 1829 iflag = intr_clear(); 1830 lock_set(&apic_ioapic_lock); 1831 1832 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1833 if (apic_reprogram_info[i].done == B_FALSE) { 1834 if (apic_reprogram_info[i].bindcpu == cpun) { 1835 /* 1836 * CPU is busy -- it's the target of 1837 * a pending reprogramming attempt 1838 */ 1839 lock_clear(&apic_ioapic_lock); 1840 intr_restore(iflag); 1841 return (PSM_FAILURE); 1842 } 1843 } 1844 } 1845 1846 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 1847 1848 apic_cpus[cpun].aci_curipl = 0; 1849 1850 i = apic_min_device_irq; 1851 for (; i <= apic_max_device_irq; i++) { 1852 /* 1853 * If there are bound interrupts on this cpu, then 1854 * rebind them to other processors. 1855 */ 1856 if ((irq_ptr = apic_irq_table[i]) != NULL) { 1857 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 1858 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 1859 ((irq_ptr->airq_temp_cpu & ~IRQ_USER_BOUND) < 1860 apic_nproc)); 1861 1862 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 1863 hardbound = 1; 1864 continue; 1865 } 1866 1867 if (irq_ptr->airq_temp_cpu == cpun) { 1868 do { 1869 bind_cpu = apic_next_bind_cpu++; 1870 if (bind_cpu >= apic_nproc) { 1871 apic_next_bind_cpu = 1; 1872 bind_cpu = 0; 1873 1874 } 1875 } while (apic_rebind_all(irq_ptr, bind_cpu)); 1876 } 1877 } 1878 } 1879 1880 lock_clear(&apic_ioapic_lock); 1881 intr_restore(iflag); 1882 1883 if (hardbound) { 1884 cmn_err(CE_WARN, "Could not disable interrupts on %d" 1885 "due to user bound interrupts", cpun); 1886 return (PSM_FAILURE); 1887 } 1888 else 1889 return (PSM_SUCCESS); 1890 } 1891 1892 /* 1893 * Bind interrupts to the CPU's local APIC. 1894 * Interrupts should not be bound to a CPU's local APIC until the CPU 1895 * is ready to receive interrupts. 1896 */ 1897 static void 1898 apic_enable_intr(processorid_t cpun) 1899 { 1900 int i; 1901 apic_irq_t *irq_ptr; 1902 ulong_t iflag; 1903 1904 iflag = intr_clear(); 1905 lock_set(&apic_ioapic_lock); 1906 1907 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 1908 1909 i = apic_min_device_irq; 1910 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 1911 if ((irq_ptr = apic_irq_table[i]) != NULL) { 1912 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 1913 (void) apic_rebind_all(irq_ptr, 1914 irq_ptr->airq_cpu); 1915 } 1916 } 1917 } 1918 1919 lock_clear(&apic_ioapic_lock); 1920 intr_restore(iflag); 1921 } 1922 1923 1924 /* 1925 * This function will reprogram the timer. 1926 * 1927 * When in oneshot mode the argument is the absolute time in future to 1928 * generate the interrupt at. 1929 * 1930 * When in periodic mode, the argument is the interval at which the 1931 * interrupts should be generated. There is no need to support the periodic 1932 * mode timer change at this time. 1933 */ 1934 static void 1935 apic_timer_reprogram(hrtime_t time) 1936 { 1937 hrtime_t now; 1938 uint_t ticks; 1939 int64_t delta; 1940 1941 /* 1942 * We should be called from high PIL context (CBE_HIGH_PIL), 1943 * so kpreempt is disabled. 1944 */ 1945 1946 if (!apic_oneshot) { 1947 /* time is the interval for periodic mode */ 1948 ticks = APIC_NSECS_TO_TICKS(time); 1949 } else { 1950 /* one shot mode */ 1951 1952 now = gethrtime(); 1953 delta = time - now; 1954 1955 if (delta <= 0) { 1956 /* 1957 * requested to generate an interrupt in the past 1958 * generate an interrupt as soon as possible 1959 */ 1960 ticks = apic_min_timer_ticks; 1961 } else if (delta > apic_nsec_max) { 1962 /* 1963 * requested to generate an interrupt at a time 1964 * further than what we are capable of. Set to max 1965 * the hardware can handle 1966 */ 1967 1968 ticks = APIC_MAXVAL; 1969 #ifdef DEBUG 1970 cmn_err(CE_CONT, "apic_timer_reprogram, request at" 1971 " %lld too far in future, current time" 1972 " %lld \n", time, now); 1973 #endif 1974 } else 1975 ticks = APIC_NSECS_TO_TICKS(delta); 1976 } 1977 1978 if (ticks < apic_min_timer_ticks) 1979 ticks = apic_min_timer_ticks; 1980 1981 apic_reg_ops->apic_write(APIC_INIT_COUNT, ticks); 1982 } 1983 1984 /* 1985 * This function will enable timer interrupts. 1986 */ 1987 static void 1988 apic_timer_enable(void) 1989 { 1990 /* 1991 * We should be Called from high PIL context (CBE_HIGH_PIL), 1992 * so kpreempt is disabled. 1993 */ 1994 1995 if (!apic_oneshot) { 1996 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 1997 (apic_clkvect + APIC_BASE_VECT) | AV_TIME); 1998 } else { 1999 /* one shot */ 2000 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 2001 (apic_clkvect + APIC_BASE_VECT)); 2002 } 2003 } 2004 2005 /* 2006 * This function will disable timer interrupts. 2007 */ 2008 static void 2009 apic_timer_disable(void) 2010 { 2011 /* 2012 * We should be Called from high PIL context (CBE_HIGH_PIL), 2013 * so kpreempt is disabled. 2014 */ 2015 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 2016 (apic_clkvect + APIC_BASE_VECT) | AV_MASK); 2017 } 2018 2019 2020 ddi_periodic_t apic_periodic_id; 2021 2022 /* 2023 * If this module needs a periodic handler for the interrupt distribution, it 2024 * can be added here. The argument to the periodic handler is not currently 2025 * used, but is reserved for future. 2026 */ 2027 static void 2028 apic_post_cyclic_setup(void *arg) 2029 { 2030 _NOTE(ARGUNUSED(arg)) 2031 /* cpu_lock is held */ 2032 /* set up a periodic handler for intr redistribution */ 2033 2034 /* 2035 * In peridoc mode intr redistribution processing is done in 2036 * apic_intr_enter during clk intr processing 2037 */ 2038 if (!apic_oneshot) 2039 return; 2040 /* 2041 * Register a periodical handler for the redistribution processing. 2042 * On X86, CY_LOW_LEVEL is mapped to the level 2 interrupt, so 2043 * DDI_IPL_2 should be passed to ddi_periodic_add() here. 2044 */ 2045 apic_periodic_id = ddi_periodic_add( 2046 (void (*)(void *))apic_redistribute_compute, NULL, 2047 apic_redistribute_sample_interval, DDI_IPL_2); 2048 } 2049 2050 static void 2051 apic_redistribute_compute(void) 2052 { 2053 int i, j, max_busy; 2054 2055 if (apic_enable_dynamic_migration) { 2056 if (++apic_nticks == apic_sample_factor_redistribution) { 2057 /* 2058 * Time to call apic_intr_redistribute(). 2059 * reset apic_nticks. This will cause max_busy 2060 * to be calculated below and if it is more than 2061 * apic_int_busy, we will do the whole thing 2062 */ 2063 apic_nticks = 0; 2064 } 2065 max_busy = 0; 2066 for (i = 0; i < apic_nproc; i++) { 2067 2068 /* 2069 * Check if curipl is non zero & if ISR is in 2070 * progress 2071 */ 2072 if (((j = apic_cpus[i].aci_curipl) != 0) && 2073 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 2074 2075 int irq; 2076 apic_cpus[i].aci_busy++; 2077 irq = apic_cpus[i].aci_current[j]; 2078 apic_irq_table[irq]->airq_busy++; 2079 } 2080 2081 if (!apic_nticks && 2082 (apic_cpus[i].aci_busy > max_busy)) 2083 max_busy = apic_cpus[i].aci_busy; 2084 } 2085 if (!apic_nticks) { 2086 if (max_busy > apic_int_busy_mark) { 2087 /* 2088 * We could make the following check be 2089 * skipped > 1 in which case, we get a 2090 * redistribution at half the busy mark (due to 2091 * double interval). Need to be able to collect 2092 * more empirical data to decide if that is a 2093 * good strategy. Punt for now. 2094 */ 2095 if (apic_skipped_redistribute) { 2096 apic_cleanup_busy(); 2097 apic_skipped_redistribute = 0; 2098 } else { 2099 apic_intr_redistribute(); 2100 } 2101 } else 2102 apic_skipped_redistribute++; 2103 } 2104 } 2105 } 2106 2107 2108 /* 2109 * The following functions are in the platform specific file so that they 2110 * can be different functions depending on whether we are running on 2111 * bare metal or a hypervisor. 2112 */ 2113 2114 /* 2115 * map an apic for memory-mapped access 2116 */ 2117 uint32_t * 2118 mapin_apic(uint32_t addr, size_t len, int flags) 2119 { 2120 /*LINTED: pointer cast may result in improper alignment */ 2121 return ((uint32_t *)psm_map_phys(addr, len, flags)); 2122 } 2123 2124 uint32_t * 2125 mapin_ioapic(uint32_t addr, size_t len, int flags) 2126 { 2127 return (mapin_apic(addr, len, flags)); 2128 } 2129 2130 /* 2131 * unmap an apic 2132 */ 2133 void 2134 mapout_apic(caddr_t addr, size_t len) 2135 { 2136 psm_unmap_phys(addr, len); 2137 } 2138 2139 void 2140 mapout_ioapic(caddr_t addr, size_t len) 2141 { 2142 mapout_apic(addr, len); 2143 } 2144 2145 /* 2146 * Check to make sure there are enough irq slots 2147 */ 2148 int 2149 apic_check_free_irqs(int count) 2150 { 2151 int i, avail; 2152 2153 avail = 0; 2154 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 2155 if ((apic_irq_table[i] == NULL) || 2156 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 2157 if (++avail >= count) 2158 return (PSM_SUCCESS); 2159 } 2160 } 2161 return (PSM_FAILURE); 2162 } 2163 2164 /* 2165 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 2166 */ 2167 int 2168 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 2169 int behavior) 2170 { 2171 int rcount, i; 2172 uchar_t start, irqno; 2173 uint32_t cpu; 2174 major_t major; 2175 apic_irq_t *irqptr; 2176 2177 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 2178 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 2179 (void *)dip, inum, pri, count, behavior)); 2180 2181 if (count > 1) { 2182 if (behavior == DDI_INTR_ALLOC_STRICT && 2183 (apic_multi_msi_enable == 0 || count > apic_multi_msi_max)) 2184 return (0); 2185 2186 if (apic_multi_msi_enable == 0) 2187 count = 1; 2188 else if (count > apic_multi_msi_max) 2189 count = apic_multi_msi_max; 2190 } 2191 2192 if ((rcount = apic_navail_vector(dip, pri)) > count) 2193 rcount = count; 2194 else if (rcount == 0 || (rcount < count && 2195 behavior == DDI_INTR_ALLOC_STRICT)) 2196 return (0); 2197 2198 /* if not ISP2, then round it down */ 2199 if (!ISP2(rcount)) 2200 rcount = 1 << (highbit(rcount) - 1); 2201 2202 mutex_enter(&airq_mutex); 2203 2204 for (start = 0; rcount > 0; rcount >>= 1) { 2205 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 2206 behavior == DDI_INTR_ALLOC_STRICT) 2207 break; 2208 } 2209 2210 if (start == 0) { 2211 /* no vector available */ 2212 mutex_exit(&airq_mutex); 2213 return (0); 2214 } 2215 2216 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 2217 /* not enough free irq slots available */ 2218 mutex_exit(&airq_mutex); 2219 return (0); 2220 } 2221 2222 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 2223 for (i = 0; i < rcount; i++) { 2224 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 2225 (uchar_t)-1) { 2226 /* 2227 * shouldn't happen because of the 2228 * apic_check_free_irqs() check earlier 2229 */ 2230 mutex_exit(&airq_mutex); 2231 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 2232 "apic_allocate_irq failed\n")); 2233 return (i); 2234 } 2235 apic_max_device_irq = max(irqno, apic_max_device_irq); 2236 apic_min_device_irq = min(irqno, apic_min_device_irq); 2237 irqptr = apic_irq_table[irqno]; 2238 #ifdef DEBUG 2239 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 2240 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 2241 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 2242 #endif 2243 apic_vector_to_irq[start + i] = (uchar_t)irqno; 2244 2245 irqptr->airq_vector = (uchar_t)(start + i); 2246 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 2247 irqptr->airq_intin_no = (uchar_t)rcount; 2248 irqptr->airq_ipl = pri; 2249 irqptr->airq_vector = start + i; 2250 irqptr->airq_origirq = (uchar_t)(inum + i); 2251 irqptr->airq_share_id = 0; 2252 irqptr->airq_mps_intr_index = MSI_INDEX; 2253 irqptr->airq_dip = dip; 2254 irqptr->airq_major = major; 2255 if (i == 0) /* they all bound to the same cpu */ 2256 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 2257 0xff, 0xff); 2258 else 2259 irqptr->airq_cpu = cpu; 2260 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 2261 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 2262 (void *)irqptr->airq_dip, irqptr->airq_vector, 2263 irqptr->airq_origirq, pri)); 2264 } 2265 mutex_exit(&airq_mutex); 2266 return (rcount); 2267 } 2268 2269 /* 2270 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 2271 */ 2272 int 2273 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 2274 int behavior) 2275 { 2276 int rcount, i; 2277 major_t major; 2278 2279 if (count > 1) { 2280 if (behavior == DDI_INTR_ALLOC_STRICT) { 2281 if (count > apic_msix_max) 2282 return (0); 2283 } else if (count > apic_msix_max) 2284 count = apic_msix_max; 2285 } 2286 2287 mutex_enter(&airq_mutex); 2288 2289 if ((rcount = apic_navail_vector(dip, pri)) > count) 2290 rcount = count; 2291 else if (rcount == 0 || (rcount < count && 2292 behavior == DDI_INTR_ALLOC_STRICT)) { 2293 rcount = 0; 2294 goto out; 2295 } 2296 2297 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 2298 /* not enough free irq slots available */ 2299 rcount = 0; 2300 goto out; 2301 } 2302 2303 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 2304 for (i = 0; i < rcount; i++) { 2305 uchar_t vector, irqno; 2306 apic_irq_t *irqptr; 2307 2308 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 2309 (uchar_t)-1) { 2310 /* 2311 * shouldn't happen because of the 2312 * apic_check_free_irqs() check earlier 2313 */ 2314 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 2315 "apic_allocate_irq failed\n")); 2316 rcount = i; 2317 goto out; 2318 } 2319 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 2320 /* 2321 * shouldn't happen because of the 2322 * apic_navail_vector() call earlier 2323 */ 2324 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 2325 "apic_allocate_vector failed\n")); 2326 rcount = i; 2327 goto out; 2328 } 2329 apic_max_device_irq = max(irqno, apic_max_device_irq); 2330 apic_min_device_irq = min(irqno, apic_min_device_irq); 2331 irqptr = apic_irq_table[irqno]; 2332 irqptr->airq_vector = (uchar_t)vector; 2333 irqptr->airq_ipl = pri; 2334 irqptr->airq_origirq = (uchar_t)(inum + i); 2335 irqptr->airq_share_id = 0; 2336 irqptr->airq_mps_intr_index = MSIX_INDEX; 2337 irqptr->airq_dip = dip; 2338 irqptr->airq_major = major; 2339 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 2340 } 2341 out: 2342 mutex_exit(&airq_mutex); 2343 return (rcount); 2344 } 2345 2346 /* 2347 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 2348 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 2349 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 2350 * requests and allocated only when pri is set. 2351 */ 2352 uchar_t 2353 apic_allocate_vector(int ipl, int irq, int pri) 2354 { 2355 int lowest, highest, i; 2356 2357 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 2358 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 2359 2360 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 2361 lowest -= APIC_VECTOR_PER_IPL; 2362 2363 #ifdef DEBUG 2364 if (apic_restrict_vector) /* for testing shared interrupt logic */ 2365 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 2366 #endif /* DEBUG */ 2367 if (pri == 0) 2368 highest -= APIC_HI_PRI_VECTS; 2369 2370 for (i = lowest; i < highest; i++) { 2371 if (APIC_CHECK_RESERVE_VECTORS(i)) 2372 continue; 2373 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 2374 apic_vector_to_irq[i] = (uchar_t)irq; 2375 return (i); 2376 } 2377 } 2378 2379 return (0); 2380 } 2381 2382 /* Mark vector as not being used by any irq */ 2383 void 2384 apic_free_vector(uchar_t vector) 2385 { 2386 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 2387 } 2388 2389 uint32_t 2390 ioapic_read(int ioapic_ix, uint32_t reg) 2391 { 2392 volatile uint32_t *ioapic; 2393 2394 ioapic = apicioadr[ioapic_ix]; 2395 ioapic[APIC_IO_REG] = reg; 2396 return (ioapic[APIC_IO_DATA]); 2397 } 2398 2399 void 2400 ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value) 2401 { 2402 volatile uint32_t *ioapic; 2403 2404 ioapic = apicioadr[ioapic_ix]; 2405 ioapic[APIC_IO_REG] = reg; 2406 ioapic[APIC_IO_DATA] = value; 2407 } 2408 2409 void 2410 ioapic_write_eoi(int ioapic_ix, uint32_t value) 2411 { 2412 volatile uint32_t *ioapic; 2413 2414 ioapic = apicioadr[ioapic_ix]; 2415 ioapic[APIC_IO_EOI] = value; 2416 } 2417 2418 static processorid_t 2419 apic_find_cpu(int flag) 2420 { 2421 processorid_t acid = 0; 2422 int i; 2423 2424 /* Find the first CPU with the passed-in flag set */ 2425 for (i = 0; i < apic_nproc; i++) { 2426 if (apic_cpus[i].aci_status & flag) { 2427 acid = i; 2428 break; 2429 } 2430 } 2431 2432 ASSERT((apic_cpus[acid].aci_status & flag) != 0); 2433 return (acid); 2434 } 2435 2436 /* 2437 * Call rebind to do the actual programming. 2438 * Must be called with interrupts disabled and apic_ioapic_lock held 2439 * 'p' is polymorphic -- if this function is called to process a deferred 2440 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 2441 * the irq pointer is retrieved. If not doing deferred reprogramming, 2442 * p is of the type 'apic_irq_t *'. 2443 * 2444 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 2445 * and it protects apic_find_cpu() from a race in which a CPU can be taken 2446 * offline after a cpu is selected, but before apic_rebind is called to 2447 * bind interrupts to it. 2448 */ 2449 int 2450 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 2451 { 2452 apic_irq_t *irqptr; 2453 struct ioapic_reprogram_data *drep = NULL; 2454 int rv; 2455 2456 if (deferred) { 2457 drep = (struct ioapic_reprogram_data *)p; 2458 ASSERT(drep != NULL); 2459 irqptr = drep->irqp; 2460 } else 2461 irqptr = (apic_irq_t *)p; 2462 2463 ASSERT(irqptr != NULL); 2464 2465 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 2466 if (rv) { 2467 /* 2468 * CPU is not up or interrupts are disabled. Fall back to 2469 * the first available CPU 2470 */ 2471 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 2472 drep); 2473 } 2474 2475 return (rv); 2476 } 2477 2478 2479 uchar_t 2480 apic_modify_vector(uchar_t vector, int irq) 2481 { 2482 apic_vector_to_irq[vector] = (uchar_t)irq; 2483 return (vector); 2484 } 2485 2486 char * 2487 apic_get_apic_type() 2488 { 2489 return (apic_psm_info.p_mach_idstring); 2490 } 2491 2492 void 2493 x2apic_update_psm() 2494 { 2495 struct psm_ops *pops = &apic_ops; 2496 2497 ASSERT(pops != NULL); 2498 2499 /* 2500 * We don't need to do any magic if one of the following 2501 * conditions is true : 2502 * - Not being run under kernel debugger. 2503 * - MP is not set. 2504 * - Booted with one CPU only. 2505 * - One CPU configured. 2506 * 2507 * We set apic_common_send_ipi() since kernel debuggers 2508 * attempt to send IPIs to other slave CPUs during 2509 * entry (exit) from (to) debugger. 2510 */ 2511 if (!(boothowto & RB_DEBUG) || use_mp == 0 || 2512 apic_nproc == 1 || boot_ncpus == 1) { 2513 pops->psm_send_ipi = x2apic_send_ipi; 2514 } else { 2515 pops->psm_send_ipi = apic_common_send_ipi; 2516 } 2517 2518 pops->psm_intr_exit = x2apic_intr_exit; 2519 pops->psm_setspl = x2apic_setspl; 2520 2521 send_dirintf = pops->psm_send_ipi; 2522 2523 apic_mode = LOCAL_X2APIC; 2524 apic_change_ops(); 2525 } 2526