1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCI_IMPL_H 27 #define _SYS_PCI_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/dditypes.h> 32 #include <sys/memlist.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined(__i386) || defined(__amd64) 39 40 /* 41 * There are two ways to access the PCI configuration space on X86 42 * Access method 2 is the older method 43 * Access method 1 is the newer method and is preferred because 44 * of the problems in trying to lock the configuration space 45 * for MP machines using method 2. See PCI Local BUS Specification 46 * Revision 2.0 section 3.6.4.1 for more details. 47 * 48 * In addition, on IBM Sandalfoot and a few related machines there's 49 * still another mechanism. See PReP 1.1 section 6.1.7. 50 */ 51 52 #define PCI_MECHANISM_UNKNOWN -1 53 #define PCI_MECHANISM_NONE 0 54 #if defined(__i386) || defined(__amd64) 55 #define PCI_MECHANISM_1 1 56 #define PCI_MECHANISM_2 2 57 #else 58 #error "Unknown processor type" 59 #endif 60 61 62 #ifndef FALSE 63 #define FALSE 0 64 #endif 65 66 #ifndef TRUE 67 #define TRUE 1 68 #endif 69 70 #define PCI_FUNC_MASK 0x07 71 72 /* these macros apply to Configuration Mechanism #1 */ 73 #define PCI_CONFADD 0xcf8 74 #define PCI_PMC 0xcfb 75 #define PCI_CONFDATA 0xcfc 76 #define PCI_CONE 0x80000000 77 #define PCI_CADDR1(bus, device, function, reg) \ 78 (PCI_CONE | (((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \ 79 | (((function) & 0x7) << 8) | ((reg) & 0xfc)) 80 81 /* these macros apply to Configuration Mechanism #2 */ 82 #define PCI_CSE_PORT 0xcf8 83 #define PCI_FORW_PORT 0xcfa 84 #define PCI_CADDR2(device, indx) \ 85 (0xc000 | (((device) & 0xf) << 8) | (indx)) 86 87 typedef struct pci_acc_cfblk { 88 uchar_t c_busnum; /* bus number */ 89 uchar_t c_devnum; /* device number */ 90 uchar_t c_funcnum; /* function number */ 91 uchar_t c_fill; /* reserve field */ 92 } pci_acc_cfblk_t; 93 94 struct pci_bus_resource { 95 struct memlist *io_ports; 96 struct memlist *mem_space; 97 struct memlist *pmem_space; 98 dev_info_t *dip; /* devinfo node */ 99 void *privdata; /* private data for configuration */ 100 uchar_t par_bus; /* parent bus number */ 101 uchar_t sub_bus; /* highest bus number beyond this bridge */ 102 uchar_t root_addr; /* legacy peer bus address assignment */ 103 uchar_t padding1; 104 #ifdef _LP64 105 uint32_t padding2; 106 #endif 107 }; 108 109 extern struct pci_bus_resource *pci_bus_res; 110 111 /* 112 * For now, x86-only to avoid conflicts with <sys/memlist_impl.h> 113 */ 114 extern struct memlist *memlist_alloc(void); 115 extern void memlist_free(struct memlist *); 116 extern void memlist_insert(struct memlist **, uint64_t, uint64_t); 117 extern int memlist_remove(struct memlist **, uint64_t, uint64_t); 118 extern uint64_t memlist_find(struct memlist **, uint64_t, int); 119 extern void memlist_dump(struct memlist *); 120 extern struct memlist *memlist_dup(struct memlist *); 121 extern int memlist_count(struct memlist *); 122 123 #endif /* __i386 || __amd64 */ 124 125 /* 126 * Parent private data structure for PCI/PCI-X/PCIe devices. 127 */ 128 typedef struct pci_parent_data { 129 uint32_t pci_bdf; /* BDF for pci/pci-x/pcie */ 130 uint8_t pci_sec_bus; /* PCIE2PCI bridge's secondary bus */ 131 uint8_t pci_phfun; /* Phantom funs for pci-x/pcie */ 132 } pci_parent_data_t; 133 134 #define PCI_GET_BDF(dip) \ 135 ((pci_parent_data_t *)DEVI((dip))->devi_parent_data)->pci_bdf 136 #define PCI_GET_SEC_BUS(dip) \ 137 ((pci_parent_data_t *)DEVI((dip))->devi_parent_data)->pci_sec_bus 138 #define PCI_GET_PHFUN(dip) \ 139 ((pci_parent_data_t *)DEVI((dip))->devi_parent_data)->pci_phfun 140 141 /* 142 * PCI capability related definitions. 143 */ 144 145 /* 146 * Minimum number of dwords to be saved. 147 */ 148 #define PCI_MSI_MIN_WORDS 3 149 #define PCI_PCIX_MIN_WORDS 2 150 #define PCI_PCIE_MIN_WORDS 5 151 152 /* 153 * Total number of dwords to be saved. 154 */ 155 #define PCI_PMCAP_NDWORDS 2 156 #define PCI_AGP_NDWORDS 3 157 #define PCI_SLOTID_NDWORDS 1 158 #define PCI_MSIX_NDWORDS 3 159 #define PCI_CAP_SZUNKNOWN 0 160 161 #define CAP_ID(confhdl, cap_ptr, xspace) \ 162 ((xspace) ? 0 : pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_ID)) 163 164 #define NEXT_CAP(confhdl, cap_ptr, xspace) \ 165 ((xspace) ? 0 : \ 166 pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_NEXT_PTR)) 167 168 extern int pci_resource_setup(dev_info_t *); 169 extern void pci_resource_destroy(dev_info_t *); 170 171 #ifdef __cplusplus 172 } 173 #endif 174 175 #endif /* _SYS_PCI_IMPL_H */ 176