1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_RXDMA_H 27 #define _SYS_NXGE_NXGE_RXDMA_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/nxge/nxge_rxdma_hw.h> 34 #include <npi_rxdma.h> 35 36 #define RXDMA_CK_DIV_DEFAULT 7500 /* 25 usec */ 37 /* 38 * Hardware RDC designer: 8 cache lines during Atlas bringup. 39 */ 40 #define RXDMA_RED_LESS_BYTES (8 * 64) /* 8 cache line */ 41 #define RXDMA_RED_LESS_ENTRIES (RXDMA_RED_LESS_BYTES/8) 42 #define RXDMA_RED_WINDOW_DEFAULT 0 43 #define RXDMA_RED_THRES_DEFAULT 0 44 45 #define RXDMA_RCR_PTHRES_DEFAULT 0x20 46 #define RXDMA_RCR_TO_DEFAULT 0x8 47 48 /* 49 * hardware workarounds: kick 16 (was 8 before) 50 */ 51 #define NXGE_RXDMA_POST_BATCH 16 52 53 #define RXBUF_START_ADDR(a, index, bsize) ((a & (index * bsize)) 54 #define RXBUF_OFFSET_FROM_START(a, start) (start - a) 55 #define RXBUF_64B_ALIGNED 64 56 57 #define NXGE_RXBUF_EXTRA 34 58 /* 59 * Receive buffer thresholds and buffer types 60 */ 61 #define NXGE_RX_BCOPY_SCALE 8 /* use 1/8 as lowest granularity */ 62 typedef enum { 63 NXGE_RX_COPY_ALL = 0, /* do bcopy on every packet */ 64 NXGE_RX_COPY_1, /* bcopy on 1/8 of buffer posted */ 65 NXGE_RX_COPY_2, /* bcopy on 2/8 of buffer posted */ 66 NXGE_RX_COPY_3, /* bcopy on 3/8 of buffer posted */ 67 NXGE_RX_COPY_4, /* bcopy on 4/8 of buffer posted */ 68 NXGE_RX_COPY_5, /* bcopy on 5/8 of buffer posted */ 69 NXGE_RX_COPY_6, /* bcopy on 6/8 of buffer posted */ 70 NXGE_RX_COPY_7, /* bcopy on 7/8 of buffer posted */ 71 NXGE_RX_COPY_NONE /* don't do bcopy at all */ 72 } nxge_rxbuf_threshold_t; 73 74 typedef enum { 75 NXGE_RBR_TYPE0 = RCR_PKTBUFSZ_0, /* bcopy buffer size 0 (small) */ 76 NXGE_RBR_TYPE1 = RCR_PKTBUFSZ_1, /* bcopy buffer size 1 (medium) */ 77 NXGE_RBR_TYPE2 = RCR_PKTBUFSZ_2 /* bcopy buffer size 2 (large) */ 78 } nxge_rxbuf_type_t; 79 80 typedef struct _rdc_errlog { 81 rdmc_par_err_log_t pre_par; 82 rdmc_par_err_log_t sha_par; 83 uint8_t compl_err_type; 84 } rdc_errlog_t; 85 86 /* 87 * Receive Statistics. 88 */ 89 typedef struct _nxge_rx_ring_stats_t { 90 uint64_t ipackets; 91 uint64_t ibytes; 92 uint32_t ierrors; 93 uint32_t multircv; 94 uint32_t brdcstrcv; 95 uint32_t norcvbuf; 96 97 uint32_t rx_inits; 98 uint32_t rx_jumbo_pkts; 99 uint32_t rx_multi_pkts; 100 uint32_t rx_mtu_pkts; 101 uint32_t rx_no_buf; 102 103 /* 104 * Receive buffer management statistics. 105 */ 106 uint32_t rx_new_pages; 107 uint32_t rx_new_mtu_pgs; 108 uint32_t rx_new_nxt_pgs; 109 uint32_t rx_reused_pgs; 110 uint32_t rx_mtu_drops; 111 uint32_t rx_nxt_drops; 112 113 /* 114 * Error event stats. 115 */ 116 uint32_t rx_rbr_tmout; 117 uint32_t pkt_too_long_err; 118 uint32_t l2_err; 119 uint32_t l4_cksum_err; 120 uint32_t fflp_soft_err; 121 uint32_t zcp_soft_err; 122 uint32_t rcr_unknown_err; 123 uint32_t dcf_err; 124 uint32_t rbr_tmout; 125 uint32_t rsp_cnt_err; 126 uint32_t byte_en_err; 127 uint32_t byte_en_bus; 128 uint32_t rsp_dat_err; 129 uint32_t rcr_ack_err; 130 uint32_t dc_fifo_err; 131 uint32_t rcr_sha_par; 132 uint32_t rbr_pre_par; 133 uint32_t port_drop_pkt; 134 uint32_t wred_drop; 135 uint32_t rbr_pre_empty; 136 uint32_t rcr_shadow_full; 137 uint32_t config_err; 138 uint32_t rcrincon; 139 uint32_t rcrfull; 140 uint32_t rbr_empty; 141 uint32_t rbrfull; 142 uint32_t rbrlogpage; 143 uint32_t cfiglogpage; 144 uint32_t rcrto; 145 uint32_t rcrthres; 146 uint32_t mex; 147 rdc_errlog_t errlog; 148 } nxge_rx_ring_stats_t, *p_nxge_rx_ring_stats_t; 149 150 typedef struct _nxge_rdc_sys_stats { 151 uint32_t pre_par; 152 uint32_t sha_par; 153 uint32_t id_mismatch; 154 uint32_t ipp_eop_err; 155 uint32_t zcp_eop_err; 156 } nxge_rdc_sys_stats_t, *p_nxge_rdc_sys_stats_t; 157 158 159 typedef struct _rx_msg_t { 160 nxge_os_dma_common_t buf_dma; 161 nxge_os_mutex_t lock; 162 struct _nxge_t *nxgep; 163 struct _rx_rbr_ring_t *rx_rbr_p; 164 boolean_t spare_in_use; 165 boolean_t free; 166 uint32_t ref_cnt; 167 #ifdef RXBUFF_USE_SEPARATE_UP_CNTR 168 uint32_t pass_up_cnt; 169 boolean_t release; 170 #endif 171 nxge_os_frtn_t freeb; 172 size_t bytes_arrived; 173 size_t bytes_expected; 174 size_t block_size; 175 uint32_t block_index; 176 uint32_t pkt_buf_size; 177 uint32_t pkt_buf_size_code; 178 uint32_t max_pkt_bufs; 179 uint32_t cur_usage_cnt; 180 uint32_t max_usage_cnt; 181 uchar_t *buffer; 182 uint32_t pri; 183 uint32_t shifted_addr; 184 boolean_t use_buf_pool; 185 p_mblk_t rx_mblk_p; 186 boolean_t rx_use_bcopy; 187 } rx_msg_t, *p_rx_msg_t; 188 189 typedef struct _rx_dma_handle_t { 190 nxge_os_dma_handle_t dma_handle; /* DMA handle */ 191 nxge_os_acc_handle_t acc_handle; /* DMA memory handle */ 192 npi_handle_t npi_handle; 193 } rx_dma_handle_t, *p_rx_dma_handle_t; 194 195 196 /* Receive Completion Ring */ 197 typedef struct _rx_rcr_ring_t { 198 nxge_os_dma_common_t rcr_desc; 199 200 struct _nxge_t *nxgep; 201 202 p_nxge_rx_ring_stats_t rdc_stats; 203 204 int poll_flag; /* 1 if polling mode */ 205 206 rcrcfig_a_t rcr_cfga; 207 rcrcfig_b_t rcr_cfgb; 208 209 nxge_os_mutex_t lock; 210 uint16_t index; 211 uint16_t rdc; 212 boolean_t full_hdr_flag; /* 1: 18 bytes header */ 213 uint16_t sw_priv_hdr_len; /* 0 - 192 bytes (SW) */ 214 uint32_t comp_size; /* # of RCR entries */ 215 uint64_t rcr_addr; 216 uint_t comp_wrap_mask; 217 uint_t comp_rd_index; 218 uint_t comp_wt_index; 219 220 p_rcr_entry_t rcr_desc_first_p; 221 p_rcr_entry_t rcr_desc_first_pp; 222 p_rcr_entry_t rcr_desc_last_p; 223 p_rcr_entry_t rcr_desc_last_pp; 224 225 p_rcr_entry_t rcr_desc_rd_head_p; /* software next read */ 226 p_rcr_entry_t rcr_desc_rd_head_pp; 227 228 uint64_t rcr_tail_pp; 229 uint64_t rcr_head_pp; 230 struct _rx_rbr_ring_t *rx_rbr_p; 231 uint32_t intr_timeout; 232 uint32_t intr_threshold; 233 uint64_t max_receive_pkts; 234 mac_resource_handle_t rcr_mac_handle; 235 uint32_t rcvd_pkt_bytes; /* Received bytes of a packet */ 236 } rx_rcr_ring_t, *p_rx_rcr_ring_t; 237 238 239 240 /* Buffer index information */ 241 typedef struct _rxbuf_index_info_t { 242 uint32_t buf_index; 243 uint32_t start_index; 244 uint32_t buf_size; 245 uint64_t dvma_addr; 246 uint64_t kaddr; 247 } rxbuf_index_info_t, *p_rxbuf_index_info_t; 248 249 /* Buffer index information */ 250 251 typedef struct _rxring_info_t { 252 uint32_t hint[3]; 253 uint32_t block_size_mask; 254 uint16_t max_iterations; 255 rxbuf_index_info_t buffer[NXGE_DMA_BLOCK]; 256 } rxring_info_t, *p_rxring_info_t; 257 258 259 typedef enum { 260 RBR_POSTING = 1, /* We may post rx buffers. */ 261 RBR_UNMAPPING, /* We are in the process of unmapping. */ 262 RBR_UNMAPPED /* The ring is unmapped. */ 263 } rbr_state_t; 264 265 266 /* Receive Buffer Block Ring */ 267 typedef struct _rx_rbr_ring_t { 268 nxge_os_dma_common_t rbr_desc; 269 p_rx_msg_t *rx_msg_ring; 270 p_nxge_dma_common_t *dma_bufp; 271 rbr_cfig_a_t rbr_cfga; 272 rbr_cfig_b_t rbr_cfgb; 273 rbr_kick_t rbr_kick; 274 log_page_vld_t page_valid; 275 log_page_mask_t page_mask_1; 276 log_page_mask_t page_mask_2; 277 log_page_value_t page_value_1; 278 log_page_value_t page_value_2; 279 log_page_relo_t page_reloc_1; 280 log_page_relo_t page_reloc_2; 281 log_page_hdl_t page_hdl; 282 283 boolean_t cfg_set; 284 285 nxge_os_mutex_t lock; 286 nxge_os_mutex_t post_lock; 287 uint16_t index; 288 struct _nxge_t *nxgep; 289 uint16_t rdc; 290 uint16_t rdc_grp_id; 291 uint_t rbr_max_size; 292 uint64_t rbr_addr; 293 uint_t rbr_wrap_mask; 294 uint_t rbb_max; 295 uint_t rbb_added; 296 uint_t block_size; 297 uint_t num_blocks; 298 uint_t tnblocks; 299 uint_t pkt_buf_size0; 300 uint_t pkt_buf_size0_bytes; 301 uint_t npi_pkt_buf_size0; 302 uint_t pkt_buf_size1; 303 uint_t pkt_buf_size1_bytes; 304 uint_t npi_pkt_buf_size1; 305 uint_t pkt_buf_size2; 306 uint_t pkt_buf_size2_bytes; 307 uint_t npi_pkt_buf_size2; 308 309 uint32_t *rbr_desc_vp; 310 311 p_rx_rcr_ring_t rx_rcr_p; 312 313 uint_t rbr_wr_index; 314 uint_t rbr_rd_index; 315 316 rxring_info_t *ring_info; 317 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 318 uint64_t hv_rx_buf_base_ioaddr_pp; 319 uint64_t hv_rx_buf_ioaddr_size; 320 uint64_t hv_rx_cntl_base_ioaddr_pp; 321 uint64_t hv_rx_cntl_ioaddr_size; 322 boolean_t hv_set; 323 #endif 324 uint_t rbr_consumed; 325 uint_t rbr_threshold_hi; 326 uint_t rbr_threshold_lo; 327 nxge_rxbuf_type_t rbr_bufsize_type; 328 boolean_t rbr_use_bcopy; 329 330 /* 331 * <rbr_ref_cnt> is a count of those receive buffers which 332 * have been loaned to the kernel. We will not free this 333 * ring until the reference count reaches zero (0). 334 */ 335 uint32_t rbr_ref_cnt; 336 rbr_state_t rbr_state; /* POSTING, etc */ 337 /* 338 * Receive buffer allocation types: 339 * ddi_dma_mem_alloc(), contig_mem_alloc(), kmem_alloc() 340 */ 341 buf_alloc_type_t rbr_alloc_type; 342 } rx_rbr_ring_t, *p_rx_rbr_ring_t; 343 344 /* Receive Mailbox */ 345 typedef struct _rx_mbox_t { 346 nxge_os_dma_common_t rx_mbox; 347 rxdma_cfig1_t rx_cfg1; 348 rxdma_cfig2_t rx_cfg2; 349 uint64_t mbox_addr; 350 boolean_t cfg_set; 351 352 nxge_os_mutex_t lock; 353 uint16_t index; 354 struct _nxge_t *nxgep; 355 uint16_t rdc; 356 } rx_mbox_t, *p_rx_mbox_t; 357 358 359 typedef struct _rx_rbr_rings_t { 360 p_rx_rbr_ring_t *rbr_rings; 361 uint32_t ndmas; 362 } rx_rbr_rings_t, *p_rx_rbr_rings_t; 363 364 typedef struct _rx_rcr_rings_t { 365 p_rx_rcr_ring_t *rcr_rings; 366 uint32_t ndmas; 367 } rx_rcr_rings_t, *p_rx_rcr_rings_t; 368 369 typedef struct _rx_mbox_areas_t { 370 p_rx_mbox_t *rxmbox_areas; 371 uint32_t ndmas; 372 boolean_t mbox_allocated; 373 } rx_mbox_areas_t, *p_rx_mbox_areas_t; 374 375 /* 376 * Global register definitions per chip and they are initialized 377 * using the function zero control registers. 378 * . 379 */ 380 381 typedef struct _rxdma_globals { 382 boolean_t mode32; 383 uint16_t rxdma_ck_div_cnt; 384 uint16_t rxdma_red_ran_init; 385 uint32_t rxdma_eing_timeout; 386 } rxdma_globals_t, *p_rxdma_globals; 387 388 389 /* 390 * Receive DMA Prototypes. 391 */ 392 nxge_status_t nxge_init_rxdma_channels(p_nxge_t); 393 void nxge_uninit_rxdma_channels(p_nxge_t); 394 395 nxge_status_t nxge_init_rxdma_channel(p_nxge_t, int); 396 void nxge_uninit_rxdma_channel(p_nxge_t, int); 397 398 nxge_status_t nxge_init_rxdma_channel_rcrflush(p_nxge_t, uint8_t); 399 nxge_status_t nxge_reset_rxdma_channel(p_nxge_t, uint16_t); 400 nxge_status_t nxge_init_rxdma_channel_cntl_stat(p_nxge_t, 401 uint16_t, p_rx_dma_ctl_stat_t); 402 nxge_status_t nxge_enable_rxdma_channel(p_nxge_t, 403 uint16_t, p_rx_rbr_ring_t, p_rx_rcr_ring_t, 404 p_rx_mbox_t); 405 nxge_status_t nxge_init_rxdma_channel_event_mask(p_nxge_t, 406 uint16_t, p_rx_dma_ent_msk_t); 407 408 nxge_status_t nxge_rxdma_hw_mode(p_nxge_t, boolean_t); 409 void nxge_hw_start_rx(p_nxge_t); 410 void nxge_fixup_rxdma_rings(p_nxge_t); 411 nxge_status_t nxge_dump_rxdma_channel(p_nxge_t, uint8_t); 412 413 void nxge_rxdma_fix_channel(p_nxge_t, uint16_t); 414 void nxge_rxdma_fixup_channel(p_nxge_t, uint16_t, int); 415 int nxge_rxdma_get_ring_index(p_nxge_t, uint16_t); 416 417 void nxge_rxdma_regs_dump_channels(p_nxge_t); 418 nxge_status_t nxge_rxdma_handle_sys_errors(p_nxge_t); 419 void nxge_rxdma_inject_err(p_nxge_t, uint32_t, uint8_t); 420 421 extern nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 422 extern nxge_status_t nxge_alloc_rxb(p_nxge_t nxgep, int channel); 423 extern void nxge_free_rxb(p_nxge_t nxgep, int channel); 424 425 #ifdef __cplusplus 426 } 427 #endif 428 429 #endif /* _SYS_NXGE_NXGE_RXDMA_H */ 430