xref: /titanic_51/usr/src/uts/common/sys/nxge/nxge_impl.h (revision 37714ae43602c675f9dc59b070bfdf9fa702872c)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_IMPL_H
27 #define	_SYS_NXGE_NXGE_IMPL_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 /*
34  * NIU HV API version definitions.
35  */
36 #define	NIU_MAJOR_VER		1
37 #define	NIU_MINOR_VER		1
38 
39 #if defined(sun4v)
40 
41 /*
42  * NIU HV API v1.0 definitions
43  */
44 #define	N2NIU_RX_LP_CONF		0x142
45 #define	N2NIU_RX_LP_INFO		0x143
46 #define	N2NIU_TX_LP_CONF		0x144
47 #define	N2NIU_TX_LP_INFO		0x145
48 
49 #endif /* defined(sun4v) */
50 
51 #ifndef _ASM
52 
53 #include	<sys/types.h>
54 #include	<sys/byteorder.h>
55 #include	<sys/debug.h>
56 #include	<sys/stropts.h>
57 #include	<sys/stream.h>
58 #include	<sys/strlog.h>
59 #include	<sys/strsubr.h>
60 #include	<sys/cmn_err.h>
61 #include	<sys/vtrace.h>
62 #include	<sys/kmem.h>
63 #include	<sys/ddi.h>
64 #include	<sys/sunddi.h>
65 #include	<sys/strsun.h>
66 #include	<sys/stat.h>
67 #include	<sys/cpu.h>
68 #include	<sys/kstat.h>
69 #include	<inet/common.h>
70 #include	<inet/ip.h>
71 #include	<sys/dlpi.h>
72 #include	<inet/nd.h>
73 #include	<netinet/in.h>
74 #include	<sys/ethernet.h>
75 #include	<sys/vlan.h>
76 #include	<sys/pci.h>
77 #include	<sys/taskq.h>
78 #include	<sys/atomic.h>
79 
80 #include 	<sys/nxge/nxge_defs.h>
81 #include 	<sys/nxge/nxge_hw.h>
82 #include 	<sys/nxge/nxge_mac.h>
83 #include	<sys/nxge/nxge_mii.h>
84 #include	<sys/nxge/nxge_fm.h>
85 #include	<sys/netlb.h>
86 
87 #include	<sys/ddi_intr.h>
88 #include 	<sys/mac_provider.h>
89 #include	<sys/mac_ether.h>
90 
91 #if	defined(sun4v)
92 #include	<sys/hypervisor_api.h>
93 #include 	<sys/machsystm.h>
94 #include 	<sys/hsvc.h>
95 #endif
96 
97 #include 	<sys/dld.h>
98 
99 /*
100  * Handy macros (taken from bge driver)
101  */
102 #define	RBR_SIZE			4
103 #define	DMA_COMMON_CHANNEL(area)	((area.dma_channel))
104 #define	DMA_COMMON_VPTR(area)		((area.kaddrp))
105 #define	DMA_COMMON_VPTR_INDEX(area, index)	\
106 					(((char *)(area.kaddrp)) + \
107 					(index * RBR_SIZE))
108 #define	DMA_COMMON_HANDLE(area)		((area.dma_handle))
109 #define	DMA_COMMON_ACC_HANDLE(area)	((area.acc_handle))
110 #define	DMA_COMMON_IOADDR(area)		((area.dma_cookie.dmac_laddress))
111 #define	DMA_COMMON_IOADDR_INDEX(area, index)	\
112 					((area.dma_cookie.dmac_laddress) + \
113 						(index * RBR_SIZE))
114 
115 #define	DMA_NPI_HANDLE(area)		((area.npi_handle)
116 
117 #define	DMA_COMMON_SYNC(area, flag)	((void) ddi_dma_sync((area).dma_handle,\
118 						(area).offset, (area).alength, \
119 						(flag)))
120 #define	DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag)	\
121 					((void) ddi_dma_sync((area).dma_handle,\
122 					(area.offset + bufoffset), len, \
123 					(flag)))
124 
125 #define	DMA_COMMON_SYNC_RBR_DESC(area, index, flag)	\
126 				((void) ddi_dma_sync((area).dma_handle,\
127 				(index * RBR_SIZE), RBR_SIZE,	\
128 				(flag)))
129 
130 #define	DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag)	\
131 			((void) ddi_dma_sync((area).dma_handle,\
132 			(index * RBR_SIZE), count * RBR_SIZE,	\
133 				(flag)))
134 #define	DMA_COMMON_SYNC_ENTRY(area, index, flag)	\
135 				((void) ddi_dma_sync((area).dma_handle,\
136 				(index * (area).block_size),	\
137 				(area).block_size, \
138 				(flag)))
139 
140 #define	NEXT_ENTRY(index, wrap)		((index + 1) & wrap)
141 #define	NEXT_ENTRY_PTR(ptr, first, last)	\
142 					((ptr == last) ? first : (ptr + 1))
143 
144 /*
145  * NPI related macros
146  */
147 #define	NXGE_DEV_NPI_HANDLE(nxgep)	(nxgep->npi_handle)
148 
149 #define	NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah)
150 #define	NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap)
151 
152 #define	NPI_ACC_HANDLE_SET(nxgep, ah)	(nxgep->npi_handle.regh = ah)
153 #define	NPI_ADD_HANDLE_SET(nxgep, ap)	\
154 		nxgep->npi_handle.is_vraddr = B_FALSE;	\
155 		nxgep->npi_handle.function.instance = nxgep->instance;   \
156 		nxgep->npi_handle.function.function = nxgep->function_num;   \
157 		nxgep->npi_handle.nxgep = (void *) nxgep;   \
158 		nxgep->npi_handle.regp = ap;
159 
160 #define	NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah)
161 #define	NPI_REG_ADD_HANDLE_SET(nxgep, ap)	\
162 		nxgep->npi_reg_handle.is_vraddr = B_FALSE;	\
163 		nxgep->npi_handle.function.instance = nxgep->instance;   \
164 		nxgep->npi_handle.function.function = nxgep->function_num;   \
165 		nxgep->npi_reg_handle.nxgep = (void *) nxgep;   \
166 		nxgep->npi_reg_handle.regp = ap;
167 
168 #define	NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah)
169 #define	NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap)
170 
171 #define	NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah)
172 #define	NPI_VREG_ADD_HANDLE_SET(nxgep, ap)	\
173 		nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \
174 		nxgep->npi_handle.function.instance = nxgep->instance;   \
175 		nxgep->npi_handle.function.function = nxgep->function_num;   \
176 		nxgep->npi_vreg_handle.nxgep = (void *) nxgep;   \
177 		nxgep->npi_vreg_handle.regp = ap;
178 
179 #define	NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah)
180 #define	NPI_V2REG_ADD_HANDLE_SET(nxgep, ap)	\
181 		nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \
182 		nxgep->npi_handle.function.instance = nxgep->instance;   \
183 		nxgep->npi_handle.function.function = nxgep->function_num;   \
184 		nxgep->npi_v2reg_handle.nxgep = (void *) nxgep;   \
185 		nxgep->npi_v2reg_handle.regp = ap;
186 
187 #define	NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh)
188 #define	NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp)
189 #define	NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh)
190 #define	NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp)
191 #define	NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh)
192 #define	NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp)
193 #define	NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh)
194 #define	NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp)
195 #define	NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh)
196 #define	NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp)
197 #define	NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh)
198 #define	NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp)
199 
200 #define	NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah)
201 #define	NPI_DMA_ACC_HANDLE_GET(dmap) 	(dmap->npi_handle.regh)
202 
203 /*
204  * DMA handles.
205  */
206 #define	NXGE_DESC_D_HANDLE_GET(desc)	(desc.dma_handle)
207 #define	NXGE_DESC_D_IOADD_GET(desc)	(desc.dma_cookie.dmac_laddress)
208 #define	NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress)
209 #define	NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress)
210 
211 #define	LDV_ON(ldv, vector)	((vector >> ldv) & 0x1)
212 #define	LDV2_ON_1(ldv, vector)	((vector >> (ldv - 64)) & 0x1)
213 #define	LDV2_ON_2(ldv, vector)	(((vector >> 5) >> (ldv - 64)) & 0x1)
214 
215 typedef uint32_t		nxge_status_t;
216 
217 typedef enum  {
218 	IDLE,
219 	PROGRESS,
220 	CONFIGURED
221 } dev_func_shared_t;
222 
223 typedef enum  {
224 	DVMA,
225 	DMA,
226 	SDMA
227 } dma_method_t;
228 
229 typedef enum  {
230 	BKSIZE_4K,
231 	BKSIZE_8K,
232 	BKSIZE_16K,
233 	BKSIZE_32K
234 } nxge_rx_block_size_t;
235 
236 #ifdef TX_ONE_BUF
237 #define	TX_BCOPY_MAX 1514
238 #else
239 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
240 #define	TX_BCOPY_MAX	4096
241 #define	TX_BCOPY_SIZE	4096
242 #else
243 #define	TX_BCOPY_MAX	2048
244 #define	TX_BCOPY_SIZE	2048
245 #endif
246 #endif
247 
248 #define	TX_STREAM_MIN 512
249 #define	TX_FASTDVMA_MIN 1024
250 
251 /*
252  * Send repeated FMA ereports or display messages about some non-fatal
253  * hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times
254  */
255 #define	NXGE_ERROR_SHOW_MAX	2
256 
257 
258 /*
259  * Defaults
260  */
261 #define	NXGE_RDC_RCR_THRESHOLD		32
262 #define	NXGE_RDC_RCR_TIMEOUT		8
263 
264 #define	NXGE_RDC_RCR_THRESHOLD_MAX	1024
265 #define	NXGE_RDC_RCR_TIMEOUT_MAX	64
266 #define	NXGE_RDC_RCR_THRESHOLD_MIN	8
267 #define	NXGE_RDC_RCR_TIMEOUT_MIN	1
268 #define	NXGE_RCR_FULL_HEADER		1
269 
270 #define	NXGE_IS_VLAN_PACKET(ptr)				\
271 	((((struct ether_vlan_header *)ptr)->ether_tpid) ==	\
272 	htons(VLAN_ETHERTYPE))
273 
274 typedef enum {
275 	NONE,
276 	SMALL,
277 	MEDIUM,
278 	LARGE
279 } dma_size_t;
280 
281 typedef enum {
282 	USE_NONE,
283 	USE_BCOPY,
284 	USE_DVMA,
285 	USE_DMA,
286 	USE_SDMA
287 } dma_type_t;
288 
289 typedef enum {
290 	NOT_IN_USE,
291 	HDR_BUF,
292 	MTU_BUF,
293 	RE_ASSEMBLY_BUF,
294 	FREE_BUF
295 } rx_page_state_t;
296 
297 struct _nxge_block_mv_t {
298 	uint32_t msg_type;
299 	dma_type_t dma_type;
300 };
301 
302 typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t;
303 
304 typedef enum {
305 	NIU_TYPE_NONE = 0,
306 
307 	/* QGC NIC */
308 	NEPTUNE_4_1GC =
309 	    (NXGE_PORT_1G_COPPER |
310 	    (NXGE_PORT_1G_COPPER << 4) |
311 	    (NXGE_PORT_1G_COPPER << 8) |
312 	    (NXGE_PORT_1G_COPPER << 12)),
313 
314 	/* Huron: 2 fiber XAUI cards */
315 	NEPTUNE_2_10GF =
316 	    (NXGE_PORT_10G_FIBRE |
317 	    (NXGE_PORT_10G_FIBRE << 4) |
318 	    (NXGE_PORT_NONE << 8) |
319 	    (NXGE_PORT_NONE << 12)),
320 
321 	/* Huron: port0 is a TN1010 copper XAUI */
322 	NEPTUNE_1_TN1010 =
323 	    (NXGE_PORT_TN1010 |
324 	    (NXGE_PORT_NONE << 4) |
325 	    (NXGE_PORT_NONE << 8) |
326 	    (NXGE_PORT_NONE << 12)),
327 
328 	/* Huron: port1 is a TN1010 copper XAUI */
329 	NEPTUNE_1_NONE_1_TN1010 =
330 	    (NXGE_PORT_NONE |
331 	    (NXGE_PORT_TN1010 << 4) |
332 	    (NXGE_PORT_NONE << 8) |
333 	    (NXGE_PORT_NONE << 12)),
334 
335 	/* Huron: 2 TN1010 copper XAUI cards */
336 	NEPTUNE_2_TN1010 =
337 	    (NXGE_PORT_TN1010 |
338 	    (NXGE_PORT_TN1010 << 4) |
339 	    (NXGE_PORT_NONE << 8) |
340 	    (NXGE_PORT_NONE << 12)),
341 
342 	/* Huron: port0 is fiber XAUI, port1 is copper XAUI */
343 	NEPTUNE_1_10GF_1_TN1010 =
344 	    (NXGE_PORT_10G_FIBRE |
345 	    (NXGE_PORT_TN1010 << 4) |
346 	    (NXGE_PORT_NONE << 8) |
347 	    (NXGE_PORT_NONE << 12)),
348 
349 	/* Huron: port0 is copper XAUI, port1 is fiber XAUI */
350 	NEPTUNE_1_TN1010_1_10GF =
351 	    (NXGE_PORT_TN1010 |
352 	    (NXGE_PORT_10G_FIBRE << 4) |
353 	    (NXGE_PORT_NONE << 8) |
354 	    (NXGE_PORT_NONE << 12)),
355 
356 	/* Maramba: port0 and port1 are fiber XAUIs */
357 	NEPTUNE_2_10GF_2_1GC =
358 	    (NXGE_PORT_10G_FIBRE |
359 	    (NXGE_PORT_10G_FIBRE << 4) |
360 	    (NXGE_PORT_1G_COPPER << 8) |
361 	    (NXGE_PORT_1G_COPPER << 12)),
362 
363 	/* Maramba: port0 and port1 are copper TN1010 XAUIs */
364 	NEPTUNE_2_TN1010_2_1GC =
365 	    (NXGE_PORT_TN1010 |
366 	    (NXGE_PORT_TN1010 << 4) |
367 	    (NXGE_PORT_1G_COPPER << 8) |
368 	    (NXGE_PORT_1G_COPPER << 12)),
369 
370 	/* Maramba: port0 is copper XAUI, port1 is Fiber XAUI */
371 	NEPTUNE_1_TN1010_1_10GF_2_1GC =
372 	    (NXGE_PORT_TN1010 |
373 	    (NXGE_PORT_10G_FIBRE << 4) |
374 	    (NXGE_PORT_1G_COPPER << 8) |
375 	    (NXGE_PORT_1G_COPPER << 12)),
376 
377 	/* Maramba: port0 is fiber XAUI, port1 is copper XAUI */
378 	NEPTUNE_1_10GF_1_TN1010_2_1GC =
379 	    (NXGE_PORT_10G_FIBRE |
380 	    (NXGE_PORT_TN1010 << 4) |
381 	    (NXGE_PORT_1G_COPPER << 8) |
382 	    (NXGE_PORT_1G_COPPER << 12)),
383 
384 	/* Maramba: port0 is fiber XAUI */
385 	NEPTUNE_1_10GF_3_1GC =
386 	    (NXGE_PORT_10G_FIBRE |
387 	    (NXGE_PORT_1G_COPPER << 4) |
388 	    (NXGE_PORT_1G_COPPER << 8) |
389 	    (NXGE_PORT_1G_COPPER << 12)),
390 
391 	/* Maramba: port0 is TN1010 copper XAUI */
392 	NEPTUNE_1_TN1010_3_1GC =
393 	    (NXGE_PORT_TN1010 |
394 	    (NXGE_PORT_1G_COPPER << 4) |
395 	    (NXGE_PORT_1G_COPPER << 8) |
396 	    (NXGE_PORT_1G_COPPER << 12)),
397 
398 	/* Maramba: port1 is fiber XAUI */
399 	NEPTUNE_1_1GC_1_10GF_2_1GC =
400 	    (NXGE_PORT_1G_COPPER |
401 	    (NXGE_PORT_10G_FIBRE << 4) |
402 	    (NXGE_PORT_1G_COPPER << 8) |
403 	    (NXGE_PORT_1G_COPPER << 12)),
404 
405 	/* Maramba: port1 is TN1010 copper XAUI */
406 	NEPTUNE_1_1GC_1_TN1010_2_1GC =
407 	    (NXGE_PORT_1G_COPPER |
408 	    (NXGE_PORT_TN1010 << 4) |
409 	    (NXGE_PORT_1G_COPPER << 8) |
410 	    (NXGE_PORT_1G_COPPER << 12)),
411 
412 	NEPTUNE_2_1GRF =
413 	    (NXGE_PORT_NONE |
414 	    (NXGE_PORT_NONE << 4) |
415 	    (NXGE_PORT_1G_RGMII_FIBER << 8) |
416 	    (NXGE_PORT_1G_RGMII_FIBER << 12)),
417 
418 	NEPTUNE_2_10GF_2_1GRF =
419 	    (NXGE_PORT_10G_FIBRE |
420 	    (NXGE_PORT_10G_FIBRE << 4) |
421 	    (NXGE_PORT_1G_RGMII_FIBER << 8) |
422 	    (NXGE_PORT_1G_RGMII_FIBER << 12)),
423 
424 	N2_NIU =
425 	    (NXGE_PORT_RSVD |
426 	    (NXGE_PORT_RSVD << 4) |
427 	    (NXGE_PORT_RSVD << 8) |
428 	    (NXGE_PORT_RSVD << 12))
429 
430 } niu_type_t;
431 
432 /*
433  * P_NEPTUNE_GENERIC:
434  *	The cover-all case for Neptune (as opposed to NIU) where we do not
435  *	care the exact platform as we do not do anything that is platform
436  *	specific.
437  * P_NEPTUNE_ATLAS_2PORT:
438  *	Dual Port Fiber Neptune based NIC (2XGF)
439  * P_NEPTUNE_ATLAS_4PORT:
440  *	Quad Port Copper Neptune based NIC (QGC)
441  * P_NEPTUNE_NIU:
442  *	This is NIU. Could be Huron, Glendale, Monza or any other NIU based
443  *	platform.
444  */
445 typedef enum {
446 	P_NEPTUNE_NONE,
447 	P_NEPTUNE_GENERIC,
448 	P_NEPTUNE_ATLAS_2PORT,
449 	P_NEPTUNE_ATLAS_4PORT,
450 	P_NEPTUNE_MARAMBA_P0,
451 	P_NEPTUNE_MARAMBA_P1,
452 	P_NEPTUNE_ALONSO,
453 	P_NEPTUNE_ROCK,
454 	P_NEPTUNE_NIU
455 } platform_type_t;
456 
457 #define	NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \
458 	(((nxgep->platform_type) == P_NEPTUNE_ATLAS_2PORT) || \
459 	    ((nxgep->platform_type) == P_NEPTUNE_ATLAS_4PORT) || \
460 	    ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \
461 	    ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1) || \
462 	    ((nxgep->platform_type) == P_NEPTUNE_GENERIC) || \
463 	    ((nxgep->platform_type) == P_NEPTUNE_ALONSO) || \
464 	    ((nxgep->platform_type) == P_NEPTUNE_ROCK))
465 
466 #define	NXGE_IS_XAUI_PLATFORM(nxgep) \
467 	(((nxgep->platform_type) == P_NEPTUNE_NIU) || \
468 	    ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \
469 	    ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1))
470 
471 
472 typedef enum {
473 	CFG_DEFAULT = 0,	/* default cfg */
474 	CFG_EQUAL,	/* Equal */
475 	CFG_FAIR,	/* Equal */
476 	CFG_CLASSIFY,
477 	CFG_L2_CLASSIFY,
478 	CFG_L3_CLASSIFY,
479 	CFG_L3_DISTRIBUTE,
480 	CFG_L3_WEB,
481 	CFG_L3_TCAM,
482 	CFG_NOT_SPECIFIED,
483 	CFG_CUSTOM	/* Custom */
484 } cfg_type_t;
485 
486 typedef enum {
487 	NO_MSG = 0x0,		/* No message output or storage. */
488 	CONSOLE = 0x1,		/* Messages are go to the console. */
489 	BUFFER = 0x2,		/* Messages are go to the system buffer. */
490 	CON_BUF = 0x3,		/* Messages are go to the console and */
491 				/* system buffer. */
492 	VERBOSE = 0x4		/* Messages are go out only in VERBOSE node. */
493 } out_msg_t, *p_out_msg_t;
494 
495 typedef enum {
496 	DBG_NO_MSG = 0x0,	/* No message output or storage. */
497 	DBG_CONSOLE = 0x1,	/* Messages are go to the console. */
498 	DBG_BUFFER = 0x2,	/* Messages are go to the system buffer. */
499 	DBG_CON_BUF = 0x3,	/* Messages are go to the console and */
500 				/* system buffer. */
501 	STR_LOG = 4		/* Sessage sent to streams logging driver. */
502 } out_dbgmsg_t, *p_out_dbgmsg_t;
503 
504 typedef enum {
505 	DDI_MEM_ALLOC,		/* default (use ddi_dma_mem_alloc) */
506 	KMEM_ALLOC,		/* use kmem_alloc(). */
507 	CONTIG_MEM_ALLOC	/* use contig_mem_alloc() (N2/NIU only) */
508 } buf_alloc_type_t;
509 
510 #define	BUF_ALLOCATED		0x00000001
511 #define	BUF_ALLOCATED_WAIT_FREE	0x00000002
512 
513 typedef struct ether_addr ether_addr_st, *p_ether_addr_t;
514 typedef struct ether_header ether_header_t, *p_ether_header_t;
515 typedef queue_t *p_queue_t;
516 typedef mblk_t *p_mblk_t;
517 
518 /*
519  * Generic phy table to support different phy types.
520  *
521  * The argument for check_link is nxgep, which is passed to check_link
522  * as an argument to the timer routine.
523  */
524 typedef struct _nxge_xcvr_table {
525 	nxge_status_t	(*serdes_init)	();	/* Serdes init routine */
526 	nxge_status_t	(*xcvr_init)	();	/* xcvr init routine */
527 	nxge_status_t	(*link_intr_stop) ();	/* Link intr disable routine */
528 	nxge_status_t	(*link_intr_start) ();	/* Link intr enable routine */
529 	nxge_status_t	(*check_link) ();	/* Link check routine */
530 
531 	uint32_t	xcvr_inuse;
532 } nxge_xcvr_table_t, *p_nxge_xcvr_table_t;
533 
534 /*
535  * Common DMA data elements.
536  */
537 typedef struct _nxge_dma_pool_t nxge_dma_pool_t, *p_nxge_dma_pool_t;
538 
539 struct _nxge_dma_common_t {
540 	uint16_t		dma_channel;
541 	void			*kaddrp;
542 	void			*last_kaddrp;
543 	void			*ioaddr_pp;
544 	void			*first_ioaddr_pp;
545 	void			*last_ioaddr_pp;
546 	ddi_dma_cookie_t 	dma_cookie;
547 	uint32_t		ncookies;
548 
549 	ddi_dma_handle_t	dma_handle;
550 	nxge_os_acc_handle_t	acc_handle;
551 	npi_handle_t		npi_handle;
552 
553 	size_t			block_size;
554 	uint32_t		nblocks;
555 	size_t			alength;
556 	uint_t			offset;
557 	uint_t			dma_chunk_index;
558 	void			*orig_ioaddr_pp;
559 	uint64_t		orig_vatopa;
560 	void			*orig_kaddrp;
561 	size_t			orig_alength;
562 	boolean_t		contig_alloc_type;
563 	/*
564 	 * Receive buffers may be allocated using
565 	 * kmem_alloc(). The buffer free function
566 	 * depends on its allocation function.
567 	 */
568 	boolean_t		kmem_alloc_type;
569 	uint32_t		buf_alloc_state;
570 	buf_alloc_type_t	buf_alloc_type;
571 	p_nxge_dma_pool_t	rx_buf_pool_p;
572 };
573 
574 typedef struct _nxge_t nxge_t, *p_nxge_t;
575 typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t;
576 
577 struct _nxge_dma_pool_t {
578 	p_nxge_dma_common_t	*dma_buf_pool_p;
579 	uint32_t		ndmas;
580 	uint32_t		*num_chunks;
581 	boolean_t		buf_allocated;
582 };
583 
584 /*
585  * Each logical device (69):
586  *	- LDG #
587  *	- flag bits
588  *	- masks.
589  *	- interrupt handler function.
590  *
591  * Generic system interrupt handler with two arguments:
592  *	(nxge_sys_intr_t)
593  *	Per device instance data structure
594  *	Logical group data structure.
595  *
596  * Logical device interrupt handler with two arguments:
597  *	(nxge_ldv_intr_t)
598  *	Per device instance data structure
599  *	Logical device number
600  */
601 typedef struct	_nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t;
602 typedef struct	_nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t;
603 typedef uint_t	(*nxge_sys_intr_t)(void *arg1, void *arg2);
604 typedef uint_t	(*nxge_ldv_intr_t)(void *arg1, void *arg2);
605 
606 /*
607  * Each logical device Group (64) needs to have the following
608  * configurations:
609  *	- timer counter (6 bits)
610  *	- timer resolution (20 bits, number of system clocks)
611  *	- system data (7 bits)
612  */
613 struct _nxge_ldg_t {
614 	uint8_t			ldg;		/* logical group number */
615 	uint8_t			vldg_index;
616 	boolean_t		arm;
617 	uint16_t		ldg_timer;	/* counter */
618 	uint8_t			func;
619 	uint8_t			vector;
620 	uint8_t			intdata;
621 	uint8_t			nldvs;
622 	p_nxge_ldv_t		ldvp;
623 	nxge_sys_intr_t		sys_intr_handler;
624 	p_nxge_t		nxgep;
625 };
626 
627 struct _nxge_ldv_t {
628 	uint8_t			ldg_assigned;
629 	uint8_t			ldv;
630 	boolean_t		is_rxdma;
631 	boolean_t		is_txdma;
632 	boolean_t		is_mif;
633 	boolean_t		is_mac;
634 	boolean_t		is_syserr;
635 	boolean_t		use_timer;
636 	uint8_t			channel;
637 	uint8_t			vdma_index;
638 	uint8_t			func;
639 	p_nxge_ldg_t		ldgp;
640 	uint8_t			ldv_flags;
641 	uint8_t			ldv_ldf_masks;
642 	nxge_ldv_intr_t		ldv_intr_handler;
643 	p_nxge_t		nxgep;
644 };
645 
646 typedef struct _nxge_logical_page_t {
647 	uint16_t		dma;
648 	uint16_t		page;
649 	boolean_t		valid;
650 	uint64_t		mask;
651 	uint64_t		value;
652 	uint64_t		reloc;
653 	uint32_t		handle;
654 } nxge_logical_page_t, *p_nxge_logical_page_t;
655 
656 /*
657  * (Internal) return values from ioctl subroutines.
658  */
659 enum nxge_ioc_reply {
660 	IOC_INVAL = -1,				/* bad, NAK with EINVAL	*/
661 	IOC_DONE,				/* OK, reply sent	*/
662 	IOC_ACK,				/* OK, just send ACK	*/
663 	IOC_REPLY,				/* OK, just send reply	*/
664 	IOC_RESTART_ACK,			/* OK, restart & ACK	*/
665 	IOC_RESTART_REPLY			/* OK, restart & reply	*/
666 };
667 
668 typedef struct _pci_cfg_t {
669 	uint16_t vendorid;
670 	uint16_t devid;
671 	uint16_t command;
672 	uint16_t status;
673 	uint8_t  revid;
674 	uint8_t  res0;
675 	uint16_t junk1;
676 	uint8_t  cache_line;
677 	uint8_t  latency;
678 	uint8_t  header;
679 	uint8_t  bist;
680 	uint32_t base;
681 	uint32_t base14;
682 	uint32_t base18;
683 	uint32_t base1c;
684 	uint32_t base20;
685 	uint32_t base24;
686 	uint32_t base28;
687 	uint32_t base2c;
688 	uint32_t base30;
689 	uint32_t res1[2];
690 	uint8_t int_line;
691 	uint8_t int_pin;
692 	uint8_t	min_gnt;
693 	uint8_t max_lat;
694 } pci_cfg_t, *p_pci_cfg_t;
695 
696 typedef struct _dev_regs_t {
697 	nxge_os_acc_handle_t	nxge_pciregh;	/* PCI config DDI IO handle */
698 	p_pci_cfg_t		nxge_pciregp;	/* mapped PCI registers */
699 
700 	nxge_os_acc_handle_t	nxge_regh;	/* device DDI IO (BAR 0) */
701 	void			*nxge_regp;	/* mapped device registers */
702 
703 	nxge_os_acc_handle_t	nxge_msix_regh;	/* MSI/X DDI handle (BAR 2) */
704 	void 			*nxge_msix_regp; /* MSI/X register */
705 
706 	nxge_os_acc_handle_t	nxge_vir_regh;	/* virtualization (BAR 4) */
707 	unsigned char		*nxge_vir_regp;	/* virtualization register */
708 
709 	nxge_os_acc_handle_t	nxge_vir2_regh;	/* second virtualization */
710 	unsigned char		*nxge_vir2_regp; /* second virtualization */
711 
712 	nxge_os_acc_handle_t	nxge_romh;	/* fcode rom handle */
713 	unsigned char		*nxge_romp;	/* fcode pointer */
714 } dev_regs_t, *p_dev_regs_t;
715 
716 
717 typedef struct _nxge_mac_addr_t {
718 	ether_addr_t	addr;
719 	uint_t		flags;
720 } nxge_mac_addr_t;
721 
722 /*
723  * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac)
724  * for each XMAC port and supports 1 unique MAC and 7 alternate MACs
725  * for each BMAC port.  The number of MACs assigned by the factory is
726  * different and is as follows,
727  * 	BMAC port:		   num_factory_mmac = num_mmac = 7
728  *	XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15
729  *	XMAC port on a 4-port NIC: num_factory_mmac = 7
730  * So num_factory_mmac is smaller than num_mmac.  nxge_m_mmac_add uses
731  * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac.
732  *
733  * total_factory_macs is the total number of factory MACs, including
734  * the unique MAC, assigned to a Neptune based NIC card, it is 32.
735  */
736 typedef struct _nxge_mmac_t {
737 	uint8_t		total_factory_macs;
738 	uint8_t		num_mmac;
739 	uint8_t		num_factory_mmac;
740 	nxge_mac_addr_t	mac_pool[XMAC_MAX_ADDR_ENTRY];
741 	ether_addr_t	factory_mac_pool[XMAC_MAX_ADDR_ENTRY];
742 	uint8_t		naddrfree;  /* number of alt mac addr available */
743 } nxge_mmac_t;
744 
745 /*
746  * mmac stats structure
747  */
748 typedef struct _nxge_mmac_stats_t {
749 	uint8_t mmac_max_cnt;
750 	uint8_t	mmac_avail_cnt;
751 	struct ether_addr mmac_avail_pool[16];
752 } nxge_mmac_stats_t, *p_nxge_mmac_stats_t;
753 
754 /*
755  * Copied from mac.h. Should be cleaned up by driver.
756  */
757 #define	MMAC_SLOT_USED		0x1   /* address slot used */
758 #define	MMAC_VENDOR_ADDR	0x2   /* address returned is vendor supplied */
759 
760 
761 #define	NXGE_MAX_MMAC_ADDRS	32
762 #define	NXGE_NUM_MMAC_ADDRS	8
763 #define	NXGE_NUM_OF_PORTS_QUAD	4
764 #define	NXGE_NUM_OF_PORTS_DUAL	2
765 
766 #define	NXGE_QGC_LP_BM_STR		"501-7606"
767 #define	NXGE_2XGF_LP_BM_STR		"501-7283"
768 #define	NXGE_QGC_PEM_BM_STR		"501-7765"
769 #define	NXGE_2XGF_PEM_BM_STR		"501-7626"
770 #define	NXGE_ALONSO_BM_STR		"373-0202-01"
771 #define	NXGE_ALONSO_MODEL_STR		"SUNW,CP3220"
772 #define	NXGE_RFEM_BM_STR		"501-7961-01"
773 #define	NXGE_RFEM_MODEL_STR		"SUNW,pcie-rfem"
774 #define	NXGE_ARTM_BM_STR		"375-3544-01"
775 #define	NXGE_ARTM_MODEL_STR		"SUNW,pcie-artm"
776 /* ROCK OBP creates a compatible property for ROCK */
777 #define	NXGE_ROCK_COMPATIBLE		"SUNW,rock-pciex108e,abcd"
778 #define	NXGE_EROM_LEN			1048576
779 
780 #include 	<sys/nxge/nxge_common_impl.h>
781 #include 	<sys/nxge/nxge_common.h>
782 #include	<sys/nxge/nxge_txc.h>
783 #include	<sys/nxge/nxge_rxdma.h>
784 #include	<sys/nxge/nxge_txdma.h>
785 #include	<sys/nxge/nxge_fflp.h>
786 #include	<sys/nxge/nxge_ipp.h>
787 #include	<sys/nxge/nxge_zcp.h>
788 #include	<sys/nxge/nxge_fzc.h>
789 #include	<sys/nxge/nxge_flow.h>
790 #include	<sys/nxge/nxge_virtual.h>
791 
792 #include	<npi_espc.h>
793 #include	<npi_vir.h>
794 
795 #include 	<sys/nxge/nxge.h>
796 
797 #include	<sys/modctl.h>
798 #include	<sys/pattr.h>
799 
800 extern int secpolicy_net_config(const cred_t *, boolean_t);
801 extern void nxge_fm_report_error(p_nxge_t, uint8_t,
802 			uint8_t, nxge_fm_ereport_id_t);
803 extern int fm_check_acc_handle(ddi_acc_handle_t);
804 extern int fm_check_dma_handle(ddi_dma_handle_t);
805 
806 /* nxge_classify.c */
807 nxge_status_t nxge_classify_init(p_nxge_t);
808 nxge_status_t nxge_classify_uninit(p_nxge_t);
809 nxge_status_t nxge_set_hw_classify_config(p_nxge_t);
810 nxge_status_t nxge_classify_exit_sw(p_nxge_t);
811 
812 /* nxge_fflp.c */
813 void nxge_put_tcam(p_nxge_t, p_mblk_t);
814 void nxge_get_tcam(p_nxge_t, p_mblk_t);
815 nxge_status_t nxge_classify_init_hw(p_nxge_t);
816 nxge_status_t nxge_classify_init_sw(p_nxge_t);
817 nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t);
818 nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t,
819 				    uint32_t);
820 
821 nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t,
822 				    tcam_class_t,
823 				    uint32_t *);
824 
825 nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t,
826 				    uint32_t);
827 
828 nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t,
829 				    uint32_t);
830 
831 uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t);
832 nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *);
833 nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t);
834 nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t);
835 
836 nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t);
837 nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t);
838 
839 nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t);
840 nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t);
841 
842 nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t);
843 nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t);
844 
845 nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t);
846 
847 nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t);
848 
849 nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t);
850 
851 void nxge_handle_tcam_fragment_bug(p_nxge_t);
852 nxge_status_t nxge_fflp_hw_reset(p_nxge_t);
853 nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t);
854 nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t);
855 
856 /* nxge_kstats.c */
857 void nxge_init_statsp(p_nxge_t);
858 void nxge_setup_kstats(p_nxge_t);
859 void nxge_setup_rdc_kstats(p_nxge_t, int);
860 void nxge_setup_tdc_kstats(p_nxge_t, int);
861 void nxge_destroy_kstats(p_nxge_t);
862 int nxge_port_kstat_update(kstat_t *, int);
863 void nxge_save_cntrs(p_nxge_t);
864 
865 int nxge_m_stat(void *arg, uint_t, uint64_t *);
866 
867 /* nxge_hw.c */
868 void
869 nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
870 void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
871 nxge_status_t nxge_global_reset(p_nxge_t);
872 uint_t nxge_intr(void *, void *);
873 void nxge_intr_enable(p_nxge_t);
874 void nxge_intr_disable(p_nxge_t);
875 void nxge_hw_blank(void *arg, time_t, uint_t);
876 void nxge_hw_id_init(p_nxge_t);
877 void nxge_hw_init_niu_common(p_nxge_t);
878 void nxge_intr_hw_enable(p_nxge_t);
879 void nxge_intr_hw_disable(p_nxge_t);
880 void nxge_hw_stop(p_nxge_t);
881 void nxge_check_hw_state(p_nxge_t);
882 
883 void nxge_rxdma_channel_put64(nxge_os_acc_handle_t,
884 	void *, uint32_t, uint16_t,
885 	uint64_t);
886 uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *,
887 	uint32_t, uint16_t);
888 
889 
890 void nxge_get32(p_nxge_t, p_mblk_t);
891 void nxge_put32(p_nxge_t, p_mblk_t);
892 
893 void nxge_hw_set_mac_modes(p_nxge_t);
894 
895 /* nxge_send.c. */
896 uint_t nxge_reschedule(caddr_t);
897 mblk_t *nxge_tx_ring_send(void *, mblk_t *);
898 int nxge_start(p_nxge_t, p_tx_ring_t, p_mblk_t);
899 
900 /* nxge_rxdma.c */
901 nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t,
902 					    uint8_t, uint8_t);
903 
904 nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t,
905 				    uint8_t, uint8_t);
906 nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t,
907 				    uint16_t);
908 nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t,
909 				    uint16_t, uint8_t);
910 
911 /* nxge_ndd.c */
912 void nxge_get_param_soft_properties(p_nxge_t);
913 void nxge_copy_hw_default_to_param(p_nxge_t);
914 void nxge_copy_param_hw_to_config(p_nxge_t);
915 void nxge_setup_param(p_nxge_t);
916 void nxge_init_param(p_nxge_t);
917 void nxge_destroy_param(p_nxge_t);
918 boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t);
919 boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t);
920 boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t);
921 
922 boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t);
923 
924 int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t);
925 int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t);
926 int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
927 int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t);
928 int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
929 int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t);
930 long nxge_strtol(char *, char **, int);
931 boolean_t nxge_param_get_instance(queue_t *, mblk_t *);
932 void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
933 boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t);
934 void nxge_nd_free(caddr_t *);
935 int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t);
936 
937 nxge_status_t nxge_set_lb_normal(p_nxge_t);
938 boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t);
939 boolean_t nxge_param_link_update(p_nxge_t);
940 int nxge_param_set_ip_opt(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t);
941 int nxge_dld_get_ip_opt(p_nxge_t, caddr_t);
942 int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *,
943 	mblk_t *, char *, caddr_t);
944 int nxge_param_rx_intr_time(p_nxge_t, queue_t *,
945 	mblk_t *, char *, caddr_t);
946 
947 
948 /* nxge_virtual.c */
949 nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *);
950 void nxge_common_lock_get(p_nxge_t);
951 void nxge_common_lock_free(p_nxge_t);
952 
953 nxge_status_t nxge_get_config_properties(p_nxge_t);
954 void nxge_get_xcvr_properties(p_nxge_t);
955 void nxge_init_vlan_config(p_nxge_t);
956 void nxge_init_mac_config(p_nxge_t);
957 
958 
959 void nxge_init_logical_devs(p_nxge_t);
960 int nxge_init_ldg_intrs(p_nxge_t);
961 
962 void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t,
963 	uint32_t);
964 
965 void nxge_init_fzc_txdma_channels(p_nxge_t);
966 
967 nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t,
968 	p_tx_ring_t, p_tx_mbox_t);
969 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t);
970 
971 nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t);
972 
973 nxge_status_t nxge_init_fzc_rx_common(p_nxge_t);
974 nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t);
975 
976 nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t,
977 	uint16_t, p_rx_rbr_ring_t);
978 nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t,
979 	uint16_t, p_rx_rcr_ring_t);
980 
981 nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t,
982 	uint16_t, p_rx_rbr_ring_t);
983 
984 
985 nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t,
986 	uint16_t, p_tx_ring_t);
987 
988 nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t,
989 	p_tx_ring_t);
990 
991 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t);
992 
993 void nxge_init_fzc_ldg_num(p_nxge_t);
994 void nxge_init_fzc_sys_int_data(p_nxge_t);
995 void nxge_init_fzc_ldg_int_timer(p_nxge_t);
996 nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on);
997 
998 /* MAC functions */
999 nxge_status_t nxge_mac_init(p_nxge_t);
1000 nxge_status_t nxge_link_init(p_nxge_t);
1001 nxge_status_t nxge_xif_init(p_nxge_t);
1002 nxge_status_t nxge_pcs_init(p_nxge_t);
1003 nxge_status_t nxge_mac_ctrl_init(p_nxge_t);
1004 nxge_status_t nxge_serdes_init(p_nxge_t);
1005 nxge_status_t nxge_serdes_reset(p_nxge_t);
1006 nxge_status_t nxge_xcvr_find(p_nxge_t);
1007 nxge_status_t nxge_get_xcvr_type(p_nxge_t);
1008 nxge_status_t nxge_setup_xcvr_table(p_nxge_t);
1009 nxge_status_t nxge_xcvr_init(p_nxge_t);
1010 nxge_status_t nxge_tx_mac_init(p_nxge_t);
1011 nxge_status_t nxge_rx_mac_init(p_nxge_t);
1012 nxge_status_t nxge_tx_mac_enable(p_nxge_t);
1013 nxge_status_t nxge_tx_mac_disable(p_nxge_t);
1014 nxge_status_t nxge_rx_mac_enable(p_nxge_t);
1015 nxge_status_t nxge_rx_mac_disable(p_nxge_t);
1016 nxge_status_t nxge_tx_mac_reset(p_nxge_t);
1017 nxge_status_t nxge_rx_mac_reset(p_nxge_t);
1018 nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t);
1019 nxge_status_t nxge_mii_xcvr_init(p_nxge_t);
1020 nxge_status_t nxge_mii_xcvr_fiber_init(p_nxge_t);
1021 nxge_status_t nxge_mii_read(p_nxge_t, uint8_t,
1022 			uint8_t, uint16_t *);
1023 nxge_status_t nxge_mii_write(p_nxge_t, uint8_t,
1024 			uint8_t, uint16_t);
1025 nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t,
1026 			uint16_t, uint16_t *);
1027 nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t,
1028 			uint8_t, uint16_t, uint16_t);
1029 nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t,
1030 			mii_bmsr_t, nxge_link_state_t *);
1031 void nxge_pcs_check(p_nxge_t, uint8_t portn, nxge_link_state_t *);
1032 nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *);
1033 nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *);
1034 nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *);
1035 nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *);
1036 nxge_status_t nxge_check_tn1010_link(p_nxge_t);
1037 void nxge_link_is_down(p_nxge_t);
1038 void nxge_link_is_up(p_nxge_t);
1039 nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t);
1040 uint32_t crc32_mchash(p_ether_addr_t);
1041 nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t);
1042 nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t);
1043 nxge_status_t nxge_10g_link_led_on(p_nxge_t);
1044 nxge_status_t nxge_10g_link_led_off(p_nxge_t);
1045 nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t);
1046 boolean_t nxge_is_valid_local_mac(ether_addr_st);
1047 nxge_status_t nxge_mac_set_framesize(p_nxge_t);
1048 
1049 /* espc (sprom) prototypes */
1050 nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t);
1051 nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *);
1052 nxge_status_t nxge_espc_num_ports_get(p_nxge_t);
1053 nxge_status_t nxge_espc_phy_type_get(p_nxge_t);
1054 nxge_status_t nxge_espc_verify_chksum(p_nxge_t);
1055 void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *);
1056 void nxge_vpd_info_get(p_nxge_t);
1057 
1058 
1059 void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...);
1060 int nxge_get_nports(p_nxge_t);
1061 
1062 void nxge_free_buf(buf_alloc_type_t, uint64_t, uint32_t);
1063 
1064 #if defined(sun4v)
1065 
1066 uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t,
1067 	uint64_t, uint64_t);
1068 #pragma weak	hv_niu_rx_logical_page_conf
1069 
1070 uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t,
1071 	uint64_t *, uint64_t *);
1072 #pragma weak	hv_niu_rx_logical_page_info
1073 
1074 uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t,
1075 	uint64_t, uint64_t);
1076 #pragma weak	hv_niu_tx_logical_page_conf
1077 
1078 uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t,
1079 	uint64_t *, uint64_t *);
1080 #pragma weak	hv_niu_tx_logical_page_info
1081 
1082 uint64_t hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie);
1083 #pragma weak	hv_niu_vr_assign
1084 
1085 uint64_t hv_niu_vr_unassign(uint32_t cookie);
1086 #pragma weak	hv_niu_vr_unassign
1087 
1088 uint64_t hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start,
1089     uint64_t *size);
1090 #pragma weak	hv_niu_vr_getinfo
1091 
1092 uint64_t hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map);
1093 #pragma weak	hv_niu_vr_get_rxmap
1094 
1095 uint64_t hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map);
1096 #pragma weak	hv_niu_vr_get_txmap
1097 
1098 uint64_t hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx,
1099     uint64_t *vchidx);
1100 #pragma weak	hv_niu_rx_dma_assign
1101 
1102 uint64_t hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t chidx);
1103 #pragma weak	hv_niu_rx_dma_unassign
1104 
1105 uint64_t hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx,
1106     uint64_t *vchidx);
1107 #pragma weak	hv_niu_tx_dma_assign
1108 
1109 uint64_t hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx);
1110 #pragma weak	hv_niu_tx_dma_unassign
1111 
1112 uint64_t hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx,
1113     uint64_t pgidx, uint64_t raddr, uint64_t size);
1114 #pragma weak	hv_niu_vrrx_logical_page_conf
1115 
1116 uint64_t hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx,
1117     uint64_t pgidx, uint64_t *raddr, uint64_t *size);
1118 #pragma weak	hv_niu_vrrx_logical_page_info
1119 
1120 uint64_t hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx,
1121     uint64_t pgidx, uint64_t raddr, uint64_t size);
1122 #pragma weak	hv_niu_vrtx_logical_page_conf
1123 
1124 uint64_t hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx,
1125     uint64_t pgidx, uint64_t *raddr, uint64_t *size);
1126 #pragma weak	hv_niu_vrtx_logical_page_info
1127 
1128 //
1129 // NIU-specific interrupt API
1130 //
1131 uint64_t hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t v_chidx,
1132     uint64_t *group, uint64_t *logdev);
1133 #pragma weak	hv_niu_vrrx_getinfo
1134 
1135 uint64_t hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t v_chidx,
1136     uint64_t *group, uint64_t *logdev);
1137 #pragma weak	hv_niu_vrtx_getinfo
1138 
1139 uint64_t hv_niu_vrrx_to_logical_dev(uint32_t cookie, uint64_t v_chidx,
1140     uint64_t *ldn);
1141 #pragma weak	hv_niu_vrrx_to_logical_dev
1142 
1143 uint64_t hv_niu_vrtx_to_logical_dev(uint32_t cookie, uint64_t v_chidx,
1144     uint64_t *ldn);
1145 #pragma weak	hv_niu_vrtx_to_logical_dev
1146 
1147 #endif /* defined(sun4v) */
1148 
1149 #ifdef NXGE_DEBUG
1150 char *nxge_dump_packet(char *, int);
1151 #endif
1152 
1153 #endif	/* !_ASM */
1154 
1155 #ifdef	__cplusplus
1156 }
1157 #endif
1158 
1159 #endif	/* _SYS_NXGE_NXGE_IMPL_H */
1160