1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_IMPL_H 27 #define _SYS_NXGE_NXGE_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * NIU HV API version definitions. 37 */ 38 #define NIU_MAJOR_VER 1 39 #define NIU_MINOR_VER 1 40 41 /* 42 * NIU HV API v1.0 definitions 43 */ 44 #define N2NIU_RX_LP_CONF 0x142 45 #define N2NIU_RX_LP_INFO 0x143 46 #define N2NIU_TX_LP_CONF 0x144 47 #define N2NIU_TX_LP_INFO 0x145 48 49 #ifndef _ASM 50 51 #include <sys/types.h> 52 #include <sys/byteorder.h> 53 #include <sys/debug.h> 54 #include <sys/stropts.h> 55 #include <sys/stream.h> 56 #include <sys/strlog.h> 57 #ifndef COSIM 58 #include <sys/strsubr.h> 59 #endif 60 #include <sys/cmn_err.h> 61 #include <sys/vtrace.h> 62 #include <sys/kmem.h> 63 #include <sys/ddi.h> 64 #include <sys/sunddi.h> 65 #include <sys/strsun.h> 66 #include <sys/stat.h> 67 #include <sys/cpu.h> 68 #include <sys/kstat.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <sys/dlpi.h> 72 #include <inet/nd.h> 73 #include <netinet/in.h> 74 #include <sys/ethernet.h> 75 #include <sys/vlan.h> 76 #include <sys/pci.h> 77 #include <sys/taskq.h> 78 #include <sys/atomic.h> 79 80 #include <sys/nxge/nxge_defs.h> 81 #include <sys/nxge/nxge_hw.h> 82 #include <sys/nxge/nxge_mac.h> 83 #include <sys/nxge/nxge_mii.h> 84 #include <sys/nxge/nxge_fm.h> 85 #if !defined(IODIAG) 86 #include <sys/netlb.h> 87 #endif 88 89 #include <sys/ddi_intr.h> 90 91 #if defined(_KERNEL) 92 #include <sys/mac.h> 93 #include <sys/mac_impl.h> 94 #include <sys/mac_ether.h> 95 #endif 96 97 #if defined(sun4v) 98 #include <sys/hypervisor_api.h> 99 #include <sys/machsystm.h> 100 #include <sys/hsvc.h> 101 #endif 102 103 #include <sys/dld.h> 104 105 /* 106 * Handy macros (taken from bge driver) 107 */ 108 #define RBR_SIZE 4 109 #define DMA_COMMON_CHANNEL(area) ((area.dma_channel)) 110 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 111 #define DMA_COMMON_VPTR_INDEX(area, index) \ 112 (((char *)(area.kaddrp)) + \ 113 (index * RBR_SIZE)) 114 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 115 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 116 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 117 #define DMA_COMMON_IOADDR_INDEX(area, index) \ 118 ((area.dma_cookie.dmac_laddress) + \ 119 (index * RBR_SIZE)) 120 121 #define DMA_NPI_HANDLE(area) ((area.npi_handle) 122 123 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 124 (area).offset, (area).alength, \ 125 (flag))) 126 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 127 ((void) ddi_dma_sync((area).dma_handle,\ 128 (area.offset + bufoffset), len, \ 129 (flag))) 130 131 #define DMA_COMMON_SYNC_RBR_DESC(area, index, flag) \ 132 ((void) ddi_dma_sync((area).dma_handle,\ 133 (index * RBR_SIZE), RBR_SIZE, \ 134 (flag))) 135 136 #define DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag) \ 137 ((void) ddi_dma_sync((area).dma_handle,\ 138 (index * RBR_SIZE), count * RBR_SIZE, \ 139 (flag))) 140 #define DMA_COMMON_SYNC_ENTRY(area, index, flag) \ 141 ((void) ddi_dma_sync((area).dma_handle,\ 142 (index * (area).block_size), \ 143 (area).block_size, \ 144 (flag))) 145 146 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 147 #define NEXT_ENTRY_PTR(ptr, first, last) \ 148 ((ptr == last) ? first : (ptr + 1)) 149 150 /* 151 * NPI related macros 152 */ 153 #define NXGE_DEV_NPI_HANDLE(nxgep) (nxgep->npi_handle) 154 155 #define NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah) 156 #define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap) 157 158 #define NPI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_handle.regh = ah) 159 #define NPI_ADD_HANDLE_SET(nxgep, ap) \ 160 nxgep->npi_handle.is_vraddr = B_FALSE; \ 161 nxgep->npi_handle.function.instance = nxgep->instance; \ 162 nxgep->npi_handle.function.function = nxgep->function_num; \ 163 nxgep->npi_handle.nxgep = (void *) nxgep; \ 164 nxgep->npi_handle.regp = ap; 165 166 #define NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah) 167 #define NPI_REG_ADD_HANDLE_SET(nxgep, ap) \ 168 nxgep->npi_reg_handle.is_vraddr = B_FALSE; \ 169 nxgep->npi_handle.function.instance = nxgep->instance; \ 170 nxgep->npi_handle.function.function = nxgep->function_num; \ 171 nxgep->npi_reg_handle.nxgep = (void *) nxgep; \ 172 nxgep->npi_reg_handle.regp = ap; 173 174 #define NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah) 175 #define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap) 176 177 #define NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah) 178 #define NPI_VREG_ADD_HANDLE_SET(nxgep, ap) \ 179 nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \ 180 nxgep->npi_handle.function.instance = nxgep->instance; \ 181 nxgep->npi_handle.function.function = nxgep->function_num; \ 182 nxgep->npi_vreg_handle.nxgep = (void *) nxgep; \ 183 nxgep->npi_vreg_handle.regp = ap; 184 185 #define NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah) 186 #define NPI_V2REG_ADD_HANDLE_SET(nxgep, ap) \ 187 nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \ 188 nxgep->npi_handle.function.instance = nxgep->instance; \ 189 nxgep->npi_handle.function.function = nxgep->function_num; \ 190 nxgep->npi_v2reg_handle.nxgep = (void *) nxgep; \ 191 nxgep->npi_v2reg_handle.regp = ap; 192 193 #define NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh) 194 #define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp) 195 #define NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh) 196 #define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp) 197 #define NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh) 198 #define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp) 199 #define NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh) 200 #define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp) 201 #define NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh) 202 #define NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp) 203 #define NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh) 204 #define NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp) 205 206 #define NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah) 207 #define NPI_DMA_ACC_HANDLE_GET(dmap) (dmap->npi_handle.regh) 208 209 /* 210 * DMA handles. 211 */ 212 #define NXGE_DESC_D_HANDLE_GET(desc) (desc.dma_handle) 213 #define NXGE_DESC_D_IOADD_GET(desc) (desc.dma_cookie.dmac_laddress) 214 #define NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress) 215 #define NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress) 216 217 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 218 #define LDV2_ON_1(ldv, vector) ((vector >> (ldv - 64)) & 0x1) 219 #define LDV2_ON_2(ldv, vector) (((vector >> 5) >> (ldv - 64)) & 0x1) 220 221 typedef uint32_t nxge_status_t; 222 223 typedef enum { 224 IDLE, 225 PROGRESS, 226 CONFIGURED 227 } dev_func_shared_t; 228 229 typedef enum { 230 DVMA, 231 DMA, 232 SDMA 233 } dma_method_t; 234 235 typedef enum { 236 BKSIZE_4K, 237 BKSIZE_8K, 238 BKSIZE_16K, 239 BKSIZE_32K 240 } nxge_rx_block_size_t; 241 242 #ifdef TX_ONE_BUF 243 #define TX_BCOPY_MAX 1514 244 #else 245 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 246 #define TX_BCOPY_MAX 4096 247 #define TX_BCOPY_SIZE 4096 248 #else 249 #define TX_BCOPY_MAX 2048 250 #define TX_BCOPY_SIZE 2048 251 #endif 252 #endif 253 254 #define TX_STREAM_MIN 512 255 #define TX_FASTDVMA_MIN 1024 256 257 /* 258 * Send repeated FMA ereports or display messages about some non-fatal 259 * hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times 260 */ 261 #define NXGE_ERROR_SHOW_MAX 2 262 263 264 /* 265 * Defaults 266 */ 267 #define NXGE_RDC_RCR_THRESHOLD 8 268 #define NXGE_RDC_RCR_TIMEOUT 16 269 270 #define NXGE_RDC_RCR_THRESHOLD_MAX 1024 271 #define NXGE_RDC_RCR_TIMEOUT_MAX 64 272 #define NXGE_RDC_RCR_THRESHOLD_MIN 1 273 #define NXGE_RDC_RCR_TIMEOUT_MIN 1 274 #define NXGE_RCR_FULL_HEADER 1 275 276 #define NXGE_IS_VLAN_PACKET(ptr) \ 277 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 278 htons(VLAN_ETHERTYPE)) 279 280 typedef enum { 281 NONE, 282 SMALL, 283 MEDIUM, 284 LARGE 285 } dma_size_t; 286 287 typedef enum { 288 USE_NONE, 289 USE_BCOPY, 290 USE_DVMA, 291 USE_DMA, 292 USE_SDMA 293 } dma_type_t; 294 295 typedef enum { 296 NOT_IN_USE, 297 HDR_BUF, 298 MTU_BUF, 299 RE_ASSEMBLY_BUF, 300 FREE_BUF 301 } rx_page_state_t; 302 303 struct _nxge_block_mv_t { 304 uint32_t msg_type; 305 dma_type_t dma_type; 306 }; 307 308 typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t; 309 310 typedef enum { 311 NIU_TYPE_NONE = 0, 312 313 /* QGC NIC */ 314 NEPTUNE_4_1GC = 315 (NXGE_PORT_1G_COPPER | 316 (NXGE_PORT_1G_COPPER << 4) | 317 (NXGE_PORT_1G_COPPER << 8) | 318 (NXGE_PORT_1G_COPPER << 12)), 319 320 /* Huron: 2 fiber XAUI cards */ 321 NEPTUNE_2_10GF = 322 (NXGE_PORT_10G_FIBRE | 323 (NXGE_PORT_10G_FIBRE << 4) | 324 (NXGE_PORT_NONE << 8) | 325 (NXGE_PORT_NONE << 12)), 326 327 /* Huron: port0 is a TN1010 copper XAUI */ 328 NEPTUNE_1_TN1010 = 329 (NXGE_PORT_TN1010 | 330 (NXGE_PORT_NONE << 4) | 331 (NXGE_PORT_NONE << 8) | 332 (NXGE_PORT_NONE << 12)), 333 334 /* Huron: port1 is a TN1010 copper XAUI */ 335 NEPTUNE_1_NONE_1_TN1010 = 336 (NXGE_PORT_NONE | 337 (NXGE_PORT_TN1010 << 4) | 338 (NXGE_PORT_NONE << 8) | 339 (NXGE_PORT_NONE << 12)), 340 341 /* Huron: 2 TN1010 copper XAUI cards */ 342 NEPTUNE_2_TN1010 = 343 (NXGE_PORT_TN1010 | 344 (NXGE_PORT_TN1010 << 4) | 345 (NXGE_PORT_NONE << 8) | 346 (NXGE_PORT_NONE << 12)), 347 348 /* Huron: port0 is fiber XAUI, port1 is copper XAUI */ 349 NEPTUNE_1_10GF_1_TN1010 = 350 (NXGE_PORT_10G_FIBRE | 351 (NXGE_PORT_TN1010 << 4) | 352 (NXGE_PORT_NONE << 8) | 353 (NXGE_PORT_NONE << 12)), 354 355 /* Huron: port0 is copper XAUI, port1 is fiber XAUI */ 356 NEPTUNE_1_TN1010_1_10GF = 357 (NXGE_PORT_TN1010 | 358 (NXGE_PORT_10G_FIBRE << 4) | 359 (NXGE_PORT_NONE << 8) | 360 (NXGE_PORT_NONE << 12)), 361 362 /* Maramba: port0 and port1 are fiber XAUIs */ 363 NEPTUNE_2_10GF_2_1GC = 364 (NXGE_PORT_10G_FIBRE | 365 (NXGE_PORT_10G_FIBRE << 4) | 366 (NXGE_PORT_1G_COPPER << 8) | 367 (NXGE_PORT_1G_COPPER << 12)), 368 369 /* Maramba: port0 and port1 are copper TN1010 XAUIs */ 370 NEPTUNE_2_TN1010_2_1GC = 371 (NXGE_PORT_TN1010 | 372 (NXGE_PORT_TN1010 << 4) | 373 (NXGE_PORT_1G_COPPER << 8) | 374 (NXGE_PORT_1G_COPPER << 12)), 375 376 /* Maramba: port0 is copper XAUI, port1 is Fiber XAUI */ 377 NEPTUNE_1_TN1010_1_10GF_2_1GC = 378 (NXGE_PORT_TN1010 | 379 (NXGE_PORT_10G_FIBRE << 4) | 380 (NXGE_PORT_1G_COPPER << 8) | 381 (NXGE_PORT_1G_COPPER << 12)), 382 383 /* Maramba: port0 is fiber XAUI, port1 is copper XAUI */ 384 NEPTUNE_1_10GF_1_TN1010_2_1GC = 385 (NXGE_PORT_10G_FIBRE | 386 (NXGE_PORT_TN1010 << 4) | 387 (NXGE_PORT_1G_COPPER << 8) | 388 (NXGE_PORT_1G_COPPER << 12)), 389 390 /* Maramba: port0 is fiber XAUI */ 391 NEPTUNE_1_10GF_3_1GC = 392 (NXGE_PORT_10G_FIBRE | 393 (NXGE_PORT_1G_COPPER << 4) | 394 (NXGE_PORT_1G_COPPER << 8) | 395 (NXGE_PORT_1G_COPPER << 12)), 396 397 /* Maramba: port0 is TN1010 copper XAUI */ 398 NEPTUNE_1_TN1010_3_1GC = 399 (NXGE_PORT_TN1010 | 400 (NXGE_PORT_1G_COPPER << 4) | 401 (NXGE_PORT_1G_COPPER << 8) | 402 (NXGE_PORT_1G_COPPER << 12)), 403 404 /* Maramba: port1 is fiber XAUI */ 405 NEPTUNE_1_1GC_1_10GF_2_1GC = 406 (NXGE_PORT_1G_COPPER | 407 (NXGE_PORT_10G_FIBRE << 4) | 408 (NXGE_PORT_1G_COPPER << 8) | 409 (NXGE_PORT_1G_COPPER << 12)), 410 411 /* Maramba: port1 is TN1010 copper XAUI */ 412 NEPTUNE_1_1GC_1_TN1010_2_1GC = 413 (NXGE_PORT_1G_COPPER | 414 (NXGE_PORT_TN1010 << 4) | 415 (NXGE_PORT_1G_COPPER << 8) | 416 (NXGE_PORT_1G_COPPER << 12)), 417 418 NEPTUNE_2_1GRF = 419 (NXGE_PORT_NONE | 420 (NXGE_PORT_NONE << 4) | 421 (NXGE_PORT_1G_RGMII_FIBER << 8) | 422 (NXGE_PORT_1G_RGMII_FIBER << 12)), 423 424 NEPTUNE_2_10GF_2_1GRF = 425 (NXGE_PORT_10G_FIBRE | 426 (NXGE_PORT_10G_FIBRE << 4) | 427 (NXGE_PORT_1G_RGMII_FIBER << 8) | 428 (NXGE_PORT_1G_RGMII_FIBER << 12)), 429 430 N2_NIU = 431 (NXGE_PORT_RSVD | 432 (NXGE_PORT_RSVD << 4) | 433 (NXGE_PORT_RSVD << 8) | 434 (NXGE_PORT_RSVD << 12)) 435 436 } niu_type_t; 437 438 /* 439 * P_NEPTUNE_GENERIC: 440 * The cover-all case for Neptune (as opposed to NIU) where we do not 441 * care the exact platform as we do not do anything that is platform 442 * specific. 443 * P_NEPTUNE_ATLAS_2PORT: 444 * Dual Port Fiber Neptune based NIC (2XGF) 445 * P_NEPTUNE_ATLAS_4PORT: 446 * Quad Port Copper Neptune based NIC (QGC) 447 * P_NEPTUNE_NIU: 448 * This is NIU. Could be Huron, Glendale, Monza or any other NIU based 449 * platform. 450 */ 451 typedef enum { 452 P_NEPTUNE_NONE, 453 P_NEPTUNE_GENERIC, 454 P_NEPTUNE_ATLAS_2PORT, 455 P_NEPTUNE_ATLAS_4PORT, 456 P_NEPTUNE_MARAMBA_P0, 457 P_NEPTUNE_MARAMBA_P1, 458 P_NEPTUNE_ALONSO, 459 P_NEPTUNE_NIU 460 } platform_type_t; 461 462 #define NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \ 463 (((nxgep->platform_type) == P_NEPTUNE_ATLAS_2PORT) || \ 464 ((nxgep->platform_type) == P_NEPTUNE_ATLAS_4PORT) || \ 465 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 466 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1) || \ 467 ((nxgep->platform_type) == P_NEPTUNE_GENERIC) || \ 468 ((nxgep->platform_type) == P_NEPTUNE_ALONSO)) 469 470 #define NXGE_IS_XAUI_PLATFORM(nxgep) \ 471 (((nxgep->platform_type) == P_NEPTUNE_NIU) || \ 472 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 473 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1)) 474 475 476 typedef enum { 477 CFG_DEFAULT = 0, /* default cfg */ 478 CFG_EQUAL, /* Equal */ 479 CFG_FAIR, /* Equal */ 480 CFG_CLASSIFY, 481 CFG_L2_CLASSIFY, 482 CFG_L3_CLASSIFY, 483 CFG_L3_DISTRIBUTE, 484 CFG_L3_WEB, 485 CFG_L3_TCAM, 486 CFG_NOT_SPECIFIED, 487 CFG_CUSTOM /* Custom */ 488 } cfg_type_t; 489 490 typedef enum { 491 NO_MSG = 0x0, /* No message output or storage. */ 492 CONSOLE = 0x1, /* Messages are go to the console. */ 493 BUFFER = 0x2, /* Messages are go to the system buffer. */ 494 CON_BUF = 0x3, /* Messages are go to the console and */ 495 /* system buffer. */ 496 VERBOSE = 0x4 /* Messages are go out only in VERBOSE node. */ 497 } out_msg_t, *p_out_msg_t; 498 499 typedef enum { 500 DBG_NO_MSG = 0x0, /* No message output or storage. */ 501 DBG_CONSOLE = 0x1, /* Messages are go to the console. */ 502 DBG_BUFFER = 0x2, /* Messages are go to the system buffer. */ 503 DBG_CON_BUF = 0x3, /* Messages are go to the console and */ 504 /* system buffer. */ 505 STR_LOG = 4 /* Sessage sent to streams logging driver. */ 506 } out_dbgmsg_t, *p_out_dbgmsg_t; 507 508 typedef enum { 509 DDI_MEM_ALLOC, /* default (use ddi_dma_mem_alloc) */ 510 KMEM_ALLOC, /* use kmem_alloc(). */ 511 CONTIG_MEM_ALLOC /* use contig_mem_alloc() (N2/NIU only) */ 512 } buf_alloc_type_t; 513 514 #define BUF_ALLOCATED 0x00000001 515 #define BUF_ALLOCATED_WAIT_FREE 0x00000002 516 517 #if defined(_KERNEL) || defined(COSIM) 518 519 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 520 typedef struct ether_header ether_header_t, *p_ether_header_t; 521 typedef queue_t *p_queue_t; 522 523 #if !defined(IODIAG) 524 typedef mblk_t *p_mblk_t; 525 #endif 526 527 /* 528 * Generic phy table to support different phy types. 529 * 530 * The argument for check_link is nxgep, which is passed to check_link 531 * as an argument to the timer routine. 532 */ 533 typedef struct _nxge_xcvr_table { 534 nxge_status_t (*serdes_init) (); /* Serdes init routine */ 535 nxge_status_t (*xcvr_init) (); /* xcvr init routine */ 536 nxge_status_t (*link_intr_stop) (); /* Link intr disable routine */ 537 nxge_status_t (*link_intr_start) (); /* Link intr enable routine */ 538 nxge_status_t (*check_link) (); /* Link check routine */ 539 540 uint32_t xcvr_inuse; 541 } nxge_xcvr_table_t, *p_nxge_xcvr_table_t; 542 543 /* 544 * Common DMA data elements. 545 */ 546 typedef struct _nxge_dma_pool_t nxge_dma_pool_t, *p_nxge_dma_pool_t; 547 548 struct _nxge_dma_common_t { 549 uint16_t dma_channel; 550 void *kaddrp; 551 void *first_kaddrp; 552 void *last_kaddrp; 553 void *ioaddr_pp; 554 void *first_ioaddr_pp; 555 void *last_ioaddr_pp; 556 ddi_dma_cookie_t dma_cookie; 557 uint32_t ncookies; 558 559 nxge_block_mv_t msg_dma_flags; 560 ddi_dma_handle_t dma_handle; 561 nxge_os_acc_handle_t acc_handle; 562 npi_handle_t npi_handle; 563 564 size_t block_size; 565 uint32_t nblocks; 566 size_t alength; 567 uint_t offset; 568 uint_t dma_chunk_index; 569 void *orig_ioaddr_pp; 570 uint64_t orig_vatopa; 571 void *orig_kaddrp; 572 size_t orig_alength; 573 boolean_t contig_alloc_type; 574 /* 575 * Receive buffers may be allocated using 576 * kmem_alloc(). The buffer free function 577 * depends on its allocation function. 578 */ 579 boolean_t kmem_alloc_type; 580 uint32_t buf_alloc_state; 581 buf_alloc_type_t buf_alloc_type; 582 p_nxge_dma_pool_t rx_buf_pool_p; 583 }; 584 585 typedef struct _nxge_t nxge_t, *p_nxge_t; 586 typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t; 587 588 struct _nxge_dma_pool_t { 589 p_nxge_dma_common_t *dma_buf_pool_p; 590 uint32_t ndmas; 591 uint32_t *num_chunks; 592 boolean_t buf_allocated; 593 }; 594 595 /* 596 * Each logical device (69): 597 * - LDG # 598 * - flag bits 599 * - masks. 600 * - interrupt handler function. 601 * 602 * Generic system interrupt handler with two arguments: 603 * (nxge_sys_intr_t) 604 * Per device instance data structure 605 * Logical group data structure. 606 * 607 * Logical device interrupt handler with two arguments: 608 * (nxge_ldv_intr_t) 609 * Per device instance data structure 610 * Logical device number 611 */ 612 typedef struct _nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t; 613 typedef struct _nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t; 614 typedef uint_t (*nxge_sys_intr_t)(void *arg1, void *arg2); 615 typedef uint_t (*nxge_ldv_intr_t)(void *arg1, void *arg2); 616 617 /* 618 * Each logical device Group (64) needs to have the following 619 * configurations: 620 * - timer counter (6 bits) 621 * - timer resolution (20 bits, number of system clocks) 622 * - system data (7 bits) 623 */ 624 struct _nxge_ldg_t { 625 uint8_t ldg; /* logical group number */ 626 uint8_t vldg_index; 627 boolean_t arm; 628 boolean_t interrupted; 629 uint16_t ldg_timer; /* counter */ 630 uint8_t func; 631 uint8_t vector; 632 uint8_t intdata; 633 uint8_t nldvs; 634 p_nxge_ldv_t ldvp; 635 nxge_sys_intr_t sys_intr_handler; 636 uint_t (*ih_cb_func)(caddr_t, caddr_t); 637 p_nxge_t nxgep; 638 }; 639 640 struct _nxge_ldv_t { 641 uint8_t ldg_assigned; 642 uint8_t ldv; 643 boolean_t is_rxdma; 644 boolean_t is_txdma; 645 boolean_t is_mif; 646 boolean_t is_mac; 647 boolean_t is_syserr; 648 boolean_t use_timer; 649 uint8_t channel; 650 uint8_t vdma_index; 651 uint8_t func; 652 p_nxge_ldg_t ldgp; 653 uint8_t ldv_flags; 654 boolean_t is_leve; 655 boolean_t is_edge; 656 uint8_t ldv_ldf_masks; 657 nxge_ldv_intr_t ldv_intr_handler; 658 uint_t (*ih_cb_func)(caddr_t, caddr_t); 659 p_nxge_t nxgep; 660 }; 661 #endif 662 663 typedef struct _nxge_logical_page_t { 664 uint16_t dma; 665 uint16_t page; 666 boolean_t valid; 667 uint64_t mask; 668 uint64_t value; 669 uint64_t reloc; 670 uint32_t handle; 671 } nxge_logical_page_t, *p_nxge_logical_page_t; 672 673 /* 674 * (Internal) return values from ioctl subroutines. 675 */ 676 enum nxge_ioc_reply { 677 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 678 IOC_DONE, /* OK, reply sent */ 679 IOC_ACK, /* OK, just send ACK */ 680 IOC_REPLY, /* OK, just send reply */ 681 IOC_RESTART_ACK, /* OK, restart & ACK */ 682 IOC_RESTART_REPLY /* OK, restart & reply */ 683 }; 684 685 typedef struct _pci_cfg_t { 686 uint16_t vendorid; 687 uint16_t devid; 688 uint16_t command; 689 uint16_t status; 690 uint8_t revid; 691 uint8_t res0; 692 uint16_t junk1; 693 uint8_t cache_line; 694 uint8_t latency; 695 uint8_t header; 696 uint8_t bist; 697 uint32_t base; 698 uint32_t base14; 699 uint32_t base18; 700 uint32_t base1c; 701 uint32_t base20; 702 uint32_t base24; 703 uint32_t base28; 704 uint32_t base2c; 705 uint32_t base30; 706 uint32_t res1[2]; 707 uint8_t int_line; 708 uint8_t int_pin; 709 uint8_t min_gnt; 710 uint8_t max_lat; 711 } pci_cfg_t, *p_pci_cfg_t; 712 713 #if defined(_KERNEL) || defined(COSIM) 714 715 typedef struct _dev_regs_t { 716 nxge_os_acc_handle_t nxge_pciregh; /* PCI config DDI IO handle */ 717 p_pci_cfg_t nxge_pciregp; /* mapped PCI registers */ 718 719 nxge_os_acc_handle_t nxge_regh; /* device DDI IO (BAR 0) */ 720 void *nxge_regp; /* mapped device registers */ 721 722 nxge_os_acc_handle_t nxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 723 void *nxge_msix_regp; /* MSI/X register */ 724 725 nxge_os_acc_handle_t nxge_vir_regh; /* virtualization (BAR 4) */ 726 unsigned char *nxge_vir_regp; /* virtualization register */ 727 728 nxge_os_acc_handle_t nxge_vir2_regh; /* second virtualization */ 729 unsigned char *nxge_vir2_regp; /* second virtualization */ 730 731 nxge_os_acc_handle_t nxge_romh; /* fcode rom handle */ 732 unsigned char *nxge_romp; /* fcode pointer */ 733 } dev_regs_t, *p_dev_regs_t; 734 735 736 typedef struct _nxge_mac_addr_t { 737 ether_addr_t addr; 738 uint_t flags; 739 } nxge_mac_addr_t; 740 741 /* 742 * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac) 743 * for each XMAC port and supports 1 unique MAC and 7 alternate MACs 744 * for each BMAC port. The number of MACs assigned by the factory is 745 * different and is as follows, 746 * BMAC port: num_factory_mmac = num_mmac = 7 747 * XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15 748 * XMAC port on a 4-port NIC: num_factory_mmac = 7 749 * So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses 750 * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac. 751 * 752 * total_factory_macs is the total number of factory MACs, including 753 * the unique MAC, assigned to a Neptune based NIC card, it is 32. 754 */ 755 typedef struct _nxge_mmac_t { 756 uint8_t total_factory_macs; 757 uint8_t num_mmac; 758 uint8_t num_factory_mmac; 759 nxge_mac_addr_t mac_pool[XMAC_MAX_ADDR_ENTRY]; 760 ether_addr_t factory_mac_pool[XMAC_MAX_ADDR_ENTRY]; 761 uint8_t naddrfree; /* number of alt mac addr available */ 762 } nxge_mmac_t; 763 764 /* 765 * mmac stats structure 766 */ 767 typedef struct _nxge_mmac_stats_t { 768 uint8_t mmac_max_cnt; 769 uint8_t mmac_avail_cnt; 770 struct ether_addr mmac_avail_pool[16]; 771 } nxge_mmac_stats_t, *p_nxge_mmac_stats_t; 772 773 #define NXGE_MAX_MMAC_ADDRS 32 774 #define NXGE_NUM_MMAC_ADDRS 8 775 #define NXGE_NUM_OF_PORTS_QUAD 4 776 #define NXGE_NUM_OF_PORTS_DUAL 2 777 778 #define NXGE_QGC_LP_BM_STR "501-7606" 779 #define NXGE_2XGF_LP_BM_STR "501-7283" 780 #define NXGE_QGC_PEM_BM_STR "501-7765" 781 #define NXGE_2XGF_PEM_BM_STR "501-7626" 782 #define NXGE_ALONSO_BM_STR "373-0202-01" 783 #define NXGE_ALONSO_MODEL_STR "SUNW,CP3220" 784 #define NXGE_RFEM_BM_STR "501-7961-01" 785 #define NXGE_RFEM_MODEL_STR "SUNW,pcie-rfem" 786 #define NXGE_ARTM_BM_STR "375-3544-01" 787 #define NXGE_ARTM_MODEL_STR "SUNW,pcie-artm" 788 #define NXGE_EROM_LEN 1048576 789 790 #endif 791 792 #include <sys/nxge/nxge_common_impl.h> 793 #include <sys/nxge/nxge_common.h> 794 #include <sys/nxge/nxge_txc.h> 795 #include <sys/nxge/nxge_rxdma.h> 796 #include <sys/nxge/nxge_txdma.h> 797 #include <sys/nxge/nxge_fflp.h> 798 #include <sys/nxge/nxge_ipp.h> 799 #include <sys/nxge/nxge_zcp.h> 800 #include <sys/nxge/nxge_fzc.h> 801 #include <sys/nxge/nxge_flow.h> 802 #include <sys/nxge/nxge_virtual.h> 803 804 #include <npi_espc.h> 805 #include <npi_vir.h> 806 807 #include <sys/nxge/nxge.h> 808 809 #include <sys/modctl.h> 810 #include <sys/pattr.h> 811 812 extern int secpolicy_net_config(const cred_t *, boolean_t); 813 extern void nxge_fm_report_error(p_nxge_t, uint8_t, 814 uint8_t, nxge_fm_ereport_id_t); 815 extern int fm_check_acc_handle(ddi_acc_handle_t); 816 extern int fm_check_dma_handle(ddi_dma_handle_t); 817 818 /* nxge_classify.c */ 819 nxge_status_t nxge_classify_init(p_nxge_t); 820 nxge_status_t nxge_classify_uninit(p_nxge_t); 821 nxge_status_t nxge_set_hw_classify_config(p_nxge_t); 822 nxge_status_t nxge_classify_exit_sw(p_nxge_t); 823 824 /* nxge_fflp.c */ 825 void nxge_put_tcam(p_nxge_t, p_mblk_t); 826 void nxge_get_tcam(p_nxge_t, p_mblk_t); 827 nxge_status_t nxge_classify_init_hw(p_nxge_t); 828 nxge_status_t nxge_classify_init_sw(p_nxge_t); 829 nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t); 830 nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t, 831 uint32_t); 832 833 nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t, 834 tcam_class_t, 835 uint32_t *); 836 837 nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t, 838 uint32_t); 839 840 nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t, 841 uint32_t); 842 843 uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t); 844 nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *); 845 nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t); 846 nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t); 847 848 nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t); 849 nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t); 850 851 nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t); 852 nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t); 853 854 nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t); 855 nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t); 856 857 nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t); 858 859 nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t); 860 861 nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t); 862 863 void nxge_handle_tcam_fragment_bug(p_nxge_t); 864 nxge_status_t nxge_fflp_hw_reset(p_nxge_t); 865 nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t); 866 nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t); 867 868 /* nxge_kstats.c */ 869 void nxge_init_statsp(p_nxge_t); 870 void nxge_setup_kstats(p_nxge_t); 871 void nxge_setup_rdc_kstats(p_nxge_t, int); 872 void nxge_setup_tdc_kstats(p_nxge_t, int); 873 void nxge_destroy_kstats(p_nxge_t); 874 int nxge_port_kstat_update(kstat_t *, int); 875 void nxge_save_cntrs(p_nxge_t); 876 877 int nxge_m_stat(void *arg, uint_t, uint64_t *); 878 879 /* nxge_hw.c */ 880 void 881 nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 882 void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 883 nxge_status_t nxge_global_reset(p_nxge_t); 884 uint_t nxge_intr(void *, void *); 885 void nxge_intr_enable(p_nxge_t); 886 void nxge_intr_disable(p_nxge_t); 887 void nxge_hw_blank(void *arg, time_t, uint_t); 888 void nxge_hw_id_init(p_nxge_t); 889 void nxge_hw_init_niu_common(p_nxge_t); 890 void nxge_intr_hw_enable(p_nxge_t); 891 void nxge_intr_hw_disable(p_nxge_t); 892 void nxge_hw_stop(p_nxge_t); 893 void nxge_check_hw_state(p_nxge_t); 894 895 void nxge_rxdma_channel_put64(nxge_os_acc_handle_t, 896 void *, uint32_t, uint16_t, 897 uint64_t); 898 uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *, 899 uint32_t, uint16_t); 900 901 902 void nxge_get32(p_nxge_t, p_mblk_t); 903 void nxge_put32(p_nxge_t, p_mblk_t); 904 905 void nxge_hw_set_mac_modes(p_nxge_t); 906 907 /* nxge_send.c. */ 908 uint_t nxge_reschedule(caddr_t); 909 910 /* nxge_rxdma.c */ 911 nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t, 912 uint8_t, uint8_t); 913 914 nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t, 915 uint8_t, uint8_t); 916 nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t, 917 uint16_t); 918 nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t, 919 uint16_t, uint8_t); 920 921 /* nxge_ndd.c */ 922 void nxge_get_param_soft_properties(p_nxge_t); 923 void nxge_copy_hw_default_to_param(p_nxge_t); 924 void nxge_copy_param_hw_to_config(p_nxge_t); 925 void nxge_setup_param(p_nxge_t); 926 void nxge_init_param(p_nxge_t); 927 void nxge_destroy_param(p_nxge_t); 928 boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t); 929 boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t); 930 boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t); 931 932 boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t); 933 934 int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t); 935 int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 936 int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 937 int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t); 938 int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 939 int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t); 940 long nxge_strtol(char *, char **, int); 941 boolean_t nxge_param_get_instance(queue_t *, mblk_t *); 942 void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 943 boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 944 void nxge_nd_free(caddr_t *); 945 int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t); 946 947 nxge_status_t nxge_set_lb_normal(p_nxge_t); 948 boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t); 949 boolean_t nxge_param_link_update(p_nxge_t); 950 int nxge_param_set_ip_opt(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 951 int nxge_dld_get_ip_opt(p_nxge_t, caddr_t); 952 int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 953 mblk_t *, char *, caddr_t); 954 int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 955 mblk_t *, char *, caddr_t); 956 957 958 /* nxge_virtual.c */ 959 nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *); 960 void nxge_common_lock_get(p_nxge_t); 961 void nxge_common_lock_free(p_nxge_t); 962 963 nxge_status_t nxge_get_config_properties(p_nxge_t); 964 void nxge_get_xcvr_properties(p_nxge_t); 965 void nxge_init_vlan_config(p_nxge_t); 966 void nxge_init_mac_config(p_nxge_t); 967 968 969 void nxge_init_logical_devs(p_nxge_t); 970 int nxge_init_ldg_intrs(p_nxge_t); 971 972 void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t, 973 uint32_t); 974 975 void nxge_init_fzc_txdma_channels(p_nxge_t); 976 977 nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t, 978 p_tx_ring_t, p_tx_mbox_t); 979 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 980 981 nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t); 982 983 nxge_status_t nxge_init_fzc_rx_common(p_nxge_t); 984 nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t); 985 986 nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t, 987 uint16_t, p_rx_rbr_ring_t); 988 nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t, 989 uint16_t, p_rx_rcr_ring_t); 990 991 nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t, 992 uint16_t, p_rx_rbr_ring_t); 993 994 995 nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t, 996 uint16_t, p_tx_ring_t); 997 998 nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t, 999 p_tx_ring_t); 1000 1001 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 1002 1003 void nxge_init_fzc_ldg_num(p_nxge_t); 1004 void nxge_init_fzc_sys_int_data(p_nxge_t); 1005 void nxge_init_fzc_ldg_int_timer(p_nxge_t); 1006 nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on); 1007 1008 /* MAC functions */ 1009 nxge_status_t nxge_mac_init(p_nxge_t); 1010 nxge_status_t nxge_link_init(p_nxge_t); 1011 nxge_status_t nxge_xif_init(p_nxge_t); 1012 nxge_status_t nxge_pcs_init(p_nxge_t); 1013 nxge_status_t nxge_mac_ctrl_init(p_nxge_t); 1014 nxge_status_t nxge_serdes_init(p_nxge_t); 1015 nxge_status_t nxge_serdes_reset(p_nxge_t); 1016 nxge_status_t nxge_xcvr_find(p_nxge_t); 1017 nxge_status_t nxge_get_xcvr_type(p_nxge_t); 1018 nxge_status_t nxge_setup_xcvr_table(p_nxge_t); 1019 nxge_status_t nxge_xcvr_init(p_nxge_t); 1020 nxge_status_t nxge_tx_mac_init(p_nxge_t); 1021 nxge_status_t nxge_rx_mac_init(p_nxge_t); 1022 nxge_status_t nxge_tx_mac_enable(p_nxge_t); 1023 nxge_status_t nxge_tx_mac_disable(p_nxge_t); 1024 nxge_status_t nxge_rx_mac_enable(p_nxge_t); 1025 nxge_status_t nxge_rx_mac_disable(p_nxge_t); 1026 nxge_status_t nxge_tx_mac_reset(p_nxge_t); 1027 nxge_status_t nxge_rx_mac_reset(p_nxge_t); 1028 nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t); 1029 nxge_status_t nxge_mii_xcvr_init(p_nxge_t); 1030 nxge_status_t nxge_mii_xcvr_fiber_init(p_nxge_t); 1031 nxge_status_t nxge_mii_read(p_nxge_t, uint8_t, 1032 uint8_t, uint16_t *); 1033 nxge_status_t nxge_mii_write(p_nxge_t, uint8_t, 1034 uint8_t, uint16_t); 1035 nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t, 1036 uint16_t, uint16_t *); 1037 nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t, 1038 uint8_t, uint16_t, uint16_t); 1039 nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t, 1040 mii_bmsr_t, nxge_link_state_t *); 1041 void nxge_pcs_check(p_nxge_t, uint8_t portn, nxge_link_state_t *); 1042 nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *); 1043 nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *); 1044 nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *); 1045 nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *); 1046 nxge_status_t nxge_check_tn1010_link(p_nxge_t); 1047 void nxge_link_is_down(p_nxge_t); 1048 void nxge_link_is_up(p_nxge_t); 1049 nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t); 1050 uint32_t crc32_mchash(p_ether_addr_t); 1051 nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t); 1052 nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t); 1053 nxge_status_t nxge_10g_link_led_on(p_nxge_t); 1054 nxge_status_t nxge_10g_link_led_off(p_nxge_t); 1055 nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t); 1056 boolean_t nxge_is_valid_local_mac(ether_addr_st); 1057 nxge_status_t nxge_mac_set_framesize(p_nxge_t); 1058 1059 /* espc (sprom) prototypes */ 1060 nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t); 1061 nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *); 1062 nxge_status_t nxge_espc_num_ports_get(p_nxge_t); 1063 nxge_status_t nxge_espc_phy_type_get(p_nxge_t); 1064 nxge_status_t nxge_espc_verify_chksum(p_nxge_t); 1065 void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *); 1066 void nxge_vpd_info_get(p_nxge_t); 1067 1068 1069 void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...); 1070 int nxge_get_nports(p_nxge_t); 1071 1072 void nxge_free_buf(buf_alloc_type_t, uint64_t, uint32_t); 1073 1074 uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t, 1075 uint64_t, uint64_t); 1076 #pragma weak hv_niu_rx_logical_page_conf 1077 1078 uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t, 1079 uint64_t *, uint64_t *); 1080 #pragma weak hv_niu_rx_logical_page_info 1081 1082 uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t, 1083 uint64_t, uint64_t); 1084 #pragma weak hv_niu_tx_logical_page_conf 1085 1086 uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t, 1087 uint64_t *, uint64_t *); 1088 #pragma weak hv_niu_tx_logical_page_info 1089 1090 uint64_t hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie); 1091 #pragma weak hv_niu_vr_assign 1092 1093 uint64_t hv_niu_vr_unassign(uint32_t cookie); 1094 #pragma weak hv_niu_vr_unassign 1095 1096 uint64_t hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, 1097 uint64_t *size); 1098 #pragma weak hv_niu_vr_getinfo 1099 1100 uint64_t hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map); 1101 #pragma weak hv_niu_vr_get_rxmap 1102 1103 uint64_t hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map); 1104 #pragma weak hv_niu_vr_get_txmap 1105 1106 uint64_t hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, 1107 uint64_t *vchidx); 1108 #pragma weak hv_niu_rx_dma_assign 1109 1110 uint64_t hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t chidx); 1111 #pragma weak hv_niu_rx_dma_unassign 1112 1113 uint64_t hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, 1114 uint64_t *vchidx); 1115 #pragma weak hv_niu_tx_dma_assign 1116 1117 uint64_t hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx); 1118 #pragma weak hv_niu_tx_dma_unassign 1119 1120 uint64_t hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, 1121 uint64_t pgidx, uint64_t raddr, uint64_t size); 1122 #pragma weak hv_niu_vrrx_logical_page_conf 1123 1124 uint64_t hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, 1125 uint64_t pgidx, uint64_t *raddr, uint64_t *size); 1126 #pragma weak hv_niu_vrrx_logical_page_info 1127 1128 uint64_t hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, 1129 uint64_t pgidx, uint64_t raddr, uint64_t size); 1130 #pragma weak hv_niu_vrtx_logical_page_conf 1131 1132 uint64_t hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, 1133 uint64_t pgidx, uint64_t *raddr, uint64_t *size); 1134 #pragma weak hv_niu_vrtx_logical_page_info 1135 1136 // 1137 // NIU-specific interrupt API 1138 // 1139 uint64_t hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t v_chidx, 1140 uint64_t *group, uint64_t *logdev); 1141 #pragma weak hv_niu_vrrx_getinfo 1142 1143 uint64_t hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t v_chidx, 1144 uint64_t *group, uint64_t *logdev); 1145 #pragma weak hv_niu_vrtx_getinfo 1146 1147 uint64_t hv_niu_vrrx_to_logical_dev(uint32_t cookie, uint64_t v_chidx, 1148 uint64_t *ldn); 1149 #pragma weak hv_niu_vrrx_to_logical_dev 1150 1151 uint64_t hv_niu_vrtx_to_logical_dev(uint32_t cookie, uint64_t v_chidx, 1152 uint64_t *ldn); 1153 #pragma weak hv_niu_vrtx_to_logical_dev 1154 1155 #ifdef NXGE_DEBUG 1156 char *nxge_dump_packet(char *, int); 1157 #endif 1158 1159 #endif /* !_ASM */ 1160 1161 #ifdef __cplusplus 1162 } 1163 #endif 1164 1165 #endif /* _SYS_NXGE_NXGE_IMPL_H */ 1166