1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_COMMON_H 27 #define _SYS_NXGE_NXGE_COMMON_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define NXGE_DMA_START B_TRUE 36 #define NXGE_DMA_STOP B_FALSE 37 38 /* 39 * Default DMA configurations. 40 */ 41 #define NXGE_RDMA_PER_NIU_PORT (NXGE_MAX_RDCS/NXGE_PORTS_NIU) 42 #define NXGE_TDMA_PER_NIU_PORT (NXGE_MAX_TDCS_NIU/NXGE_PORTS_NIU) 43 #define NXGE_RDMA_PER_NEP_PORT (NXGE_MAX_RDCS/NXGE_PORTS_NEPTUNE) 44 #define NXGE_TDMA_PER_NEP_PORT (NXGE_MAX_TDCS/NXGE_PORTS_NEPTUNE) 45 #define NXGE_RDCGRP_PER_NIU_PORT (NXGE_MAX_RDC_GROUPS/NXGE_PORTS_NIU) 46 #define NXGE_RDCGRP_PER_NEP_PORT (NXGE_MAX_RDC_GROUPS/NXGE_PORTS_NEPTUNE) 47 48 #define NXGE_TIMER_RESO 2 49 50 #define NXGE_TIMER_LDG 2 51 52 /* 53 * Receive and Transmit DMA definitions 54 */ 55 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 56 /* 57 * N2/NIU: Maximum descriptors if we need to call 58 * Hypervisor to set up the logical pages 59 * and the driver must use contiguous memory. 60 */ 61 #define NXGE_NIU_MAX_ENTRY (1 << 9) /* 512 */ 62 #define NXGE_NIU_CONTIG_RBR_MAX (NXGE_NIU_MAX_ENTRY) 63 #define NXGE_NIU_CONTIG_RCR_MAX (NXGE_NIU_MAX_ENTRY) 64 #define NXGE_NIU_CONTIG_TX_MAX (NXGE_NIU_MAX_ENTRY) 65 #endif 66 67 #ifdef _DMA_USES_VIRTADDR 68 #ifdef NIU_PA_WORKAROUND 69 #define NXGE_DMA_BLOCK (16 * 64 * 4) 70 #else 71 #define NXGE_DMA_BLOCK 1 72 #endif 73 #else 74 #define NXGE_DMA_BLOCK (64 * 64) 75 #endif 76 77 #define NXGE_RBR_RBB_MIN (128) 78 #define NXGE_RBR_RBB_MAX (64 * 128 -1) 79 80 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 81 #define NXGE_RBR_RBB_DEFAULT 512 82 #define NXGE_RBR_SPARE 0 83 #else 84 #if defined(__i386) 85 #define NXGE_RBR_RBB_DEFAULT 256 86 #else 87 #define NXGE_RBR_RBB_DEFAULT (64 * 16) /* x86 hello */ 88 #endif 89 #define NXGE_RBR_SPARE 0 90 #endif 91 92 93 #define NXGE_RCR_MIN (NXGE_RBR_RBB_MIN * 2) 94 95 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 96 #define NXGE_RCR_MAX (NXGE_NIU_CONTIG_RCR_MAX) 97 #define NXGE_RCR_DEFAULT (512) 98 #define NXGE_TX_RING_DEFAULT (512) 99 #else 100 #ifndef NIU_PA_WORKAROUND 101 #define NXGE_RCR_MAX (65355) /* MAX hardware supported */ 102 #if defined(_BIG_ENDIAN) 103 #define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 8) 104 #else 105 #ifdef USE_RX_BIG_BUF 106 #define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 8) 107 #else 108 #define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 4) 109 #endif 110 #endif 111 #if defined(__i386) 112 #define NXGE_TX_RING_DEFAULT (256) 113 #else 114 #define NXGE_TX_RING_DEFAULT (1024) 115 #endif 116 #define NXGE_TX_RING_MAX (64 * 128 - 1) 117 #else 118 #if defined(__i386) 119 #define NXGE_RCR_DEFAULT (256) 120 #define NXGE_TX_RING_DEFAULT (256) 121 #else 122 #define NXGE_RCR_DEFAULT (512) 123 #define NXGE_TX_RING_DEFAULT (512) 124 #endif 125 #define NXGE_RCR_MAX (1024) 126 #define NXGE_TX_RING_MAX (1024) 127 #endif 128 #endif 129 130 #define NXGE_TX_RECLAIM 32 131 132 /* per receive DMA channel configuration data structure */ 133 typedef struct nxge_rdc_cfg { 134 uint32_t flag; /* 0: not configured, 1: configured */ 135 struct nxge_hw_list *nxge_hw_p; 136 uint32_t partition_id; 137 uint32_t port; /* function number */ 138 uint32_t rx_group_id; 139 140 /* Partitioning, DMC function zero. */ 141 uint32_t rx_log_page_vld_page0; /* TRUE or FALSE */ 142 uint32_t rx_log_page_vld_page1; /* TRUE or FALSE */ 143 uint64_t rx_log_mask1; 144 uint64_t rx_log_value1; 145 uint64_t rx_log_mask2; 146 uint64_t rx_log_value2; 147 uint64_t rx_log_page_relo1; 148 uint64_t rx_log_page_relo2; 149 uint64_t rx_log_page_hdl; 150 151 /* WRED parameters, DMC function zero */ 152 uint32_t red_enable; 153 154 uint32_t thre_syn; 155 uint32_t win_syn; 156 uint32_t threshold; 157 uint32_t win_non_syn; 158 159 /* RXDMA configuration, DMC */ 160 char *rdc_mbaddr_p; /* mailbox address */ 161 uint32_t min_flag; /* TRUE for 18 bytes header */ 162 163 /* Software Reserved Packet Buffer Offset, DMC */ 164 uint32_t sw_offset; 165 166 /* RBR Configuration A */ 167 uint64_t rbr_staddr; /* starting address of RBR */ 168 uint32_t rbr_nblks; /* # of RBR entries */ 169 uint32_t rbr_len; /* # of RBR entries in 64B lines */ 170 171 /* RBR Configuration B */ 172 uint32_t bksize; /* Block size is fixed. */ 173 #define RBR_BKSIZE_4K 0 174 #define RBR_BKSIZE_4K_BYTES (4 * 1024) 175 #define RBR_BKSIZE_8K 1 176 #define RBR_BKSIZE_8K_BYTES (8 * 1024) 177 #define RBR_BKSIZE_16K 2 178 #define RBR_BKSIZE_16K_BYTES (16 * 1024) 179 #define RBR_BKSIZE_32K 3 180 #define RBR_BKSIZE_32K_BYTES (32 * 1024) 181 182 uint32_t bufsz2; 183 #define RBR_BUFSZ2_2K 0 184 #define RBR_BUFSZ2_2K_BYTES (2 * 1024) 185 #define RBR_BUFSZ2_4K 1 186 #define RBR_BUFSZ2_4K_BYTES (4 * 1024) 187 #define RBR_BUFSZ2_8K 2 188 #define RBR_BUFSZ2_8K_BYTES (8 * 1024) 189 #define RBR_BUFSZ2_16K 3 190 #define RBR_BUFSZ2_16K_BYTES (16 * 1024) 191 192 uint32_t bufsz1; 193 #define RBR_BUFSZ1_1K 0 194 #define RBR_BUFSZ1_1K_BYTES 1024 195 #define RBR_BUFSZ1_2K 1 196 #define RBR_BUFSZ1_2K_BYTES (2 * 1024) 197 #define RBR_BUFSZ1_4K 2 198 #define RBR_BUFSZ1_4K_BYTES (4 * 1024) 199 #define RBR_BUFSZ1_8K 3 200 #define RBR_BUFSZ1_8K_BYTES (8 * 1024) 201 202 uint32_t bufsz0; 203 #define RBR_BUFSZ0_256B 0 204 #define RBR_BUFSZ0_256_BYTES 256 205 #define RBR_BUFSZ0_512B 1 206 #define RBR_BUFSZ0_512B_BYTES 512 207 #define RBR_BUFSZ0_1K 2 208 #define RBR_BUFSZ0_1K_BYTES (1024) 209 #define RBR_BUFSZ0_2K 3 210 #define RBR_BUFSZ0_2K_BYTES (2 * 1024) 211 212 /* Receive buffers added by the software */ 213 uint32_t bkadd; /* maximum size is 1 million */ 214 215 /* Receive Completion Ring Configuration A */ 216 uint32_t rcr_len; /* # of 64B blocks, each RCR is 8B */ 217 uint64_t rcr_staddr; 218 219 /* Receive Completion Ring Configuration B */ 220 uint32_t pthres; /* packet threshold */ 221 uint32_t entout; /* enable timeout */ 222 uint32_t timeout; /* timeout value */ 223 224 /* Logical Device Group Number */ 225 uint16_t rx_ldg; 226 uint16_t rx_ld_state_flags; 227 228 /* Receive DMA Channel Event Mask */ 229 uint64_t rx_dma_ent_mask; 230 231 /* 32 bit (set to 1) or 64 bit (set to 0) addressing mode */ 232 uint32_t rx_addr_md; 233 } nxge_rdc_cfg_t, *p_nxge_rdc_cfg_t; 234 235 /* 236 * Per Transmit DMA Channel Configuration Data Structure (32 TDC) 237 */ 238 typedef struct nxge_tdc_cfg { 239 uint32_t flag; /* 0: not configured 1: configured */ 240 struct nxge_hw_list *nxge_hw_p; 241 uint32_t partition_id; 242 uint32_t port; /* function number */ 243 /* partitioning, DMC function zero (All 0s for non-partitioning) */ 244 uint32_t tx_log_page_vld_page0; /* TRUE or FALSE */ 245 uint32_t tx_log_page_vld_page1; /* TRUE or FALSE */ 246 uint64_t tx_log_mask1; 247 uint64_t tx_log_value1; 248 uint64_t tx_log_mask2; 249 uint64_t tx_log_value2; 250 uint64_t tx_log_page_relo1; 251 uint64_t tx_log_page_relo2; 252 uint64_t tx_log_page_hdl; 253 254 /* Transmit Ring Configuration */ 255 uint64_t tx_staddr; 256 uint64_t tx_rng_len; /* in 64 B Blocks */ 257 #define TX_MAX_BUF_SIZE 4096 258 259 /* TXDMA configuration, DMC */ 260 char *tdc_mbaddr_p; /* mailbox address */ 261 262 /* Logical Device Group Number */ 263 uint16_t tx_ldg; 264 uint16_t tx_ld_state_flags; 265 266 /* TXDMA event flags */ 267 uint64_t tx_event_mask; 268 269 /* Transmit threshold before reclamation */ 270 uint32_t tx_rng_threshold; 271 #define TX_RING_THRESHOLD (TX_DEFAULT_MAX_GPS/4) 272 #define TX_RING_JUMBO_THRESHOLD (TX_DEFAULT_JUMBO_MAX_GPS/4) 273 274 /* For reclaim: a wrap-around counter (packets transmitted) */ 275 uint32_t tx_pkt_cnt; 276 /* last packet with the mark bit set */ 277 uint32_t tx_lastmark; 278 } nxge_tdc_cfg_t, *p_nxge_tdc_cfg_t; 279 280 #define RDC_TABLE_ENTRY_METHOD_SEQ 0 281 #define RDC_TABLE_ENTRY_METHOD_REP 1 282 283 /* per receive DMA channel table group data structure */ 284 typedef struct nxge_rdc_grp { 285 uint32_t flag; /* 0:not configured 1: configured */ 286 uint8_t port; 287 uint8_t partition_id; 288 uint8_t rx_group_id; 289 uint8_t start_rdc; /* assume assigned in sequence */ 290 uint8_t max_rdcs; 291 uint8_t def_rdc; 292 uint8_t rdc[NXGE_MAX_RDCS]; 293 uint16_t config_method; 294 } nxge_rdc_grp_t, *p_nxge_rdc_grp_t; 295 296 /* Common RDC and TDC configuration of DMC */ 297 typedef struct _nxge_dma_common_cfg_t { 298 uint16_t rdc_red_ran_init; /* RED initial seed value */ 299 300 /* Transmit Ring */ 301 } nxge_dma_common_cfg_t, *p_nxge_dma_common_cfg_t; 302 303 /* 304 * VLAN and MAC table configurations: 305 * Each VLAN ID should belong to at most one RDC group. 306 * Each port could own multiple RDC groups. 307 * Each MAC should belong to one RDC group. 308 */ 309 typedef struct nxge_mv_cfg { 310 uint8_t flag; /* 0:unconfigure 1:configured */ 311 uint8_t rdctbl; /* RDC channel table group */ 312 uint8_t mpr_npr; /* MAC and VLAN preference */ 313 uint8_t odd_parity; 314 } nxge_mv_cfg_t, *p_nxge_mv_cfg_t; 315 316 typedef struct nxge_param_map { 317 #if defined(_BIG_ENDIAN) 318 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 319 uint32_t remove:1; /* [29] Remove */ 320 uint32_t pref:1; /* [28] preference */ 321 uint32_t rsrv:4; /* [27:24] preference */ 322 uint32_t map_to:8; /* [23:16] map to resource */ 323 uint32_t param_id:16; /* [15:0] Param ID */ 324 #else 325 uint32_t param_id:16; /* [15:0] Param ID */ 326 uint32_t map_to:8; /* [23:16] map to resource */ 327 uint32_t rsrv:4; /* [27:24] preference */ 328 uint32_t pref:1; /* [28] preference */ 329 uint32_t remove:1; /* [29] Remove */ 330 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 331 #endif 332 } nxge_param_map_t, *p_nxge_param_map_t; 333 334 typedef struct nxge_rcr_param { 335 #if defined(_BIG_ENDIAN) 336 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 337 uint32_t remove:1; /* [29] Remove */ 338 uint32_t rsrv:5; /* [28:24] preference */ 339 uint32_t rdc:8; /* [23:16] rdc # */ 340 uint32_t cfg_val:16; /* [15:0] interrupt parameter */ 341 #else 342 uint32_t cfg_val:16; /* [15:0] interrupt parameter */ 343 uint32_t rdc:8; /* [23:16] rdc # */ 344 uint32_t rsrv:5; /* [28:24] preference */ 345 uint32_t remove:1; /* [29] Remove */ 346 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 347 #endif 348 } nxge_rcr_param_t, *p_nxge_rcr_param_t; 349 350 /* Needs to have entries in the ndd table */ 351 /* 352 * Hardware properties created by fcode. 353 * In order for those properties visible to the user 354 * command ndd, we need to add the following properties 355 * to the ndd defined parameter array and data structures. 356 * 357 * Use default static configuration for x86. 358 */ 359 typedef struct nxge_hw_pt_cfg { 360 uint32_t partition_id; /* partition Id */ 361 uint32_t read_write_mode; /* read write permission mode */ 362 uint32_t function_number; /* function number */ 363 uint32_t start_tdc; /* start TDC (0 - 31) */ 364 uint32_t max_tdcs; /* max TDC in sequence */ 365 uint32_t start_rdc; /* start RDC (0 - 31) */ 366 uint32_t max_rdcs; /* max rdc in sequence */ 367 uint32_t ninterrupts; /* obp interrupts(mac/mif/syserr) */ 368 uint32_t mac_ldvid; 369 uint32_t mif_ldvid; 370 uint32_t ser_ldvid; 371 uint32_t def_rdc; /* default RDC */ 372 uint32_t drr_wt; /* port DRR weight */ 373 uint32_t rx_full_header; /* select the header flag */ 374 uint32_t start_grpid; /* starting group ID */ 375 uint32_t max_grpids; /* max group ID */ 376 uint32_t start_rdc_grpid; /* starting RDC group ID */ 377 uint32_t max_rdc_grpids; /* max RDC group ID */ 378 uint32_t start_ldg; /* starting logical group # */ 379 uint32_t max_ldgs; /* max logical device group */ 380 uint32_t max_ldvs; /* max logical devices */ 381 uint32_t start_mac_entry; /* where to put the first mac */ 382 uint32_t max_macs; /* the max mac entry allowed */ 383 uint32_t mac_pref; /* preference over VLAN */ 384 uint32_t def_mac_rxdma_grpid; /* default RDC group ID */ 385 uint32_t start_vlan; /* starting VLAN ID */ 386 uint32_t max_vlans; /* max VLAN ID */ 387 uint32_t vlan_pref; /* preference over MAC */ 388 uint32_t def_vlan_rxdma_grpid; /* default RDC group Id */ 389 390 /* Expand if we have more hardware or default configurations */ 391 uint16_t ldg[NXGE_INT_MAX_LDG]; 392 uint16_t ldg_chn_start; 393 } nxge_hw_pt_cfg_t, *p_nxge_hw_pt_cfg_t; 394 395 396 /* per port configuration */ 397 typedef struct nxge_dma_pt_cfg { 398 uint8_t mac_port; /* MAC port (function) */ 399 nxge_hw_pt_cfg_t hw_config; /* hardware configuration */ 400 401 uint32_t alloc_buf_size; 402 uint32_t rbr_size; 403 uint32_t rcr_size; 404 405 /* 406 * Configuration for hardware initialization based on the 407 * hardware properties or the default properties. 408 */ 409 uint32_t tx_dma_map; /* Transmit DMA channel bit map */ 410 411 /* Receive DMA channel */ 412 nxge_rdc_grp_t rdc_grps[NXGE_MAX_RDC_GROUPS]; 413 414 uint16_t rcr_timeout[NXGE_MAX_RDCS]; 415 uint16_t rcr_threshold[NXGE_MAX_RDCS]; 416 uint8_t rcr_full_header; 417 uint16_t rx_drr_weight; 418 419 /* Add more stuff later */ 420 } nxge_dma_pt_cfg_t, *p_nxge_dma_pt_cfg_t; 421 422 /* classification configuration */ 423 typedef struct nxge_class_pt_cfg { 424 425 /* MAC table */ 426 nxge_mv_cfg_t mac_host_info[NXGE_MAX_MACS]; 427 428 /* VLAN table */ 429 nxge_mv_cfg_t vlan_tbl[NXGE_MAX_VLANS]; 430 /* class config value */ 431 uint32_t init_h1; 432 uint16_t init_h2; 433 uint8_t mcast_rdcgrp; 434 uint8_t mac_rdcgrp; 435 uint32_t class_cfg[TCAM_CLASS_MAX]; 436 } nxge_class_pt_cfg_t, *p_nxge_class_pt_cfg_t; 437 438 /* per Neptune sharable resources among ports */ 439 typedef struct nxge_common { 440 uint32_t partition_id; 441 boolean_t mode32; 442 /* DMA Channels: RDC and TDC */ 443 nxge_rdc_cfg_t rdc_config[NXGE_MAX_RDCS]; 444 nxge_tdc_cfg_t tdc_config[NXGE_MAX_TDCS]; 445 nxge_dma_common_cfg_t dma_common_config; 446 447 uint32_t timer_res; 448 boolean_t ld_sys_error_set; 449 uint8_t sys_error_owner; 450 451 /* Layer 2/3/4 */ 452 uint16_t class2_etype; 453 uint16_t class3_etype; 454 455 /* FCRAM (hashing) */ 456 uint32_t hash1_initval; 457 uint32_t hash2_initval; 458 } nxge_common_t, *p_nxge_common_t; 459 460 /* 461 * Partition (logical domain) configuration per Neptune/NIU. 462 */ 463 typedef struct nxge_part_cfg { 464 uint32_t rdc_grpbits; /* RDC group bit masks */ 465 uint32_t tdc_bitmap; /* bounded TDC */ 466 nxge_dma_pt_cfg_t pt_config[NXGE_MAX_PORTS]; 467 468 /* Flow Classification Partition (flow partition select register) */ 469 uint8_t hash_lookup; /* external lookup is available */ 470 uint8_t base_mask; /* select bits in base_h1 to replace */ 471 /* bits [19:15} in Hash 1. */ 472 uint8_t base_h1; /* value to replace Hash 1 [19:15]. */ 473 474 /* Add more here */ 475 uint32_t attributes; /* permission and attribute bits */ 476 #define FZC_SERVICE_ENTITY 0x01 477 #define FZC_READ_WRITE 0x02 478 #define FZC_READ_ONLY 0x04 479 } nxge_part_cfg_t, *p_nxge_part_cfg_t; 480 481 typedef struct nxge_hw_list { 482 struct nxge_hw_list *next; 483 nxge_os_mutex_t nxge_cfg_lock; 484 nxge_os_mutex_t nxge_tcam_lock; 485 nxge_os_mutex_t nxge_vlan_lock; 486 nxge_os_mutex_t nxge_mdio_lock; 487 nxge_os_mutex_t nxge_mii_lock; 488 489 nxge_dev_info_t *parent_devp; 490 struct _nxge_t *nxge_p[NXGE_MAX_PORTS]; 491 uint32_t ndevs; 492 uint32_t flags; 493 uint32_t magic; 494 uint32_t niu_type; 495 uint32_t platform_type; 496 uint8_t xcvr_addr[NXGE_MAX_PORTS]; 497 } nxge_hw_list_t, *p_nxge_hw_list_t; 498 499 #ifdef __cplusplus 500 } 501 #endif 502 503 #endif /* _SYS_NXGE_NXGE_COMMON_H */ 504