1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 22 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 23 /* All Rights Reserved */ 24 25 /* 26 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 27 * Copyright 2023 Oxide Computer Company 28 */ 29 30 #ifndef _SYS_ASY_H 31 #define _SYS_ASY_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #include <sys/tty.h> 38 #include <sys/ksynch.h> 39 #include <sys/dditypes.h> 40 41 /* 42 * internal bus type naming 43 */ 44 #define ASY_BUS_PCI (0) 45 #define ASY_BUS_ISA (1) 46 #define ASY_BUS_UNKNOWN (-1) 47 48 #define ASY_MINOR_LEN (40) 49 50 #define COM1_IOADDR 0x3f8 51 #define COM2_IOADDR 0x2f8 52 #define COM3_IOADDR 0x3e8 53 #define COM4_IOADDR 0x2e8 54 55 /* 56 * Definitions for INS8250 / 16550 chips 57 */ 58 59 /* defined as offsets from the data register */ 60 #define DAT 0 /* receive/transmit data */ 61 #define ICR 1 /* interrupt control register */ 62 #define ISR 2 /* interrupt status register */ 63 #define LCR 3 /* line control register */ 64 #define MCR 4 /* modem control register */ 65 #define LSR 5 /* line status register */ 66 #define MSR 6 /* modem status register */ 67 #define SCR 7 /* scratch register */ 68 #define DLL 0 /* divisor latch (lsb) */ 69 #define DLH 1 /* divisor latch (msb) */ 70 #define FIFOR ISR /* FIFO register for 16550 */ 71 #define EFR ISR /* Enhanced feature register for 16650 */ 72 73 /* 74 * INTEL 8210-A/B & 16450/16550 Registers Structure. 75 */ 76 77 /* Line Control Register */ 78 #define WLS0 0x01 /* word length select bit 0 */ 79 #define WLS1 0x02 /* word length select bit 2 */ 80 #define STB 0x04 /* number of stop bits */ 81 #define PEN 0x08 /* parity enable */ 82 #define EPS 0x10 /* even parity select */ 83 #define SETBREAK 0x40 /* break key */ 84 #define DLAB 0x80 /* divisor latch access bit */ 85 #define RXLEN 0x03 /* # of data bits per received/xmitted char */ 86 #define STOP1 0x00 87 #define STOP2 0x04 88 #define PAREN 0x08 89 #define PAREVN 0x10 90 #define PARMARK 0x20 91 #define SNDBRK 0x40 92 #define EFRACCESS 0xBF /* magic value for 16650 EFR access */ 93 94 #define BITS5 0x00 /* 5 bits per char */ 95 #define BITS6 0x01 /* 6 bits per char */ 96 #define BITS7 0x02 /* 7 bits per char */ 97 #define BITS8 0x03 /* 8 bits per char */ 98 99 /* Line Status Register */ 100 #define RCA 0x01 /* data ready */ 101 #define OVRRUN 0x02 /* overrun error */ 102 #define PARERR 0x04 /* parity error */ 103 #define FRMERR 0x08 /* framing error */ 104 #define BRKDET 0x10 /* a break has arrived */ 105 #define XHRE 0x20 /* tx hold reg is now empty */ 106 #define XSRE 0x40 /* tx shift reg is now empty */ 107 #define RFBE 0x80 /* rx FIFO Buffer error */ 108 109 /* Interrupt Id Regisger */ 110 #define MSTATUS 0x00 /* modem status changed */ 111 #define NOINTERRUPT 0x01 /* no interrupt pending */ 112 #define TxRDY 0x02 /* Transmitter Holding Register Empty */ 113 #define RxRDY 0x04 /* Receiver Data Available */ 114 #define FFTMOUT 0x0c /* FIFO timeout - 16550AF */ 115 #define RSTATUS 0x06 /* Receiver Line Status */ 116 117 /* Interrupt Enable Register */ 118 #define RIEN 0x01 /* Received Data Ready */ 119 #define TIEN 0x02 /* Tx Hold Register Empty */ 120 #define SIEN 0x04 /* Receiver Line Status */ 121 #define MIEN 0x08 /* Modem Status */ 122 123 /* Modem Control Register */ 124 #define DTR 0x01 /* Data Terminal Ready */ 125 #define RTS 0x02 /* Request To Send */ 126 #define OUT1 0x04 /* Aux output - not used */ 127 #define OUT2 0x08 /* turns intr to 386 on/off */ 128 #define ASY_LOOP 0x10 /* loopback for diagnostics */ 129 130 /* Modem Status Register */ 131 #define DCTS 0x01 /* Delta Clear To Send */ 132 #define DDSR 0x02 /* Delta Data Set Ready */ 133 #define DRI 0x04 /* Trail Edge Ring Indicator */ 134 #define DDCD 0x08 /* Delta Data Carrier Detect */ 135 #define CTS 0x10 /* Clear To Send */ 136 #define DSR 0x20 /* Data Set Ready */ 137 #define RI 0x40 /* Ring Indicator */ 138 #define DCD 0x80 /* Data Carrier Detect */ 139 140 #define DELTAS(x) ((x)&(DCTS|DDSR|DRI|DDCD)) 141 #define STATES(x) ((x)&(CTS|DSR|RI|DCD)) 142 143 /* flags for FCR (FIFO Control register) */ 144 #define FIFO_OFF 0x00 /* fifo disabled */ 145 #define FIFO_ON 0x01 /* fifo enabled */ 146 #define FIFORXFLSH 0x02 /* flush receiver FIFO */ 147 #define FIFOTXFLSH 0x04 /* flush transmitter FIFO */ 148 #define FIFODMA 0x08 /* DMA mode 1 */ 149 #define FIFOEXTRA1 0x10 /* Longer fifos on some 16650's */ 150 #define FIFOEXTRA2 0x20 /* Longer fifos on some 16650's and 16750 */ 151 #define FIFO_TRIG_1 0x00 /* 1 byte trigger level */ 152 #define FIFO_TRIG_4 0x40 /* 4 byte trigger level */ 153 #define FIFO_TRIG_8 0x80 /* 8 byte trigger level */ 154 #define FIFO_TRIG_14 0xC0 /* 14 byte trigger level */ 155 156 /* Serial in/out requests */ 157 158 #define OVERRUN 040000 159 #define FRERROR 020000 160 #define PERROR 010000 161 #define S_ERRORS (PERROR|OVERRUN|FRERROR) 162 163 /* EFR - Enhanced feature register for 16650 */ 164 #define ENHENABLE 0x10 165 166 /* SCR - scratch register */ 167 #define SCRTEST 0x5a /* arbritrary value for testing SCR register */ 168 169 /* 170 * Ring buffer and async line management definitions. 171 */ 172 #define RINGBITS 16 /* # of bits in ring ptrs */ 173 #define RINGSIZE (1<<RINGBITS) /* size of ring */ 174 #define RINGMASK (RINGSIZE-1) 175 #define RINGFRAC 12 /* fraction of ring to force flush */ 176 177 #define RING_INIT(ap) ((ap)->async_rput = (ap)->async_rget = 0) 178 #define RING_CNT(ap) (((ap)->async_rput >= (ap)->async_rget) ? \ 179 ((ap)->async_rput - (ap)->async_rget):\ 180 ((0x10000 - (ap)->async_rget) + (ap)->async_rput)) 181 #define RING_FRAC(ap) ((int)RING_CNT(ap) >= (int)(RINGSIZE/RINGFRAC)) 182 #define RING_POK(ap, n) ((int)RING_CNT(ap) < (int)(RINGSIZE-(n))) 183 #define RING_PUT(ap, c) \ 184 ((ap)->async_ring[(ap)->async_rput++ & RINGMASK] = (uchar_t)(c)) 185 #define RING_UNPUT(ap) ((ap)->async_rput--) 186 #define RING_GOK(ap, n) ((int)RING_CNT(ap) >= (int)(n)) 187 #define RING_GET(ap) ((ap)->async_ring[(ap)->async_rget++ & RINGMASK]) 188 #define RING_EAT(ap, n) ((ap)->async_rget += (n)) 189 #define RING_MARK(ap, c, s) \ 190 ((ap)->async_ring[(ap)->async_rput++ & RINGMASK] = ((uchar_t)(c)|(s))) 191 #define RING_UNMARK(ap) \ 192 ((ap)->async_ring[((ap)->async_rget) & RINGMASK] &= ~S_ERRORS) 193 #define RING_ERR(ap, c) \ 194 ((ap)->async_ring[((ap)->async_rget) & RINGMASK] & (c)) 195 196 /* 197 * Asy tracing macros. These are a bit similar to some macros in sys/vtrace.h . 198 * 199 * XXX - Needs review: would it be better to use the macros in sys/vtrace.h ? 200 */ 201 #ifdef DEBUG 202 #define DEBUGWARN0(fac, format) \ 203 if (debug & (fac)) \ 204 cmn_err(CE_WARN, format) 205 #define DEBUGNOTE0(fac, format) \ 206 if (debug & (fac)) \ 207 cmn_err(CE_NOTE, format) 208 #define DEBUGNOTE1(fac, format, arg1) \ 209 if (debug & (fac)) \ 210 cmn_err(CE_NOTE, format, arg1) 211 #define DEBUGNOTE2(fac, format, arg1, arg2) \ 212 if (debug & (fac)) \ 213 cmn_err(CE_NOTE, format, arg1, arg2) 214 #define DEBUGNOTE3(fac, format, arg1, arg2, arg3) \ 215 if (debug & (fac)) \ 216 cmn_err(CE_NOTE, format, arg1, arg2, arg3) 217 #define DEBUGCONT0(fac, format) \ 218 if (debug & (fac)) \ 219 cmn_err(CE_CONT, format) 220 #define DEBUGCONT1(fac, format, arg1) \ 221 if (debug & (fac)) \ 222 cmn_err(CE_CONT, format, arg1) 223 #define DEBUGCONT2(fac, format, arg1, arg2) \ 224 if (debug & (fac)) \ 225 cmn_err(CE_CONT, format, arg1, arg2) 226 #define DEBUGCONT3(fac, format, arg1, arg2, arg3) \ 227 if (debug & (fac)) \ 228 cmn_err(CE_CONT, format, arg1, arg2, arg3) 229 #define DEBUGCONT4(fac, format, arg1, arg2, arg3, arg4) \ 230 if (debug & (fac)) \ 231 cmn_err(CE_CONT, format, arg1, arg2, arg3, arg4) 232 #define DEBUGCONT10(fac, format, \ 233 arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10) \ 234 if (debug & (fac)) \ 235 cmn_err(CE_CONT, format, \ 236 arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10) 237 #else 238 #define DEBUGWARN0(fac, format) 239 #define DEBUGNOTE0(fac, format) 240 #define DEBUGNOTE1(fac, format, arg1) 241 #define DEBUGNOTE2(fac, format, arg1, arg2) 242 #define DEBUGNOTE3(fac, format, arg1, arg2, arg3) 243 #define DEBUGCONT0(fac, format) 244 #define DEBUGCONT1(fac, format, arg1) 245 #define DEBUGCONT2(fac, format, arg1, arg2) 246 #define DEBUGCONT3(fac, format, arg1, arg2, arg3) 247 #define DEBUGCONT4(fac, format, arg1, arg2, arg3, arg4) 248 #define DEBUGCONT10(fac, format, \ 249 arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10) 250 #endif 251 252 /* 253 * Hardware channel common data. One structure per port. 254 * Each of the fields in this structure is required to be protected by a 255 * mutex lock at the highest priority at which it can be altered. 256 * The asy_flags, and asy_next fields can be altered by interrupt 257 * handling code that must be protected by the mutex whose handle is 258 * stored in asy_excl_hi. All others can be protected by the asy_excl 259 * mutex, which is lower priority and adaptive. 260 */ 261 262 struct asycom { 263 int asy_flags; /* random flags */ 264 /* protected by asy_excl_hi lock */ 265 uint_t asy_hwtype; /* HW type: ASY16550A, etc. */ 266 uint_t asy_use_fifo; /* HW FIFO use it or not ?? */ 267 uint_t asy_fifo_buf; /* With FIFO = 16, otherwise = 1 */ 268 uint_t asy_flags2; /* flags which don't change, no lock */ 269 uint8_t *asy_ioaddr; /* i/o address of ASY port */ 270 struct asyncline *asy_priv; /* protocol private data -- asyncline */ 271 dev_info_t *asy_dip; /* dev_info */ 272 int asy_unit; /* which port */ 273 ddi_iblock_cookie_t asy_iblock; 274 kmutex_t asy_excl; /* asy adaptive mutex */ 275 kmutex_t asy_excl_hi; /* asy spinlock mutex */ 276 kmutex_t asy_soft_lock; /* soft lock for guarding softpend. */ 277 int asysoftpend; /* Flag indicating soft int pending. */ 278 ddi_softintr_t asy_softintr_id; 279 ddi_iblock_cookie_t asy_soft_iblock; 280 281 /* 282 * The asy_soft_sr mutex should only be taken by the soft interrupt 283 * handler and the driver DDI_SUSPEND/DDI_RESUME code. It 284 * shouldn't be taken by any code that may get called indirectly 285 * by the soft interrupt handler (e.g. as a result of a put or 286 * putnext call). 287 */ 288 kmutex_t asy_soft_sr; /* soft int suspend/resume mutex */ 289 uchar_t asy_msr; /* saved modem status */ 290 uchar_t asy_mcr; /* soft carrier bits */ 291 uchar_t asy_lcr; /* console lcr bits */ 292 uchar_t asy_bidx; /* console baud rate index */ 293 tcflag_t asy_cflag; /* console mode bits */ 294 struct cons_polledio polledio; /* polled I/O functions */ 295 ddi_acc_handle_t asy_iohandle; /* Data access handle */ 296 tcflag_t asy_ocflag; /* old console mode bits */ 297 uchar_t asy_com_port; /* COM port number, or zero */ 298 uchar_t asy_fifor; /* FIFOR register setting */ 299 #ifdef DEBUG 300 int asy_msint_cnt; /* number of times in async_msint */ 301 #endif 302 }; 303 304 /* 305 * Asychronous protocol private data structure for ASY. 306 * Each of the fields in the structure is required to be protected by 307 * the lower priority lock except the fields that are set only at 308 * base level but cleared (with out lock) at interrupt level. 309 */ 310 311 struct asyncline { 312 int async_flags; /* random flags */ 313 kcondvar_t async_flags_cv; /* condition variable for flags */ 314 kcondvar_t async_ops_cv; /* condition variable for async_ops */ 315 dev_t async_dev; /* device major/minor numbers */ 316 mblk_t *async_xmitblk; /* transmit: active msg block */ 317 struct asycom *async_common; /* device common data */ 318 tty_common_t async_ttycommon; /* tty driver common data */ 319 bufcall_id_t async_wbufcid; /* id for pending write-side bufcall */ 320 size_t async_wbufcds; /* Buffer size requested in bufcall */ 321 timeout_id_t async_polltid; /* softint poll timeout id */ 322 timeout_id_t async_dtrtid; /* delaying DTR turn on */ 323 timeout_id_t async_utbrktid; /* hold minimum untimed break time id */ 324 325 /* 326 * The following fields are protected by the asy_excl_hi lock. 327 * Some, such as async_flowc, are set only at the base level and 328 * cleared (without the lock) only by the interrupt level. 329 */ 330 uchar_t *async_optr; /* output pointer */ 331 int async_ocnt; /* output count */ 332 uint_t async_rput; /* producing pointer for input */ 333 uint_t async_rget; /* consuming pointer for input */ 334 335 /* 336 * Each character stuffed into the ring has two bytes associated 337 * with it. The first byte is used to indicate special conditions 338 * and the second byte is the actual data. The ring buffer 339 * needs to be defined as ushort_t to accomodate this. 340 */ 341 ushort_t async_ring[RINGSIZE]; 342 343 short async_break; /* break count */ 344 int async_inflow_source; /* input flow control type */ 345 346 union { 347 struct { 348 uchar_t _hw; /* overrun (hw) */ 349 uchar_t _sw; /* overrun (sw) */ 350 } _a; 351 ushort_t uover_overrun; 352 } async_uover; 353 #define async_overrun async_uover._a.uover_overrun 354 #define async_hw_overrun async_uover._a._hw 355 #define async_sw_overrun async_uover._a._sw 356 short async_ext; /* modem status change count */ 357 short async_work; /* work to do flag */ 358 timeout_id_t async_timer; /* close drain progress timer */ 359 360 mblk_t *async_suspqf; /* front of suspend queue */ 361 mblk_t *async_suspqb; /* back of suspend queue */ 362 int async_ops; /* active operations counter */ 363 }; 364 365 /* definitions for async_flags field */ 366 #define ASYNC_EXCL_OPEN 0x10000000 /* exclusive open */ 367 #define ASYNC_WOPEN 0x00000001 /* waiting for open to complete */ 368 #define ASYNC_ISOPEN 0x00000002 /* open is complete */ 369 #define ASYNC_OUT 0x00000004 /* line being used for dialout */ 370 #define ASYNC_CARR_ON 0x00000008 /* carrier on last time we looked */ 371 #define ASYNC_STOPPED 0x00000010 /* output is stopped */ 372 #define ASYNC_DELAY 0x00000020 /* waiting for delay to finish */ 373 #define ASYNC_BREAK 0x00000040 /* waiting for break to finish */ 374 #define ASYNC_BUSY 0x00000080 /* waiting for transmission to finish */ 375 #define ASYNC_DRAINING 0x00000100 /* waiting for output to drain */ 376 #define ASYNC_SERVICEIMM 0x00000200 /* queue soft interrupt as soon as */ 377 #define ASYNC_HW_IN_FLOW 0x00000400 /* input flow control in effect */ 378 #define ASYNC_HW_OUT_FLW 0x00000800 /* output flow control in effect */ 379 #define ASYNC_PROGRESS 0x00001000 /* made progress on output effort */ 380 #define ASYNC_CLOSING 0x00002000 /* processing close on stream */ 381 #define ASYNC_OUT_SUSPEND 0x00004000 /* waiting for TIOCSBRK to finish */ 382 #define ASYNC_HOLD_UTBRK 0x00008000 /* waiting for untimed break hold */ 383 /* the minimum time */ 384 #define ASYNC_DTR_DELAY 0x00010000 /* delaying DTR turn on */ 385 #define ASYNC_SW_IN_FLOW 0x00020000 /* sw input flow control in effect */ 386 #define ASYNC_SW_OUT_FLW 0x00040000 /* sw output flow control in effect */ 387 #define ASYNC_SW_IN_NEEDED 0x00080000 /* sw input flow control char is */ 388 /* needed to be sent */ 389 #define ASYNC_OUT_FLW_RESUME 0x00100000 /* output need to be resumed */ 390 /* because of transition of flow */ 391 /* control from stop to start */ 392 #define ASYNC_DDI_SUSPENDED 0x00200000 /* suspended by DDI */ 393 #define ASYNC_RESUME_BUFCALL 0x00400000 /* call bufcall when resumed by DDI */ 394 395 /* asy_hwtype definitions */ 396 #define ASY8250A 0x2 /* 8250A or 16450 */ 397 #define ASY16550 0x3 /* broken FIFO which must not be used */ 398 #define ASY16550A 0x4 /* usable FIFO */ 399 #define ASY16650 0x5 400 #define ASY16750 0x6 401 402 /* definitions for asy_flags field */ 403 #define ASY_NEEDSOFT 0x00000001 404 #define ASY_DOINGSOFT 0x00000002 405 #define ASY_PPS 0x00000004 406 #define ASY_PPS_EDGE 0x00000008 407 #define ASY_DOINGSOFT_RETRY 0x00000010 408 #define ASY_RTS_DTR_OFF 0x00000020 409 #define ASY_IGNORE_CD 0x00000040 410 #define ASY_CONSOLE 0x00000080 411 #define ASY_DDI_SUSPENDED 0x00000100 /* suspended by DDI */ 412 413 /* definitions for asy_flags2 field */ 414 #define ASY2_NO_LOOPBACK 0x00000001 /* Device doesn't support loopback */ 415 416 /* definitions for async_inflow_source field in struct asyncline */ 417 #define IN_FLOW_NULL 0x00000000 418 #define IN_FLOW_RINGBUFF 0x00000001 419 #define IN_FLOW_STREAMS 0x00000002 420 #define IN_FLOW_USER 0x00000004 421 422 /* 423 * OUTLINE defines the high-order flag bit in the minor device number that 424 * controls use of a tty line for dialin and dialout simultaneously. 425 */ 426 #ifdef _LP64 427 #define OUTLINE (1 << (NBITSMINOR32 - 1)) 428 #else 429 #define OUTLINE (1 << (NBITSMINOR - 1)) 430 #endif 431 #define UNIT(x) (getminor(x) & ~OUTLINE) 432 433 /* 434 * ASYSETSOFT macro to pend a soft interrupt if one isn't already pending. 435 */ 436 437 #define ASYSETSOFT(asy) { \ 438 ASSERT(MUTEX_HELD(&asy->asy_excl_hi)); \ 439 if (mutex_tryenter(&asy->asy_soft_lock)) { \ 440 asy->asy_flags |= ASY_NEEDSOFT; \ 441 if (!asy->asysoftpend) { \ 442 asy->asysoftpend = 1; \ 443 mutex_exit(&asy->asy_soft_lock); \ 444 ddi_trigger_softintr(asy->asy_softintr_id); \ 445 } \ 446 else \ 447 mutex_exit(&asy->asy_soft_lock); \ 448 } \ 449 } 450 451 #ifdef __cplusplus 452 } 453 #endif 454 455 #endif /* _SYS_ASY_H */ 456