1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2002-2005 Neterion, Inc. 29 * All right Reserved. 30 * 31 * FileName : xgell.h 32 * 33 * Description: Link Layer driver declaration 34 * 35 */ 36 37 #ifndef _SYS_XGELL_H 38 #define _SYS_XGELL_H 39 40 #pragma ident "%Z%%M% %I% %E% SMI" 41 42 #include <sys/types.h> 43 #include <sys/errno.h> 44 #include <sys/param.h> 45 #include <sys/stropts.h> 46 #include <sys/stream.h> 47 #include <sys/strsubr.h> 48 #include <sys/kmem.h> 49 #include <sys/conf.h> 50 #include <sys/devops.h> 51 #include <sys/ksynch.h> 52 #include <sys/stat.h> 53 #include <sys/modctl.h> 54 #include <sys/debug.h> 55 #include <sys/pci.h> 56 #include <sys/ethernet.h> 57 #include <sys/vlan.h> 58 #include <sys/dlpi.h> 59 #include <sys/taskq.h> 60 #include <sys/cyclic.h> 61 62 #include <sys/pattr.h> 63 #include <sys/strsun.h> 64 65 #include <sys/mac.h> 66 #include <sys/mac_ether.h> 67 68 #ifdef __cplusplus 69 extern "C" { 70 #endif 71 72 #define XGELL_DESC "Xframe I/II 10Gb Ethernet %I%" 73 #define XGELL_IFNAME "xge" 74 #define XGELL_TX_LEVEL_LOW 8 75 #define XGELL_TX_LEVEL_HIGH 32 76 77 #include <xgehal.h> 78 79 #if defined(__sparc) || defined(__amd64) 80 #define XGELL_L3_ALIGNED 1 81 #endif 82 83 /* 84 * These default values can be overridden by vaules in xge.conf. 85 * In xge.conf user has to specify actual (not percentages) values. 86 */ 87 #define XGELL_RX_BUFFER_TOTAL XGE_HAL_RING_RXDS_PER_BLOCK(1) * 6 88 #define XGELL_RX_BUFFER_POST_HIWAT XGE_HAL_RING_RXDS_PER_BLOCK(1) * 5 89 90 /* Control driver to copy or DMA received packets */ 91 #define XGELL_RX_DMA_LOWAT 256 92 93 #define XGELL_RING_MAIN_QID 0 94 95 #if defined(__x86) 96 #define XGELL_TX_DMA_LOWAT 128 97 #else 98 #define XGELL_TX_DMA_LOWAT 1024 99 #endif 100 101 /* 102 * Try to collapse up to XGELL_RX_PKT_BURST packets into single mblk 103 * sequence before mac_rx() is called. 104 */ 105 #define XGELL_RX_PKT_BURST 32 106 107 /* About 1s */ 108 #define XGE_DEV_POLL_TICKS drv_usectohz(1000000) 109 110 #define XGELL_LSO_MAXLEN 65535 111 #define XGELL_CONF_ENABLE_BY_DEFAULT 1 112 #define XGELL_CONF_DISABLE_BY_DEFAULT 0 113 114 /* LRO configuration */ 115 #define XGE_HAL_DEFAULT_LRO_SG_SIZE 8 /* <=2 LRO fix not required */ 116 #define XGE_HAL_DEFAULT_LRO_FRM_LEN 65535 117 118 /* 119 * If HAL could provide defualt values to all tunables, we'll remove following 120 * macros. 121 * Before removing, please refer to xgehal-config.h for more details. 122 */ 123 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 124 125 /* bimodal adaptive schema defaults - ENABLED */ 126 #define XGE_HAL_DEFAULT_BIMODAL_INTERRUPTS -1 127 #define XGE_HAL_DEFAULT_BIMODAL_TIMER_LO_US 24 128 #define XGE_HAL_DEFAULT_BIMODAL_TIMER_HI_US 256 129 130 /* interrupt moderation/utilization defaults */ 131 #define XGE_HAL_DEFAULT_TX_URANGE_A 5 132 #define XGE_HAL_DEFAULT_TX_URANGE_B 15 133 #define XGE_HAL_DEFAULT_TX_URANGE_C 30 134 #define XGE_HAL_DEFAULT_TX_UFC_A 15 135 #define XGE_HAL_DEFAULT_TX_UFC_B 30 136 #define XGE_HAL_DEFAULT_TX_UFC_C 45 137 #define XGE_HAL_DEFAULT_TX_UFC_D 60 138 #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 139 #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 140 #define XGE_HAL_DEFAULT_TX_TIMER_VAL 10000 141 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_B 512 /* bimodal */ 142 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_N 256 /* normal UFC */ 143 #define XGE_HAL_DEFAULT_RX_URANGE_A 10 144 #define XGE_HAL_DEFAULT_RX_URANGE_B 30 145 #define XGE_HAL_DEFAULT_RX_URANGE_C 50 146 #define XGE_HAL_DEFAULT_RX_UFC_A 1 147 #define XGE_HAL_DEFAULT_RX_UFC_B_J 2 148 #define XGE_HAL_DEFAULT_RX_UFC_B_N 8 149 #define XGE_HAL_DEFAULT_RX_UFC_C_J 4 150 #define XGE_HAL_DEFAULT_RX_UFC_C_N 16 151 #define XGE_HAL_DEFAULT_RX_UFC_D 32 152 #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 153 #define XGE_HAL_DEFAULT_RX_TIMER_VAL 384 154 155 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_J 2048 156 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_N 4096 157 #define XGE_HAL_DEFAULT_FIFO_QUEUE_INTR 0 158 #define XGE_HAL_DEFAULT_FIFO_RESERVE_THRESHOLD 0 159 #define XGE_HAL_DEFAULT_FIFO_MEMBLOCK_SIZE PAGESIZE 160 161 /* 162 * this will force HAL to allocate extra copied buffer per TXDL which 163 * size calculated by formula: 164 * 165 * (ALIGNMENT_SIZE * ALIGNED_FRAGS) 166 */ 167 #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE 4096 168 #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 1 169 #if defined(__x86) 170 #define XGE_HAL_DEFAULT_FIFO_FRAGS 128 171 #else 172 #define XGE_HAL_DEFAULT_FIFO_FRAGS 64 173 #endif 174 #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 18 175 176 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_J 2 177 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_N 2 178 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_DEFAULT 1 179 #define XGE_HAL_DEFAULT_BACKOFF_INTERVAL_US 64 180 #define XGE_HAL_DEFAULT_RING_PRIORITY 0 181 #define XGE_HAL_DEFAULT_RING_MEMBLOCK_SIZE PAGESIZE 182 183 #define XGE_HAL_DEFAULT_RING_NUM 8 184 #define XGE_HAL_DEFAULT_TMAC_UTIL_PERIOD 5 185 #define XGE_HAL_DEFAULT_RMAC_UTIL_PERIOD 5 186 #define XGE_HAL_DEFAULT_RMAC_HIGH_PTIME 65535 187 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q0Q3 187 188 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q4Q7 187 189 #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_EN 1 190 #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_DIS 0 191 #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_EN 1 192 #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_DIS 0 193 #define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */ 194 #define XGE_HAL_DEFAULT_ISR_POLLING_CNT 0 195 #define XGE_HAL_DEFAULT_LATENCY_TIMER 255 196 #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION XGE_HAL_TWO_SPLIT_TRANSACTION 197 #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 198 #define XGE_HAL_DEFAULT_MMRB_COUNT 1 /* 1k */ 199 #define XGE_HAL_DEFAULT_SHARED_SPLITS 1 200 #define XGE_HAL_DEFAULT_STATS_REFRESH_TIME 1 201 202 /* 203 * default the size of buffers allocated for ndd interface functions 204 */ 205 #define XGELL_STATS_BUFSIZE 4096 206 #define XGELL_PCICONF_BUFSIZE 2048 207 #define XGELL_ABOUT_BUFSIZE 512 208 #define XGELL_IOCTL_BUFSIZE 64 209 #define XGELL_DEVCONF_BUFSIZE 4096 210 211 /* 212 * xgell_event_e 213 * 214 * This enumeration derived from xgehal_event_e. It extends it 215 * for the reason to get serialized context. 216 */ 217 /* Renamb the macro from HAL */ 218 #define XGELL_EVENT_BASE XGE_LL_EVENT_BASE 219 typedef enum xgell_event_e { 220 /* LL events */ 221 XGELL_EVENT_RESCHED_NEEDED = XGELL_EVENT_BASE + 1, 222 } xgell_event_e; 223 224 typedef struct { 225 int rx_pkt_burst; 226 int rx_buffer_total; 227 int rx_buffer_post_hiwat; 228 int rx_dma_lowat; 229 int tx_dma_lowat; 230 int msi_enable; 231 int lso_enable; 232 } xgell_config_t; 233 234 typedef struct xgell_rx_buffer_t { 235 struct xgell_rx_buffer_t *next; 236 void *vaddr; 237 dma_addr_t dma_addr; 238 ddi_dma_handle_t dma_handle; 239 ddi_acc_handle_t dma_acch; 240 void *lldev; 241 frtn_t frtn; 242 #ifdef XGELL_L3_ALIGNED 243 unsigned char header[XGE_HAL_TCPIP_HEADER_MAX_SIZE * 2 244 + 8]; 245 #endif 246 } xgell_rx_buffer_t; 247 248 /* Buffer pool for all rings */ 249 typedef struct xgell_rx_buffer_pool_t { 250 uint_t total; /* total buffers */ 251 uint_t size; /* buffer size */ 252 xgell_rx_buffer_t *head; /* header pointer */ 253 uint_t free; /* free buffers */ 254 uint_t post; /* posted buffers */ 255 uint_t post_hiwat; /* hiwat to stop post */ 256 spinlock_t pool_lock; /* buffer pool lock */ 257 } xgell_rx_buffer_pool_t; 258 259 typedef struct xgelldev xgelldev_t; 260 261 typedef struct xgell_ring_t { 262 xge_hal_channel_h channelh; 263 xgelldev_t *lldev; 264 mac_resource_handle_t handle; /* per ring cookie */ 265 } xgell_ring_t; 266 267 struct xgelldev { 268 caddr_t ndp; 269 mac_handle_t mh; 270 int instance; 271 dev_info_t *dev_info; 272 xge_hal_device_h devh; 273 xgell_ring_t ring_main; 274 xgell_rx_buffer_pool_t bf_pool; 275 int resched_avail; 276 int resched_send; 277 int resched_retry; 278 int tx_copied_max; 279 xge_hal_channel_h fifo_channel; 280 volatile int is_initialized; 281 xgell_config_t config; 282 volatile int in_reset; 283 timeout_id_t timeout_id; 284 kmutex_t genlock; 285 }; 286 287 typedef struct { 288 mblk_t *mblk; 289 ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS]; 290 int handle_cnt; 291 } xgell_txd_priv_t; 292 293 typedef struct { 294 xgell_rx_buffer_t *rx_buffer; 295 } xgell_rxd_priv_t; 296 297 int xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info, 298 xgelldev_t **lldev_out); 299 300 void xgell_device_free(xgelldev_t *lldev); 301 302 int xgell_device_register(xgelldev_t *lldev, xgell_config_t *config); 303 304 int xgell_device_unregister(xgelldev_t *lldev); 305 306 void xgell_callback_link_up(void *userdata); 307 308 void xgell_callback_link_down(void *userdata); 309 310 int xgell_onerr_reset(xgelldev_t *lldev); 311 312 void xge_device_poll_now(void *data); 313 314 #ifdef __cplusplus 315 } 316 #endif 317 318 #endif /* _SYS_XGELL_H */ 319