1 /* 2 * sfe_util.h: header to support the gem layer used by Masa Murayama 3 * 4 * Copyright (c) 2002-2008 Masayuki Murayama. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the author nor the names of its contributors may be 17 * used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 */ 33 34 #ifndef _SFE_UTIL_H_ 35 #define _SFE_UTIL_H_ 36 #include <sys/mac.h> 37 #include <sys/mac_ether.h> 38 39 /* 40 * Useful macros and typedefs 41 */ 42 43 #define GEM_NAME_LEN 32 44 45 #define GEM_TX_TIMEOUT (drv_usectohz(5*1000000)) 46 #define GEM_TX_TIMEOUT_INTERVAL (drv_usectohz(1*1000000)) 47 #define GEM_LINK_WATCH_INTERVAL (drv_usectohz(1*1000000)) /* 1 sec */ 48 49 /* general return code */ 50 #define GEM_SUCCESS 0 51 #define GEM_FAILURE (-1) 52 53 /* return code of gem_tx_done */ 54 #define INTR_RESTART_TX 0x80000000 55 56 typedef int32_t seqnum_t; 57 58 /* 59 * I/O instructions 60 */ 61 #define OUTB(dp, p, v) \ 62 ddi_put8((dp)->regs_handle, \ 63 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 64 #define OUTW(dp, p, v) \ 65 ddi_put16((dp)->regs_handle, \ 66 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 67 #define OUTL(dp, p, v) \ 68 ddi_put32((dp)->regs_handle, \ 69 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 70 #define OUTLINL(dp, p, v) \ 71 ddi_put32((dp)->regs_handle, \ 72 (void *)((caddr_t)((dp)->base_addr) + (p)), v); \ 73 (void) INL((dp), (p)) 74 #define INB(dp, p) \ 75 ddi_get8((dp)->regs_handle, \ 76 (void *)(((caddr_t)(dp)->base_addr) + (p))) 77 #define INW(dp, p) \ 78 ddi_get16((dp)->regs_handle, \ 79 (void *)(((caddr_t)(dp)->base_addr) + (p))) 80 #define INL(dp, p) \ 81 ddi_get32((dp)->regs_handle, \ 82 (void *)(((caddr_t)(dp)->base_addr) + (p))) 83 84 struct gem_stats { 85 uint32_t intr; 86 87 uint32_t crc; 88 uint32_t errrcv; 89 uint32_t overflow; 90 uint32_t frame; 91 uint32_t missed; 92 uint32_t runt; 93 uint32_t frame_too_long; 94 uint32_t norcvbuf; 95 uint32_t sqe; 96 97 uint32_t collisions; 98 uint32_t first_coll; 99 uint32_t multi_coll; 100 uint32_t excoll; 101 uint32_t xmit_internal_err; 102 uint32_t nocarrier; 103 uint32_t defer; 104 uint32_t errxmt; 105 uint32_t underflow; 106 uint32_t xmtlatecoll; 107 uint32_t noxmtbuf; 108 uint32_t jabber; 109 110 uint64_t rbytes; 111 uint64_t obytes; 112 uint64_t rpackets; 113 uint64_t opackets; 114 uint32_t rbcast; 115 uint32_t obcast; 116 uint32_t rmcast; 117 uint32_t omcast; 118 uint32_t rcv_internal_err; 119 }; 120 #define GEM_MAXTXSEGS 4 121 #define GEM_MAXRXSEGS 1 122 123 #define GEM_MAXTXFRAGS 8 124 #define GEM_MAXRXFRAGS 4 125 /* TX buffer management */ 126 struct txbuf { 127 struct txbuf *txb_next; 128 129 /* pointer to original mblk */ 130 mblk_t *txb_mp; 131 132 /* dma mapping for current packet */ 133 ddi_dma_cookie_t txb_dmacookie[GEM_MAXTXFRAGS]; 134 uint_t txb_nfrags; 135 136 /* bounce buffer management */ 137 ddi_dma_handle_t txb_bdh; 138 ddi_acc_handle_t txb_bah; 139 caddr_t txb_buf; /* vaddr of bounce buffer */ 140 uint64_t txb_buf_dma; /* paddr of bounce buffer */ 141 142 /* timeout management */ 143 clock_t txb_stime; 144 145 /* Hardware descriptor info */ 146 seqnum_t txb_desc; 147 int txb_ndescs; 148 uint64_t txb_flag; 149 }; 150 151 152 /* RX buffer management */ 153 struct rxbuf { 154 /* Hardware independent section */ 155 struct rxbuf *rxb_next; 156 struct gem_dev *rxb_devp; 157 158 /* dma mapping management */ 159 ddi_dma_handle_t rxb_dh; 160 caddr_t rxb_buf; 161 size_t rxb_buf_len; 162 ddi_dma_cookie_t rxb_dmacookie[GEM_MAXRXFRAGS]; 163 uint_t rxb_nfrags; 164 165 /* bounce buffer management */ 166 ddi_acc_handle_t rxb_bah; 167 }; 168 169 struct mcast_addr { 170 struct ether_addr addr; 171 uint32_t hash; 172 }; 173 174 #define GEM_MAXMC 64 175 #define GEM_MCALLOC (sizeof (struct mcast_addr) * GEM_MAXMC) 176 177 #define SUB(x, y) ((seqnum_t)((x) - (y))) 178 #define SLOT(seqnum, size) (((unsigned int)(seqnum)) & ((size)-1)) 179 180 /* 181 * mac soft state 182 */ 183 struct gem_dev { 184 dev_info_t *dip; 185 mac_handle_t mh; 186 char name[GEM_NAME_LEN]; 187 void *base_addr; 188 ddi_acc_handle_t regs_handle; 189 ddi_iblock_cookie_t iblock_cookie; 190 191 /* MAC address information */ 192 struct ether_addr cur_addr; 193 struct ether_addr dev_addr; 194 195 /* Descriptor rings, io area */ 196 ddi_dma_handle_t desc_dma_handle; 197 ddi_acc_handle_t desc_acc_handle; 198 caddr_t rx_ring; 199 caddr_t tx_ring; 200 caddr_t io_area; 201 /* caddr_t rx_buf; */ 202 203 uint64_t rx_ring_dma; 204 uint64_t tx_ring_dma; 205 uint64_t io_area_dma; 206 207 /* RX slot ring management */ 208 kmutex_t intrlock; 209 boolean_t intr_busy; 210 seqnum_t rx_active_head; 211 seqnum_t rx_active_tail; 212 mac_resource_handle_t mac_rx_ring_ha; 213 /* Rx buffer management */ 214 struct rxbuf *rx_buf_head; 215 struct rxbuf *rx_buf_tail; 216 struct rxbuf *rx_buf_freelist; 217 int rx_buf_allocated; 218 int rx_buf_freecnt; 219 int rx_buf_len; 220 221 /* TX descriptor ring management */ 222 seqnum_t tx_desc_head; 223 seqnum_t tx_desc_tail; 224 seqnum_t tx_desc_intr; 225 226 /* TX buffur ring management */ 227 kmutex_t xmitlock; 228 kcondvar_t tx_drain_cv; 229 seqnum_t tx_active_head; 230 seqnum_t tx_active_tail; 231 seqnum_t tx_softq_head; 232 seqnum_t tx_softq_tail; 233 seqnum_t tx_free_head; 234 seqnum_t tx_free_tail; 235 int tx_max_packets; 236 237 /* TX buffer resource management */ 238 struct txbuf *tx_buf; 239 seqnum_t tx_slots_base; 240 241 /* TX state management */ 242 int tx_busy; 243 int tx_reclaim_busy; 244 clock_t tx_blocked; 245 246 /* NIC state */ 247 volatile boolean_t mac_active; /* tx and rx are running */ 248 volatile int nic_state; /* logical driver state */ 249 #define NIC_STATE_STOPPED 0 250 #define NIC_STATE_INITIALIZED 1 251 #define NIC_STATE_ONLINE 2 252 volatile boolean_t mac_suspended; 253 254 /* robustness: timer and watchdog */ 255 volatile timeout_id_t timeout_id; 256 257 258 /* MII management */ 259 boolean_t anadv_autoneg:1; 260 boolean_t anadv_1000fdx:1; 261 boolean_t anadv_1000hdx:1; 262 boolean_t anadv_100t4:1; 263 boolean_t anadv_100fdx:1; 264 boolean_t anadv_100hdx:1; 265 boolean_t anadv_10fdx:1; 266 boolean_t anadv_10hdx:1; 267 boolean_t anadv_flow_control:2; 268 boolean_t mii_advert_ro:1; 269 270 boolean_t full_duplex:1; 271 int speed:3; 272 #define GEM_SPD_10 0 273 #define GEM_SPD_100 1 274 #define GEM_SPD_1000 2 275 #define GEM_SPD_NUM 3 276 unsigned int flow_control:2; 277 #define FLOW_CONTROL_NONE 0 278 #define FLOW_CONTROL_SYMMETRIC 1 279 #define FLOW_CONTROL_TX_PAUSE 2 280 #define FLOW_CONTROL_RX_PAUSE 3 281 282 boolean_t mii_supress_msg:1; 283 284 uint32_t mii_phy_id; 285 uint16_t mii_status; 286 uint16_t mii_advert; 287 uint16_t mii_lpable; 288 uint16_t mii_exp; 289 uint16_t mii_ctl1000; 290 uint16_t mii_stat1000; 291 uint16_t mii_xstatus; 292 int8_t mii_phy_addr; /* must be signed */ 293 294 uint8_t mii_state; 295 #define MII_STATE_UNKNOWN 0 296 #define MII_STATE_RESETTING 1 297 #define MII_STATE_AUTONEGOTIATING 2 298 #define MII_STATE_AN_DONE 3 299 #define MII_STATE_MEDIA_SETUP 4 300 #define MII_STATE_LINKUP 5 301 #define MII_STATE_LINKDOWN 6 302 303 clock_t mii_last_check; /* in tick */ 304 clock_t mii_timer; /* in tick */ 305 #define MII_RESET_TIMEOUT drv_usectohz(1000*1000) 306 #define MII_AN_TIMEOUT drv_usectohz(5000*1000) 307 #define MII_LINKDOWN_TIMEOUT drv_usectohz(10000*1000) 308 clock_t mii_interval; /* in tick */ 309 clock_t linkup_delay; /* in tick */ 310 311 volatile timeout_id_t link_watcher_id; 312 313 ddi_softintr_t soft_id; 314 315 /* multcast list management */ 316 int16_t mc_count; 317 int16_t mc_count_req; 318 struct mcast_addr *mc_list; 319 uint32_t rxmode; 320 #define RXMODE_PROMISC 0x01 321 #define RXMODE_ALLMULTI_REQ 0x02 322 #define RXMODE_MULTI_OVF 0x04 323 #define RXMODE_ENABLE 0x08 324 #define RXMODE_ALLMULTI (RXMODE_ALLMULTI_REQ | RXMODE_MULTI_OVF) 325 #define RXMODE_BITS \ 326 "\020" \ 327 "\004ENABLE" \ 328 "\003MULTI_OVF" \ 329 "\002ALLMULTI_REQ" \ 330 "\001PROMISC" 331 332 /* statistcs */ 333 struct gem_stats stats; 334 335 /* pointer to local structure */ 336 void *private; 337 int priv_size; 338 339 /* polling mode */ 340 int poll_pkt_delay; /* in number of packets */ 341 342 /* descriptor area */ 343 int tx_desc_size; 344 int rx_desc_size; 345 346 /* configuration */ 347 struct gem_conf { 348 /* name */ 349 char gc_name[GEM_NAME_LEN]; 350 351 /* specification on tx and rx dma engine */ 352 long gc_tx_buf_align; 353 int gc_tx_max_frags; 354 int gc_tx_max_descs_per_pkt; 355 int gc_tx_buf_size; 356 int gc_tx_buf_limit; 357 int gc_tx_desc_unit_shift; 358 int gc_tx_ring_size; 359 int gc_tx_ring_limit; 360 int gc_tx_copy_thresh; 361 boolean_t gc_tx_auto_pad; 362 boolean_t gc_tx_desc_write_oo; 363 364 long gc_rx_buf_align; 365 int gc_rx_max_frags; 366 int gc_rx_desc_unit_shift; 367 int gc_rx_ring_size; 368 int gc_rx_copy_thresh; 369 int gc_rx_buf_max; 370 int gc_rx_header_len; 371 372 int gc_io_area_size; 373 374 /* memory mapping attributes */ 375 struct ddi_device_acc_attr gc_dev_attr; 376 struct ddi_device_acc_attr gc_buf_attr; 377 struct ddi_device_acc_attr gc_desc_attr; 378 379 /* dma attributes */ 380 ddi_dma_attr_t gc_dma_attr_desc; 381 ddi_dma_attr_t gc_dma_attr_txbuf; 382 ddi_dma_attr_t gc_dma_attr_rxbuf; 383 384 /* tx time out parameters */ 385 clock_t gc_tx_timeout; 386 clock_t gc_tx_timeout_interval; 387 388 /* auto negotiation capability */ 389 int gc_flow_control; 390 391 /* MII mode */ 392 int gc_mii_mode; 393 #define GEM_MODE_100BASETX 0 394 #define GEM_MODE_1000BASET 1 395 #define GEM_MODE_1000BASETX 2 396 397 /* MII link state watch parameters */ 398 clock_t gc_mii_linkdown_timeout; 399 clock_t gc_mii_link_watch_interval; 400 clock_t gc_mii_reset_timeout; 401 402 clock_t gc_mii_an_watch_interval; 403 clock_t gc_mii_an_timeout; 404 clock_t gc_mii_an_wait; 405 clock_t gc_mii_an_delay; 406 407 /* MII configuration */ 408 int gc_mii_addr_min; 409 int gc_mii_linkdown_action; 410 int gc_mii_linkdown_timeout_action; 411 #define MII_ACTION_NONE 0 412 #define MII_ACTION_RESET 1 413 #define MII_ACTION_RSA 2 414 boolean_t gc_mii_dont_reset; 415 boolean_t gc_mii_an_oneshot; 416 boolean_t gc_mii_hw_link_detection; 417 boolean_t gc_mii_stop_mac_on_linkdown; 418 419 /* I/O methods */ 420 421 /* mac operation */ 422 int (*gc_attach_chip)(struct gem_dev *dp); 423 int (*gc_reset_chip)(struct gem_dev *dp); 424 int (*gc_init_chip)(struct gem_dev *dp); 425 int (*gc_start_chip)(struct gem_dev *dp); 426 int (*gc_stop_chip)(struct gem_dev *dp); 427 uint32_t (*gc_multicast_hash)(struct gem_dev *dp, uint8_t *); 428 int (*gc_set_rx_filter)(struct gem_dev *dp); 429 int (*gc_set_media)(struct gem_dev *dp); 430 int (*gc_get_stats)(struct gem_dev *dp); 431 uint_t (*gc_interrupt)(struct gem_dev *dp); 432 433 /* descriptor operation */ 434 int (*gc_tx_desc_write)(struct gem_dev *dp, int slot, 435 ddi_dma_cookie_t *dmacookie, 436 int frags, uint64_t flag); 437 #define GEM_TXFLAG_INTR 0x00000001ull 438 #define GEM_TXFLAG_TCP 0x00000002ull 439 #define GEM_TXFLAG_TCP_SHIFT 1ull 440 #define GEM_TXFLAG_UDP 0x00000004ull 441 #define GEM_TXFLAG_UDP_SHIFT 2ull 442 #define GEM_TXFLAG_IPv4 0x00000008ull 443 #define GEM_TXFLAG_IPv4_SHIFT 3ull 444 #define GEM_TXFLAG_IPv6 0x00000010ull 445 #define GEM_TXFLAG_IPv6_SHIFT 4ull 446 #define GEM_TXFLAG_HEAD 0x00000020ull 447 #define GEM_TXFLAG_TAIL 0x00000040ull 448 #define GEM_TXFLAG_SWVTAG 0x00000080ull 449 #define GEM_TXFLAG_PRIVATE 0x0000ff00ull 450 #define GEM_TXFLAG_PRIVATE_SHIFT 8ull 451 #define GEM_TXFLAG_PRIVATE_MASK 0xffull 452 #define GEM_TXFLAG_VID 0x0fff0000ull 453 #define GEM_TXFLAG_VID_SHIFT 16ull 454 #define GEM_TXFLAG_VID_MASK 0xfffull 455 #define GEM_TXFLAG_CFI 0x10000000ull 456 #define GEM_TXFLAG_PRI 0xe0000000ull 457 #define GEM_TXFLAG_PRI_SHIFT 29ull 458 #define GEM_TXFLAG_PRI_MASK 0x7ull 459 #define GEM_TXFLAG_VTAG 0xffff0000ull 460 #define GEM_TXFLAG_VTAG_SHIFT 16ull 461 #define GEM_TXFLAG_HCKSTART 0x000000ff00000000ull 462 #define GEM_TXFLAG_HCKSTART_SHIFT 32ull 463 #define GEM_TXFLAG_HCKSTUFF 0x0000ff0000000000ull 464 #define GEM_TXFLAG_HCKSTUFF_SHIFT 40ull 465 #define GEM_TXFLAG_TCPHLEN 0x0000ff0000000000ull 466 #define GEM_TXFLAG_TCPHLEN_SHIFT 40ull 467 #define GEM_TXFLAG_MSS 0xffff000000000000ull 468 #define GEM_TXFLAG_MSS_SHIFT 48ull 469 470 void (*gc_tx_start) (struct gem_dev *dp, int slot, int frags); 471 void (*gc_rx_desc_write)(struct gem_dev *dp, int slot, 472 ddi_dma_cookie_t *dmacookie, int frags); 473 void (*gc_rx_start)(struct gem_dev *dp, int slot, int frags); 474 475 uint_t (*gc_tx_desc_stat) 476 (struct gem_dev *dp, int slot, int descs); 477 #define GEM_TX_DONE 0x00010000 478 #define GEM_TX_ERR 0x00020000 479 480 481 uint64_t (*gc_rx_desc_stat) 482 (struct gem_dev *dp, int slot, int frags); 483 484 #define GEM_RX_CKSUM 0xffff000000000000ull 485 #define GEM_RX_CKSUM_SHIFT 48 486 #define GEM_RX_PRI 0x0000e00000000000ull 487 #define GEM_RX_PRI_SHIFT 45 488 #define GEM_RX_CFI 0x0000100000000000ull 489 #define GEM_RX_VID 0x00000fff00000000ull 490 #define GEM_RX_VID_SHIFT 32 491 #define GEM_RX_VTAG 0x0000ffff00000000ull 492 #define GEM_RX_VTAG_SHIFT 32 493 494 #define GEM_RX_CKSUM_IPv6 0x00080000ul 495 #define GEM_RX_CKSUM_IPv6_SHIFT 19 496 #define GEM_RX_CKSUM_IPv4 0x00040000ul 497 #define GEM_RX_CKSUM_IPv4_SHIFT 18 498 #define GEM_RX_CKSUM_UDP 0x00020000ul 499 #define GEM_RX_CKSUM_UDP_SHIFT 17 500 #define GEM_RX_CKSUM_TCP 0x00010000ul 501 #define GEM_RX_CKSUM_TCP_SHIFT 16 502 #define GEM_RX_ERR 0x00008000ul 503 #define GEM_RX_DONE 0x00004000ul 504 #define GEM_RX_LEN 0x00003ffful /* 16KB - 1 */ 505 506 void (*gc_tx_desc_init)(struct gem_dev *dp, int slot); 507 void (*gc_rx_desc_init)(struct gem_dev *dp, int slot); 508 void (*gc_tx_desc_clean)(struct gem_dev *dp, int slot); 509 void (*gc_rx_desc_clean)(struct gem_dev *dp, int slot); 510 511 /* mii operations */ 512 int (*gc_mii_probe)(struct gem_dev *dp); 513 int (*gc_mii_init)(struct gem_dev *dp); 514 int (*gc_mii_config)(struct gem_dev *dp); 515 void (*gc_mii_sync)(struct gem_dev *dp); 516 uint16_t (*gc_mii_read)(struct gem_dev *dp, uint_t reg); 517 void (*gc_mii_write)(struct gem_dev *dp, 518 uint_t reg, uint16_t val); 519 void (*gc_mii_tune_phy)(struct gem_dev *dp); 520 521 /* packet in/out operation for copy-style */ 522 void (*gc_put_packet)(struct gem_dev *dp, 523 mblk_t *, void *, size_t); 524 mblk_t *(*gc_get_packet)(struct gem_dev *dp, 525 struct rxbuf *, size_t); 526 int gc_nports; 527 528 /* hw checksum */ 529 uint32_t gc_hck_rx_start; 530 } gc; 531 532 uint32_t misc_flag; 533 #define GEM_LSO 0x00000400 534 #define GEM_CTRL_PKT 0x00000200 535 #define GEM_SOFTINTR 0x00000100 536 #define GEM_POLL_RXONLY 0x00000080 537 #define GEM_VLAN_HARD 0x00000040 538 #define GEM_VLAN_SOFT 0x00000020 539 #define GEM_VLAN (GEM_VLAN_HARD | GEM_VLAN_SOFT) 540 #define GEM_CKSUM_HEADER_IPv4 0x00000010 541 #define GEM_CKSUM_PARTIAL 0x00000008 542 #define GEM_CKSUM_FULL_IPv6 0x00000004 543 #define GEM_CKSUM_FULL_IPv4 0x00000002 544 #define GEM_NOINTR 0x00000001 545 546 volatile timeout_id_t intr_watcher_id; 547 548 uint_t mtu; 549 550 /* performance tuning parameters */ 551 uint_t txthr; /* tx fifo threshoold */ 552 uint_t txmaxdma; /* tx max dma burst size */ 553 uint_t rxthr; /* rx fifo threshoold */ 554 uint_t rxmaxdma; /* tx max dma burst size */ 555 556 /* kstat stuff */ 557 kstat_t *ksp; 558 559 /* multiple port device support */ 560 struct gem_dev *next; /* pointer to next port on the same device */ 561 int port; 562 563 /* ndd stuff */ 564 caddr_t nd_data_p; 565 caddr_t nd_arg_p; 566 567 #ifdef GEM_DEBUG_LEVEL 568 int tx_cnt; 569 #endif 570 }; 571 572 /* 573 * Exported functions 574 */ 575 boolean_t gem_get_mac_addr_conf(struct gem_dev *); 576 int gem_mii_probe_default(struct gem_dev *); 577 int gem_mii_config_default(struct gem_dev *); 578 boolean_t gem_mii_link_check(struct gem_dev *dp); 579 uint16_t gem_mii_read(struct gem_dev *, uint_t); 580 void gem_mii_write(struct gem_dev *, uint_t, uint16_t); 581 int gem_reclaim_txbuf(struct gem_dev *dp); 582 int gem_restart_nic(struct gem_dev *dp, uint_t flags); 583 #define GEM_RESTART_NOWAIT 0x00000002 584 #define GEM_RESTART_KEEP_BUF 0x00000001 585 boolean_t gem_tx_done(struct gem_dev *); 586 int gem_receive(struct gem_dev *); 587 int gem_receive_copy(struct gem_dev *); 588 struct gem_dev *gem_do_attach(dev_info_t *, int, 589 struct gem_conf *, void *, ddi_acc_handle_t *, void *, int); 590 591 mblk_t *gem_send_common(struct gem_dev *, mblk_t *, uint32_t); 592 #define GEM_SEND_COPY 0x00008000 593 #define GEM_SEND_CTRL 0x000000ff /* private flags for control packets */ 594 #define GEM_SEND_VTAG 0xffff0000 595 #define GEM_SEND_VTAG_SHIFT 16 596 597 mblk_t *gem_get_packet_default(struct gem_dev *, struct rxbuf *, size_t); 598 599 uint32_t gem_ether_crc_le(const uint8_t *addr, int len); 600 uint32_t gem_ether_crc_be(const uint8_t *addr, int len); 601 int gem_do_detach(dev_info_t *); 602 603 int gem_getlongprop_buf(dev_t dev, dev_info_t *dip, 604 int flags, char *name, void *buf, int *lenp); 605 int gem_getprop(dev_t dev, dev_info_t *dip, 606 int flags, char *name, int defvalue); 607 608 struct rxbuf *gem_get_rxbuf(struct gem_dev *, int); 609 610 void gem_rx_desc_dma_sync(struct gem_dev *, int, int, int); 611 void gem_tx_desc_dma_sync(struct gem_dev *, int, int, int); 612 613 int gem_resume(dev_info_t *); 614 int gem_suspend(dev_info_t *); 615 uint8_t gem_search_pci_cap(dev_info_t *dip, ddi_acc_handle_t, uint8_t); 616 int gem_pci_set_power_state(dev_info_t *, ddi_acc_handle_t, uint_t); 617 int gem_pci_regs_map_setup(dev_info_t *, uint32_t, uint32_t, 618 struct ddi_device_acc_attr *, caddr_t *, ddi_acc_handle_t *); 619 void gem_mod_init(struct dev_ops *, char *); 620 void gem_mod_fini(struct dev_ops *); 621 622 #define GEM_GET_DEV(dip) \ 623 ((struct gem_dev *)(ddi_get_driver_private(dip))) 624 #endif /* _SFE_UTIL_H_ */ 625