1a72f7ea6Sql147931 /* 2*9aa73b68SQin Michael Li * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3a72f7ea6Sql147931 * Use is subject to license terms. 4a72f7ea6Sql147931 */ 5a72f7ea6Sql147931 /* 6a72f7ea6Sql147931 * Copyright (c) 2004, 2005 David Young. All rights reserved. 7a72f7ea6Sql147931 * 8a72f7ea6Sql147931 * Programmed for NetBSD by David Young. 9a72f7ea6Sql147931 * 10a72f7ea6Sql147931 * Redistribution and use in source and binary forms, with or without 11a72f7ea6Sql147931 * modification, are permitted provided that the following conditions 12a72f7ea6Sql147931 * are met: 13a72f7ea6Sql147931 * 1. Redistributions of source code must retain the above copyright 14a72f7ea6Sql147931 * notice, this list of conditions and the following disclaimer. 15a72f7ea6Sql147931 * 2. Redistributions in binary form must reproduce the above copyright 16a72f7ea6Sql147931 * notice, this list of conditions and the following disclaimer in the 17a72f7ea6Sql147931 * documentation and/or other materials provided with the distribution. 18a72f7ea6Sql147931 * 3. The name of David Young may not be used to endorse or promote 19a72f7ea6Sql147931 * products derived from this software without specific prior 20a72f7ea6Sql147931 * written permission. 21a72f7ea6Sql147931 * 22a72f7ea6Sql147931 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 23a72f7ea6Sql147931 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24a72f7ea6Sql147931 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 25a72f7ea6Sql147931 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 26a72f7ea6Sql147931 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27a72f7ea6Sql147931 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 28a72f7ea6Sql147931 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29a72f7ea6Sql147931 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30a72f7ea6Sql147931 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31a72f7ea6Sql147931 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32a72f7ea6Sql147931 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33a72f7ea6Sql147931 * OF SUCH DAMAGE. 34a72f7ea6Sql147931 */ 35a72f7ea6Sql147931 /* 36a72f7ea6Sql147931 * Control input/output with the Philips SA2400 RF front-end and 37a72f7ea6Sql147931 * the baseband processor built into the Realtek RTL8180. 38a72f7ea6Sql147931 */ 39a72f7ea6Sql147931 #include <sys/types.h> 40*9aa73b68SQin Michael Li #include <sys/sysmacros.h> 41a72f7ea6Sql147931 #include "rtwreg.h" 42a72f7ea6Sql147931 #include "max2820reg.h" 43a72f7ea6Sql147931 #include "sa2400reg.h" 44a72f7ea6Sql147931 #include "si4136reg.h" 45a72f7ea6Sql147931 #include "rtwvar.h" 46a72f7ea6Sql147931 #include "rtwphyio.h" 47a72f7ea6Sql147931 #include "rtwphy.h" 48a72f7ea6Sql147931 49a72f7ea6Sql147931 static int rtw_macbangbits_timeout = 100; 50a72f7ea6Sql147931 51a72f7ea6Sql147931 uint8_t 52a72f7ea6Sql147931 rtw_bbp_read(struct rtw_regs *regs, uint_t addr) 53a72f7ea6Sql147931 { 54a72f7ea6Sql147931 RTW_WRITE(regs, RTW_BB, 55a72f7ea6Sql147931 LSHIFT(addr, RTW_BB_ADDR_MASK) | RTW_BB_RD_MASK | RTW_BB_WR_MASK); 56a72f7ea6Sql147931 DELAY(10); 57a72f7ea6Sql147931 RTW_WBR(regs, RTW_BB, RTW_BB); 58a72f7ea6Sql147931 return (MASK_AND_RSHIFT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK)); 59a72f7ea6Sql147931 } 60a72f7ea6Sql147931 61a72f7ea6Sql147931 int 62a72f7ea6Sql147931 rtw_bbp_write(struct rtw_regs *regs, uint_t addr, uint_t val) 63a72f7ea6Sql147931 { 64a72f7ea6Sql147931 #define BBP_WRITE_ITERS 50 65a72f7ea6Sql147931 #define BBP_WRITE_DELAY 1 66a72f7ea6Sql147931 int i; 67a72f7ea6Sql147931 uint32_t wrbbp, rdbbp; 68a72f7ea6Sql147931 69a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHYIO, 70a72f7ea6Sql147931 "%s: bbp[%u] <- %u\n", __func__, addr, val); 71a72f7ea6Sql147931 72a72f7ea6Sql147931 wrbbp = LSHIFT(addr, RTW_BB_ADDR_MASK) | RTW_BB_WREN | 73a72f7ea6Sql147931 LSHIFT(val, RTW_BB_WR_MASK) | RTW_BB_RD_MASK, 74a72f7ea6Sql147931 rdbbp = LSHIFT(addr, RTW_BB_ADDR_MASK) | 75a72f7ea6Sql147931 RTW_BB_WR_MASK | RTW_BB_RD_MASK; 76a72f7ea6Sql147931 77a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHYIO, 78a72f7ea6Sql147931 "%s: rdbbp = %08x, wrbbp = %08x\n", __func__, rdbbp, wrbbp); 79a72f7ea6Sql147931 80a72f7ea6Sql147931 for (i = BBP_WRITE_ITERS; --i >= 0; ) { 81a72f7ea6Sql147931 RTW_RBW(regs, RTW_BB, RTW_BB); 82a72f7ea6Sql147931 RTW_WRITE(regs, RTW_BB, wrbbp); 83a72f7ea6Sql147931 RTW_SYNC(regs, RTW_BB, RTW_BB); 84a72f7ea6Sql147931 RTW_WRITE(regs, RTW_BB, rdbbp); 85a72f7ea6Sql147931 RTW_SYNC(regs, RTW_BB, RTW_BB); 86a72f7ea6Sql147931 DELAY(BBP_WRITE_DELAY); /* 1 microsecond */ 87a72f7ea6Sql147931 if (MASK_AND_RSHIFT(RTW_READ(regs, RTW_BB), 88a72f7ea6Sql147931 RTW_BB_RD_MASK) == val) { 89a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHYIO, 90a72f7ea6Sql147931 "%s: finished in %dus\n", __func__, 91a72f7ea6Sql147931 BBP_WRITE_DELAY * (BBP_WRITE_ITERS - i)); 92a72f7ea6Sql147931 return (0); 93a72f7ea6Sql147931 } 94a72f7ea6Sql147931 DELAY(BBP_WRITE_DELAY); /* again */ 95a72f7ea6Sql147931 } 96a72f7ea6Sql147931 cmn_err(CE_NOTE, "%s: timeout\n", __func__); 97a72f7ea6Sql147931 return (-1); 98a72f7ea6Sql147931 } 99a72f7ea6Sql147931 100a72f7ea6Sql147931 /* 101a72f7ea6Sql147931 * Help rtw_rf_hostwrite bang bits to RF over 3-wire interface. 102a72f7ea6Sql147931 */ 103a72f7ea6Sql147931 static void 104a72f7ea6Sql147931 rtw_rf_hostbangbits(struct rtw_regs *regs, uint32_t bits, int lo_to_hi, 105a72f7ea6Sql147931 uint_t nbits) 106a72f7ea6Sql147931 { 107a72f7ea6Sql147931 int i; 108a72f7ea6Sql147931 uint32_t mask, reg; 109a72f7ea6Sql147931 110a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHYIO, 111a72f7ea6Sql147931 "%s: %u bits, %08x, %s\n", __func__, nbits, bits, 112a72f7ea6Sql147931 (lo_to_hi) ? "lo to hi" : "hi to lo"); 113a72f7ea6Sql147931 114a72f7ea6Sql147931 reg = RTW_PHYCFG_HST; 115a72f7ea6Sql147931 RTW_WRITE(regs, RTW_PHYCFG, reg); 116a72f7ea6Sql147931 RTW_SYNC(regs, RTW_PHYCFG, RTW_PHYCFG); 117a72f7ea6Sql147931 118a72f7ea6Sql147931 if (lo_to_hi) 119a72f7ea6Sql147931 mask = 0x1; 120a72f7ea6Sql147931 else 121a72f7ea6Sql147931 mask = 1 << (nbits - 1); 122a72f7ea6Sql147931 123a72f7ea6Sql147931 for (i = 0; i < nbits; i++) { 124a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHYBITIO, 125a72f7ea6Sql147931 "%s: bits %08x mask %08x -> bit %08x\n", 126a72f7ea6Sql147931 __func__, bits, mask, bits & mask); 127a72f7ea6Sql147931 128a72f7ea6Sql147931 if ((bits & mask) != 0) 129a72f7ea6Sql147931 reg |= RTW_PHYCFG_HST_DATA; 130a72f7ea6Sql147931 else 131a72f7ea6Sql147931 reg &= ~RTW_PHYCFG_HST_DATA; 132a72f7ea6Sql147931 133a72f7ea6Sql147931 reg |= RTW_PHYCFG_HST_CLK; 134a72f7ea6Sql147931 RTW_WRITE(regs, RTW_PHYCFG, reg); 135a72f7ea6Sql147931 RTW_SYNC(regs, RTW_PHYCFG, RTW_PHYCFG); 136a72f7ea6Sql147931 137a72f7ea6Sql147931 DELAY(2); /* arbitrary delay */ 138a72f7ea6Sql147931 139a72f7ea6Sql147931 reg &= ~RTW_PHYCFG_HST_CLK; 140a72f7ea6Sql147931 RTW_WRITE(regs, RTW_PHYCFG, reg); 141a72f7ea6Sql147931 RTW_SYNC(regs, RTW_PHYCFG, RTW_PHYCFG); 142a72f7ea6Sql147931 143a72f7ea6Sql147931 if (lo_to_hi) 144a72f7ea6Sql147931 mask <<= 1; 145a72f7ea6Sql147931 else 146a72f7ea6Sql147931 mask >>= 1; 147a72f7ea6Sql147931 } 148a72f7ea6Sql147931 149a72f7ea6Sql147931 reg |= RTW_PHYCFG_HST_EN; 150a72f7ea6Sql147931 RTW_WRITE(regs, RTW_PHYCFG, reg); 151a72f7ea6Sql147931 RTW_SYNC(regs, RTW_PHYCFG, RTW_PHYCFG); 152a72f7ea6Sql147931 } 153a72f7ea6Sql147931 154a72f7ea6Sql147931 /* 155a72f7ea6Sql147931 * Help rtw_rf_macwrite: tell MAC to bang bits to RF over the 3-wire 156a72f7ea6Sql147931 * interface. 157a72f7ea6Sql147931 */ 158a72f7ea6Sql147931 static int 159a72f7ea6Sql147931 rtw_rf_macbangbits(struct rtw_regs *regs, uint32_t reg) 160a72f7ea6Sql147931 { 161a72f7ea6Sql147931 int i; 162a72f7ea6Sql147931 163a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHY, "%s: %08x\n", __func__, reg); 164a72f7ea6Sql147931 165a72f7ea6Sql147931 RTW_WRITE(regs, RTW_PHYCFG, RTW_PHYCFG_MAC_POLL | reg); 166a72f7ea6Sql147931 167a72f7ea6Sql147931 RTW_WBR(regs, RTW_PHYCFG, RTW_PHYCFG); 168a72f7ea6Sql147931 169a72f7ea6Sql147931 for (i = rtw_macbangbits_timeout; --i >= 0; DELAY(1)) { 170a72f7ea6Sql147931 if ((RTW_READ(regs, RTW_PHYCFG) & RTW_PHYCFG_MAC_POLL) == 0) { 171a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHY, 172a72f7ea6Sql147931 "%s: finished in %dus\n", __func__, 173a72f7ea6Sql147931 rtw_macbangbits_timeout - i); 174a72f7ea6Sql147931 return (0); 175a72f7ea6Sql147931 } 176a72f7ea6Sql147931 RTW_RBR(regs, RTW_PHYCFG, RTW_PHYCFG); /* paranoia? */ 177a72f7ea6Sql147931 } 178a72f7ea6Sql147931 179a72f7ea6Sql147931 cmn_err(CE_NOTE, "%s: RTW_PHYCFG_MAC_POLL still set.\n", __func__); 180a72f7ea6Sql147931 return (-1); 181a72f7ea6Sql147931 } 182a72f7ea6Sql147931 183a72f7ea6Sql147931 /*ARGSUSED*/ 184a72f7ea6Sql147931 static uint32_t 185a72f7ea6Sql147931 rtw_grf5101_host_crypt(uint_t addr, uint32_t val) 186a72f7ea6Sql147931 { 187a72f7ea6Sql147931 /* TBD */ 188a72f7ea6Sql147931 return (0); 189a72f7ea6Sql147931 } 190a72f7ea6Sql147931 191a72f7ea6Sql147931 static uint32_t 192a72f7ea6Sql147931 rtw_grf5101_mac_crypt(uint_t addr, uint32_t val) 193a72f7ea6Sql147931 { 194a72f7ea6Sql147931 uint32_t data_and_addr; 195a72f7ea6Sql147931 #define EXTRACT_NIBBLE(d, which) (((d) >> (4 * (which))) & 0xf) 196a72f7ea6Sql147931 static uint8_t caesar[16] = 197a72f7ea6Sql147931 { 198a72f7ea6Sql147931 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, 199a72f7ea6Sql147931 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 200a72f7ea6Sql147931 }; 201a72f7ea6Sql147931 202a72f7ea6Sql147931 data_and_addr = caesar[EXTRACT_NIBBLE(val, 2)] | 203a72f7ea6Sql147931 (caesar[EXTRACT_NIBBLE(val, 1)] << 4) | 204a72f7ea6Sql147931 (caesar[EXTRACT_NIBBLE(val, 0)] << 8) | 205a72f7ea6Sql147931 (caesar[(addr >> 1) & 0xf] << 12) | 206a72f7ea6Sql147931 ((addr & 0x1) << 16) | 207a72f7ea6Sql147931 (caesar[EXTRACT_NIBBLE(val, 3)] << 24); 208a72f7ea6Sql147931 return (LSHIFT(data_and_addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK | 209a72f7ea6Sql147931 RTW_PHYCFG_MAC_PHILIPS_DATA_MASK)); 210a72f7ea6Sql147931 #undef EXTRACT_NIBBLE 211a72f7ea6Sql147931 } 212a72f7ea6Sql147931 213a72f7ea6Sql147931 static const char * 214a72f7ea6Sql147931 rtw_rfchipid_string(enum rtw_rfchipid rfchipid) 215a72f7ea6Sql147931 { 216a72f7ea6Sql147931 switch (rfchipid) { 217a72f7ea6Sql147931 case RTW_RFCHIPID_MAXIM: 218a72f7ea6Sql147931 return ("Maxim"); 219a72f7ea6Sql147931 case RTW_RFCHIPID_PHILIPS: 220a72f7ea6Sql147931 return ("Philips"); 221a72f7ea6Sql147931 case RTW_RFCHIPID_GCT: 222a72f7ea6Sql147931 return ("GCT"); 223a72f7ea6Sql147931 case RTW_RFCHIPID_RFMD: 224a72f7ea6Sql147931 return ("RFMD"); 225a72f7ea6Sql147931 case RTW_RFCHIPID_INTERSIL: 226a72f7ea6Sql147931 return ("Intersil"); 227a72f7ea6Sql147931 default: 228a72f7ea6Sql147931 return ("unknown"); 229a72f7ea6Sql147931 } 230a72f7ea6Sql147931 } 231a72f7ea6Sql147931 232a72f7ea6Sql147931 /* 233a72f7ea6Sql147931 * Bang bits over the 3-wire interface. 234a72f7ea6Sql147931 */ 235a72f7ea6Sql147931 int 236a72f7ea6Sql147931 rtw_rf_hostwrite(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 237a72f7ea6Sql147931 uint_t addr, uint32_t val) 238a72f7ea6Sql147931 { 239a72f7ea6Sql147931 uint_t nbits; 240a72f7ea6Sql147931 int lo_to_hi; 241a72f7ea6Sql147931 uint32_t bits; 242a72f7ea6Sql147931 243a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHYIO, "%s: %s[%u] <- %08x\n", __func__, 244a72f7ea6Sql147931 rtw_rfchipid_string(rfchipid), addr, val); 245a72f7ea6Sql147931 246a72f7ea6Sql147931 switch (rfchipid) { 247a72f7ea6Sql147931 case RTW_RFCHIPID_MAXIM: 248a72f7ea6Sql147931 nbits = 16; 249a72f7ea6Sql147931 lo_to_hi = 0; 250a72f7ea6Sql147931 bits = LSHIFT(val, MAX2820_TWI_DATA_MASK) | 251a72f7ea6Sql147931 LSHIFT(addr, MAX2820_TWI_ADDR_MASK); 252a72f7ea6Sql147931 break; 253a72f7ea6Sql147931 case RTW_RFCHIPID_PHILIPS: 254a72f7ea6Sql147931 bits = LSHIFT(val, SA2400_TWI_DATA_MASK) | 255a72f7ea6Sql147931 LSHIFT(addr, SA2400_TWI_ADDR_MASK) | SA2400_TWI_WREN; 256a72f7ea6Sql147931 nbits = 32; 257a72f7ea6Sql147931 lo_to_hi = 1; 258a72f7ea6Sql147931 break; 259a72f7ea6Sql147931 case RTW_RFCHIPID_GCT: 260a72f7ea6Sql147931 case RTW_RFCHIPID_RFMD: 261a72f7ea6Sql147931 if (rfchipid == RTW_RFCHIPID_GCT) 262a72f7ea6Sql147931 bits = rtw_grf5101_host_crypt(addr, val); 263a72f7ea6Sql147931 else { 264a72f7ea6Sql147931 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 265a72f7ea6Sql147931 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 266a72f7ea6Sql147931 } 267a72f7ea6Sql147931 nbits = 22; 268a72f7ea6Sql147931 lo_to_hi = 0; 269a72f7ea6Sql147931 break; 270a72f7ea6Sql147931 case RTW_RFCHIPID_INTERSIL: 271a72f7ea6Sql147931 default: 272a72f7ea6Sql147931 cmn_err(CE_WARN, "%s: unknown rfchipid %d\n", 273a72f7ea6Sql147931 __func__, rfchipid); 274a72f7ea6Sql147931 return (-1); 275a72f7ea6Sql147931 } 276a72f7ea6Sql147931 277a72f7ea6Sql147931 rtw_rf_hostbangbits(regs, bits, lo_to_hi, nbits); 278a72f7ea6Sql147931 279a72f7ea6Sql147931 return (0); 280a72f7ea6Sql147931 } 281a72f7ea6Sql147931 282a72f7ea6Sql147931 static uint32_t 283a72f7ea6Sql147931 rtw_maxim_swizzle(uint_t addr, uint32_t val) 284a72f7ea6Sql147931 { 285a72f7ea6Sql147931 uint32_t hidata, lodata; 286a72f7ea6Sql147931 287a72f7ea6Sql147931 lodata = MASK_AND_RSHIFT(val, RTW_MAXIM_LODATA_MASK); 288a72f7ea6Sql147931 hidata = MASK_AND_RSHIFT(val, RTW_MAXIM_HIDATA_MASK); 289a72f7ea6Sql147931 return (LSHIFT(lodata, RTW_PHYCFG_MAC_MAXIM_LODATA_MASK) | 290a72f7ea6Sql147931 LSHIFT(hidata, RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK) | 291a72f7ea6Sql147931 LSHIFT(addr, RTW_PHYCFG_MAC_MAXIM_ADDR_MASK)); 292a72f7ea6Sql147931 } 293a72f7ea6Sql147931 294a72f7ea6Sql147931 /* 295a72f7ea6Sql147931 * Tell the MAC what to bang over the 3-wire interface. 296a72f7ea6Sql147931 */ 297a72f7ea6Sql147931 int 298a72f7ea6Sql147931 rtw_rf_macwrite(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, 299a72f7ea6Sql147931 uint_t addr, uint32_t val) 300a72f7ea6Sql147931 { 301a72f7ea6Sql147931 uint32_t reg; 302a72f7ea6Sql147931 303a72f7ea6Sql147931 RTW_DPRINTF(RTW_DEBUG_PHYIO, "%s: %s[%u] <- %08x\n", __func__, 304a72f7ea6Sql147931 rtw_rfchipid_string(rfchipid), addr, val); 305a72f7ea6Sql147931 306a72f7ea6Sql147931 switch (rfchipid) { 307a72f7ea6Sql147931 case RTW_RFCHIPID_GCT: 308a72f7ea6Sql147931 reg = rtw_grf5101_mac_crypt(addr, val); 309a72f7ea6Sql147931 break; 310a72f7ea6Sql147931 case RTW_RFCHIPID_MAXIM: 311a72f7ea6Sql147931 reg = rtw_maxim_swizzle(addr, val); 312a72f7ea6Sql147931 break; 313a72f7ea6Sql147931 default: 314a72f7ea6Sql147931 case RTW_RFCHIPID_PHILIPS: 315a72f7ea6Sql147931 316a72f7ea6Sql147931 reg = LSHIFT(addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK) | 317a72f7ea6Sql147931 LSHIFT(val, RTW_PHYCFG_MAC_PHILIPS_DATA_MASK); 318a72f7ea6Sql147931 } 319a72f7ea6Sql147931 320a72f7ea6Sql147931 switch (rfchipid) { 321a72f7ea6Sql147931 case RTW_RFCHIPID_GCT: 322a72f7ea6Sql147931 case RTW_RFCHIPID_MAXIM: 323a72f7ea6Sql147931 case RTW_RFCHIPID_RFMD: 324a72f7ea6Sql147931 reg |= RTW_PHYCFG_MAC_RFTYPE_RFMD; 325a72f7ea6Sql147931 break; 326a72f7ea6Sql147931 case RTW_RFCHIPID_INTERSIL: 327a72f7ea6Sql147931 reg |= RTW_PHYCFG_MAC_RFTYPE_INTERSIL; 328a72f7ea6Sql147931 break; 329a72f7ea6Sql147931 case RTW_RFCHIPID_PHILIPS: 330a72f7ea6Sql147931 reg |= RTW_PHYCFG_MAC_RFTYPE_PHILIPS; 331a72f7ea6Sql147931 break; 332a72f7ea6Sql147931 default: 333a72f7ea6Sql147931 cmn_err(CE_WARN, "%s: unknown rfchipid %d\n", 334a72f7ea6Sql147931 __func__, rfchipid); 335a72f7ea6Sql147931 return (-1); 336a72f7ea6Sql147931 } 337a72f7ea6Sql147931 338a72f7ea6Sql147931 return (rtw_rf_macbangbits(regs, reg)); 339a72f7ea6Sql147931 } 340