1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _RGE_HW_H 27 #define _RGE_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 37 38 /* 39 * First section: 40 * Identification of the various Realtek GigE chips 41 */ 42 43 /* 44 * Driver support device 45 */ 46 #define VENDOR_ID_REALTECK 0x10EC 47 #define DEVICE_ID_8169 0x8169 /* PCI */ 48 #define DEVICE_ID_8110 0x8169 /* PCI */ 49 #define DEVICE_ID_8168 0x8168 /* PCI-E */ 50 #define DEVICE_ID_8111 0x8168 /* PCI-E */ 51 #define DEVICE_ID_8169SC 0x8167 /* PCI */ 52 #define DEVICE_ID_8110SC 0x8167 /* PCI */ 53 54 #define RGE_REGISTER_MAX 0x0100 55 56 57 /* 58 * Second section: 59 * Offsets of important registers & definitions for bits therein 60 */ 61 /* 62 * MAC address register, initial value is autoloaded from the 63 * EEPROM EthernetID field 64 */ 65 #define ID_0_REG 0x0000 66 #define ID_1_REG 0x0001 67 #define ID_2_REG 0x0002 68 #define ID_3_REG 0x0003 69 #define ID_4_REG 0x0004 70 #define ID_5_REG 0x0005 71 72 /* 73 * Multicast register 74 */ 75 #define MULTICAST_0_REG 0x0008 76 #define MULTICAST_1_REG 0x0009 77 #define MULTICAST_2_REG 0x000a 78 #define MULTICAST_3_REG 0x000b 79 #define MULTICAST_4_REG 0x000c 80 #define MULTICAST_5_REG 0x000d 81 #define MULTICAST_6_REG 0x000e 82 #define MULTICAST_7_REG 0x000f 83 #define RGE_MCAST_NUM 8 /* total 8 registers: MAR0 - MAR7 */ 84 85 /* 86 * Dump Tally Counter Command register 87 */ 88 #define DUMP_COUNTER_REG_0 0x0010 89 #define DUMP_COUNTER_REG_RESV 0x00000037 90 #define DUMP_START 0x00000008 91 #define DUMP_COUNTER_REG_1 0x0014 92 93 /* 94 * Register for start address of transmit descriptors 95 */ 96 #define NORMAL_TX_RING_ADDR_LO_REG 0x0020 97 #define NORMAL_TX_RING_ADDR_HI_REG 0x0024 98 #define HIGH_TX_RING_ADDR_LO_REG 0x0028 99 #define HIGH_TX_RING_ADDR_HI_REG 0x002c 100 101 /* 102 * Commond register 103 */ 104 #define RT_COMMAND_REG 0x0037 105 #define RT_COMMAND_RESV 0xe3 106 #define RT_COMMAND_RESET 0x10 107 #define RT_COMMAND_RX_ENABLE 0x08 108 #define RT_COMMAND_TX_ENABLE 0x04 109 110 /* 111 * Transmit priority polling register 112 */ 113 #define TX_RINGS_POLL_REG 0x0038 114 #define HIGH_TX_RING_POLL 0x80 115 #define NORMAL_TX_RING_POLL 0x40 116 #define FORCE_SW_INT 0x01 117 118 /* 119 * Interrupt mask & status register 120 */ 121 #define INT_MASK_REG 0x003c 122 #define INT_STATUS_REG 0x003e 123 #define SYS_ERR_INT 0x8000 124 #define TIME_OUT_INT 0x4000 125 #define SW_INT 0x0100 126 #define NO_TXDESC_INT 0x0080 127 #define RX_FIFO_OVERFLOW_INT 0x0040 128 #define LINK_CHANGE_INT 0x0020 129 #define NO_RXDESC_INT 0x0010 130 #define TX_ERR_INT 0x0008 131 #define TX_OK_INT 0x0004 132 #define RX_ERR_INT 0x0002 133 #define RX_OK_INT 0x0001 134 135 #define INT_REG_RESV 0x3e00 136 #define INT_MASK_ALL 0xffff 137 #define INT_MASK_NONE 0x0000 138 #define RGE_RX_INT (RX_OK_INT | RX_ERR_INT | \ 139 NO_RXDESC_INT) 140 #define RGE_INT_MASK (RGE_RX_INT | LINK_CHANGE_INT) 141 142 /* 143 * Transmit configuration register 144 */ 145 #define TX_CONFIG_REG 0x0040 146 #define TX_CONFIG_REG_RESV 0x8070f8ff 147 #define HW_VERSION_ID_0 0x7c000000 148 #define INTER_FRAME_GAP_BITS 0x03080000 149 #define TX_INTERFRAME_GAP_802_3 0x03000000 150 #define HW_VERSION_ID_1 0x00800000 151 #define MAC_LOOPBACK_ENABLE 0x00060000 152 #define CRC_APPEND_ENABLE 0x00010000 153 #define TX_DMA_BURST_BITS 0x00000700 154 155 #define TX_DMA_BURST_UNLIMIT 0x00000700 156 #define TX_DMA_BURST_1024B 0x00000600 157 #define TX_DMA_BURST_512B 0x00000500 158 #define TX_DMA_BURST_256B 0x00000400 159 #define TX_DMA_BURST_128B 0x00000300 160 #define TX_DMA_BURST_64B 0x00000200 161 #define TX_DMA_BURST_32B 0x00000100 162 #define TX_DMA_BURST_16B 0x00000000 163 164 #define MAC_VER_8169 0x00000000 165 #define MAC_VER_8169S_D 0x00800000 166 #define MAC_VER_8169S_E 0x04000000 167 #define MAC_VER_8169SB 0x10000000 168 #define MAC_VER_8169SC 0x18000000 169 #define MAC_VER_8168 0x20000000 170 #define MAC_VER_8168B_B 0x30000000 171 #define MAC_VER_8168B_C 0x38000000 172 173 #define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \ 174 TX_DMA_BURST_1024B) 175 /* 176 * Receive configuration register 177 */ 178 #define RX_CONFIG_REG 0x0044 179 #define RX_CONFIG_REG_RESV 0xfffe1880 180 #define RX_RER8_ENABLE 0x00010000 181 #define RX_FIFO_THRESHOLD_BITS 0x0000e000 182 #define RX_FIFO_THRESHOLD_NONE 0x0000e000 183 #define RX_FIFO_THRESHOLD_1024B 0x0000c000 184 #define RX_FIFO_THRESHOLD_512B 0x0000a000 185 #define RX_FIFO_THRESHOLD_256B 0x00008000 186 #define RX_FIFO_THRESHOLD_128B 0x00006000 187 #define RX_FIFO_THRESHOLD_64B 0x00004000 188 #define RX_DMA_BURST_BITS 0x00000700 189 #define RX_DMA_BURST_UNLIMITED 0x00000700 190 #define RX_DMA_BURST_1024B 0x00000600 191 #define RX_DMA_BURST_512B 0x00000500 192 #define RX_DMA_BURST_256B 0x00000400 193 #define RX_DMA_BURST_128B 0x00000300 194 #define RX_DMA_BURST_64B 0x00000200 195 #define RX_EEPROM_9356 0x00000040 196 #define RX_ACCEPT_ERR_PKT 0x00000020 197 #define RX_ACCEPT_RUNT_PKT 0x00000010 198 #define RX_ACCEPT_BROADCAST_PKT 0x000000008 199 #define RX_ACCEPT_MULTICAST_PKT 0x000000004 200 #define RX_ACCEPT_MAC_MATCH_PKT 0x000000002 201 #define RX_ACCEPT_ALL_PKT 0x000000001 202 203 #define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \ 204 RX_DMA_BURST_1024B | \ 205 RX_ACCEPT_BROADCAST_PKT | \ 206 RX_ACCEPT_MULTICAST_PKT | \ 207 RX_ACCEPT_MAC_MATCH_PKT) 208 209 /* 210 * Timer count register 211 */ 212 #define TIMER_COUNT_REG 0x0048 213 214 /* 215 * Missed packet counter: indicates the number of packets 216 * discarded due to Rx FIFO overflow 217 */ 218 #define RX_PKT_MISS_COUNT_REG 0x004c 219 220 /* 221 * 93c46(93c56) commond register: 222 */ 223 #define RT_93c46_COMMOND_REG 0x0050 224 #define RT_93c46_MODE_BITS 0xc0 225 #define RT_93c46_MODE_NORMAL 0x00 226 #define RT_93c46_MODE_AUTOLOAD 0x40 227 #define RT_93c46_MODE_PROGRAM 0x80 228 #define RT_93c46_MODE_CONFIG 0xc0 229 230 #define RT_93c46_EECS 0x08 231 #define RT_93c46_EESK 0x04 232 #define RT_93c46_EEDI 0x02 233 #define RT_93c46_EEDO 0x01 234 235 /* 236 * Configuration registers 237 */ 238 #define RT_CONFIG_0_REG 0x0051 239 #define RT_CONFIG_1_REG 0x0052 240 #define RT_CONFIG_2_REG 0x0053 241 #define RT_CONFIG_3_REG 0x0054 242 #define RT_CONFIG_4_REG 0x0055 243 #define RT_CONFIG_5_REG 0x0056 244 245 /* 246 * Timer interrupt register 247 */ 248 #define TIMER_INT_REG 0x0058 249 #define TIMER_INT_NONE 0x00000000 250 251 /* 252 * PHY access register 253 */ 254 #define PHY_ACCESS_REG 0x0060 255 #define PHY_ACCESS_WR_FLAG 0x80000000 256 #define PHY_ACCESS_REG_BITS 0x001f0000 257 #define PHY_ACCESS_DATA_BITS 0x0000ffff 258 #define PHY_DATA_MASK 0xffff 259 #define PHY_REG_MASK 0x1f 260 #define PHY_REG_SHIFT 16 261 262 /* 263 * CSI data register (for PCIE chipset) 264 */ 265 #define RT_CSI_DATA_REG 0x0064 266 267 /* 268 * CSI access register (for PCIE chipset) 269 */ 270 #define RT_CSI_ACCESS_REG 0x0068 271 272 /* 273 * PHY status register 274 */ 275 #define PHY_STATUS_REG 0x006c 276 #define PHY_STATUS_TBI 0x80 277 #define PHY_STATUS_TX_FLOW 0x40 278 #define PHY_STATUS_RX_FLOW 0x20 279 #define PHY_STATUS_1000MF 0x10 280 #define PHY_STATUS_100M 0x08 281 #define PHY_STATUS_10M 0x04 282 #define PHY_STATUS_LINK_UP 0x02 283 #define PHY_STATUS_DUPLEX_FULL 0x01 284 285 #define RGE_SPEED_1000M 1000 286 #define RGE_SPEED_100M 100 287 #define RGE_SPEED_10M 10 288 #define RGE_SPEED_UNKNOWN 0 289 290 /* 291 * EPHY access register (for PCIE chipset) 292 */ 293 #define EPHY_ACCESS_REG 0x0080 294 #define EPHY_ACCESS_WR_FLAG 0x80000000 295 #define EPHY_ACCESS_REG_BITS 0x001f0000 296 #define EPHY_ACCESS_DATA_BITS 0x0000ffff 297 #define EPHY_DATA_MASK 0xffff 298 #define EPHY_REG_MASK 0x1f 299 #define EPHY_REG_SHIFT 16 300 301 /* 302 * Receive packet maximum size register 303 * -- the maximum rx size supported is (16K - 1) bytes 304 */ 305 #define RX_MAX_PKTSIZE_REG 0x00da 306 #define RX_PKTSIZE_JUMBO 0x1bfa /* 7K bytes */ 307 #define RX_PKTSIZE_STD 0x05fa /* 1530 bytes */ 308 309 /* 310 * C+ command register 311 */ 312 #define CPLUS_COMMAND_REG 0x00e0 313 #define CPLUS_RESERVE 0xfd87 314 #define CPLUS_BIT14 0x4000 315 #define CPLUS_BIG_ENDIAN 0x0400 316 #define RX_VLAN_DETAG 0x0040 317 #define RX_CKSM_OFFLOAD 0x0020 318 #define DUAL_PCI_CYCLE 0x0010 319 #define MUL_PCI_RW_ENABLE 0x0008 320 321 /* 322 * Receive descriptor start address 323 */ 324 #define RX_RING_ADDR_LO_REG 0x00e4 325 #define RX_RING_ADDR_HI_REG 0x00e8 326 327 /* 328 * Max transmit packet size register 329 */ 330 #define TX_MAX_PKTSIZE_REG 0x00ec 331 #define TX_MAX_PKTSIZE_REG_RESV 0xc0 332 #define TX_PKTSIZE_JUMBO 0x3b /* Realtek suggested value */ 333 #define TX_PKTSIZE_STD 0x32 /* document suggested value */ 334 335 #define RESV_82_REG 0x0082 336 #define RESV_E2_REG 0x00e2 337 338 /* 339 * PHY registers 340 */ 341 /* 342 * Basic mode control register 343 */ 344 #define PHY_BMCR_REG 0x00 345 #define PHY_RESET 0x8000 346 #define PHY_LOOPBACK 0x4000 347 #define PHY_SPEED_0 0x2000 348 #define PHY_SPEED_1 0x0040 349 #define PHY_SPEED_BITS (PHY_SPEED_0 | PHY_SPEED_1) 350 #define PHY_SPEED_1000M PHY_SPEED_1 351 #define PHY_SPEED_100M PHY_SPEED_0 352 #define PHY_SPEED_10M 0x0000 353 #define PHY_SPEED_RES (PHY_SPEED_0 | PHY_SPEED_1) 354 #define PHY_AUTO_NEGO 0x1000 355 #define PHY_RESTART_ANTO_NEGO 0x0200 356 #define PHY_DUPLEX_FULL 0x0100 357 #define PHY_BMCR_CLEAR 0xff40 358 359 /* 360 * Basic mode status register 361 */ 362 #define PHY_BMSR_REG 0x01 363 #define PHY_100BASE_T4 0x8000 364 #define PHY_100BASE_TX_FULL 0x4000 365 #define PHY_100BASE_TX_HALF 0x2000 366 #define PHY_10BASE_T_FULL 0x1000 367 #define PHY_10BASE_T_HALF 0x0800 368 #define PHY_100BASE_T2_FULL 0x0400 369 #define PHY_100BASE_T2_HALF 0x0200 370 #define PHY_1000BASE_T_EXT 0x0100 371 #define PHY_AUTO_NEGO_END 0x0020 372 #define PHY_REMOTE_FAULT 0x0010 373 #define PHY_AUTO_NEGO_ABLE 0x0008 374 #define PHY_LINK_UP 0x0004 375 #define PHY_JABBER_DETECT 0x0002 376 #define PHY_EXT_ABLE 0x0001 377 378 /* 379 * PHY identifier register 380 */ 381 #define PHY_ID_REG_1 0x02 382 #define PHY_ID_REG_2 0x03 383 #define PHY_VER_MASK 0x000f 384 #define PHY_VER_S 0x0000 385 #define PHY_VER_SB 0x0010 386 387 /* 388 * Auto-negotiation advertising register 389 */ 390 #define PHY_ANAR_REG 0x04 391 #define ANAR_NEXT_PAGE 0x8000 392 #define ANAR_REMOTE_FAULT 0x2000 393 #define ANAR_ASY_PAUSE 0x0800 394 #define ANAR_PAUSE 0x0400 395 #define ANAR_100BASE_T4 0x0200 396 #define ANAR_100BASE_TX_FULL 0x0100 397 #define ANAR_100BASE_TX_HALF 0x0080 398 #define ANAR_10BASE_T_FULL 0x0040 399 #define ANAR_10BASE_T_HALF 0x0020 400 #define ANAR_RESV_BITS 0x501f 401 402 /* 403 * Auto-negotiation link partner ability register 404 */ 405 #define PHY_ANLPAR_REG 0x05 406 407 /* 408 * Auto-negotiation expansion register 409 */ 410 #define PHY_ANER_REG 0x06 411 412 /* 413 * Auto-negotiation next page transmit register 414 */ 415 #define PHY_ANNPTR_REG 0x07 416 417 /* 418 * Auto-negotiation next page receive register 419 */ 420 #define PHY_ANNPRR_REG 0x08 421 422 /* 423 * 1000Base-T control register 424 */ 425 #define PHY_GBCR_REG 0x09 426 #define GBCR_MODE_JITTER 0x2000 427 #define GBCR_MODE_MASTER 0x4000 428 #define GBCR_MODE_SLAVE 0x6000 429 #define GBCR_1000BASE_T_FULL 0x0200 430 #define GBCR_1000BASE_T_HALF 0x0100 431 #define GBCR_DEFAULT 0x273a 432 433 /* 434 * 1000Base-T status register 435 */ 436 #define PHY_GBSR_REG 0x0a 437 #define LP_1000BASE_T_FULL 0x0800 438 #define LP_1000BASE_T_HALF 0x0400 439 440 /* 441 * 1000Base-T extended status register 442 */ 443 #define PHY_GBESR_REG 0x0f 444 445 #define PHY_1F_REG 0x1f 446 #define PHY_1D_REG 0x1d 447 #define PHY_1C_REG 0x1c 448 #define PHY_1B_REG 0x1b 449 #define PHY_18_REG 0x18 450 #define PHY_15_REG 0x15 451 #define PHY_13_REG 0x13 452 #define PHY_12_REG 0x12 453 #define PHY_0E_REG 0x0e 454 #define PHY_0C_REG 0x0c 455 #define PHY_0B_REG 0x0b 456 457 /* 458 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 459 */ 460 461 #define MII_AN_LPNXTPG 8 462 #define MII_1000BASE_T_CONTROL 9 463 #define MII_1000BASE_T_STATUS 10 464 #define MII_IEEE_EXT_STATUS 15 465 466 /* 467 * New bits in the MII_CONTROL register 468 */ 469 #define MII_CONTROL_1000MB 0x0040 470 471 /* 472 * New bits in the MII_AN_ADVERT register 473 */ 474 #define MII_ABILITY_ASYM_PAUSE 0x0800 475 #define MII_ABILITY_PAUSE 0x0400 476 477 /* 478 * Values for the <selector> field of the MII_AN_ADVERT register 479 */ 480 #define MII_AN_SELECTOR_8023 0x0001 481 482 /* 483 * Bits in the MII_1000BASE_T_CONTROL register 484 * 485 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 486 * (otherwise, roles are automatically negotiated). When this bit is set, 487 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 488 */ 489 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 490 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 491 #define MII_1000BT_CTL_ADV_FDX 0x0200 492 #define MII_1000BT_CTL_ADV_HDX 0x0100 493 494 /* 495 * Vendor-specific MII registers 496 */ 497 #define MII_EXT_CONTROL MII_VENDOR(0) 498 #define MII_EXT_STATUS MII_VENDOR(1) 499 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 500 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 501 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 502 #define MII_AUX_CONTROL MII_VENDOR(8) 503 #define MII_AUX_STATUS MII_VENDOR(9) 504 #define MII_INTR_STATUS MII_VENDOR(10) 505 #define MII_INTR_MASK MII_VENDOR(11) 506 #define MII_HCD_STATUS MII_VENDOR(13) 507 508 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 509 510 /* 511 * Bits in the MII_AUX_STATUS register 512 */ 513 #define MII_AUX_STATUS_MODE_MASK 0x0700 514 #define MII_AUX_STATUS_MODE_1000_F 0x0700 515 #define MII_AUX_STATUS_MODE_1000_H 0x0600 516 #define MII_AUX_STATUS_MODE_100_F 0x0500 517 #define MII_AUX_STATUS_MODE_100_4 0x0400 518 #define MII_AUX_STATUS_MODE_100_H 0x0300 519 #define MII_AUX_STATUS_MODE_10_F 0x0200 520 #define MII_AUX_STATUS_MODE_10_H 0x0100 521 #define MII_AUX_STATUS_MODE_NONE 0x0000 522 #define MII_AUX_STATUS_MODE_SHIFT 8 523 524 #define MII_AUX_STATUS_PAR_FAULT 0x0080 525 #define MII_AUX_STATUS_REM_FAULT 0x0040 526 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 527 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 528 529 #define MII_AUX_STATUS_LINKUP 0x0004 530 #define MII_AUX_STATUS_RX_PAUSE 0x0002 531 #define MII_AUX_STATUS_TX_PAUSE 0x0001 532 533 /* 534 * Third section: 535 * Hardware-defined data structures 536 * 537 * Note that the chip is naturally little-endian, so, for a little-endian 538 * host, the structures defined below match those descibed in the PRM. 539 * For big-endian hosts, some structures have to be swapped around. 540 */ 541 542 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 543 #error Host endianness not defined 544 #endif 545 546 /* 547 * Architectural constants: absolute maximum numbers of each type of ring 548 */ 549 550 #define RGE_SEND_SLOTS 1024 551 #define RGE_RECV_SLOTS 1024 552 #define RGE_BUFF_SIZE_STD 1536 /* 1536 bytes */ 553 #define RGE_BUFF_SIZE_JUMBO 7168 /* maximum 7K */ 554 #define RGE_JUMBO_SIZE 7014 555 #define RGE_JUMBO_MTU 7000 556 #define RGE_STATS_DUMP_SIZE 64 557 558 typedef struct rge_bd { 559 volatile uint32_t flags_len; 560 volatile uint32_t vlan_tag; 561 volatile uint32_t host_buf_addr; 562 volatile uint32_t host_buf_addr_hi; 563 } rge_bd_t; 564 565 #define BD_FLAG_HW_OWN 0x80000000 566 #define BD_FLAG_EOR 0x40000000 567 #define BD_FLAG_PKT_START 0x20000000 568 #define BD_FLAG_PKT_END 0x10000000 569 570 #define RBD_FLAG_MULTICAST 0x08000000 571 #define RBD_FLAG_UNICAST 0x04000000 572 #define RBD_FLAG_BROADCAST 0x02000000 573 #define RBD_FLAG_PKT_4096 0x00400000 574 #define RBD_FLAG_ERROR 0x00200000 575 #define RBD_FLAG_RUNT 0x00100000 576 #define RBD_FLAG_CRC_ERR 0x00080000 577 #define RBD_FLAG_PROTOCOL 0x00060000 578 #define RBD_FLAG_IP 0x00060000 579 #define RBD_FLAG_UDP 0x00040000 580 #define RBD_FLAG_TCP 0x00020000 581 #define RBD_FLAG_NONE_IP 0x00000000 582 #define RBD_IP_CKSUM_ERR 0x00010000 583 #define RBD_UDP_CKSUM_ERR 0x00008000 584 #define RBD_TCP_CKSUM_ERR 0x00004000 585 #define RBD_CKSUM_ERR 0x0001c000 586 #define RBD_FLAGS_MASK 0xffffc000 587 #define RBD_LEN_MASK 0x00003fff 588 589 #define RBD_VLAN_PKT 0x00010000 590 #define RBD_VLAN_TAG 0x0000ffff 591 592 593 #define SBD_FLAG_LARGE_SEND 0x08000000 594 #define SBD_FLAG_SEG_MAX 0x07ff0000 595 #define SBD_FLAG_IP_CKSUM 0x00040000 596 #define SBD_FLAG_UDP_CKSUM 0x00020000 597 #define SBD_FLAG_TCP_CKSUM 0x00010000 598 #define SBD_FLAG_TCP_UDP_CKSUM 0x00030000 599 #define SBD_LEN_MASK 0x0000ffff 600 601 #define SBD_VLAN_PKT 0x00020000 602 #define SBD_VLAN_TAG 0x0000ffff 603 604 #define SBD_FLAG_TX_PKT (BD_FLAG_HW_OWN | BD_FLAG_PKT_START | \ 605 BD_FLAG_PKT_END) 606 607 /* 608 * Chip VLAN TCI format 609 * bit0-3: VIDH The high 4 bits of a 12-bit VLAN ID 610 * bit4: CFI Canonical format indicator 611 * bit5-7: 3-bit 8-level priority 612 * bit8-15: The low 8 bits of a 12-bit VLAN ID 613 */ 614 #define TCI_OS2CHIP(tci) (((tci & 0xff) << 8) | (tci >> 8)) 615 #define TCI_CHIP2OS(tci) (((tci & 0xff00) >> 8) | (tci << 8)) 616 617 /* 618 * Hardware-defined Status Block 619 */ 620 typedef struct rge_hw_stats { 621 uint64_t xmt_ok; 622 uint64_t rcv_ok; 623 uint64_t xmt_err; 624 uint32_t rcv_err; 625 uint16_t in_discards; 626 uint16_t frame_err; 627 uint32_t xmt_1col; 628 uint32_t xmt_mcol; 629 uint64_t unicast_rcv; 630 uint64_t brdcst_rcv; 631 uint32_t multi_rcv; 632 uint16_t xmt_abt; 633 uint16_t xmt_undrn; 634 } rge_hw_stats_t; /* total 64 bytes */ 635 636 #ifdef __cplusplus 637 } 638 #endif 639 640 #endif /* _RGE_HW_H */ 641